Semiconductor devices

Abstract

A transistor with stable electrical characteristics comprising an oxide semiconductor film is provided. In this transistor, a first oxide semiconductor film capable of at least suppressing oxygen release from the oxide film is formed on an oxide film that is capable of releasing oxygen upon heating. A second oxide semiconductor film is formed on the first oxide semiconductor film. By employing a structure in which oxide semiconductor films are stacked, oxygen release from the oxide film can be suppressed when the second oxide semiconductor film is formed, and oxygen can be released from the oxide film through subsequent heat treatment. Therefore, oxygen can be appropriately supplied to the second oxide semiconductor film through the first oxide semiconductor film. By supplying oxygen to the second oxide semiconductor film, oxygen defects are suppressed, resulting in stable electrical characteristics.

Description

Technical Field

[0001] This invention relates to semiconductor devices comprising oxide semiconductors.

[0002] Note that in this specification, a semiconductor device refers to any device that can operate by utilizing the characteristics of semiconductors. Therefore, transistors, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. Background Technology

[0003] The technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as suitable semiconductor thin films for use in transistors. However, oxide semiconductors are also attracting attention as alternative materials.

[0004] For example, a transistor has been disclosed in which the active layer of the transistor comprises an amorphous oxide semiconductor film containing indium (In), gallium (Ga) and zinc (Zn) (see Patent Document 1).

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2006-165528 Transistors containing oxide semiconductor films have the following characteristics: they operate at higher speeds (or have higher field-effect mobility) compared to transistors containing amorphous silicon films, and are easier to manufacture compared to transistors containing polycrystalline silicon films.

[0006] However, transistors containing oxide semiconductor films have been found to have several problems, one of which is the instability of their electrical characteristics. Specifically, the threshold voltage of the transistor has been shown to drift negatively due to exposure to visible or ultraviolet light or bias temperature stress testing (BT stress testing), thus causing the transistor to tend to be normally-on. One cause of this problem is oxygen defects in the oxide semiconductor film.

[0007] For example, when the oxide semiconductor film is amorphous, the bonding state between metal atoms and oxygen atoms in the oxide semiconductor film is disordered, which easily leads to oxygen defects. This can potentially cause changes in the electrical properties (e.g., electrical conductivity) of the oxide semiconductor film. Such changes can cause variations in the electrical properties of transistors, thereby reducing the reliability of semiconductor devices containing those transistors.

[0008] Another example of a method to reduce oxygen defects generated in an oxide semiconductor film is to supply oxygen from an oxide film or similar material formed near the oxide semiconductor film to fill the oxygen defects. However, before the oxide semiconductor film is formed (in other words, before oxygen is supplied to the oxide semiconductor film), oxygen may be released from the oxide film or similar material formed near the oxide semiconductor film due to heat treatment or the like, thus preventing sufficient oxygen supply to the oxide semiconductor film. Summary of the Invention

[0009] In view of the above problems, one of the objectives of the present invention is to provide a transistor comprising an oxide semiconductor film having stable electrical properties.

[0010] A first oxide semiconductor film capable of at least suppressing oxygen release from the oxide film is formed on an oxide film capable of releasing oxygen upon heating, and a second oxide semiconductor film is formed on the first oxide semiconductor film. By employing the above-described structure with stacked oxide semiconductor films, oxygen release from the oxide film can be suppressed during the formation of the second oxide semiconductor film, and oxygen can be released from the oxide film through subsequent heat treatment. Therefore, oxygen can be appropriately supplied to the second oxide semiconductor film through the first oxide semiconductor film. By supplying oxygen to the second oxide semiconductor film, the generation of oxygen defects is suppressed, resulting in stable electrical properties.

[0011] Furthermore, both the first and second oxide semiconductor films are oxide films containing at least indium, gallium, and zinc. The indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film. Therefore, by forming the second oxide semiconductor film on the first oxide semiconductor film containing the same type of material, a film including crystals grown from the interface with the first oxide semiconductor film can be formed. This will be explained in detail below.

[0012] One aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film; and a second oxide semiconductor film formed on the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films comprising at least indium, gallium, and zinc, wherein the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0013] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; and a gate electrode formed in a region contacting the gate insulating film and overlapping the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0014] Note that the percentages mentioned in this specification refer to the proportions of the components contained in each film. In particular, in many cases, it refers to the percentages of the first oxide semiconductor film and the second oxide semiconductor film.

[0015] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; a gate electrode formed in a region contacting the gate insulating film and overlapping with the second oxide semiconductor film; a protective insulating film formed on the gate electrode; an interlayer insulating film formed on the protective insulating film; and a source electrode and a drain electrode formed on the interlayer insulating film and electrically connected to the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0016] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; a gate electrode formed in a region contacting the gate insulating film and overlapping the second oxide semiconductor film; a protective insulating film formed on the gate electrode; an interlayer insulating film formed on the protective insulating film; a first opening and a second opening formed in the gate insulating film, the protective insulating film, and the interlayer insulating film; and a source electrode and a drain electrode filled in the first opening and the second opening and electrically connected to the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0017] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; a gate electrode formed in a region contacting the gate insulating film and overlapping with the second oxide semiconductor film; an insulating film formed in the region overlapping with the gate electrode; a sidewall insulating film formed on the sides of the gate electrode and the insulating film in a cross-section along the channel length direction; a source electrode and a drain electrode formed in contact with the sidewall insulating film and electrically connected to the second oxide semiconductor film; and a protective insulating film and an interlayer insulating film formed at least on the source electrode and the drain electrode. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0018] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; a gate electrode formed in a region contacting the gate insulating film and overlapping the second oxide semiconductor film; a source electrode in contact with one side of the second oxide semiconductor film and a drain electrode in contact with the other side of the second oxide semiconductor film in a cross-section along the channel length direction; a first conductive film formed on one side of the gate electrode; a second conductive film formed on the other side of the gate electrode; sidewall insulating films formed on the sides of the first and second conductive films; and protective insulating films and interlayer insulating films formed at least on the gate electrode, the source electrode, and the drain electrode. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0019] In any of the above structures, at least a portion of the first conductive film is formed on the source electrode through the gate insulating film, and at least a portion of the second conductive film is formed on the drain electrode through the gate insulating film.

[0020] Thus, by forming the first and second conductive films in contact with the gate electrode, a region (also known as the Lov region) overlapping the source and drain electrodes across the gate insulating film can be created. This suppresses the decrease in conduction current caused by miniaturization.

[0021] Another aspect of the present invention is a semiconductor device comprising: a first oxide semiconductor film formed on an oxide film; a second oxide semiconductor film formed on the first oxide semiconductor film; a gate insulating film formed on the second oxide semiconductor film; a gate electrode contacting the gate insulating film and covering the top and side surfaces of the second oxide semiconductor film; a protective insulating film and an interlayer insulating film formed on the gate electrode; and a source electrode and a drain electrode in a cross-section along the channel length direction, in an opening passing through the interlayer insulating film, the protective insulating film, the gate insulating film, and the second oxide semiconductor film, contacting the side surfaces of the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are each oxide films containing at least indium, gallium, and zinc, and the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0022] In any of the above structures, it is preferred that the source electrode and the drain electrode include surfaces planarized by chemical mechanical polishing.

[0023] When forming source and drain electrodes with surfaces planarized by chemical mechanical polishing, etching using a resist mask is not performed, so even when the width of the channel in the length direction of the source and drain electrodes is reduced, precise machining can still be performed accurately.

[0024] In any of the above structures, it is preferred that the first oxide semiconductor film includes a low-resistance region and a high-resistance region, the high-resistance region being located at least further outward than the second oxide semiconductor film.

[0025] The high-resistivity region of the first oxide semiconductor film, formed on the outer side of the second oxide semiconductor film, serves as a separation layer between the transistors. This structure can suppress electrical connections between adjacent transistors.

[0026] Furthermore, in any of the above structures, it is preferred that the second oxide semiconductor film includes a channel region and a pair of low-resistance regions in contact with the channel region. By forming a pair of low-resistance regions in contact with the channel region of the second oxide semiconductor film, the contact resistance between the second oxide semiconductor film and the source electrode and the drain electrode can be reduced.

[0027] Furthermore, in any of the above structures, it is preferred that the second oxide semiconductor film includes high-resistance regions on both sides of the channel width direction. By forming high-resistance regions on both sides of the second oxide semiconductor film in the channel width direction, the formation of parasitic channels in the second oxide semiconductor film can be suppressed.

[0028] Furthermore, in any of the above structures, it is preferred that the gallium content in the first oxide semiconductor film is equal to or greater than the indium content, and that the indium content in the second oxide semiconductor film is greater than the gallium content. When the indium content in the second oxide semiconductor film is greater than the gallium content, the crystallinity of the second oxide semiconductor film can be improved.

[0029] Furthermore, in any of the above structures, it is preferred that the first oxide semiconductor film is formed using an oxide with an atomic ratio of In:Ga:Zn=1:1:1 or In:Ga:Zn=1:3:2, and the second oxide semiconductor film is formed using an oxide with an atomic ratio of In:Ga:Zn=3:1:2.

[0030] Furthermore, in any of the above structures, it is preferred that the second oxide semiconductor film includes a crystalline portion, and the c-axis of the crystalline portion is aligned in a direction parallel to the normal vector of the surface on which the second oxide semiconductor film is formed. By including a crystalline portion in the second oxide semiconductor film, the bonding state between metal atoms and oxygen atoms in the second oxide semiconductor film is ordered, thereby suppressing oxygen defects.

[0031] Furthermore, in any of the above structures, it is preferred that the protective insulating film is an aluminum oxide film, and that the aluminum oxide film density is 3.2 g / cm³. 3 The above describes how using the alumina film as a protective insulating film can achieve a shielding effect that prevents impurities such as hydrogen and moisture from penetrating the second oxide semiconductor film or prevents oxygen from escaping from the second oxide semiconductor film.

[0032] The present invention can provide a transistor with stable electrical properties using an oxide semiconductor film. Attached Figure Description

[0033] Figure 1A It is a plan view showing one way of a semiconductor device, and Figure 1B and Figure 1C This is a cross-sectional view showing one way a semiconductor device is constructed; Figures 2A to 2D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 3A to 3D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 4A It is a plan view showing one way of a semiconductor device, and Figure 4B and Figure 4C This is a cross-sectional view showing one way a semiconductor device is constructed; Figures 5A to 5D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 6A to 6C This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 7A It is a plan view showing one way of a semiconductor device, and Figure 7B and Figure 7C This is a cross-sectional view showing one way a semiconductor device is constructed; Figures 8A to 8D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 9A It is a plan view showing one method of manufacturing a semiconductor device, and Figure 9B and Figure 9C This is a cross-sectional view illustrating one method of manufacturing a semiconductor device; Figure 10A It is a plan view showing one method of manufacturing a semiconductor device, and Figure 10B and Figure 10C This is a cross-sectional view illustrating one method of manufacturing a semiconductor device; Figures 11A to 11D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 12A to 12C This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 13A It is a plan view showing one way of a semiconductor device, and Figure 13B and Figure 13C This is a cross-sectional view showing one way a semiconductor device is constructed; Figures 14A to 14D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 15A to 15D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 16A to 16D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 17A and Figure 17B This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figure 18A It is a plan view showing one way of a semiconductor device, and Figure 18B and Figure 18C This is a cross-sectional view showing one way a semiconductor device is constructed; Figures 19A to 19D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 20A to 20D This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 21A to 21CThis is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device; Figures 22A to 22C These are cross-sectional views, plan views, and circuit diagrams illustrating one configuration of a semiconductor device; Figure 23A and Figure 23B It is a circuit diagram and perspective view showing one manner of a semiconductor device; Figure 24A This is a cross-sectional view showing one way a semiconductor device is constructed, and Figure 24B This is a plan view illustrating one method of using a semiconductor device; Figure 25A and Figure 25B This is a circuit diagram illustrating one method of using a semiconductor device; Figure 26 This is a block diagram illustrating one manner of a semiconductor device; Figure 27 This is a block diagram illustrating one manner of a semiconductor device; Figure 28 This is a block diagram illustrating one manner of a semiconductor device; Figure 29 This is a flowchart illustrating the manufacturing process of a sputtering target. Detailed Implementation

[0034] The embodiments of the invention disclosed in this specification will now be described in detail with reference to the accompanying drawings. However, the invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited solely to the embodiments described below.

[0035] Note that, for ease of understanding, the positions, sizes, and extents of the structures shown in the accompanying drawings and other materials do not always represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings and other materials.

[0036] Furthermore, the ordinal numbers such as "first," "second," and "third" used in this specification and other documents are appended to avoid confusion among the constituent elements, and are not intended to limit the number of elements.

[0037] Furthermore, in this specification, "above" or "below" is not limited to the positional relationship of the constituent elements being "directly above" or "directly below". For example, "gate electrode on the gate insulating film" does not exclude the possibility that there are other constituent elements between the gate insulating film and the gate electrode.

[0038] Furthermore, in this specification and the like, the terms "electrode" or "wiring" do not limit the function of the constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0039] Furthermore, when using transistors with different polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification and the like, the "source" and "drain" can be used interchangeably.

[0040] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, there are no particular limitations on what constitutes an "element that has a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected objects. For example, an "element that has a certain electrical function" includes not only electrodes and wiring, but also switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0041] Implementation Method 1 In this embodiment, refer to Figures 1A to 1C , Figures 2A to 2D as well as Figures 3A to 3D One method of manufacturing a semiconductor device is described.

[0042] <Structure Example 1 of a Semiconductor Device> Figures 1A to 1C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. Figure 1A It's a floor plan. Figure 1B Equivalent to along Figure 1A The cross-sectional view of X1-Y1 in the diagram. Figure 1C Equivalent to along Figure 1A The cross-sectional view of V1-W1 in the diagram. Note that in Figure 1A In order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0043] Figures 1A to 1C The semiconductor device shown includes: an oxide film 104; a first oxide semiconductor film 106 formed on the oxide film 104; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0044] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are each oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0045] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. By increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0046] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0047] Here, we consider a structure in which the first oxide semiconductor film 106 is not formed. In this case, the second oxide semiconductor film 108 is formed directly on the oxide film 104. For example, when the second oxide semiconductor film 108 is formed by heating at a temperature such as 400°C, oxygen is released from the oxide film 104 before the second oxide semiconductor film 108 is formed. As a result, the amount of oxygen released from the oxide film 104 after the second oxide semiconductor film 108 is formed is reduced, and oxygen cannot be adequately supplied to the second oxide semiconductor film 108. Furthermore, when the oxide film 104 is formed using a different material than the second oxide semiconductor film 108, for example, when the oxide film 104 is formed using a silicon oxide film, there is a concern that silicon contained in the oxide film 104 may be mixed into the second oxide semiconductor film 108 as an impurity, thus hindering the crystallization of the second oxide semiconductor film 108.

[0048] However, by employing the structure shown in this embodiment, for example, by forming the first oxide semiconductor film 106 at a low temperature (e.g., above room temperature and below 200°C) after forming the oxide film 104 and forming the second oxide semiconductor film 108 at a high temperature (e.g., above 250°C and below 500°C, preferably above 300°C and below 400°C), the release of oxygen from the oxide film 104 can be suppressed by the first oxide semiconductor film 106. Furthermore, since the second oxide semiconductor film 108 is formed on the first oxide semiconductor film 106 formed using the same type of material, there are no or very few impurities mixed into the second oxide semiconductor film 108, thereby enabling the formation of an oxide semiconductor film including crystals grown from the interface with the first oxide semiconductor film 106.

[0049] In other words, the first oxide semiconductor film 106 suppresses the release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0050] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing the generation of oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0051] The high crystallinity of the second oxide semiconductor film 108 enables the ordered bonding state between metal atoms and oxygen atoms in the second oxide semiconductor film, thereby suppressing the generation of oxygen defects. In addition, even if oxygen defects are generated, oxygen can be supplied from the oxide film 104 to fill the oxygen defects.

[0052] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0053] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0054] Alternatively, a structure can be adopted including: a protective insulating film 114 formed on the gate electrode 112; an interlayer insulating film 116 formed on the protective insulating film 114; and a source electrode 118a and a drain electrode 118b formed on the interlayer insulating film 116 and electrically connected to the second oxide semiconductor film 108. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0055] The constituent elements of the semiconductor device that can be used in the present invention will now be described in detail.

[0056] [Detailed Description of the Substrate] While there are no particular restrictions on the substrates that can be used for substrate 102, they must at least have heat resistance sufficient to withstand the degree of subsequent heat treatment. For example, glass substrates such as barium borosilicate glass or aluminum borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc., can be used. In addition, single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates made of silicon germanium, SOI substrates, etc., can also be used.

[0057] [Detailed Description of Oxide Film] The oxide film 104 prevents the diffusion of impurities such as hydrogen and moisture from the substrate 102, and can be formed using a single-layer or multilayer structure selected from silicon oxide films, silicon oxynitride films, and silicon oxynitride films. Furthermore, as another effect of the oxide film 104, it is preferable to have the effect of supplying oxygen to the subsequently formed first oxide semiconductor film 106 and second oxide semiconductor film 108. For example, when a silicon oxide film is used as the oxide film 104, a portion of the oxygen can be removed by heating the oxide film 104, thereby supplying oxygen to the first oxide semiconductor film 106 and second oxide semiconductor film 108 to fill oxygen defects in the first oxide semiconductor film 106 and second oxide semiconductor film 108.

[0058] In particular, it is preferable that the oxide film 104 contains oxygen in addition to at least a stoichiometric amount; for example, SiO2 is preferably used as the oxide film 104. 2+α (α>0) represents the silicon oxide film. By using the above-mentioned silicon oxide film as the oxide film 104, oxygen can be supplied to the first oxide semiconductor film 106 and the second oxide semiconductor film 108.

[0059] [Detailed Description of the First Oxide Semiconductor Film] The first oxide semiconductor film 106 uses an oxide film containing at least indium, gallium, and zinc, thereby allowing the use of In-Ga-Zn type oxides (also known as IGZO). Furthermore, In-Ga-Zn type oxides refer to oxides containing In, Ga, and Zn, but may also contain metal elements other than In, Ga, and Zn. For example, In-Sn-Ga-Zn type oxides, In-Hf-Ga-Zn type oxides, and In-Al-Ga-Zn type oxides can be used.

[0060] Furthermore, the indium content in the first oxide semiconductor film 106 is less than that in the second oxide semiconductor film 108, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108. Additionally, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. That is, it is preferable to use an oxide whose composition can be expressed as In ≤ Ga. For example, it is preferable to use In-Ga-Zn type oxides or oxides with an atomic ratio of In:Ga:Zn = 1:1:1 or In:Ga:Zn = 1:3:2, or oxides with compositions close to these.

[0061] Furthermore, the first oxide semiconductor film 106 can be formed using methods such as sputtering, ALD (Atomic Layer Deposition), vapor deposition, or coating. The thickness of the first oxide semiconductor film 106 is greater than 5 nm and less than 200 nm, preferably more than 10 nm and less than 30 nm. The first oxide semiconductor film 106 is in a single-crystal, polycrystalline, or amorphous state.

[0062] [Detailed Description of Second Oxide Semiconductor Film] The second oxide semiconductor film 108 uses an oxide film containing at least indium, gallium, and zinc, thereby allowing the use of In-Ga-Zn type oxides (also known as IGZO). Furthermore, In-Ga-Zn type oxides refer to oxides containing In, Ga, and Zn, but may also contain metal elements other than In, Ga, and Zn. For example, In-Sn-Ga-Zn type oxides, In-Hf-Ga-Zn type oxides, and In-Al-Ga-Zn type oxides can be used.

[0063] Furthermore, the indium content in the second oxide semiconductor film 108 is greater than that in the first oxide semiconductor film 106, and the gallium content in the second oxide semiconductor film 108 is less than that in the first oxide semiconductor film 106. That is, it is preferable to use an oxide whose composition can be expressed as In > Ga. For example, In-Ga-Zn oxides or oxides with an atomic ratio of In:Ga:Zn=3:1:2 or In:Ga:Zn=2:1:3, or similar compositions, can be used.

[0064] Furthermore, methods for forming the second oxide semiconductor film 108 include sputtering, ALD, evaporation, and coating. The thickness of the second oxide semiconductor film 108 is greater than 5 nm and less than 200 nm, preferably 10 nm or more and less than 30 nm. The second oxide semiconductor film 108 preferably has a crystalline structure, such as single crystal, polycrystalline (also called polycrystal), or microcrystal.

[0065] Furthermore, the second oxide semiconductor film 108 is preferably a CAAC-OS (C-axis Aligned Crystalline Oxide Semiconductor) film. The CAAC-OS film is neither completely single-crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystalline-amorphous mixed-phase structure having crystalline portions within an amorphous phase. In many cases, the size of these crystalline portions is large enough to be contained within a cube with a side length less than 100 nm. Furthermore, in images observed using a transmission electron microscope (TEM), the boundary between the amorphous and crystalline portions within the CAAC-OS film is indistinct. Moreover, grain boundaries (also called grain boundaries) are not observable in the CAAC-OS film using TEM. Therefore, in the CAAC-OS film, the reduction in electron mobility due to grain boundaries is suppressed.

[0066] The c-axis of the crystalline portion in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formed surface or the surface normal vector of the CAAC-OS film. When viewed from a direction perpendicular to the ab plane, it exhibits a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Furthermore, the directions of the a-axis and b-axis may differ between different crystalline portions. In this specification, when only "perpendicular" is used, it includes a range of 85° or more and 95° or less. Conversely, when only "parallel" is used, it includes a range of -5° or more and 5° or less.

[0067] Furthermore, the distribution of crystalline portions in a CAAC-OS film can be uneven. For example, during the formation of a CAAC-OS film, compared to some cases, when crystal growth occurs from the surface side of the oxide semiconductor film, the proportion of crystalline portions near the surface of the oxide semiconductor film is sometimes higher. Additionally, by adding impurities to the CAAC-OS film, the crystalline portions in the impurity-added regions are sometimes amorphized.

[0068] Because the c-axis of the crystalline portion included in the CAAC-OS film is parallel to the normal vector of the formed surface or the surface normal vector of the CAAC-OS film, it sometimes faces different directions depending on the shape of the CAAC-OS film (the cross-sectional shape of the formed surface or the cross-sectional shape of the surface). Alternatively, the c-axis direction of the crystalline portion is parallel to the normal vector of the formed surface or the surface normal vector during the formation of the CAAC-OS film. The crystalline portion is formed through crystallization treatment such as film formation or subsequent heat treatment.

[0069] Transistors using CAAC-OS films exhibit minimal changes in their electrical characteristics caused by visible or ultraviolet light irradiation. Furthermore, threshold voltage fluctuations and deviations can be suppressed. Therefore, these transistors demonstrate high reliability.

[0070] Furthermore, crystalline or crystalline oxide semiconductors can further reduce bulk defects. Moreover, by improving the flatness of the surface of the crystalline or crystalline oxide semiconductor film, transistors using this oxide semiconductor can achieve field-effect mobilities exceeding those of transistors using amorphous oxide semiconductors. To improve the flatness of the oxide semiconductor film surface, it is preferable to form the oxide semiconductor on a flat surface; specifically, the oxide semiconductor is formed on a surface with an average surface roughness (Ra) of 0.15 nm or less, preferably 0.1 nm or less.

[0071] Note that Ra is an extension of the arithmetic mean roughness defined in JIS B0601 to three dimensions so that it can be applied to surfaces. It can be expressed as "the value obtained by averaging the absolute values ​​of the deviations from the reference surface to the specified surface", as defined by the following formula.

[0072] [Equation 1] Here, the designated surface refers to the surface that becomes the object of roughness measurement, and it is a quadrilateral region represented by four points at coordinates (x1, y1, f(x1, y1)), (x1, y2, f(x1, y2)), (x2, y1, f(x2, y1)), and (x2, y2, f(x2, y2)). The area of ​​the rectangle projected onto the xy plane by the designated surface is S0, and the height of the reference surface (the average height of the designated surface) is Z0. Ra can be measured using an atomic force microscope (AFM).

[0073] Furthermore, when a CAAC-OS film is used as the second oxide semiconductor film 108, three methods can be cited as methods for forming the CAAC-OS film. The first method is to form the oxide semiconductor film at a film-forming temperature of 200°C or higher and 450°C or lower. This forms crystalline portions in the oxide semiconductor film where the c-axis is aligned in a direction parallel to the normal vector of the formed surface or the normal vector of the surface. The second method is to perform a heat treatment at 200°C or higher and 700°C or lower after forming the oxide semiconductor film to a thin thickness. This forms crystalline portions in the oxide semiconductor film where the c-axis is aligned in a direction parallel to the normal vector of the formed surface or the normal vector of the surface. The third method is to perform a heat treatment at 200°C or higher and 700°C or lower after forming the first oxide semiconductor film to a thin thickness, and then form the second oxide semiconductor film. This forms crystalline portions in the oxide semiconductor film where the c-axis is aligned in a direction parallel to the normal vector of the formed surface or the normal vector of the surface.

[0074] Furthermore, by performing film formation while heating the substrate 102, the concentration of impurities such as hydrogen or water contained in the formed second oxide semiconductor film 108 can be reduced. Additionally, damage caused by sputtering can be mitigated, making this method preferable. Alternatively, the second oxide semiconductor film 108 can also be formed using methods such as ALD, vapor deposition, or coating.

[0075] In addition, when forming a crystalline oxide semiconductor film (single crystal or microcrystal) other than a CAAC-OS film as the second oxide semiconductor film 108, there are no particular restrictions on the film formation temperature.

[0076] Furthermore, the bandgap of the second oxide semiconductor film 108 is 2.8 eV to 3.2 eV, which is greater than the 1.1 eV bandgap of silicon. Additionally, the minority carrier density of the second oxide semiconductor film 108 is 1 × 10⁻⁶. -9 / cm 3 This is greater than the intrinsic carrier density of silicon, which is 1 × 10⁻⁶. 11 / cm 3 Much smaller.

[0077] The majority carriers (electrons) of the second oxide semiconductor film 108 flow only from the source of the transistor. Furthermore, because the channel formation region can be completely depleted, the transistor's cutoff current is extremely small. The transistor using the second oxide semiconductor film 108 has an extremely small cutoff current, that is, less than 10 μA / mm at room temperature and less than 1 μA / mm at temperatures between 85°C and 95°C.

[0078] Furthermore, in an n-channel transistor, the cutoff current described in this specification refers to the current flowing between the source and drain electrodes when the drain electrode potential is higher than the source and gate electrode potentials, and the gate electrode potential is below 0V when the source electrode potential is used as a reference. Alternatively, in a p-channel transistor, the cutoff current described in this specification refers to the current flowing between the source and drain electrodes when the drain electrode potential is lower than the source and gate electrode potentials, and the gate electrode potential is above 0V when the source electrode potential is used as a reference.

[0079] Furthermore, the transistor containing the second oxide semiconductor film 108 has an ideally low S value. Additionally, the transistor has high reliability.

[0080] [Detailed Description of Gate Insulating Film] As the gate insulating film 110, silicon oxide film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film, aluminum oxynitride film, or silicon oxynitride film, etc., can be used. The portion of the gate insulating film 110 that contacts the second oxide semiconductor film 108 preferably contains oxygen. In particular, the gate insulating film 110 preferably contains oxygen in an amount exceeding its stoichiometric composition; for example, when a silicon oxide film is used as the gate insulating film 110, SiO₂ is preferably used. 2+a A film with (a>0). By using this silicon oxide film as a gate insulating film 110, oxygen can be supplied to the second oxide semiconductor film 108, thus giving it good electrical properties.

[0081] Furthermore, hafnium oxide, yttrium oxide, and hafnium silicate (HfSi) can be used as the gate insulating film 110. x O y (x>0, y>0)), Hafnium silicate with added nitrogen (HfSiO) x N y (x>0, y>0), hafnium aluminate (HfAl) x O y (x>0, y>0) and high-k materials such as lanthanum oxide. By using the above materials, the gate leakage current can be reduced. Moreover, the gate insulating film 110 can be either a single-layer structure or a multilayer structure.

[0082] Furthermore, the thickness of the gate insulating film 110 can be set to be 1 nm or more and 500 nm or less. Additionally, there are no particular limitations on the manufacturing method of the gate insulating film 110; for example, sputtering, MBE, PE-CVD, pulsed laser deposition, ALD, etc., can be appropriately utilized.

[0083] [Detailed Description of the Gate Electrode] As the gate electrode 112, for example, metallic materials such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, or alloys containing these metallic materials, can be used. Alternatively, the gate electrode 112 can also be formed using conductive metal oxides. As conductive metal oxides, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium tin oxide (In₂O₃-SnO₂, sometimes abbreviated as ITO), indium zinc oxide (In₂O₃-ZnO), or metal oxides formed by containing silicon or silicon oxide in these metal oxide materials can be used. Furthermore, the gate electrode 112 can be formed using the above materials in a single layer or in a stack. There are no particular limitations on its formation method; various film formation methods such as vapor deposition, PE-CVD, sputtering, or spin coating can be used.

[0084] [Detailed Description of Protective Insulating Film] The protective insulating film 114 is preferably made of an inorganic insulating film, such as a single layer or stack of oxide insulating films such as silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, gallium oxide film, or hafnium oxide film. Alternatively, a single layer or stack of nitride insulating films such as silicon nitride film, silicon oxynitride film, aluminum nitride film, or aluminum oxynitride film can be formed on the aforementioned oxide insulating film. For example, a stack of silicon oxide film and aluminum oxide film can be sequentially formed from the gate electrode 112 side by sputtering. Furthermore, there are no particular limitations on the manufacturing method of the protective insulating film 114; for example, sputtering, MBE, PE-CVD, pulsed laser deposition, ALD, etc., can be appropriately used.

[0085] Furthermore, in particular, a high-density inorganic insulating film can be provided as the protective insulating film 114. For example, an alumina film can be formed using a sputtering method. This is achieved by setting the density of the alumina film to a high density (film density of 3.2 g / cm³). 3 The above, preferably 3.6 g / cm³ 3 The above methods achieve a shielding effect (blocking effect) that prevents impurities such as hydrogen and moisture from entering the second oxide semiconductor film 108 or from escaping oxygen from the second oxide semiconductor film 108. Therefore, the alumina film serves as a protective film to prevent impurities such as hydrogen and moisture, which are the main causes of variations in the second oxide semiconductor film 108 during and after the manufacturing process, from entering the second oxide semiconductor film 108, and to prevent the release of oxygen, a major component of the second oxide semiconductor film 108. Furthermore, the film density can be measured using methods such as Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR).

[0086] [Detailed Description of Interlayer Insulation Film] Inorganic insulating films are preferably used as the interlayer insulating film 116, and single layers or stacks of silicon oxide films, silicon oxynitride films, silicon nitride films, and silicon oxynitride films can be used. In addition, there are no particular restrictions on the manufacturing method of the interlayer insulating film 116, and sputtering, MBE, PE-CVD, pulsed laser deposition, ALD, etc. can be appropriately used.

[0087] [Detailed Description of Source and Drain Electrodes] As the source electrode 118a and drain electrode 118b, for example, a metal film containing elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the aforementioned elements can be used. Alternatively, a structure can be adopted in which a high-melting-point metal film such as titanium, molybdenum, or tungsten, or their metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film), can be stacked on one or both sides of the lower and upper sides of a metal film such as aluminum or copper. Furthermore, conductive metal oxides can be used to form conductive films for the source electrode 118a and drain electrode 118b. Indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium tin oxide (In₂O₃-SnO₂, abbreviated as ITO), and indium zinc oxide (In₂O₃-ZnO) can be used. The conductive films for the source electrode and drain electrode can be formed in a single layer or in layers using the above materials. There are no particular restrictions on the formation method; various film formation methods such as vapor deposition, PE-CVD, sputtering, or spin coating can be used.

[0088] Furthermore, in the semiconductor device manufacturing method 1 described later, refer to Figures 2A to 2D as well as Figures 3A to 3D Provide a detailed explanation of the other constituent elements.

[0089] <Semiconductor Device Manufacturing Method 1> Below, refer to Figures 2A to 2D as well as Figures 3A to 3D For this embodiment Figures 1A to 1C An example of a method for manufacturing a semiconductor device is illustrated.

[0090] First, a substrate 102 is prepared. Then, an oxide film 104, a first oxide semiconductor film 106, and a second oxide semiconductor film 108 are formed on the substrate 102 (see reference). Figure 2A ).

[0091] Alternatively, plasma treatment can be performed on the substrate 102 before forming the oxide film 104. As a plasma treatment, backsputtering can be performed, for example, by introducing argon gas to generate plasma. Backsputtering refers to a method of surface modification by applying a voltage to one side of the substrate 102 using an RF power supply under an argon atmosphere to generate plasma near the substrate 102. Alternatively, nitrogen, helium, oxygen, or other alternatives to the argon atmosphere can be used. By performing backsputtering, powdery substances (also known as particles or dust) adhering to the surface of the substrate 102 can be removed.

[0092] As a method for forming the second oxide semiconductor film 108, the oxide semiconductor film is etched using a dry etching method. As the etching gas, BCl3, Cl2, or O2 can be used. A dry etching apparatus utilizing a high-density plasma source, such as ECR (electron cyclotron resonance) or ICP (inductively coupled plasma), can be used to increase the etching rate. Furthermore, in the process of forming the second oxide semiconductor film 108, the implementer can appropriately select the etching conditions of the second oxide semiconductor film 108 to prevent the first oxide semiconductor film 106 from being processed into an island-like shape. Additionally, the ends of the second oxide semiconductor film 108 preferably have a taper angle of 20° to 50°.

[0093] Furthermore, it is preferable to form the oxide film 104, the first oxide semiconductor film 106, and the second oxide semiconductor film 108 continuously without contact with the atmosphere; in particular, it is preferable to form the first oxide semiconductor film 106 and the second oxide semiconductor film 108 continuously. In this way, by forming the oxide film 104, the first oxide semiconductor film 106, and the second oxide semiconductor film 108 continuously without contact with the atmosphere, it is possible to suppress the incorporation of impurity elements such as moisture and hydrogen contained in the atmosphere into each interface.

[0094] Furthermore, in the process of forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108, it is preferable that the first oxide semiconductor film 106 and the second oxide semiconductor film 108 contain as little hydrogen or water as possible. For example, as a pretreatment for the process of forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108, it is preferable to preheat the substrate 102 on which the oxide film 104 is disposed in the preheating chamber of the sputtering apparatus, so as to remove impurities such as hydrogen and moisture adsorbed on the substrate 102 and the oxide film 104 and to exhaust the gas. However, it is preferable to set the preheating temperature to a temperature at which no oxygen is released or only a small amount of oxygen is released from the oxide film 104. In addition, it is preferable to form the first oxide semiconductor film 106 and the second oxide semiconductor film 108 in a film-forming chamber (also called a film-forming processing chamber) where residual moisture is removed, and more preferably, to use a sputtering apparatus with a multi-chamber structure having multiple film-forming chambers and to continuously form the first oxide semiconductor film 106 and the second oxide semiconductor film 108 in a vacuum.

[0095] Furthermore, to remove moisture from the preheating chamber and the film-forming chamber, an adsorption-type vacuum pump, such as a cryogenic pump, an ion pump, or a titanium sublimation pump, is preferably used. Additionally, a turbopump equipped with a cold trap can be used as the exhaust unit. Because compounds containing hydrogen atoms, such as hydrogen atoms and water (H₂O), and even more preferably compounds containing carbon atoms are exhausted from the preheating chamber and the film-forming chamber using a cryogenic pump, the concentration of impurities such as hydrogen and moisture contained in the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be reduced.

[0096] In this embodiment, a metal oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 is used as the first oxide semiconductor film 106, and a metal oxide target with an atomic ratio of In:Ga:Zn = 3:1:2 is used as the second oxide semiconductor film 108. The first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed by sputtering. However, the targets that can be used for the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are not limited to the materials and compositions of these targets. Furthermore, targets with single-crystal or polycrystalline properties are preferably used as targets for the first oxide semiconductor film 106 and the second oxide semiconductor film 108. By using a crystalline target, the formed film also has crystalline properties, and in particular, c-axis oriented crystals are easily formed in the formed film.

[0097] Here, a method for manufacturing a sputtering target composed of an oxide semiconductor with a crystalline region having a c-axis parallel to the normal vector of the upper surface will be described (see reference). Figure 29 ).

[0098] First, weigh the raw materials of the sputtering target (step S101).

[0099] Here, InO is prepared as a raw material for sputtering targets. x Raw materials (including In), GaO Y Raw materials (including Ga) and ZnO Z Raw materials (raw materials containing Zn). Additionally, X, Y, and Z are any positive numbers; for example, X can be set to 1.5, Y to 1.5, and Z to 1. Of course, the above raw materials are just an example; the raw materials can be appropriately selected to obtain the desired compound. For example, MO can also be used. Y Raw material to replace GaO YRaw materials. Here, M can be Sn, Hf, or Al. Alternatively, M can also be a lanthanide element such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Although an example using three raw materials is shown in this embodiment, it is not limited to this. For example, this embodiment can also be applied to cases using four or more raw materials.

[0100] Next, InO x Raw materials, GaO Y Raw materials and ZnO Z The raw materials are mixed in a specified ratio.

[0101] As a specified ratio, for example, InO can be used x Raw materials, GaO Y Raw materials and ZnO Z The molar ratio of the raw materials is set to 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4, or 3:1:2. By using a mixture of materials with this ratio, a sputtering target composed of oxide semiconductors with crystalline regions having a c-axis parallel to the normal vector of the upper surface can be easily formed.

[0102] Specifically, when manufacturing In-Ga-Zn type oxide sputtering targets with an In:Ga:Zn ratio of 1:1:1 [atomic ratio], each raw material is weighed in a manner that satisfies the In2O3:Ga2O3:ZnO ratio of 1:1:2 [molar ratio].

[0103] Additionally, when using MO Y Raw material to replace GaO Y When using raw materials, InO can also be used. X Raw materials, MO Y Raw materials and ZnO Z The molar ratio of the raw materials is set to 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4 or 3:1:2.

[0104] First, a method for manufacturing a sputtering target using a wet process is described. After weighing the raw materials for the sputtering target, the raw materials are pulverized and mixed using a ball mill or the like to produce a compound powder. Then, ion-exchanged water, organic additives, etc., are mixed into the compound powder to produce a slurry (step S111).

[0105] Next, the slurry is spread across a mold lined with a water-permeable filter to remove moisture. This mold can be made of metal or oxide materials with a rectangular or circular top surface. Additionally, the bottom of the mold can have one or more holes. These holes allow for rapid removal of moisture from the slurry. The filter can be made of porous resin, porous cloth, or the like.

[0106] Moisture in the slurry is removed by depressurization and drainage through a hole at the bottom of the mold filled with slurry. The slurry, now dehydrated, is then allowed to dry naturally. Thus, the slurry, with its moisture removed, is shaped to fit the interior of the mold (step S113).

[0107] Next, the shaped body is baked at 1400°C in an oxygen (O2) atmosphere (step S114). Through the above steps, sputtering targets can be obtained by wet process.

[0108] Next, a method for manufacturing a dry sputtering target is described. After weighing the raw material of the sputtering target, the raw material is pulverized and mixed using a ball mill or the like to produce a compound powder. (Step S121)

[0109] Next, the obtained compound powder is spread on the mold and pressurized using a pressurizing device to form the compound powder into a molded body (step S122).

[0110] The resulting molded body is placed in a heating device such as an electric furnace and baked at 1400°C in an oxygen (O2) atmosphere (step S123). In this embodiment, the method of performing the molding and baking processes separately as in steps S122 and S123 is referred to as the cold pressing method. The hot pressing method, in which the molding and baking processes are performed simultaneously, will be described below.

[0111] First, the steps S101 to S121 described above are performed. Next, while the obtained compound powder is spread across a mold and heated to 1000°C under an argon (Ar) atmosphere, the compound powder placed inside the mold is pressurized using a pressurizing device. Thus, by applying pressure while baking the compound powder, the compound powder can be shaped to obtain a shaped body (step S125). Through the above steps, a sputtering target can be obtained using a dry method.

[0112] Furthermore, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be formed by sputtering under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas and oxygen.

[0113] In addition, the temperature at which the first oxide semiconductor film 106 is formed is preferably above room temperature and below 200°C, and the temperature at which the second oxide semiconductor film 108 is formed is preferably above 250°C and below 500°C, more preferably above 300°C and below 400°C.

[0114] As described above, by forming the first oxide semiconductor film 106 at a low temperature (above room temperature and below 200°C) and forming the second oxide semiconductor film 108 at a high temperature (above 250°C and below 500°C), oxygen released from the oxide film 104 can be suppressed and the crystallinity of the second oxide semiconductor film 108 can be improved.

[0115] Furthermore, immediately after the formation of the first oxide semiconductor film 106 and the second oxide semiconductor film 108, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 preferably contain more oxygen than their stoichiometric composition, i.e., they are in an oxygen supersaturated state. For example, when forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108 using a sputtering method, it is preferable to perform film formation under conditions where the oxygen content of the film-forming gas is high, and it is particularly preferable to perform film formation under an oxygen atmosphere (100% oxygen gas). For example, when In-Ga-Zn oxides (IGZO) are used as the first oxide semiconductor film 106 and the second oxide semiconductor film 108, and film formation is performed under conditions where the oxygen content of the film-forming gas is high (especially under an atmosphere where the oxygen gas is 100%), even if the film formation temperature is set to 300°C or higher, the release of Zn from the film can be suppressed.

[0116] Furthermore, when forming the first oxide semiconductor film 106 using the aforementioned metal oxide target, the composition of the target sometimes differs from the composition of the film formed on the substrate. For example, when using a metal oxide target with an In:Ga:Zn ratio of 1:1:1 [atomic ratio], the composition of the first oxide semiconductor film 106 may sometimes be In:Ga:Zn = 1:1:0.6 to 0.8 [atomic ratio], depending on the film formation conditions. This is believed to be due to the following reasons: ZnO sublimates during the formation of the first oxide semiconductor film 106 and the second oxide semiconductor film 108, or the sputtering rates of the components of In₂O₃, Ga₂O₃, and ZnO are different.

[0117] Therefore, when forming a thin film with a desired composition, the composition of the metal oxide target needs to be adjusted in advance. For example, if the composition of the first oxide semiconductor film 106 is set to In:Ga:Zn = 1:1:1 [atomic ratio], the composition of the metal oxide target can be set to In:Ga:Zn = 1:1:1.5 [atomic ratio]. In other words, the ZnO content of the metal oxide target can be increased in advance. Note that the target composition is not limited to the above values ​​and can be appropriately adjusted according to the film formation conditions or the composition of the formed thin film. In addition, by increasing the ZnO content of the metal oxide target, the crystallinity of the obtained thin film is improved, which is preferred. Similarly, the composition of the metal oxide target for the second oxide semiconductor film 108 can also be adjusted when forming a thin film with a desired composition, as described above for the first oxide semiconductor film 106.

[0118] Furthermore, the relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, a dense first oxide semiconductor film 106 and a second oxide semiconductor film 108 can be formed.

[0119] Furthermore, the sputtering gas used when forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is preferably a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed.

[0120] Furthermore, the second oxide semiconductor film 108 can be heat-treated after its formation. The temperature for this heat treatment is set to 300°C or higher and 700°C or lower than the strain point of the substrate. This heat treatment removes excess hydrogen (including water and hydroxyl groups) from the second oxide semiconductor film 108. Note that this heat treatment is sometimes described as a dehydration treatment (dehydrogenation treatment) in this specification, etc.

[0121] However, since oxygen may detach from the oxide film 104 during dehydration, the implementer can appropriately set the temperature of the dehydration treatment to a temperature that can remove excess hydrogen (including water and hydroxyl groups) from the second oxide semiconductor film 108 and suppress oxygen detachment from the oxide film 104. Furthermore, while oxygen may detach from the oxide film 104 through dehydrogenation, the formation of the first oxide semiconductor film 106 allows for effective dehydrogenation by suppressing oxygen detachment from the oxide film 104.

[0122] For example, the object to be treated can be placed in an electric furnace using a resistance heating element and heated at 450°C for 1 hour under a nitrogen atmosphere. During this period, the second oxide semiconductor film 108 is not exposed to the atmosphere to avoid the introduction of water or hydrogen.

[0123] Heat treatment equipment is not limited to electric furnaces; devices that utilize heat conduction or thermal radiation from a medium such as a heated gas can also be used to heat the workpiece. For example, GRTA (Gas Rapid Thermal Anneal) devices and LRTA (Lamp Rapid Thermal Anneal) devices, among other RTA (Rapid Thermal Anneal) devices, can be used. An LRTA device heats the workpiece using radiation from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device uses a high-temperature gas for heat treatment. The gas used is a rare gas such as argon or an inert gas such as nitrogen that does not react with the workpiece even during heat treatment.

[0124] For example, GRTA treatment can be used as this heat treatment, which involves immersing the object to be treated in a heated inert gas atmosphere for several minutes, and then removing the object from the inert gas atmosphere. By using GRTA treatment, high-temperature heat treatment can be performed in a short time. Furthermore, this method can be applied even if the temperature conditions exceed the heat resistance temperature of the object being treated. Additionally, the inert gas can be converted into an oxygen-containing gas during the treatment.

[0125] Furthermore, as an inert gas atmosphere, it is preferable to use an atmosphere that is mainly composed of nitrogen or rare gases (helium, neon, argon, etc.) and does not contain water, hydrogen, etc. For example, the purity of the rare gas such as nitrogen, helium, neon, argon, etc. introduced into the heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0126] Furthermore, during the aforementioned dehydration treatment (dehydrogenation treatment), oxygen in the main constituent material of the second oxide semiconductor film 108 may also be lost and reduced. Oxygen defects exist in the oxygen-desorbed portions of the second oxide semiconductor film 108, and these oxygen defects generate donor levels that cause variations in the electrical characteristics of the transistor. Therefore, when performing the dehydration treatment (dehydrogenation treatment), it is preferable to supply oxygen to the second oxide semiconductor film 108. By supplying oxygen to the second oxide semiconductor film 108, the oxygen defects in the second oxide semiconductor film 108 can be filled.

[0127] An example of a method for filling oxygen defects in the second oxide semiconductor film 108 is as follows: After dehydration treatment (dehydrogenation treatment) of the second oxide semiconductor film 108, high-purity oxygen gas, high-purity nitrous oxide gas, or ultra-dry air (air with a moisture content of less than 20 ppm (dew point conversion, -55°C), preferably less than 1 ppm, and more preferably less than 10 ppb, when measured using a dew point meter in CRDS (cavity ring-down laser spectroscopy) mode) is introduced into the same furnace. The oxygen gas or nitrous oxide gas preferably does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen or nitrous oxide gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (that is, the concentration of impurities in the oxygen or nitrous oxide gas is preferably less than 1 ppm, more preferably less than 0.1 ppm).

[0128] Another example of a method for supplying oxygen to the second oxide semiconductor film 108 is as follows: oxygen is supplied to the second oxide semiconductor film 108 by adding oxygen (containing at least any one of oxygen free radicals, oxygen atoms, and oxygen ions). Methods for adding oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment.

[0129] Another example of a method for supplying oxygen to the second oxide semiconductor film 108 is as follows: oxygen is supplied to the second oxide semiconductor film 108 by heating the oxide film 104 or the gate insulating film 110 formed thereafter, causing a portion of the oxygen to escape. In particular, in this embodiment, it is preferable to supply oxygen to the second oxide semiconductor film 108 by allowing the oxygen released from the oxide film 104 to permeate through the first oxide semiconductor film 106.

[0130] As described above, preferably, after forming the second oxide semiconductor film 108, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or water from the second oxide semiconductor film 108 to achieve high purity, so that the oxide semiconductor film contains as few impurities as possible. Furthermore, oxygen, which is simultaneously reduced by the dehydration treatment (dehydrogenation treatment), is added to the second oxide semiconductor film 108, or oxygen is supplied to compensate for oxygen defects in the second oxide semiconductor film 108. Additionally, in this specification, the treatment of supplying oxygen to the second oxide semiconductor film 108 is sometimes referred to as an oxidation treatment, or the treatment that causes the oxygen contained in the second oxide semiconductor film 108 to exceed its stoichiometric composition is sometimes referred to as an over-oxidation treatment.

[0131] Furthermore, although the structure described above involves dehydration (dehydrogenation) and oxidation treatment after the second oxide semiconductor film 108 is processed into islands, the disclosed invention is not limited to this. This treatment can also be performed before the second oxide semiconductor film 108 is processed into islands. Additionally, a heat treatment can be performed after the formation of the subsequently formed interlayer insulating film 116, supplying oxygen from the oxide film 104 or the gate insulating film 110, etc., to the second oxide semiconductor film 108.

[0132] As described above, by performing a dehydration treatment (dehydrogenation treatment) to remove hydrogen or water from the second oxide semiconductor film 108, and by performing an oxidation treatment to replenish the oxygen defects in the second oxide semiconductor film 108, an intrinsic type I oxide semiconductor film or an oxide semiconductor film that is infinitely close to type I can be obtained. In the above-mentioned oxide semiconductor film, the number of carriers originating from donors is extremely small (nearly 0), and the carrier concentration is less than 1×10⁻⁶. 14 / cm 3 Preferred size is below 1×10 12 / cm 3 More preferably, less than 1'10 11 / cm 3 .

[0133] Furthermore, the second oxide semiconductor film 108 is preferably a highly purified film that contains virtually no impurities such as copper, aluminum, or chlorine. In the transistor manufacturing process, it is preferable to appropriately select processes that do not raise concerns about these impurities contaminating or adhering to the surface of the second oxide semiconductor film 108. Additionally, when these impurities adhere to the surface of the second oxide semiconductor film 108, it is preferable to remove the impurities by exposure to oxalic acid or dilute hydrofluoric acid, or by plasma treatment (e.g., N₂O plasma treatment). Specifically, the copper concentration of the second oxide semiconductor film 108 is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 1×10 17 atoms / cm 3 Below. Furthermore, the aluminum concentration of the second oxide semiconductor film 108 is 1×10⁻⁶. 18 atoms / cm 3 Below. Additionally, the chlorine concentration of the second oxide semiconductor film 108 is 2 × 10⁻⁶. 18 atoms / cm 3 the following.

[0134] Furthermore, the second oxide semiconductor film 108 preferably achieves high purity by sufficiently removing impurities such as hydrogen or by supplying sufficient oxygen to achieve an oxygen supersaturated state. Specifically, the hydrogen concentration of the second oxide semiconductor film 108 is 5×10⁻⁶. 19atoms / cm 3 The following is preferred: 5×10 18 atoms / cm 3 Hereinafter, 5×10 is preferred. 17 atoms / cm 3 The hydrogen concentration in the second oxide semiconductor film 108 is measured using secondary ion mass spectrometry (SIMS). Furthermore, it is preferable to provide an insulating film (SiO2) containing excess oxygen in contact with the second oxide semiconductor film 108, in a manner that surrounds it. x (etc.) to supply sufficient oxygen so that the second oxide semiconductor film 108 becomes oxygen supersaturated.

[0135] As an insulating film containing excess oxygen, SiO₂ is formed by appropriately setting the film formation conditions of PE-CVD or sputtering methods to contain a large amount of oxygen. X The insulating film may be a silicon oxynitride film. Furthermore, when it is necessary to contain a large amount of excess oxygen in the insulating film, oxygen is added to the insulating film by ion implantation, ion doping, or plasma treatment.

[0136] Additionally, because the hydrogen concentration in the insulating film containing excess oxygen is 7.2 × 10⁻⁶. 20 atoms / cm 3 At the above levels, the non-uniformity of the initial characteristics of the transistor increases, the L-length dependence of the transistor's electrical characteristics increases, and the electrical characteristics of the transistor deteriorate significantly during BT stress testing. Therefore, the hydrogen concentration of the insulating film containing excess oxygen is below 7.2 × 10⁻⁶. 20 atoms / cm 3 In other words, the hydrogen concentration of the second oxide semiconductor film 108 is preferably 5 × 10⁸. 19 atoms / cm 3 The hydrogen concentration of the insulating film containing excess oxygen is preferably below 7.2 × 10⁻⁶. 20 atoms / cm 3 .

[0137] Furthermore, it is preferable to provide a barrier film (e.g., AlO) that suppresses the release of oxygen from the second oxide semiconductor film 108 by surrounding the second oxide semiconductor film 108 and being disposed on the outside of the insulating film containing excess oxygen. x ).

[0138] By surrounding the second oxide semiconductor film 108 with an insulating or barrier film containing excess oxygen, the second oxide semiconductor film 108 can be made into a state that is substantially consistent with the stoichiometric composition or a supersaturated state in which oxygen is more abundant than the stoichiometric composition.

[0139] Next, a gate insulating film 110 and a conductive film 111 are formed on the first oxide semiconductor film 106 and the second oxide semiconductor film 108 (see reference). Figure 2B ).

[0140] Next, a photoresist mask is formed on the conductive film 111 using a photolithography process, and the gate electrode 112 is selectively etched. Then, the photoresist mask is removed (see reference). Figure 2C ).

[0141] Alternatively, a resist mask for forming the gate electrode 112 can be formed using inkjet printing. When forming the resist mask using inkjet printing, a photomask is not required, thereby reducing manufacturing costs. Furthermore, the etching of the gate electrode 112 can be performed using either dry etching or wet etching, or both.

[0142] Next, a resist mask 132 is formed on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 2D ).

[0143] Next, a photolithography process is used to selectively expose and develop the resist mask 132 to form the resist mask 132a. Then, using the gate electrode 112 and the resist mask 132a as masks, the dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108. By introducing the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to the region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to the region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see reference). Figure 3A ).

[0144] Dopant 142 is an impurity that alters the conductivity of the first oxide semiconductor film 106 and the second oxide semiconductor film 108. Dopant 142 can be any one or more elements selected from Group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).

[0145] Alternatively, the dopant 142 can be introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 by implantation through another film (e.g., the gate insulating film 110). Methods for introducing the dopant 142 include ion implantation, ion doping, and plasma immersion ion implantation. In this case, elemental ions or ions of fluorides or chlorides of the dopant 142 are preferred.

[0146] The dopant 142 introduction process can be controlled by appropriately setting the implantation conditions such as accelerating voltage and dosage, or by adjusting the thickness of the film through which the dopant 142 penetrates. In this embodiment, phosphorus is used as the dopant 142 for phosphorus ion introduction via ion implantation. Alternatively, the dosage of the dopant 142 can be set to 1×10⁻⁶. 13 ions / cm 2 Above and 5×10 16 ions / cm 2 the following.

[0147] The concentration of dopant 142 in the low-resistivity region 108b is preferably 5 × 10⁻⁶. 18 / cm 3 Above and 1×10 22 / cm 3 the following.

[0148] Alternatively, dopant 142 can be introduced while heating substrate 102.

[0149] Furthermore, the process of introducing dopant 142 into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be performed multiple times, and a variety of dopants can be used.

[0150] Alternatively, heat treatment can be performed after the introduction of dopant 142. Preferred heating conditions include a temperature of 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower; an oxygen atmosphere; and a duration of 1 hour. Alternatively, heat treatment can be performed under a nitrogen atmosphere, under reduced pressure, or in atmospheric (ultra-dry air) conditions.

[0151] Furthermore, when the second oxide semiconductor film 108 is a crystalline oxide semiconductor film or a CAAC-OS film, sometimes a portion of it becomes amorphous due to the introduction of dopant 142. In this case, the crystallinity of the second oxide semiconductor film 108 can be restored by performing a heat treatment after introducing dopant 142.

[0152] Next, the resist mask 132a is removed to form a protective insulating film 114 and an interlayer insulating film 116 on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 3B ).

[0153] Next, a photoresist mask is formed on the interlayer insulating film 116 using a photolithography process. The gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form an opening reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b formed in the second oxide semiconductor film 108). Then, the photoresist mask is removed (see reference). Figure 3C ).

[0154] Next, a conductive film is formed in the opening, and a photoresist mask is formed on the conductive film using a photolithography process. Then, selective etching is performed to form the source electrode 118a and the drain electrode 118b (see reference). Figure 3D ).

[0155] In addition, in this embodiment, such as Figure 3D As shown, in the cross-section along the channel length, the distance between the gate electrode 112 and the opening forming the active electrode 118a is not equal to the distance between the gate electrode 112 and the opening forming the drain electrode 118b. By adopting the above structure, the cutoff current can be suppressed.

[0156] Through the above processes, it is possible to manufacture Figures 1A to 1C The semiconductor device shown.

[0157] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, the generation of oxygen defects in the second oxide semiconductor film is suppressed, thereby providing a transistor with stable electrical characteristics.

[0158] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0159] Implementation Method 2 In this embodiment, refer to Figures 4A to 4C , Figures 5A to 5D as well as Figures 6A to 6C A modified example of the semiconductor device shown in Embodiment 1 and a manufacturing method different from that of the semiconductor device shown in Embodiment 1 will be described. Furthermore, using... Figures 1A to 1C , Figures 2A to 2D as well as Figures 3A to 3D The same symbols are shown, and their repeated descriptions are omitted. Furthermore, detailed descriptions of identical parts are also omitted.

[0160] <Structure Example 2 of a Semiconductor Device> Figures 4A to 4C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. Figure 4A It's a floor plan. Figure 4B Equivalent to along Figure 4A Cross-sectional view of X2-Y2 in the figure. Figure 4CEquivalent to along Figure 4A The cross-sectional view of V2-W2 in the diagram. Note that in... Figure 4A In order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0161] Figures 4A to 4C The semiconductor device shown includes: an oxide film 104; a first oxide semiconductor film 106 formed on the oxide film 104; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0162] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0163] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. By increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0164] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0165] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0166] In other words, the first oxide semiconductor film 106 suppresses the release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0167] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0168] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0169] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0170] Additionally, it may include: a protective insulating film 114 formed on the gate electrode 112; an interlayer insulating film 116 formed on the protective insulating film 114; a source electrode 118a and a drain electrode 118b filled in the first opening 151a and the second opening 151b of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 and electrically connected to the second oxide semiconductor film 108; a wiring 119a electrically connected to the source electrode 118a; and a wiring 119b electrically connected to the drain electrode 118b. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0171] The semiconductor device shown in this embodiment differs from the semiconductor device shown in Embodiment 1 in that the semiconductor device shown in this embodiment includes: a source electrode 118a filled in a first opening 151a of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116; a drain electrode 118b filled in a second opening 151b of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b.

[0172] Furthermore, as shown in the semiconductor device manufacturing method below, the semiconductor device of this embodiment forms the openings (first opening 151a and second opening 151b) for filling the source electrode 118a and drain electrode 118b in two stages. Additionally, the source electrode 118a and drain electrode 118b are formed by dividing the conductive film 118 through CMP processing. Therefore, when forming the source electrode 118a and drain electrode 118b, a photolithography process is not required, allowing the source electrode 118a and drain electrode 118b to be formed without being affected by the accuracy of the exposure machine or misalignment of the photomask. Thus, the semiconductor device of this embodiment has a structure suitable for miniaturization. Furthermore, by adopting the above structure, for example, the distance between the source-side contact region or drain-side contact region and the gate electrode 112 can be reduced to 0.05 μm or more and 0.1 μm or less. Therefore, since the resistance between the source and drain can be reduced, the electrical characteristics of the semiconductor device (e.g., the on-current characteristics of the transistor) can be improved.

[0173] Note that the details of the constituent elements that can be used in the semiconductor device shown in this embodiment are the same as those in the structure shown in Embodiment 1, and therefore their description is omitted. Structures not used in Embodiment 1 are described below.

[0174] [Detailed Wiring Instructions] For example, wiring 119a and wiring 119b can be made of metal films containing elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the aforementioned elements. Alternatively, a structure can be adopted in which high-melting-point metal films such as titanium, molybdenum, and tungsten, or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film), are laminated on one or both sides of the aluminum, copper, or other metal film. Furthermore, conductive metal oxides can be used to form conductive films for wiring 119a and wiring 119b. Indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium tin oxide (In₂O₃-SnO₂, abbreviated as ITO), and indium zinc oxide (In₂O₃-ZnO) can be used. The conductive films for wiring 119a and wiring 119b can be formed in single layers or in stacks using the aforementioned materials. There are no particular restrictions on the formation method; various film formation methods such as vapor deposition, PE-CVD, sputtering, or spin coating can be used.

[0175] Furthermore, in the semiconductor device manufacturing method 2 described later, refer to Figure 5A As for 5D and Figures 6A to 6C Provide a detailed explanation of the other constituent elements.

[0176] <Semiconductor Device Manufacturing Method 2> Below, refer to Figures 5A to 5D as well as Figures 6A to 6C For this embodiment Figures 4A to 4C An example of a method for manufacturing a semiconductor device is illustrated.

[0177] First, it can be manufactured by referring to the manufacturing method shown in Embodiment 1. Figure 5A The semiconductor device is shown in the indicated state. Note that... Figure 5A The cross-sectional view shown is the same as Figure 3B The cross-sectional views shown are the same.

[0178] Next, a photoresist mask is formed on the interlayer insulating film 116 using a photolithography process. The gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form a first opening 151a reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b). Then, the photoresist mask is removed (see reference). Figure 5B ).

[0179] Furthermore, for the exposure process described above in the photolithography step, extremely ultraviolet (EUV) light with a short wavelength, i.e., a few nm to tens of nm, is preferred. Exposure using UV light offers high resolution and a large depth of focus, thus enabling the formation of fine patterns. Additionally, as long as a sufficiently fine pattern can be formed, other methods such as inkjet printing can be used to form the resist mask. In this case, the material used as the resist mask does not need to be photosensitive.

[0180] Next, a photoresist mask is formed on the first opening 151a and the interlayer insulating film 116. The gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form the second opening 151b reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b). Then, the photoresist mask is removed (see reference). Figure 5C Thus, a pair of openings are formed by sandwiching the gate electrode 112 between the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116.

[0181] Next, a conductive film 118 is formed on the interlayer insulating film 116 in such a way that the first opening 151a and the second opening 151b are filled (see reference). Figure 5D ).

[0182] Next, the source electrode 118a and drain electrode 118b filling the first opening 151a and the second opening 151b are formed by performing CMP (Chemical Mechanical Polishing) on ​​the conductive film 118 in such a way as to remove the conductive film 118 disposed on the interlayer insulating film 116 (at least the area overlapping with the gate electrode 112). (Refer to...) Figure 6A ).

[0183] In this embodiment, the source electrode 118a and the drain electrode 118b are formed by performing CMP treatment on the conductive film 118 while exposing the surface of the interlayer insulating film 116. Additionally, depending on the CMP treatment conditions, the surface of the protective insulating film 114 may also be polished.

[0184] Here, CMP treatment refers to a method of planarizing the surface of a workpiece through a combination of chemical and mechanical processes. More specifically, CMP treatment is a method in which a polishing cloth is attached to a polishing table, and a slurry (polishing agent) is supplied between the workpiece and the polishing cloth while the polishing table and the workpiece are rotated or shaken separately. The surface of the workpiece is polished by the chemical reaction between the slurry and the workpiece surface, as well as the mechanical polishing action of the polishing cloth and the workpiece.

[0185] Furthermore, CMP treatment can be performed either once or multiple times. When performing CMP treatment in multiple stages, it is preferable to perform a high-polish initial polishing followed by a low-polish fine polishing. By combining polishing processes with different polishing rates, the surface flatness of the source electrode 118a, drain electrode 118b, and interlayer insulating film 116 can be further improved.

[0186] In this embodiment, the conductive film 118 is removed using CMP treatment, but other polishing (grinding, cutting) treatments can also be used. Alternatively, polishing treatments such as CMP treatment can be combined with etching (dry etching, wet etching) treatments or plasma treatments. For example, dry etching or plasma treatment (back sputtering, etc.) can be performed after CMP treatment to improve the flatness of the treated surface. When polishing treatment is combined with etching treatment, plasma treatment, etc., there are no particular restrictions on the order of the processes, and they can be appropriately set according to the material, thickness, and surface unevenness of the conductive film 118.

[0187] As described above, the source electrode 118a and drain electrode 118b are disposed to fill the openings (first opening 151a and second opening 151b) provided in the interlayer insulating film 116, the protective insulating film 114, and the gate insulating film 110. Therefore, the distance between the region of the source electrode 118a that contacts the second oxide semiconductor film 108 (source-side contact region) and the gate electrode 112 is determined based on the width between the end of the first opening 151a and the gate electrode 112. Figure 6A L in SG Similarly, the distance between the area of ​​the drain electrode 118b that contacts the second oxide semiconductor film 108 (drain-side contact area) and the gate electrode 112 is determined based on the width between the end of the second opening 151b and the gate electrode 112. Figure 6A L in DG ).

[0188] When a first opening 151a for setting the source electrode 118a and a second opening 151b for setting the drain electrode 118b are formed in a single process, the minimum processing dimension of the width of the channel in the length direction between the first opening 151a and the second opening 151b is limited by the resolution limit of the exposure apparatus used to form the mask. Therefore, it is not easy to sufficiently reduce the distance between the first opening 151a and the second opening 151b, and consequently, it is also not easy to reduce the distance (L) between the source-side contact area and the drain contact area and the gate electrode 112. SG and L DG ).

[0189] However, in the manufacturing method shown in this embodiment, since two masks are used to form the first opening 151a and the second opening 151b, the positions of the openings can be freely set without relying on the resolution limit of the exposure apparatus. Therefore, for example, the distance (L) between the source-side contact area or the drain-side contact area and the gate electrode 112 can be adjusted. SG or L DG Shrink to above 0.05 μm and below 0.1 μm. By shrinking L SG and L DG This can reduce the resistance between the source and drain, thereby improving the electrical characteristics of the semiconductor device (e.g., the on-current characteristics of the transistor).

[0190] Furthermore, since etching with a resist mask is not used in the process of removing the conductive film 118 on the interlayer insulating film 116 to form the source electrode 118a and drain electrode 118b, precise processing can be performed accurately when miniaturizing the width of the channel in the length direction of the source electrode 118a and drain electrode 118b. Therefore, in the semiconductor device manufacturing process, miniature structures with minimal deviations in shape and characteristics can be manufactured with high yield.

[0191] Next, a conductive film 119 is formed on the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b (see reference). Figure 6B ).

[0192] Next, a photoresist mask is formed on the conductive film 119 using a photolithography process to form wiring 119a electrically connected to the source electrode 118a and wiring 119b electrically connected to the drain electrode 118b (see reference). Figure 6C ).

[0193] Through the above processes, it is possible to manufacture Figures 4A to 4C The semiconductor device shown.

[0194] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0195] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0196] Implementation Method 3 In this embodiment, refer to Figures 7A to 7C , Figures 8A to 8D , Figure 9A To Figure 9 C, Figures 10A to 10C , Figures 11A to 11D as well as Figures 12A to 12C Modified examples of the semiconductor devices shown in Embodiments 1 and 2, and manufacturing methods different from those used in Embodiments 1 and 2, will be described. Furthermore, using... Figures 1A to 1C , Figures 2A to 2D , Figures 3A to 3D , Figures 4A to 4C , Figures 5A to 5D as well as Figures 6A to 6C The symbols shown are the same as those shown, and their repeated descriptions are omitted.

[0197] <Structure Example 3 of a Semiconductor Device> Figures 7A to 7C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. Figure 7A It's a floor plan. Figure 7B Equivalent to along Figure 7A Cross-sectional view of X3-Y3 in the figure. Figure 7C Equivalent to along Figure 7A The cross-sectional view of V3-W3 in the diagram. Note that in... Figure 7A In order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0198] Figures 7A to 7C The semiconductor device shown includes: an oxide film 104; a first oxide semiconductor film 106 formed on the oxide film 104; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0199] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0200] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. By increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0201] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0202] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0203] In other words, the first oxide semiconductor film 106 suppresses the release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0204] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0205] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0206] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0207] Additionally, it may include: an insulating film 113 formed in the region overlapping with the gate electrode 112; a sidewall insulating film 115 formed on the sides of the gate electrode 112 and the insulating film 113 in a cross-section along the channel length direction; a source electrode 118a and a drain electrode 118b that contact the sidewall insulating film 115 and are electrically connected to the second oxide semiconductor film 108; a protective insulating film 114 and an interlayer insulating film 116 formed at least on the source electrode 118a and the drain electrode 118b; an insulating film 120 formed on the interlayer insulating film 116; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b through openings provided in the insulating film 120, the interlayer insulating film 116, and the protective insulating film 114. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0208] The structure of the semiconductor device shown in this embodiment differs from that of the semiconductor device shown in Embodiment 1 in that the structure of the semiconductor device shown in this embodiment includes an insulating film 113 on the gate electrode 112, a sidewall insulating film 115 disposed on the side of the gate electrode 112, a source electrode 118a and a drain electrode 118b formed in contact with the sidewall insulating film 115, and an insulating film 120.

[0209] Furthermore, in the semiconductor device shown in this embodiment, the source electrode 118a and the drain electrode 118b are formed by removing a portion of the conductive film after a planarization process (also called a polishing process) is performed on the insulating film 113 and the sidewall insulating film 115 to remove the conductive film. Therefore, a photolithography process is not required when forming the source electrode 118a and the drain electrode 118b, and the source electrode 118a and the drain electrode 118b can be formed without being affected by the accuracy of the exposure machine or the misalignment of the photomask. Thus, the semiconductor device shown in this embodiment has a structure suitable for miniaturization.

[0210] Note that the details of the constituent elements that can be used in the semiconductor device shown in this embodiment are the same as those in Embodiments 1 and 2, and therefore their descriptions are omitted. Structures not used in Embodiments 1 and 2 are described below.

[0211] [Detailed Description of Insulating Film and Sidewall Insulating Film] Inorganic insulating films are preferably used for insulating film 113, sidewall insulating film 115, and insulating film 120. Single layers or stacks of silicon oxide film, silicon oxynitride film, silicon nitride film, and silicon oxynitride film can be used. In addition, there are no particular restrictions on the manufacturing method of insulating film 113, sidewall insulating film 115, and insulating film 120. For example, sputtering, MBE, PE-CVD, pulsed laser deposition, ALD, etc. can be appropriately used.

[0212] Furthermore, in the semiconductor device manufacturing method 3 described later, refer to Figures 8A to 8D , Figure 9A To Figure 9 C, Figures 10A to 10C , Figures 11A to 11D as well as Figures 12A to 12C Provide a detailed explanation of the other constituent elements.

[0213] <Semiconductor Device Manufacturing Method 3> Below, refer to Figures 8A to 8D , Figure 9A To Figure 9 C, Figures 10A to 10C , Figures 11A to 11D as well as Figures 12A to 12C For this embodiment Figures 7A to 7C An example of a method for manufacturing a semiconductor device is illustrated.

[0214] First, it can be manufactured by referring to the manufacturing method shown in Embodiment 1. Figure 8A The semiconductor device is shown in the indicated state. Note that... Figure 8A The cross section shown is Figure 2B The cross-sections shown are the same.

[0215] Next, an insulating film 113a is formed on the conductive film 111 (see reference). Figure 8B ).

[0216] Next, a photoresist mask is formed on the insulating film 113a using a photolithography process, and the insulating film 113a and the conductive film 111 are selectively etched to form the insulating film 113 and the gate electrode 112 (see reference). Figure 8C ).

[0217] Next, a resist mask 134 is formed on the gate insulating film 110 and the insulating film 113 (see reference). Figure 8D ).

[0218] Next, a photolithography process is used to selectively expose and develop the resist mask 134 to form resist mask 134a or resist mask 134b. Then, using the gate electrode 112, insulating film 113, and resist mask (resist mask 134a or resist mask 134b) as a mask, dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108. By introducing dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to the region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to the region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see reference). Figure 9B and Figure 10B ).

[0219] Note that in this embodiment, in order to clearly indicate the positions of the low-resistance regions 106b and 108b formed by introducing dopant 142, in Figure 9A To Figure 9C and Figures 10A to 10C Cross-sectional and plan views are used for illustration.

[0220] Figure 9A It's a floor plan. Figure 9B Equivalent to along Figure 9A Cross-sectional view of X3-Y3 in the figure. Figure 9C Equivalent to along Figure 9A The cross-sectional view of V3-W3 in the diagram. Note that in... Figure 9A In order to avoid complexity, some components of the semiconductor device (e.g., gate insulating film 110, etc.) are omitted. Additionally, Figure 10A It's a floor plan. Figure 10B Equivalent to along Figure 10A Cross-sectional view of X3-Y3 in the figure. Figure 10C Equivalent to along Figure 10A The cross-sectional view of V3-W3 in the diagram. Note that in... Figure 10AIn order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0221] Additionally, refer to Figure 9A To Figure 9C and Figure 10A Figure 10C Two manufacturing methods are described for the locations where low-resistance regions 106b and 108b are formed. Note that... Figures 9A to 9C The method shown and Figures 10A to 10C The methods shown are all embodiments of the present invention.

[0222] The following explanation Figures 9A to 9C The manufacturing method shown is the same as Figures 10A to 10C The differences in manufacturing methods are shown.

[0223] exist Figures 9A to 9C In the manufacturing method shown, the resist mask 134a is formed on the outer side of the second oxide semiconductor film 108 (see reference). Figures 9A to 9C ).

[0224] On the other hand, Figures 10A to 10C In the manufacturing method shown, the resist mask 134b is also formed between the long sides of the second oxide semiconductor film 108 (see reference). Figures 10A to 10C ).

[0225] exist Figures 9A to 9C In the manufacturing method shown, since the entire region outside the channel region 108a becomes the low-resistance region 108b, the contact area of ​​the subsequently formed source electrode 118a and drain electrode 118b can be expanded. On the other hand, in Figures 10A to 10C In the manufacturing method shown, by making the long side direction of the second oxide semiconductor film 108 have a resistance that is higher than that of the low resistance region 108b, the formation of parasitic channels (also called parasitic transistors) that may form in the long side direction of the second oxide semiconductor film 108 can be suppressed.

[0226] As described above, semiconductor devices with different effects can be manufactured by changing the shapes of resist mask 134a and resist mask 134b.

[0227] Next, the resist mask (resist mask 134a or resist mask 134b) is removed to form an insulating film 115a on the gate insulating film 110 and the insulating film 113 (see reference). Figure 11A ).

[0228] Next, the sidewall insulating film 115 is formed by etching the insulating film 115a. By performing a highly anisotropic etching process on the insulating film 115a, the sidewall insulating film 115 can be formed in a self-aligned manner. For example, dry etching is preferably used as the etching method. Furthermore, fluorine-containing gases such as trifluoromethane, octafluorocyclobutane, and tetrafluoromethane can be used as etching gases for dry etching. Rare gases or hydrogen can also be added to the etching gas. The dry etching method preferably uses reactive ion etching (RIE) where a high-frequency voltage is applied to the substrate. After forming the sidewall insulating film 115, the gate insulating film 110 is processed using the gate electrode 112, the insulating film 113, and the sidewall insulating film 115 as a mask, exposing the first oxide semiconductor film 106 and the second oxide semiconductor film 108 (see reference). Figure 11B Alternatively, the gate insulating film 110 can be processed when the sidewall insulating film 115 is formed.

[0229] In this embodiment, immediately after forming the gate electrode 112 and the insulating film 113, the dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 using the gate electrode 112, the insulating film 113, and a resist mask (resist mask 134a or resist mask 134b) as a mask. However, the dopant 142 can also be introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 using the gate electrode 112, the insulating film 113, the sidewall insulating film 115, and the resist mask after forming the sidewall insulating film 115. By employing the above steps, the regions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 overlapping with the sidewall insulating film 115 can be included in the high-resistance region.

[0230] Next, a conductive film is formed by covering the first oxide semiconductor film 106, the second oxide semiconductor film 108, the insulating film 113, and the sidewall insulating film 115, and then a photolithography and etching process is performed on the conductive film to form a conductive film 118 (see reference). Figure 11C ).

[0231] Next, insulating films 114a and 116a are formed on the first oxide semiconductor film 106 and the conductive film 118 (see reference). Figure 11D ).

[0232] Next, CMP processing is performed on insulating films 114a, 116a, and 118 to remove conductive film 118 disposed on insulating film 113 (at least the area overlapping with gate electrode 112), thereby dividing insulating films 114a, 116a, and 118, thereby forming protective insulating film 114, interlayer insulating film 116, source electrode 118a, and drain electrode 118b while gate electrode 112 is sandwiched (see reference). Figure 12A ).

[0233] In addition, Figure 12A Although the surfaces of the source electrode 118a and drain electrode 118b are on the same plane as the surfaces of the insulating film 113 and the interlayer insulating film 116, when polishing the surfaces of the source electrode 118a and drain electrode 118b, the insulating film 113, and the interlayer insulating film 116 using a CMP apparatus, sometimes the surfaces of the source electrode 118a and drain electrode 118b are at different heights from the surfaces of the insulating film 113 or the interlayer insulating film 116, resulting in steps. For example, sometimes the surfaces of the source electrode 118a and drain electrode 118b are lower than the surface of the insulating film 113 (becoming concave). Additionally, depending on the CMP processing conditions, the sidewall insulating film 115 may also be polished.

[0234] Note that the CMP treatment here can refer to the CMP treatment of the conductive film 118 described in Embodiment 2.

[0235] Next, an insulating film 120 is formed on the protective insulating film 114, the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b (see reference). Figure 12B ).

[0236] Next, a photoresist mask is formed on the insulating film 120 using a photolithography process. The protective insulating film 114, the interlayer insulating film 116, and the insulating film 120 are selectively etched to form openings reaching the source electrode 118a and the drain electrode 118b. The photoresist mask is then removed. A conductive film is then formed covering these openings. A photoresist mask is formed on this conductive film using a photolithography process. The conductive film is then selectively etched to form wirings 119a and 119b (see reference). Figure 12C ).

[0237] Through the above processes, it is possible to manufacture Figures 7A to 7C The semiconductor device shown.

[0238] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0239] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0240] Implementation Method 4 In this embodiment, refer to Figures 13A to 13C , Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D as well as Figures 17A to 17B Modified examples of the semiconductor devices shown in Embodiments 1 to 3, and manufacturing methods different from those used in Embodiments 1 to 3, will be described. Furthermore, methods using... Figures 1A to 1C , Figures 2A to 2D , Figures 3A to 3D , Figures 4A to 4C , Figures 5A to 5D , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8D , Figure 9A To Figure 9 C, Figures 10A to 10C , Figures 11A to 11D as well as Figures 12A to 12C The symbols shown are the same as those shown, and their repeated descriptions are omitted.

[0241] <Structure Example 4 of a Semiconductor Device> Figures 13A to 13C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. Figure 13A It's a floor plan. Figure 13B Equivalent to along Figure 13A Cross-sectional view of X4-Y4 in the figure. Figure 13C Equivalent to along Figure 13A The cross-sectional view of V4-W4 in the diagram. Note that in... Figure 13A In order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0242] Figures 13A to 13CThe semiconductor device shown includes: an oxide film 104; a first oxide semiconductor film 106 formed on the oxide film 104; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0243] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0244] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. By increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0245] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0246] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0247] In other words, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0248] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0249] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0250] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0251] Additionally, it may include: a source electrode 118a in contact with one side of the second oxide semiconductor film 108 in a cross-section along the length of the channel; a drain electrode 118b in contact with the other side of the second oxide semiconductor film 108; a first conductive film 121a formed on one side of the gate electrode 112; a second conductive film 121b formed on the other side of the gate electrode 112; a sidewall insulating film 115 formed on the sides of the first conductive film 121a and the second conductive film 121b; a protective insulating film 114 formed on the first oxide semiconductor film 106, the source electrode 118a, the drain electrode 118b, the sidewall insulating film 115, and the gate electrode 112; an interlayer insulating film 116 formed on the protective insulating film 114; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b, respectively. In addition, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0252] The structure of the semiconductor device shown in this embodiment differs from that of the semiconductor device shown in Embodiment 1 in that: in the structure of the semiconductor device shown in this embodiment, a first conductive film 121a, a second conductive film 121b, and a sidewall insulating film 115 are formed on both sides of the gate electrode 112; and a source electrode 118a that contacts one side of the second oxide semiconductor film 108 and a drain electrode 118b that contacts the other side are formed on the cross-section of the second oxide semiconductor film 108 in the channel length direction.

[0253] Furthermore, in the semiconductor device shown in this embodiment, at least a portion of the first conductive film 121a formed on one side of the gate electrode 112 is formed on the source electrode 118a through the gate insulating film 110, and at least a portion of the second conductive film 121b formed on the other side of the gate electrode 112 is formed on the drain electrode 118b through the gate insulating film 110. Thus, a portion of the gate electrode 112 (specifically, the gate electrode 112, the first conductive film 121a, and the second conductive film 121b) can be provided to overlap with the source electrode 118a and the drain electrode 118b through the gate insulating film 110 (also called the Lov region). Therefore, the semiconductor device shown in this embodiment has a structure suitable for miniaturization, and also has a structure suitable for suppressing the decrease in conduction current that occurs with miniaturization.

[0254] Note that the details of each component that can be used in the semiconductor device shown in this embodiment are the same as those in the structures shown in Embodiments 1 to 3, and therefore their descriptions are omitted. Structures not used in Embodiments 1 to 3 are described below.

[0255] [Detailed Description of the First and Second Conductive Films] The first conductive film 121a and the second conductive film 121b only need to be conductive. For example, they can be formed by processing metal films such as tungsten and titanium, or silicon films containing impurity elements such as phosphorus and boron. Alternatively, a polycrystalline silicon film can be formed on the gate electrode 112, etched to form a conductive film in contact with the gate electrode 112, doped to introduce impurity elements such as phosphorus and boron, and then heat-treated to form the conductive first conductive film 121a and the second conductive film 121b.

[0256] Furthermore, in the semiconductor device manufacturing method 4 described later, refer to Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D as well as Figures 17A to 17B Provide a detailed explanation of the other constituent elements.

[0257] <Semiconductor Device Manufacturing Method 4> Below, refer to Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D as well as Figures 17A to 17B For this embodiment Figures 13A to 13C An example of a method for manufacturing a semiconductor device is illustrated.

[0258] First, it can be manufactured by referring to the manufacturing method shown in Embodiment 1. Figure 14A The semiconductor device is shown in the indicated state. Note that... Figure 14A The cross section shown is Figure 2B The modified example of the semiconductor device shown differs from the other in that the area of ​​the second oxide semiconductor film 108 is different.

[0259] Next, conductive films are formed on the first oxide semiconductor film 106 and the second oxide semiconductor film 108. A photoresist mask is formed on the conductive films using a photolithography process, and the conductive films are selectively etched to form the conductive film 118 (see reference). Figure 14B ).

[0260] Next, the conductive film 118 is subjected to CMP treatment to remove a portion of the conductive film 118, thereby exposing the second oxide semiconductor film 108. This CMP treatment removes the conductive film 118 in the region overlapping with the second oxide semiconductor film 108, thereby forming the source electrode 118a and the drain electrode 118b (see reference). Figure 14C ).

[0261] Note that the CMP treatment here can refer to the CMP treatment of the conductive film 118 described in Embodiment 2.

[0262] Next, a gate insulating film 110 and a conductive film 111 are formed on the first oxide semiconductor film 106, the second oxide semiconductor film 108, the source electrode 118a, and the drain electrode 118b (see reference). Figure 14D ).

[0263] Next, a photoresist mask is formed on the conductive film 111 using a photolithography process, and the conductive film 111 is selectively etched to form the gate electrode 112 (see reference). Figure 15A ).

[0264] Next, a resist mask 136 is formed on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 15B ).

[0265] Next, the photolithography process is used to selectively expose and develop the resist mask 136 to form the resist mask 136a. Then, using the gate electrode 112 and the resist mask 136a as masks, the dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108. By introducing the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to the region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to the region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see reference). Figure 15C ).

[0266] Note that in this embodiment, the structure in which dopant 142 is introduced into the first oxide semiconductor film 106 through the source electrode 118a and the drain electrode 118b to form a low-resistance region 106b is described, but it is not limited to this. The impurity concentration of the first oxide semiconductor film 106 in the region overlapping with the source electrode 118a and the drain electrode 118b may also be the same as that in the high-resistance region 106a.

[0267] Next, the resist mask 136a is removed to form a conductive film 121 on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 15D ).

[0268] Next, an insulating film 115a is formed on the conductive film 121 (see reference). Figure 16A ).

[0269] Next, the sidewall insulating film 115 is formed by etching the insulating film 115a. By performing a highly anisotropic etching process on the insulating film 115a, the sidewall insulating film 115 can be formed in a self-aligned manner. For example, dry etching is preferably used as the etching method. Furthermore, fluorine-containing gases such as trifluoromethane, octafluorocyclobutane, and tetrafluoromethane can be used as etching gases for dry etching. Rare gases or hydrogen can also be added to the etching gas. The dry etching method preferably uses reactive ion etching (RIE) where a high-frequency voltage is applied to the substrate. After forming the sidewall insulating film 115, the conductive film 121 and the gate insulating film 110 are processed using the gate electrode 112 and the sidewall insulating film 115 as masks, exposing the first oxide semiconductor film 106, the source electrode 118a, and the drain electrode 118b (see reference). Figure 16B Alternatively, the conductive film 121 and the gate insulating film 110 can be processed when the sidewall insulating film 115 is formed. In this embodiment, the conductive film 121 is divided into a first conductive film 121a and a second conductive film 121b, a portion of the gate insulating film 110 is removed, and a portion of the surface of the source electrode 118a and the drain electrode 118b is exposed.

[0270] Next, a protective insulating film 114 and an interlayer insulating film 116 are formed in such a manner that they cover the first oxide semiconductor film 106, the gate electrode 112, the sidewall insulating film 115, the first conductive film 121a, the second conductive film 121b, the source electrode 118a, and the drain electrode 118b (see reference). Figure 16C ).

[0271] Next, a photoresist mask is formed on the interlayer insulating film 116 using a photolithography process. The protective insulating film 114 and the interlayer insulating film 116 are selectively etched to form openings reaching the source electrode 118a and the drain electrode 118b. The photoresist mask is then removed (see reference). Figure 16D ).

[0272] Next, a conductive film 119 is formed on the interlayer insulating film 116 in a manner that fills the opening (see reference). Figure 17A ).

[0273] Next, a photoresist mask is formed on the conductive film 119 using a photolithography process, and the conductive film 119 is selectively etched to form wirings 119a and 119b (see reference). Figure 17B ).

[0274] Through the above processes, it is possible to manufacture Figures 13A to 13C The semiconductor device shown.

[0275] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0276] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0277] Implementation Method 5 In this embodiment, refer to Figures 18A to 18C , Figures 19A to 19D , Figures 20A to 20D as well as Figures 21A to 21C Modified examples of the semiconductor devices shown in Embodiments 1 to 4, and manufacturing methods different from those used in Embodiments 1 to 4, will be described. Furthermore, methods using... Figures 1A to 1C , Figures 2A to 2D , Figures 3A to 3D , Figures 4A to 4C , Figures 5A to 5D , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8D , Figure 9A To Figure 9 C, Figures 10A to 10C , Figures 11A to 11D , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D as well as Figures 17A to 17B The symbols shown are the same as those shown, and their repeated descriptions are omitted.

[0278] <Structure Example 5 of a Semiconductor Device> Figures 18A to 18C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. Figure 18A It's a floor plan. Figure 18B Equivalent to along Figure 18A The cross-sectional view of X5-Y5 in the figure. Figure 18C Equivalent to along Figure 18A The cross-sectional view of V5-W5 in the diagram. Note that in... Figure 18A In order to avoid making things complicated, some of the components of a semiconductor device (e.g., gate insulating film 110, etc.) are omitted.

[0279] Figures 18A to 18C The semiconductor device shown includes: an oxide film 104; a first oxide semiconductor film 106 formed on the oxide film 104; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0280] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0281] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. By increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0282] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0283] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0284] In other words, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0285] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0286] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0287] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0288] Additionally, it may include: a protective insulating film 114 formed on the gate electrode 112; an interlayer insulating film 116 formed on the protective insulating film 114; a source electrode 118a and a drain electrode 118b that are in contact with the side of the second oxide semiconductor film 108 in an opening passing through the interlayer insulating film 116, the protective insulating film 114, the gate insulating film 110, and the second oxide semiconductor film 108 in a cross-section along the channel length direction; a wiring 119a electrically connected to the source electrode 118a; and a wiring 119b electrically connected to the drain electrode 118b. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0289] The structure of the semiconductor device shown in this embodiment differs from that of the semiconductor device shown in Embodiment 1 in that: in the structure of the semiconductor device shown in this embodiment, a source electrode 118a and a drain electrode 118b are formed, which are filled in the openings of the gate insulating film 110, the protective insulating film 114, the interlayer insulating film 116 and the second oxide semiconductor film 108, as well as wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b.

[0290] Furthermore, the structure of the semiconductor device shown in this embodiment differs from that of the semiconductor device shown in Embodiment 1 in that the shape of the second oxide semiconductor film 108 and the shape of the gate insulating film 110 and the gate electrode 112 covering the top and side surfaces of the channel region 108a of the second oxide semiconductor film 108 are different.

[0291] Furthermore, in the semiconductor device shown in this embodiment, its channel is formed on the top and side surfaces of the second oxide semiconductor film 108 (specifically, the channel region 108a).

[0292] Thus, in the semiconductor device shown in this embodiment, a thick (so-called plate-like) second oxide semiconductor film 108 is formed, a gate insulating film 110 is formed to cover the top and side surfaces of the second oxide semiconductor film 108, and a gate electrode 112 is formed thereon. Therefore, since the channel width is the sum of the top surface length and the side surface length of the second oxide semiconductor film 108 (specifically, the channel region 108a), the actual channel width can be increased without increasing the width of the top surface of the second oxide semiconductor film 108. By increasing the channel width, the decrease in the transistor's on-current or the non-uniformity of its electrical characteristics can be suppressed.

[0293] Note that the details of each component that can be used in the semiconductor device shown in this embodiment are the same as those in embodiments 1 to 4, and therefore their description is omitted. Structures not used in embodiments 1 to 4 are described below.

[0294] [Detailed Description of Second Oxide Semiconductor Film] The second oxide semiconductor film 108 can have the same structure as that shown in Embodiment 1, but its thickness is different from that of Embodiment 1. The thickness of the second oxide semiconductor film 108 shown in this embodiment is greater than 5 nm and less than 500 nm, preferably more than 100 nm and less than 300 nm.

[0295] Furthermore, in the semiconductor device manufacturing method 5 described later, refer to Figures 19A to 19D , Figures 20A to 20C as well as Figures 21A to 21C Provide a detailed explanation of the other constituent elements.

[0296] <Semiconductor Device Manufacturing Method 5> Below, refer to Figures 19A to 19D , Figures 20A to 20C as well as Figures 21A to 21C For this embodiment Figures 18A to 18C An example of a method for manufacturing a semiconductor device is illustrated.

[0297] First, it can be manufactured by referring to the manufacturing method shown in Embodiment 1. Figure 19A The semiconductor device is shown in the indicated state. Note that... Figure 19A The cross section shown is Figure 2A The modified example of the semiconductor device shown differs from the other in that the thickness of the second oxide semiconductor film 108 is different.

[0298] Next, a gate insulating film 110 and a conductive film 111 are formed on the first oxide semiconductor film 106 and the second oxide semiconductor film 108 (see reference). Figure 19B ).

[0299] Next, a photoresist mask is formed on the conductive film 111 using a photolithography process, and the conductive film 111 is selectively etched to form the gate electrode 112 (see reference). Figure 19C ).

[0300] Next, a resist mask 138 is formed on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 19D ).

[0301] Next, a photolithography process is used to selectively expose and develop the resist mask 138 to form the resist mask 138a. Then, using the gate electrode 112 and the resist mask 138a as masks, a dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108. By introducing the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to the region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to the region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see reference). Figure 20A ).

[0302] Note that in this embodiment, the structure in which dopant 142 is introduced into the first oxide semiconductor film 106 through the second oxide semiconductor film 108 to form a low-resistance region 106b is described, but it is not limited thereto. The impurity concentration of the first oxide semiconductor film 106 in the region overlapping with the second oxide semiconductor film 108 may also be the same as that of the high-resistance region 106a.

[0303] Next, the resist mask 138a is removed to form a protective insulating film 114 and an interlayer insulating film 116 on the gate insulating film 110 and the gate electrode 112 (see reference). Figure 20B ).

[0304] Next, a photoresist mask is formed on the interlayer insulating film 116 using a photolithography process. The interlayer insulating film 116, the protective insulating film 114, and the second oxide semiconductor film 108 are selectively etched to form an opening 153a reaching the first oxide semiconductor film 106. The photoresist mask is then removed (see reference). Figure 20C ).

[0305] Next, a photoresist mask is formed on the opening 153a and the interlayer insulating film 116 using a photolithography process. The interlayer insulating film 116, the protective insulating film 114, and the second oxide semiconductor film 108 are selectively etched to form the opening 153b reaching the first oxide semiconductor film 106. The photoresist mask is then removed (see reference). Figure 20D Thus, a pair of openings are formed between the gate electrode 112 and the channel region 108a.

[0306] Note that in this embodiment, the openings 153a and 153b are formed in a manner that reaches the first oxide semiconductor film 106, but this is not a limitation. For example, the openings 153a and 153b may also be formed in a manner that reaches the oxide film 104.

[0307] Furthermore, in the manufacturing method shown in this embodiment, similar to the manufacturing method shown in Embodiment 2, since two masks are used to form the openings 153a and 153b, the positions of the openings can be freely set without relying on the resolution limit of the exposure apparatus. Therefore, for example, the distance between the source-side contact region or the drain-side contact region and the gate electrode 112 can be reduced to 0.05 μm or more and 0.1 μm or less. By reducing the distance between the source-side contact region or the drain-side contact region and the gate electrode 112, the resistance between the source and drain can be reduced, thereby improving the electrical characteristics of the semiconductor device (e.g., the on-current characteristics of a transistor).

[0308] Next, a conductive film 118 is formed on the interlayer insulating film 116 by filling the openings 153a and 153b (see reference). Figure 21A ).

[0309] Next, by performing CMP treatment on the conductive film 118, which removes the conductive film 118 disposed on the interlayer insulating film 116 (at least the area overlapping with the gate electrode 112), a source electrode 118a and a drain electrode 118b filling the openings 153a and 153b are formed (see reference). Figure 21B ).

[0310] In addition, in this embodiment, the contact area between the source electrode 118a and the drain electrode 118b and the second oxide semiconductor film 108 is the side of the second oxide semiconductor film 108 in the opening through the interlayer insulating film 116, the protective insulating film 114, the gate insulating film 110 and the second oxide semiconductor film 108.

[0311] Next, a conductive film is formed on the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b. A photoresist mask is then formed on the conductive film using a photolithography process, thereby forming wiring 119a electrically connected to the source electrode 118a and wiring 119b electrically connected to the drain electrode 118b (see reference). Figure 21C ).

[0312] Through the above processes, it is possible to manufacture Figures 18A to 18C The semiconductor device shown.

[0313] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0314] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0315] Implementation Method 6 In this embodiment, an example of a structure using the semiconductor device shown in this specification will be described with reference to the accompanying drawings. This structure is able to retain stored content even without a power supply and has no limit on the number of writes.

[0316] Figures 22A to 22C This is an example of the structure of a semiconductor device. Figure 22A A cross-sectional view of a semiconductor device is shown. Figure 22B A plan view of a semiconductor device is shown. Figure 22C A circuit diagram of a semiconductor device is shown here. Figure 22A Equivalent to along Figure 22B The C1-C2 and D1-D2 sections in the diagram.

[0317] Figure 22A and Figure 22BThe semiconductor device shown has a transistor 260 using a first semiconductor material at its lower part and a transistor 300 using a second semiconductor material at its upper part. The structure of the semiconductor device shown in Embodiment 3 can be used as the transistor 300 using the second semiconductor material. Furthermore, although not described in this embodiment, the structures of the semiconductor devices used in Embodiments 1, 2, 4, and 5 can also be applied.

[0318] Here, the first semiconductor material and the second semiconductor material are preferably materials with different band gaps. For example, a semiconductor material other than oxide semiconductor (such as crystalline silicon) can be used as the first semiconductor material, and an oxide semiconductor can be used as the second semiconductor material. Transistors using materials other than oxide semiconductors, such as crystalline silicon, are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors can retain charge for a long time due to their properties.

[0319] Furthermore, although the above description focuses on the case where all transistors are n-channel transistors, p-channel transistors can of course be used.

[0320] Figure 22A The transistor 260 includes: a channel forming region 216 disposed in a substrate 200 containing a semiconductor material (e.g., crystalline silicon); an impurity region 220 disposed in a manner sandwiching the channel forming region 216; an intermetallic compound region 224 contacting the impurity region 220; a gate insulating film 208 disposed on the channel forming region 216; and a gate electrode 210 disposed on the gate insulating film 208. Note that although the source electrode or drain electrode of the transistor is sometimes not shown in the drawings, this state is sometimes referred to as a transistor for convenience. Furthermore, in this case, for the purpose of illustrating the connection relationship of the transistor, the source region or drain region is sometimes referred to as the source electrode or drain electrode. That is, in this specification, the source electrode may include the source region.

[0321] Additionally, a device separation insulating film 206 is disposed on the substrate 200 surrounding the transistor 260, and an insulating film 228 and an oxide film 230 are disposed on the substrate 200 covering the transistor 260. Furthermore, to achieve high integration, such as... Figure 22A As shown, it is preferable to use a structure in which the transistor 260 does not have a sidewall insulating film. However, if the characteristics of the transistor 260 are important, a sidewall insulating film may be provided on the side of the gate electrode 210, and an impurity region 220 containing regions with different impurity concentrations may be provided.

[0322] The transistor 260, using a crystalline silicon substrate, is capable of high-speed operation. Therefore, by using this transistor as a readout transistor, information can be read out at high speed. An insulating film and an oxide film are formed to cover the transistor 260. As a process prior to forming the transistor 300 and the capacitor element 264, the insulating film and oxide film are subjected to CMP treatment to form a planarized insulating film 228 and oxide film 230, while exposing the top surface of the gate electrode 210.

[0323] As the insulating film 228, inorganic insulating films such as silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, silicon oxynitride film, and aluminum oxynitride film can typically be used. Additionally, the oxide film 230 can be an oxide film such as silicon oxide film, silicon oxynitride film, and silicon oxynitride film. Both the insulating film 228 and the oxide film 230 can be formed using methods such as plasma CVD or sputtering.

[0324] In addition, the insulating film 228 can be made of organic materials such as polyimide resins, acrylic resins, and benzocyclobutene resins. Besides the aforementioned organic materials, low-dielectric-constant materials (low-k materials) can also be used. When using organic materials, the insulating film 228 can be formed using wet methods such as spin coating or printing.

[0325] Furthermore, in this embodiment, a silicon nitride film is used as the insulating film 228, and a silicon oxide film is used as the oxide film 230.

[0326] A first oxide semiconductor film 106 and a second oxide semiconductor film 108 are formed on an oxide film 230 that has been sufficiently planarized through polishing (e.g., CMP treatment). Furthermore, the average surface roughness of the oxide film 230 is preferably 0.15 nm or less.

[0327] Figure 22A The transistor 300 shown is a transistor that uses oxide semiconductor in the channel formation region. Here, the second oxide semiconductor film 108 included in the transistor 300 is preferably a high-purity oxide semiconductor film. By using a high-purity oxide semiconductor, a transistor 300 with extremely excellent cutoff characteristics can be obtained.

[0328] Transistor 300 has a low cutoff current, so it can retain stored content for a long time. In other words, because there is no need for refresh operations, or because semiconductor memory devices with very low refresh frequency can be manufactured, power consumption can be significantly reduced.

[0329] A single-layer or stacked insulating film 302 and an insulating film 304 are provided on the transistor 300. In this embodiment, a stack of silicon oxide film and aluminum oxide film stacked from one side of the transistor 300 is used as the insulating film 302 and the insulating film 304. Furthermore, the aluminum oxide film is set to a high density (e.g., a film density of 3.2 g / cm³). 3 The above, preferably 3.6 g / cm³ 3 The above can impart stable electrical characteristics to transistor 300, so it is preferred.

[0330] Furthermore, a conductive film 306 is provided in the area where it overlaps with the wiring 119a connected to the source electrode 118a of the transistor 300, separated by the insulating film 302. The wiring 119a, the insulating film 302, and the conductive film 306 constitute a capacitor element 364. In other words, the source electrode 118a of the transistor 300 serves as one electrode of the capacitor element 364, and the conductive film 306 serves as the other electrode of the capacitor element 364. Alternatively, when a capacitor is not required, a structure without the capacitor element 364 can be used. Furthermore, the capacitor element 364 can also be separately disposed above the transistor 300.

[0331] An insulating film 304 is provided on the transistor 300 and the capacitor element 364. Furthermore, wiring 308 for connecting the transistor 300 to other transistors is provided on the insulating film 304. The wiring 308 is formed in such a way that it fills the openings formed in the insulating film 302, the insulating film 304, etc., and is electrically connected to the drain electrode 118b.

[0332] In addition, Figure 22A and Figure 22B Preferably, transistors 260 and 300 are arranged in a manner that overlaps at least partially, and the source or drain region of transistor 260 and the second oxide semiconductor film 108 are arranged in a manner that overlaps partially. Additionally, transistor 300 and capacitor element 364 are arranged in a manner that overlaps at least partially with transistor 260. For example, the conductive film 306 of capacitor element 364 is arranged in a manner that overlaps at least partially with the gate electrode 210 of transistor 260. By adopting this planar layout, the footprint of the semiconductor device can be reduced, thereby achieving high integration.

[0333] then, Figure 22C Showing the corresponding Figure 22A and 22B An example of a circuit structure.

[0334] exist Figure 22CIn this configuration, the first wiring (line 1) is electrically connected to one of the source and drain electrodes of transistor 260, and the second wiring (line 2) is electrically connected to the other of the source and drain electrodes of transistor 260. Furthermore, the third wiring (line 3) is electrically connected to one of the source and drain electrodes of transistor 300, and the fourth wiring (line 4) is electrically connected to the gate electrode of transistor 300. Additionally, the gate electrode of transistor 260 and the other of the source and drain electrodes of transistor 300 are electrically connected to one electrode of capacitor element 364, and the fifth wiring (line 2) is electrically connected to the other electrode of capacitor element 364.

[0335] exist Figure 22C In the semiconductor device shown, by effectively utilizing the feature that can maintain the potential of the gate electrode of transistor 260, information can be written, held, and read out as shown below.

[0336] The writing and retention of information are explained. First, the potential of the fourth wiring is set to the potential that turns transistor 300 on, thus turning transistor 300 on. As a result, the potential of the third wiring is applied to the gate electrode of transistor 260 and capacitor element 364. That is, a predetermined charge is applied to the gate electrode of transistor 260 (writing). Here, either a charge with two different potential levels (hereinafter referred to as Low level charge and High level charge) is applied. Then, by setting the potential of the fourth wiring to the potential that turns transistor 300 off, transistor 300 is turned off, and the charge applied to the gate electrode of transistor 260 is retained (retention).

[0337] Because the cutoff current of transistor 300 is extremely small, the charge on the gate electrode of transistor 260 is maintained for a long time.

[0338] Next, the information readout will be explained. When a predetermined potential (constant potential) is applied to the first wiring, and an appropriate potential (readout potential) is applied to the fifth wiring, the second wiring has a different potential depending on the amount of charge held at the gate electrode of transistor 260. This is because, generally speaking, in the case of an n-channel transistor 260, the apparent threshold V when a high-level charge is applied to the gate electrode of transistor 260 is... th_H The apparent threshold V is lower than the low-level charge applied to the gate electrode of transistor 260. th_L This is because... Here, the apparent threshold voltage refers to the potential of the fifth wiring required to make transistor 260 "on". Therefore, by setting the potential of the fifth wiring to V... th_H and V th_LThe potential V0 between these values ​​can be used to identify the charge applied to the gate electrode of transistor 260. For example, during writing, when a High level charge is supplied, if the potential of the fifth wiring is V0 (>V... th_H If transistor 260 is in the "conducting state", then transistor 260 becomes "conducting". When supplied with a low level of charge, even if the potential of the fifth wiring is V0 ( <V th_L Transistor 260 also remains in the "off state". Therefore, the held information can be read from the potential of the second wiring.

[0339] Note that when configuring the memory cells in an array, it is necessary to read only the information from the desired memory cells. Thus, without reading any information, a potential less than V is applied to the fifth wiring that keeps transistor 260 in a "cut-off" state regardless of the gate electrode's state. th_H The potential is sufficient. Alternatively, a potential greater than V can be used to keep transistor 260 in the "conducting state" regardless of the state of the gate electrode. th_L The potential can be applied to the fifth wiring.

[0340] In the semiconductor device shown in this embodiment, by using transistors with extremely low cutoff current where oxide semiconductors are used in their channel formation regions, stored content can be retained for an extremely long period. That is, because refresh operations are unnecessary, or the frequency of refresh operations can be reduced to an extremely low level, power consumption can be significantly reduced. Furthermore, stored content can be retained for a long period even without a power supply (preferably with a fixed potential).

[0341] Furthermore, in the semiconductor device shown in this embodiment, writing information does not require high voltage, and there is no problem of component degradation. For example, unlike conventional non-volatile memories, there is no need to inject or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur. That is to say, in the semiconductor device according to the disclosed invention, there is no limit to the number of times it can be rewritten, which is a problem existing in conventional non-volatile memories, thus significantly improving reliability. Moreover, since information is written based on the on or off state of the transistor, high-speed operation can be easily achieved.

[0342] The transistor 300 includes: a first oxide semiconductor film 106 formed on the oxide film 230; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0343] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0344] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. Thus, by increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0345] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0346] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0347] In other words, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0348] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0349] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0350] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0351] Implementation Method 7 In this embodiment, the structure of the semiconductor device shown in Embodiments 1 to 5 is referred to... Figures 23A to 23B as well as Figures 24A to 24B A structure different from that shown in Embodiment 6 will be described. This structure can retain the stored content even without a power supply, and there is no limit to the number of writes.

[0352] Figure 23A This illustrates an example of the circuit structure of a semiconductor device. Figure 23B This is a schematic diagram illustrating an example of a semiconductor device. First, regarding... Figure 23A The semiconductor device shown will be described, and then... Figure 23B The semiconductor device shown will be described.

[0353] exist Figure 23A In the semiconductor device shown, the bit line BL is electrically connected to the source electrode or drain electrode of the transistor 300, the word line WL is electrically connected to the gate electrode of the transistor 300, and the source electrode or drain electrode of the transistor 300 is electrically connected to the first terminal of the capacitor element 354.

[0354] The transistor 300, which uses an oxide semiconductor, has the characteristic of having a very small cutoff current. Therefore, by turning off the transistor 300, the potential of the first terminal of the capacitor element 354 (or the charge accumulated in the capacitor element 354) can be maintained for a very long time.

[0355] Next, explain the... Figure 23A The semiconductor device (memory unit 350) shown is used to write and retain information.

[0356] First, transistor 300 is turned on by setting the potential of word line WL to a potential that turns transistor 300 on. This applies the potential of bit line BL to the first terminal of capacitor element 354 (write). Then, transistor 300 is turned off by setting the potential of word line WL to a potential that turns transistor 300 off, thereby maintaining the potential of the first terminal of capacitor element 354 (hold).

[0357] Because the cutoff current of transistor 300 is extremely small, it can maintain the potential of the first terminal of capacitor element 354 (or the charge accumulated in capacitor element) for a long time.

[0358] Next, the reading of information will be explained. When transistor 300 is turned on, the floating bit line BL is connected to capacitor element 354, and thus, the charge is redistributed between bit line BL and capacitor element 354. As a result, the potential of bit line BL changes. The amount of change in the potential of bit line BL varies depending on the potential of the first terminal of capacitor element 354 (or the charge accumulated in capacitor element 354).

[0359] For example, when V represents the potential of the first terminal of capacitor element 354, C represents the capacitance of capacitor element 354, CB represents the capacitive component of bit line BL (hereinafter also referred to as bit line capacitance), and VB0 represents the potential of bit line BL before charge redistribution, the potential of bit line BL after charge redistribution becomes (CB*VB0+C*V) / (CB+C). Therefore, as a state of storage cell 350, when the potential of the first terminal of capacitor element 354 is in two states, V1 and V0 (V1>V0), the potential of bit line BL at holding potential V1 (=(CB*VB0+C*V1) / (CB+C)) is higher than the potential of bit line BL at holding potential V0 (=(CB*VB0+C*V0) / (CB+C)).

[0360] Furthermore, information can be read by comparing the potential of bit line BL with a specified potential.

[0361] in this way, Figure 23A The semiconductor device shown can maintain the charge accumulated in the capacitor element 354 for a long time by utilizing the extremely low cutoff current of the transistor 300. In other words, because no refresh operation is required, or the refresh operation frequency can be extremely low, power consumption can be significantly reduced. Furthermore, the stored content can be maintained for a long time even without a power supply.

[0362] Next to Figure 23B The semiconductor device shown will be described.

[0363] Figure 23B The semiconductor device shown has a memory cell array 351a and a memory cell array 351b on its upper part as a memory circuit. The memory cell array 351a and the memory cell array 351b have multiple Figure 23A The storage unit 350 is shown. Furthermore... Figure 23B The semiconductor device shown has peripheral circuitry 353 at its lower part for operating memory cell arrays 351a and 351b. Furthermore, peripheral circuitry 353 is electrically connected to memory cell arrays 351a and 351b.

[0364] By adopting Figure 23BThe structure shown allows the peripheral circuit 353 to be positioned directly below the memory cell arrays 351a and 351b, thereby enabling the miniaturization of the semiconductor device.

[0365] The transistor disposed in the peripheral circuit 353 is preferably made of a semiconductor material different from that of the transistor 300. For example, silicon, germanium, silicon-germanium, silicon carbide, or gallium arsenide can be used, and single-crystal semiconductors are preferred. In addition, organic semiconductor materials can also be used. Transistors using such semiconductor materials can operate at sufficiently high speeds. Thus, by utilizing this transistor, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be successfully implemented.

[0366] in addition, Figure 23B The semiconductor device shown illustrates a structure with two stacked memory cell arrays (memory cell array 351a and memory cell array 351b), but the number of stacked memory cell arrays is not limited to this. A structure with three or more stacked memory cell arrays can also be used.

[0367] Next, refer to Figure 24A and Figure 24B right Figure 23A The specific structure of the storage unit 350 shown will be explained.

[0368] Figure 24A and Figure 24B An example of the structure of storage unit 350 is shown. Figure 24A This is a cross-sectional view showing storage cell 350. Figure 24B This is a plan view showing storage cell 350. Here, Figure 24A Equivalent to along Figure 24B Cross-sectional views of F1-F2 and G1-G2.

[0369] Figure 24A and Figure 24B The transistor 300 shown can have the same structure as that shown in Embodiment 3 or Embodiment 6. However, it can also have the structure of the transistor shown in other embodiments.

[0370] The transistor 300 includes: a first oxide semiconductor film 106 formed on an oxide film 274; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0371] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium and zinc, and the gallium content in the first oxide semiconductor film 106 is greater than that in the second oxide semiconductor film 108.

[0372] Furthermore, the gallium content in the first oxide semiconductor film 106 is equal to or greater than the indium content. Additionally, the indium content in the second oxide semiconductor film 108 is greater than the gallium content. Thus, by increasing the indium content in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be improved.

[0373] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0374] In addition, a second oxide semiconductor film 108 is formed on a first oxide semiconductor film 106 formed using the same type of material, thereby forming an oxide semiconductor film having a crystalline portion at the interface with the first oxide semiconductor film 106.

[0375] In other words, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed, and serves as the substrate film for the second oxide semiconductor film 108, thereby improving the crystallinity of the second oxide semiconductor film 108. Furthermore, after the second oxide semiconductor film 108 is formed, heat treatment or similar processes can be performed to release oxygen from the oxide film 104 and supply this oxygen through the first oxide semiconductor film 106 to the second oxide semiconductor film 108.

[0376] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0377] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0378] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0379] Additionally, it may include: an insulating film 113 disposed in the region overlapping with the gate electrode 112; a sidewall insulating film 115 formed on the sidewalls of the gate electrode 112 and the insulating film 113; a source electrode 118a and a drain electrode 118b electrically connected to the second oxide semiconductor film 108; an insulating film 120 formed on the interlayer insulating film 116; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b through openings disposed in the insulating film 120, the interlayer insulating film 116, and the protective insulating film 114. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0380] Furthermore, an insulating film 258 is formed on the transistor 300, and a conductive film 262 is disposed in the region where the insulating film 258 overlaps with the wiring 119a connected to the source electrode 118a of the transistor 300. The wiring 119a, the insulating film 258, and the conductive film 262 constitute a capacitor element 354. In other words, the source electrode 118a of the transistor 300 serves as one electrode of the capacitor element 354, and the conductive film 262 serves as the other electrode of the capacitor element 354.

[0381] Furthermore, a single-layer or multi-layer insulating film 256 is provided on the transistor 300 and the capacitor element 354. A wiring 272 for connecting to adjacent memory cells is also provided on the insulating film 256. The wiring 272 is electrically connected to the drain electrode 118b of the transistor 300 through openings and wiring 119b formed in the insulating films 256 and 258. However, the wiring 272 and the drain electrode 118b can also be directly connected. Additionally, the wiring 272 is equivalent to... Figure 23A The bit line BL in the circuit diagram.

[0382] exist Figure 24A and Figure 24B In this context, the drain electrode 118b of transistor 300 can also be used as the source electrode of a transistor included in an adjacent memory cell.

[0383] Thus, by adopting Figure 24B The planar layout shown can reduce the footprint of semiconductor devices, thereby enabling high integration.

[0384] As described above, the stacked memory cells are formed using transistors that utilize oxide semiconductors. Because transistors using oxide semiconductors have low cutoff current, it is possible to retain stored content for extended periods. In other words, because the refresh frequency can be extremely low, power consumption can be significantly reduced.

[0385] As described above, a semiconductor device with novel features can be realized by integrating the peripheral circuitry of a transistor using materials other than oxide semiconductors (in other words, a transistor capable of operating at sufficiently high speeds) with the memory circuitry of a transistor using oxide semiconductors (more broadly, a transistor with very low cutoff current). Furthermore, by employing a stacked structure of the peripheral circuitry and the memory circuitry, the semiconductor device can be integrated.

[0386] As described above, it is possible to provide a semiconductor device that achieves miniaturization and high integration and imparts high electrical characteristics, as well as a method for manufacturing the semiconductor device.

[0387] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0388] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0389] Implementation Method 8 In this embodiment, refer to Figures 25A to 25B , Figure 26 , Figure 27 as well as Figure 28 Examples of applying the semiconductor device shown in the above embodiments to portable devices such as mobile phones, smartphones, and e-book readers will be described.

[0390] In portable devices such as mobile phones, smartphones, and e-readers, SRAM or DRAM is used for temporary storage of image data. SRAM or DRAM is used because flash memory has a slow response time and is unsuitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

[0391] like Figure 25AAs shown, in a typical SRAM, a memory cell consists of six transistors, 801 to 806, which are driven by X decoder 807 and Y decoder 808. Transistors 803 and 805, as well as transistors 804 and 806, form an inverter, enabling high-speed operation. However, because a memory cell consists of six transistors, it suffers from a large cell area. With the minimum size set to F according to design rules, the cell area of ​​an SRAM is typically 100 to 150 F. 2 Therefore, the unit price of each bit of SRAM is the highest among various types of memory.

[0392] On the other hand, in DRAM, such as Figure 25B As shown, a memory cell consists of a transistor 811 and a storage capacitor 812, which are driven by an X decoder 813 and a Y decoder 814. Since a cell consists of one transistor and one capacitor, it occupies a small area. The storage area of ​​DRAM is typically 10F. 2 Note that DRAM requires constant refreshing, thus consuming power even when not being overwritten.

[0393] In contrast, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F. 2 It operates at a speed of approximately 100 km / h and does not require frequent refresh operations. This allows for a reduction in storage unit size and also lowers power consumption.

[0394] then, Figure 26 A block diagram of a portable device is shown. Figure 26 The portable device shown includes: an RF circuit 901; an analog baseband circuit 902; a digital baseband circuit 903; a battery 904; a power supply circuit 905; an application processor 906; a flash memory 910; a display controller 911; a storage circuit 912; a display 913; a touch sensor 919; an audio circuit 917; and a keyboard 918. The display 913 includes: a display unit 914; a source driver 915; and a gate driver 916. The application processor 906 includes: a CPU (Central Processing Unit) 907; a DSP (Digital Signal Processor) 908; and an IF 909. The storage circuit 912 is generally composed of SRAM or DRAM. By using the semiconductor device described in the above embodiment in this part, information can be written and read at high speed, stored content can be retained for a long time, and power consumption can be significantly reduced.

[0395] then, Figure 27 An example is shown of a storage circuit 950 in which the semiconductor device described in the above embodiments is used in a display. Figure 27 The storage circuit 950 shown includes: memory 952; memory 953; switch 954; switch 955; and memory controller 951. Additionally, the storage circuit is connected to: a display controller 956 for reading and controlling image data (input image data) input from signal lines and data stored in memory 952 and memory 953 (stored image data); and a display 957 for displaying data based on signals from the display controller 956.

[0396] First, an image data (input image data A) is generated by an application processor (not shown). This input image data A is stored in memory 952 via switch 954. Then, the image data (stored image data A) stored in memory 952 is sent to display 957 via switch 955 and display controller 956 for display.

[0397] When the input image data A remains unchanged, the stored image data A is typically read from the memory 952 by the display controller 956 via the switch 955 at a cycle of approximately 30 to 60 Hz.

[0398] Additionally, for example, when the user performs a screen rewriting operation (that is, when the input image data A changes), the application processor generates new image data (input image data B). This input image data B is stored in memory 953 via switch 954. During this period, stored image data A is also periodically read from memory 952 via switch 955. When a new image (stored image data B) is stored in memory 953, stored image data B is read from the next frame of display 957 and sent to display 957 via switch 955 and display controller 956 for display. This reading continues until the next new image data is stored in memory 952.

[0399] As described above, the display 957 displays image data by alternately writing and reading image data using memory 952 and memory 953. Furthermore, memory 952 and memory 953 are not limited to two different memories; a single memory can also be used in a partitioned manner. By using the semiconductor device described in the above embodiment for memory 952 and memory 953, information can be written and read at high speed, stored content can be retained for a long time, and power consumption can be significantly reduced.

[0400] then, Figure 28 A block diagram of an e-book reader is shown. Figure 28The e-book reader shown includes: a battery 1001; a power supply circuit 1002; a microprocessor 1003; a flash memory 1004; an audio circuit 1005; a keyboard 1006; a storage circuit 1007; a touch screen 1008; a display 1009; and a display controller 1010.

[0401] Here, the semiconductor device described in the above embodiments can be used for Figure 28 The storage circuit 1007 has the function of temporarily storing the contents of the book. For example, a user might use a highlighting function. When reading an e-book reader, a user sometimes needs to mark a specific section. This marking function is called a highlighting function, which makes the section stand out by changing the display color, underlining, making the text bold, or changing the font. The highlighting function stores and retains the information of the section specified by the user. When this information is to be retained for a long time, it can also be copied to the flash memory 1004. Even in this case, by using the semiconductor device described in the above embodiment, information can be written and read at high speed, stored content can be retained for a long time, and power consumption can be significantly reduced.

[0402] As described above, the portable device shown in this embodiment is equipped with the semiconductor device according to the above embodiment. Therefore, a portable device that can read information at high speed, retain stored content for a long time, and significantly reduce power consumption can be realized.

[0403] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods described in other embodiments.

[0404] Symbol Explanation 102: Substrate; 104: Oxide film; 106: First oxide semiconductor film; 106a: High resistance region; 106b: Low resistance region; 108: Second oxide semiconductor film; 108a: Channel region; 108b: Low resistance region; 110: Gate insulating film; 111: Conductive film; 112: Gate electrode; 113: Insulating film; 113a: Insulating film; 114: Protective insulating film; 114a: Insulating film; 115: Sidewall insulating film; 115a: Insulating film; 116: Interlayer insulating film; 116a: Insulating film; 118: Conductive film; 118a: Source electrode; 118b: Drain electrode; 119: Conductive film; 119a: Wiring; 119b: Wiring; 120: Insulating film; 121: Conductive film. 121a: First conductive film, 121b: Second conductive film, 132: Resist mask, 132a: Resist mask, 134: Resist mask, 134a: Resist mask, 134b: Resist mask, 136: Resist mask, 136a: Resist mask, 138: Resist mask, 138a: Resist mask, 142: Dopant, 151a: First opening, 151b: Second opening, 153a: Opening, 153b: Opening, 200: Substrate, 206: Component separation insulating film, 208: Gate insulating film, 210: Gate electrode, 216: Channel formation region, 220: Impurity region, 224: Intermetallic compound region, 228: Insulating film, 230: Oxide film, 2 56: Insulating film, 258: Insulating film, 260: Transistor, 262: Conductive film, 264: Capacitor element, 272: Wiring, 274: Oxide film, 300: Transistor, 302: Insulating film, 304: Insulating film, 306: Conductive film, 308: Wiring, 350: Memory cell, 351a: Memory cell array, 351b: Memory cell array, 353: Peripheral circuit, 354: Capacitor element, 364: Capacitor element, 801: Transistor, 802: Transistor, 803: Transistor, 804: Transistor, 805: Transistor, 806: Transistor, 807: X decoder, 808: Y decoder, 811: Transistor, 812: Storage capacitor, 813: X decoder, 8 14: Y decoder, 901: RF circuit, 902: Analog baseband circuit, 903: Digital baseband circuit, 904: Battery, 905: Power supply circuit, 906: Application processor, 907: CPU, 908: DSP, 909: IF, 910: Flash memory, 911: Display controller, 912: Storage circuit, 913: Display, 914: Display unit, 915: Source driver, 916: Gate driver, 917: Audio circuit, 918: Keyboard, 919: Touch sensor, 950: Storage circuit, 951: Memory controller, 952: Memory, 953: Memory, 954: Switch, 955: Switch, 956: Display controller, 957: Display.1001: Battery; 1002: Power supply circuit; 1003: Microprocessor; 1004: Flash memory; 1005: Audio circuit; 1006: Keyboard; 1007: Storage circuit; 1008: Touch screen; 1009: Display; 1010: Display controller.

[0405] This application is based on Japanese Patent Application No. 2011-282509, filed with the Japan Patent Office on December 23, 2011, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes: The first insulating layer on the first channel forming region; A first conductive layer is located on the first insulating layer and has a region that overlaps with the first channel forming region; A second insulating layer is located on the silicon and on the side of the first conductive layer; An oxide semiconductor layer is located on the second insulating layer and includes the second channel formation region; The third insulating layer on the oxide semiconductor layer; The second conductive layer is located on the third insulating layer and has a region that overlaps with the oxide semiconductor layer; The fourth insulating layer on the second conductive layer; The third conductive layer is located on the fourth insulating layer and is connected to the oxide semiconductor layer via a first opening provided in the fourth insulating layer; A fourth conductive layer is located on the fourth insulating layer and is connected to the oxide semiconductor layer via a second opening provided in the fourth insulating layer; The fifth insulating layer on the third conductive layer; and The fifth conductive layer on the fifth insulating layer, The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer. The second conductive layer has a region that functions as the gate electrode of the second transistor. The third conductive layer has a region that functions as one electrode of the capacitor element. The fifth conductive layer has a region that functions as another electrode of the capacitor element. The fifth insulating layer has a region that functions as a dielectric for the capacitor element. Furthermore, the region where the third conductive layer overlaps with the fifth conductive layer has a region that overlaps with the first conductive layer.

2. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes: The first insulating layer on the first channel forming region; A first conductive layer is located on the first insulating layer and has a region that overlaps with the first channel forming region; A second insulating layer is located on the silicon and on the side of the first conductive layer; An oxide semiconductor layer is located on the second insulating layer and includes the second channel formation region; The third insulating layer on the oxide semiconductor layer; The second conductive layer is located on the third insulating layer and has a region that overlaps with the oxide semiconductor layer; The fourth insulating layer on the second conductive layer; The third conductive layer is located on the fourth insulating layer and is connected to the oxide semiconductor layer via a first opening provided in the fourth insulating layer; A fourth conductive layer is located on the fourth insulating layer and is connected to the oxide semiconductor layer via a second opening provided in the fourth insulating layer; The fifth insulating layer on the third conductive layer; and The fifth conductive layer on the fifth insulating layer, The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer. The second conductive layer has a region that functions as the gate electrode of the second transistor. The third conductive layer has a region that functions as one electrode of the capacitor element. The fifth conductive layer has a region that functions as another electrode of the capacitor element. The fifth insulating layer has a region that functions as a dielectric for the capacitor element. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the first conductive layer. The region where the third conductive layer overlaps with the fifth conductive layer has a region that overlaps with the first channel formation region. Furthermore, the oxide semiconductor layer has a region that overlaps with the third conductive layer and the fourth conductive layer.

3. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes a first insulating layer on the first channel formation region. The semiconductor device includes a first conductive layer located on the first insulating layer and having a region overlapping the first channel formation region. The semiconductor device includes a second insulating layer located on the silicon and on the side of the first conductive layer. The semiconductor device includes a third insulating layer on the second insulating layer. The semiconductor device includes an oxide semiconductor layer located on the third insulating layer and including the second channel formation region. The semiconductor device includes a fourth insulating layer on the oxide semiconductor layer. The semiconductor device includes a second conductive layer located on the fourth insulating layer and having a region overlapping the oxide semiconductor layer. The semiconductor device includes a fifth insulating layer on the second conductive layer. The semiconductor device includes a third conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a first opening in the fifth insulating layer. The semiconductor device includes a fourth conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a second opening in the fifth insulating layer. The semiconductor device includes a sixth insulating layer on the third conductive layer. The semiconductor device includes a fifth conductive layer on the sixth insulating layer. The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer via the sixth conductive layer. The second conductive layer serves as the gate electrode of the second transistor. The third conductive layer serves as one of the electrodes of the capacitor element. The fifth conductive layer serves as another electrode for the capacitor element. The sixth insulating layer serves as the dielectric of the capacitor element. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the first conductive layer. Furthermore, the region where the third conductive layer overlaps with the fifth conductive layer has a region that overlaps with the sixth conductive layer.

4. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes a first insulating layer on the first channel formation region. The semiconductor device includes a first conductive layer located on the first insulating layer and having a region overlapping the first channel formation region. The semiconductor device includes a second insulating layer located on the silicon and on the side of the first conductive layer. The semiconductor device includes a third insulating layer on the second insulating layer. The semiconductor device includes an oxide semiconductor layer located on the third insulating layer and including the second channel formation region. The semiconductor device includes a fourth insulating layer on the oxide semiconductor layer. The semiconductor device includes a second conductive layer located on the fourth insulating layer and having a region overlapping the oxide semiconductor layer. The semiconductor device includes a fifth insulating layer on the second conductive layer. The semiconductor device includes a third conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a first opening in the fifth insulating layer. The semiconductor device includes a fourth conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a second opening in the fifth insulating layer. The semiconductor device includes a sixth insulating layer on the third conductive layer. The semiconductor device includes a fifth conductive layer on the sixth insulating layer. The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer via the sixth conductive layer. The second conductive layer serves as the gate electrode of the second transistor. The third conductive layer serves as one of the electrodes of the capacitor element. The fifth conductive layer serves as another electrode for the capacitor element. The sixth insulating layer serves as the dielectric of the capacitor element. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the first conductive layer. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the sixth conductive layer. The region where the fifth conductive layer overlaps with the sixth conductive layer has a region that overlaps with the first channel formation region. Furthermore, the oxide semiconductor layer has a region that overlaps with the third conductive layer and the fourth conductive layer.

5. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes a first insulating layer on the first channel formation region. The semiconductor device includes a first conductive layer located on the first insulating layer and having a region overlapping the first channel formation region. The semiconductor device includes a second insulating layer located on the silicon and on the side of the first conductive layer. The semiconductor device includes a third insulating layer on the second insulating layer. The semiconductor device includes an oxide semiconductor layer located on the third insulating layer and including the second channel formation region. The semiconductor device includes a fourth insulating layer on the oxide semiconductor layer. The semiconductor device includes a second conductive layer located on the fourth insulating layer and having a region overlapping the oxide semiconductor layer. The semiconductor device includes a fifth insulating layer on the second conductive layer. The semiconductor device includes a third conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a first opening in the fifth insulating layer. The semiconductor device includes a fourth conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a second opening in the fifth insulating layer. The semiconductor device includes a sixth insulating layer on the third conductive layer. The semiconductor device includes a fifth conductive layer on the sixth insulating layer. The semiconductor device includes a seventh insulating layer on the fifth conductive layer. The semiconductor device includes a seventh conductive layer on the seventh insulating layer. The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer via the sixth conductive layer. The second conductive layer serves as the gate electrode of the second transistor. The third conductive layer serves as one of the electrodes of the capacitor element. The fifth conductive layer serves as another electrode for the capacitor element. The sixth insulating layer serves as the dielectric of the capacitor element. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the first conductive layer. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the sixth conductive layer. The seventh conductive layer is connected to the fourth conductive layer. Furthermore, the seventh conductive layer has a region that overlaps with the oxide semiconductor layer.

6. A semiconductor device, comprising: A first transistor includes a first channel formation region having silicon. The second transistor includes a second channel formation region having an oxide semiconductor; and Capacitor components, The semiconductor device includes a first insulating layer on the first channel formation region. The semiconductor device includes a first conductive layer located on the first insulating layer and having a region overlapping the first channel formation region. The semiconductor device includes a second insulating layer located on the silicon and on the side of the first conductive layer. The semiconductor device includes a third insulating layer on the second insulating layer. The semiconductor device includes an oxide semiconductor layer located on the third insulating layer and including the second channel formation region. The semiconductor device includes a fourth insulating layer on the oxide semiconductor layer. The semiconductor device includes a second conductive layer located on the fourth insulating layer and having a region overlapping the oxide semiconductor layer. The semiconductor device includes a fifth insulating layer on the second conductive layer. The semiconductor device includes a third conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a first opening in the fifth insulating layer. The semiconductor device includes a fourth conductive layer located on the fifth insulating layer and connected to the oxide semiconductor layer via a second opening in the fifth insulating layer. The semiconductor device includes a sixth insulating layer on the third conductive layer. The semiconductor device includes a fifth conductive layer on the sixth insulating layer. The semiconductor device includes a seventh insulating layer on the fifth conductive layer. The semiconductor device includes a seventh conductive layer on the seventh insulating layer. The first conductive layer has a region that functions as the gate electrode of the first transistor. The first conductive layer is connected to the third conductive layer via the sixth conductive layer. The second conductive layer serves as the gate electrode of the second transistor. The third conductive layer serves as one of the electrodes of the capacitor element. The fifth conductive layer serves as another electrode for the capacitor element. The sixth insulating layer serves as the dielectric of the capacitor element. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the first conductive layer. The region where the third conductive layer overlaps with the fifth conductive layer also has a region that overlaps with the sixth conductive layer. The region where the fifth conductive layer overlaps with the sixth conductive layer has a region that overlaps with the first channel formation region. The oxide semiconductor layer has a region that overlaps with the third conductive layer and the fourth conductive layer. The seventh conductive layer is connected to the fourth conductive layer. Furthermore, the seventh conductive layer has a region that overlaps with the oxide semiconductor layer.

7. A semiconductor device, comprising: The first oxide semiconductor film on the oxide film; The second oxide semiconductor film on the first oxide semiconductor film; The gate insulating film on the second oxide semiconductor film; A gate electrode having a region that overlaps with the second oxide semiconductor film via the gate insulating film; as well as An insulating film formed on the gate electrode, In the second oxide semiconductor film, the region overlapping with the gate electrode functions as a channel region. The first oxide semiconductor film and the second oxide semiconductor film are oxide films containing at least indium, gallium, and zinc. The indium content of the first oxide semiconductor film is less than the indium content of the second oxide semiconductor film. The gallium content of the first oxide semiconductor film is greater than that of the second oxide semiconductor film. Furthermore, the hydrogen concentration of the insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 .

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