Image sensor and method of forming the same

Abstract

This invention discloses a method for forming a patterned sensor, comprising: providing a substrate; etching the substrate to form trenches in the substrate; and pre-treating the surface of the trenches before forming an epitaxial doped layer in the trenches to change the ion doping concentration gradient distribution in a portion of the substrate at the trench interface, thereby reducing the mutual compensation caused by the diffusion of doped ions near the PN junction interface of the photodiode in subsequent process steps, thereby improving the full-well capacity of the photodiode.

Description

Technical Field

[0001] This invention relates to the field of image sensors, and more particularly to an image sensor and a method for forming the same. Background Technology

[0002] In the fabrication of image sensors, doping is one of the most crucial steps. The manipulation of doping not only creates varying degrees of isolation but also directly affects the electrical characteristics of the device, thus influencing its performance. In actual fabrication processes, doping is primarily achieved through direct ion implantation. When forming an N-type well, phosphorus (P) and group V elements such as arsenic (As) and antimony (Sb) are implanted. Conversely, when forming a P-type well, group III elements such as boron (B) and indium (In) are implanted. A PN junction is formed when the P-type and N-type wells come into contact, and the junction capacitance directly affects the full-well capacity (FWC), the most important performance parameter of an image sensor.

[0003] However, the energy of ion implantation increases with the required implantation depth. The increased lattice scattering from implanted ions leads to a wider lateral expansion range for higher-energy ions, resulting in an actual doped region larger than the implantation region defined by the photomask. Dopant ions scattered outside the implantation region can invade well regions with opposite doping types, producing a doping compensation effect that partially cancels out the doping concentration, reducing the junction capacitance density at that location. Furthermore, the annealing process in the fabrication steps causes further diffusion of dopants along the concentration gradient, increasing the degree of dopant interdiffusion in the PN junction, thus making the junction capacitance loss even more significant.

[0004] The key to significantly improving FWC lies in reducing doping compensation caused by injection scattering and thermal diffusion. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a method for forming a patterned sensor, comprising: providing a substrate; etching the substrate to form trenches in the substrate; and pre-treating the surface of the trenches before forming an epitaxial doped layer in the trenches to change the ion doping concentration gradient distribution in a portion of the substrate at the trench interface, thereby reducing the mutual compensation caused by the diffusion of doped ions near the PN junction interface of the photodiode in subsequent process steps, thereby improving the full-well capacity of the photodiode.

[0006] In some embodiments, pretreatment of the trench surface includes: forming an interface material layer on the trench surface, and simultaneously using a high-temperature process for forming the interface material layer to diffuse doped ions from the substrate into the interface material layer, thereby changing the ion doping concentration gradient distribution of the substrate material at the trench interface.

[0007] In some embodiments, pretreatment of the trench surface includes: forming an interface material layer on the trench surface, and using high-temperature heat treatment to diffuse doped ions from the substrate into the interface material layer, thereby changing the ion doping concentration gradient distribution of the substrate material at the trench interface.

[0008] In some embodiments, after trenches are formed in the substrate, the trench surface is pretreated to cause the first type of doping concentration at the trench interface to change from low concentration to high concentration along a direction perpendicular to the trench surface from the trench surface into the substrate.

[0009] In some embodiments, the substrate material has a certain concentration of first-type doping.

[0010] In some embodiments, the substrate material is ion implanted to form a first type of doping with a certain concentration.

[0011] In some embodiments, after the interface material layer is formed, the interface material layer is removed by an isotropic etching method.

[0012] In some embodiments, the interface material layer is a silicon oxide layer formed by thermal oxidation or a polycrystalline silicon layer formed by deposition, or other material layers that can absorb elements of the first doping type in the substrate.

[0013] In some embodiments, the temperature range of the high-temperature formation process of the interface material layer is 750 degrees Celsius to 1200 degrees Celsius.

[0014] In some embodiments, the temperature range of the heat treatment process is 750 degrees Celsius to 1200 degrees Celsius.

[0015] In some embodiments, forming a photodiode by forming an epitaxial doped layer in the trench includes: forming an intrinsic or low-doped epitaxial layer on the surface of the trench; and continuing to epitaxially form a second doped epitaxial layer on the surface of the first doped epitaxial layer, with a doping type opposite to that of the substrate, to fill the trench and form the photodiode.

[0016] In some embodiments, in subsequent process flows, growth or annealing is performed using thermal budget conditions no higher than those for forming the interface material layer, further reducing the diffusion of doped ions near the trench interface, thereby further reducing the mutual compensation of doped ions near the PN junction interface of the photodiode.

[0017] Compared with existing technologies, this patent uses epitaxial growth after deep trench etching instead of traditional ion implantation, optimizing existing doping methods, improving junction capacitance, and thus increasing the full-well capacity (FWC) of the photodiode. For the interface heat treatment repair process during growth, this solution employs designed heat treatment conditions. Leveraging the gettering properties of the interface repair layer, the doping concentration near the deep trench surface is readjusted, minimizing the impact of subsequent annealing. This significantly reduces the mutual compensation phenomenon of doping in subsequent processes, striving to obtain the ideal junction capacitance value. Attached Figure Description

[0018] Figure 1 This is a functional block diagram of an image sensor as an exemplary embodiment of the present invention.

[0019] Figure 2 A circuit diagram of a pixel circuit for a four-transistor ("4T") pixel in a pixel array, which is an exemplary embodiment of the present invention.

[0020] Figures 3 to 8 This is a cross-sectional schematic diagram of the image sensor formation process, which is an exemplary embodiment of the present invention. Detailed Implementation

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0022] Figure 1 This is a functional block diagram of an image sensor 100 as an exemplary embodiment of the present invention.

[0023] The image sensor 100 includes a pixel array 105, a readout circuit 110, a functional logic 115, and a control circuit 120.

[0024] Pixel array 105 includes a two-dimensional (“2D”) array of multiple image sensor pixels (e.g., pixels P1, P2…Pn). As shown, each pixel is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

[0025] After each pixel has acquired its image data or image charge, the image data is read out by readout circuit 110 and transmitted to functional logic 115. Readout circuit 110 may include amplifier circuitry, analog-to-digital converter (“ADC”), etc. Functional logic 115 may simply store or process the image data. In one embodiment, readout circuit 110 may read out one row of image data at a time along readout column line 102, or may utilize other techniques (not shown) to read out the image data, such as column / row readout, serial readout, or simultaneous parallel readout of all pixels.

[0026] Control circuitry 120 is connected to pixel array 105 to control pixel array 105. For example, control circuitry 120 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal may be a global shutter signal, enabling all pixels within pixel array 105 to simultaneously capture their respective image data during a single acquisition window. In other embodiments, the shutter signal may be a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

[0027] Figure 2 A circuit diagram of a pixel circuit 101 for a four-transistor (“4T”) pixel in a pixel array, which is an exemplary embodiment of the present invention.

[0028] Pixel circuit 101 is used to implement Figure 1 This describes one possible pixel circuit architecture for each pixel within the pixel array 105. However, it should be understood that the embodiments described herein are not limited to a 4T pixel architecture; they can also be applied to 3T designs, 5T designs, and various other pixel architectures.

[0029] exist Figure 2 In each pixel Px of the pixel circuit 101, there are a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower transistor T3, and a selection transistor T4.

[0030] In some embodiments, the number of photodiodes PD can be one, two, four, or other numbers. For example, four photodiodes PD can share a floating diffusion region FD. During operation, a transfer transistor T1 receives a signal Tx that transfers the charge accumulated in the photodiodes PD to the floating diffusion region FD. In one embodiment, the floating diffusion node FD can be coupled to a storage capacitor for temporarily storing image charge.

[0031] Reset transistor T2 is coupled between voltage source VDD and floating diffusion region FD to reset the pixel under the control of reset signal RST (e.g., discharging or charging FD and PD to a preset voltage). Source follower transistor T3 is coupled between voltage source VDD and select transistor T4. Select transistor T4, under the control of select signal SEL, selectively couples the output of pixel circuit 101 to readout column line 102. Reset transistor T2 and source follower transistor T3 can also be coupled to different voltage sources VDD.

[0032] In one embodiment, the TX signal, RST signal, and SEL signal are generated by the control circuit 120. For example, in an embodiment where the pixel array 105 operates using a global shutter, the global shutter signal is coupled to the gate of each transfer transistor T1 in the entire pixel array 105 to simultaneously initiate charge transfer from the photodiode PD of each pixel.

[0033] This invention provides a method for forming a high-performance image sensor, including providing a substrate; etching the substrate to form trenches in the substrate; and pre-treating the surface of the trenches before forming an epitaxial doped layer within the trenches to alter the ion doping concentration gradient distribution in a portion of the substrate at the trench interface. This reduces mutual compensation caused by the diffusion of doped ions near the PN junction interface of the photodiode in subsequent process steps, thereby improving the full-well capacity of the photodiode. The image sensor formation process is described below with reference to the accompanying drawings.

[0034] refer to Figure 3 A substrate 21 is provided. Optionally, the substrate 21 can be a semiconductor material, such as silicon, germanium, silicon-germanium, silicon-germanium-on-insulator (SGOI), or a combination thereof. Optionally, the substrate material has a certain concentration of first-type doping. For example, it can be doped with P-type or N-type ions by epitaxy. Optionally, the substrate 21 material can be formed with a certain concentration of first-type doping by ion implantation. For example, P-type or N-type ion implantation. For ease of description, the embodiments of the present invention are described using a P-type substrate 21 as an example. For example, the dopant ions of the substrate 21 can be boron.

[0035] refer to Figure 4 The substrate 21 is etched to form trenches 22. The trenches 22 are used for subsequent formation of epitaxial doped layers to form photodiodes.

[0036] refer to Figure 5 The surface of trench 22 is pretreated so that part of the substrate 24 at the interface of trench 22 (e.g., Figure 6The ion doping concentration gradient distribution in the photodiode is changed to reduce the mutual compensation caused by the diffusion of dopant ions near the PN junction interface of the photodiode in subsequent processes, thereby improving the full-well capacity of the photodiode.

[0037] Specifically, after forming trenches in substrate 22, the surface of trench 22 is pretreated to make the interface of trench 22 (e.g.) Figure 6 The first type of doping concentration of the substrate 24 in the middle varies from low concentration to high concentration along the direction of the vertical trench 22 surface from the trench surface into the substrate 21.

[0038] refer to Figure 5 In one embodiment, an interface material layer 23 is formed on the surface of the trench 22. Simultaneously, a high-temperature process used in the formation of the interface material layer 23 causes dopant ions in the substrate 21 to diffuse into the interface material layer 23, thereby altering the ion doping concentration gradient distribution of the substrate 21 material at the trench 22 interface. Specifically, during the formation of the interface material layer 23, a high-temperature process is used to diffuse dopant ions (e.g., B ions) into the interface material layer 23. The temperature range for the high-temperature formation process of the interface material layer 23 is 750 degrees Celsius to 1200 degrees Celsius.

[0039] refer to Figure 5 In another embodiment, an interface material layer 23 is formed on the surface of the trench 22, and dopant ions in the substrate 21 diffuse into the interface material layer 23 through high-temperature heat treatment, thereby changing the ion doping concentration gradient distribution of the substrate 21 material at the interface of the trench 22. That is, after the interface material layer 23 is formed, a heat treatment process is used to diffuse dopant ions (e.g., B ions) into the interface material layer 23. The temperature range of the heat treatment process for the interface material layer 23 is 750 degrees Celsius to 1200 degrees Celsius.

[0040] In this embodiment of the invention, the interface material layer 23 may be a silicon oxide layer formed by thermal oxidation or a polycrystalline silicon layer formed by deposition, or other material layers that can absorb elements of the first doping type (e.g., B) in the substrate 21.

[0041] For oxides, growth methods that consume substrate material (such as thermo-oxidative growth) can be used. The high temperature during oxide growth can help the oxide layer enrich impurity atoms in the substrate, further reducing the noise level of the photodiode.

[0042] Alternatively, polycrystalline silicon can be directly deposited and grown on the surface of trench 22 to optimize the lattice structure of the trench 22 interface. The temperature required for polycrystalline silicon growth can help the atoms on the surface of trench 22 rearrange the lattice. At the same time, since polycrystalline silicon has more dislocations and defects, the high-temperature growth process can adsorb and pin the atoms in the substrate 21 into the polycrystalline silicon.

[0043] refer to Figure 7 After forming the interface material layer 23, the interface material layer 23 is removed using an isotropic etching method. The dopant ion concentration gradient distribution in some areas of the substrate 24 has changed.

[0044] refer to Figure 8 An intrinsic or low-doped epitaxial layer 25 is formed on the surface of trench 22. A second doped epitaxial layer 26, with a doping type opposite to that of the substrate 21, is then epitaxially formed on the surface of the first doped epitaxial layer 25 to fill the trench 22, forming a photodiode. The photodiode is formed by epitaxially creating an N-type second doped epitaxial layer 26, which, together with the substrate 21 and the first doped epitaxial layer 25. In some embodiments, the first doped epitaxial layer 25 may not be present; that is, the second epitaxial doped layer 26 is formed directly on the surface of trench 22.

[0045] In some embodiments, in subsequent process flows, growth or annealing is performed using thermal budget conditions no higher than those for forming the interface material layer 23, to further reduce the diffusion of doped ions near the trench 22 interface, thereby further reducing the mutual compensation of doped ions near the PN junction interface of the photodiode.

[0046] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming a graphic sensor, characterized in that, include: Provide substrate; The substrate is etched to form trenches in the substrate; Before forming a photodiode by forming an epitaxial doped layer in the trench, the surface of the trench is pretreated to change the ion doping concentration gradient distribution in part of the substrate at the trench interface. This reduces the mutual compensation caused by the diffusion of doped ions near the PN junction interface of the photodiode in subsequent processes, thereby improving the full-well capacity of the photodiode.

2. The method as described in claim 1, characterized in that, Pretreatment of the trench surface includes: An interface material layer is formed on the surface of the trench. At the same time, the high-temperature process used in the formation of the interface material layer causes the doped ions in the substrate to diffuse into the interface material layer, thereby changing the ion doping concentration gradient distribution of the substrate material at the trench interface.

3. The method as described in claim 1, characterized in that, Pretreatment of the trench surface includes: An interface material layer is formed on the surface of the trench, and high-temperature heat treatment is used to diffuse doped ions from the substrate into the interface material layer, thereby changing the ion doping concentration gradient distribution of the substrate material at the trench interface.

4. The method as described in claim 1, characterized in that, After trenches are formed in the substrate, the trench surface is pretreated to cause the first type of doping concentration at the trench interface to change from low concentration to high concentration along the direction perpendicular to the trench surface from the trench surface into the substrate.

5. The method as described in claim 1, characterized in that, The substrate material has a certain concentration of type I doping.

6. The method as described in claim 1, characterized in that, The substrate material is ion implanted to form a first type of doping with a certain concentration.

7. The method as described in claim 2 or 3, characterized in that, After the interface material layer is formed, it is removed by an isotropic etching method.

8. The method as described in claim 2 or 3, characterized in that, The interface material layer is a silicon oxide layer formed by thermal oxidation or a polycrystalline silicon layer formed by deposition, or other material layers that can absorb elements of the first doping type in the substrate.

9. The method as described in claim 2, characterized in that, The temperature range of the high-temperature formation process for the interface material layer is 750 degrees Celsius to 1200 degrees Celsius.

10. The method as described in claim 3, characterized in that, The temperature range of the heat treatment process is 750 degrees Celsius to 1200 degrees Celsius.

11. The method as described in claim 1, characterized in that, Forming a photodiode by forming an epitaxial doped layer within the trench includes: An intrinsic or low-doped first epitaxial layer is formed on the surface of the trench; A second doped epitaxial layer with the opposite doping type to the substrate is formed on the surface of the first doped epitaxial layer to fill the trench and form the photodiode.

12. The method as described in claim 2 or 3, characterized in that, In subsequent process flows, growth or annealing is performed using thermal budget conditions no higher than those for forming the interface material layer, further reducing the diffusion of doped ions near the trench interface, thereby further reducing the mutual compensation of doped ions near the PN junction interface of the photodiode.

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