An image sensor forming method and an image sensor
By employing a double bonding process and deep trench epitaxial growth of the photosensitive area in a back-illuminated image sensor, the problems of crosstalk and insufficient photosensitive area capacity in high-pixel designs are solved, achieving high signal-to-noise ratio and simplified process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2021-02-26
- Publication Date
- 2026-06-19
AI Technical Summary
Existing back-illuminated image sensors suffer from crosstalk, insufficient photosensitive area capacity, and temperature limitations in high-pixel designs, resulting in poor signal-to-noise ratio.
A two-stage bonding process is employed to first form a deep trench isolation region on the front side of the image sensor, and then epitaxially grow a photosensitive region within the deep trench to increase the doping concentration and enhance the full-well capacity of the photosensitive region. This is combined with the use of polysilicon to achieve circuit control.
It improves the full-well capacity of the photosensitive area of the image sensor, simplifies the process flow, avoids damage to the front-side devices caused by high-temperature processing, and enhances the signal-to-noise ratio and process feasibility.
Smart Images
Figure CN114975490B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of storage processing, and in particular to a method for forming an image sensor and an image sensor. Background Technology
[0002] In the design of back-illuminated image sensors, deep trenches on the back are typically used to isolate individual pixels and reduce crosstalk caused by incoming light. Crosstalk is divided into electrical crosstalk and optical crosstalk. Electrical crosstalk is mainly addressed by ion implantation to form a doped isolation layer on the sidewalls of the deep trench, thus isolating the photosensitive pixel area. Optical crosstalk is mainly reduced by growing oxide or other low-refractive-index thin films on the sidewalls of the deep trench and using total internal reflection.
[0003] In traditional processes, deep trench etching is typically performed on the back side of the device layer, followed by ion implantation. However, ion implantation creates lattice damage regions and deformable clusters, and some ions are not implanted at their replacement sites. Therefore, thermal annealing is usually required to repair lattice defects and allow most implanted ions to move to their replacement sites. Thermal annealing typically operates at temperatures above 800°C. Excessive temperatures can cause significant damage to the front-side devices and must be carefully controlled. However, this can lead to uneven doping, resulting in localized dark currents and other adverse effects within the deep trenches.
[0004] Furthermore, alignment issues arise during deep trench etching on the back side, causing the back isolation area to fail to connect with the front isolation area, resulting in crosstalk. Moreover, in high-pixel back-illuminated sensor products, especially those above 64 Mbits, the full-well capacity of the photosensitive area is limited due to the smaller pixel size and the influence of ion implantation depth, typically only a few thousand electrons, which is detrimental to improving the maximum signal-to-noise ratio of the image sensor. Summary of the Invention
[0005] The purpose of this invention is to provide a method for forming an image sensor, which is simple in process, has high full-scale capacitance, and is not limited by temperature. Specific solutions include:
[0006] The formation process of the image sensor includes at least two bonding processes on the semiconductor substrate wafer; wherein,
[0007] Before the first bonding, a lateral PN junction and a pinning layer are formed in the semiconductor substrate wafer, and a logic circuit region is formed after the first bonding and before the second bonding.
[0008] Furthermore, the method specifically includes:
[0009] A first photosensitive region, a first isolation region, and a pinning layer are formed on the front side of the semiconductor substrate wafer, and the first photosensitive region and the first isolation region form the lateral PN junction;
[0010] The first bonding is performed on the front side of the semiconductor substrate wafer;
[0011] A second photosensitive region, a second isolation region, and the logic circuit region are formed on the back side of the semiconductor substrate wafer;
[0012] A second bonding is performed on the back side of the semiconductor substrate wafer;
[0013] The front side of the semiconductor substrate wafer is thinned, and subsequent processes for the image sensor are completed.
[0014] Furthermore, the front side of the semiconductor substrate wafer has a first hard mask layer, and the method for forming the first photosensitive area and the first isolation area includes:
[0015] Based on the first hard mask layer, the semiconductor substrate is etched to form a first trench;
[0016] A first epitaxial layer is formed on the surface of the first trench.
[0017] Self-aligned etching is performed on the first epitaxial layer and the semiconductor substrate to form a second trench;
[0018] At least one second epitaxial layer is formed on the surface of the first epitaxial layer and the second trench to form a second epitaxial layer. The second epitaxial layer, the first epitaxial layer, and the semiconductor substrate form the first photosensitive region.
[0019] An oxide layer is deposited on the surface of the second epitaxial layer;
[0020] A polycrystalline semiconductor is filled on the surface of the oxide layer to form the first isolation region. The polycrystalline semiconductor is adapted to be connected to different potentials to improve the depletion of doped ions in the first photosensitive region.
[0021] Furthermore, the method for forming the pinning layer includes:
[0022] A second hard mask layer is formed on the surfaces of the first photosensitive area and the first isolation area;
[0023] Based on the second photoresist pattern, the first photosensitive area is etched to form the third trench;
[0024] A third epitaxy is performed on the surfaces of the second hard mask layer and the third trench, and the pinning layer is formed in the third trench, the pinning layer having the opposite conductivity type to the first photosensitive region.
[0025] Further, the step of performing a third epitaxy on the second hard mask layer and the surface of the third trench, and forming the pinning layer within the third trench, includes:
[0026] The third epitaxial layer is made of polycrystalline semiconductor material, and the polycrystalline semiconductor is grown in the third trench to form the pinning layer.
[0027] The third epitaxial layer is formed by continuing the third epitaxial process. The third epitaxial layer includes a polycrystalline semiconductor layer grown on the surface of the second hard mask layer and a semiconductor layer with gradually increasing doping concentration formed on the surface of the pinned layer.
[0028] Further, forming a second hard mask layer on the surfaces of the first photosensitive area and the first isolation area includes:
[0029] The surfaces of the first photosensitive area and the first isolation area are smoothed;
[0030] A second hard mask layer is formed by depositing a medium layer on the surfaces of the first photosensitive area and the first isolation area.
[0031] Furthermore, the first bonding process includes:
[0032] The surface of the third epitaxial layer is planarized.
[0033] The third epitaxial layer is bonded to the first carrier wafer.
[0034] Furthermore, the second epitaxial layer includes an intrinsic semiconductor layer and / or a fourth epitaxial layer with a conductivity type opposite to that of the first epitaxial layer.
[0035] Furthermore, the second extension includes:
[0036] Undoped and / or doped semiconductors are epitaxially grown on the surfaces of the first epitaxial layer and the second trench to form an intrinsic semiconductor layer and / or the fourth epitaxial layer.
[0037] Furthermore, after filling the polycrystalline semiconductor, the polycrystalline semiconductor and oxide layer on the front surface of the semiconductor substrate are removed.
[0038] Furthermore, the doping concentration of the first epitaxial layer is not less than 2 × 10⁻⁶. 16 cm -3 .
[0039] Further, the formation of the second photosensitive region, the second isolation region, and the logic circuit region on the back side of the semiconductor substrate wafer on the semiconductor substrate includes:
[0040] A second photosensitive region and a second isolation region are formed on the back side of the semiconductor substrate wafer, and are electrically connected to the first photosensitive region and the first isolation region, respectively;
[0041] The logic circuit region is formed on the second photosensitive region and the second isolation region.
[0042] Furthermore, the second photosensitive region and / or the second isolation region are formed by ion implantation.
[0043] Furthermore, the second bonding includes:
[0044] A metal interconnect structure is formed on the back side of the semiconductor substrate wafer, and surface passivation is performed.
[0045] The back side of the semiconductor substrate wafer is bonded to the second carrier wafer.
[0046] Furthermore, the thinning of the front side of the semiconductor substrate wafer includes:
[0047] Thinning to the second hard mask layer;
[0048] Chemical mechanical polishing is performed to remove the second hard mask layer;
[0049] The subsequent processes include:
[0050] A high dielectric constant material layer is formed on the front side of the semiconductor substrate wafer;
[0051] An image sensor is formed by sequentially setting an isolation grid, a color filter, and a microlens on the surface of the high dielectric constant material layer.
[0052] Furthermore, the high dielectric constant material layer includes one or more combinations of aluminum oxide, tantalum oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide.
[0053] Furthermore, the present invention also provides an image sensor formed using the image sensor forming method mentioned above.
[0054] This invention, through the aforementioned scheme and a two-step bonding process, employs a method in image sensor fabrication where a deep trench isolation region is first formed on the front side. Then, a portion of the photosensitive region is epitaxially grown within the deep trench, increasing the full-well capacity of the photosensitive region by raising the doping concentration. In subsequent processes, polysilicon can be grown within the deep trench, allowing for control via contact circuitry. This invention's technology is highly feasible due to its simple process, high full-well capacity, and self-alignment, making it unaffected by temperature limitations. Attached Figure Description
[0055] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.
[0056] Figure 1 This is a flowchart of the image sensor formation process in this invention;
[0057] Figures 2-13 This is a schematic diagram of the structure during the formation process of the image sensor in this invention.
[0058] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation
[0059] This invention provides a method for forming an image sensor, primarily applied to the fabrication process of back-illuminated image sensors. Through a two-step bonding process, a deep trench isolation region is first formed on the front side of the image sensor. Then, a portion of the photosensitive region is epitaxially grown within the deep trench. The full-well capacity of the photosensitive region is increased by raising the doping concentration.
[0060] Specifically, in one embodiment of the present invention, the image sensor forming method includes: the image sensor forming process includes at least two bonding processes for a semiconductor substrate wafer; wherein, before the first bonding, a lateral PN junction and a pinning layer are formed in the semiconductor substrate wafer, and a logic circuit region is formed after the first bonding and before the second bonding.
[0061] Traditional image sensor fabrication processes typically involve only one bonding operation, while this application employs a two-bonding method. In a specific implementation, such as... Figure 1 As shown, the method includes the following steps:
[0062] Step S100: A first photosensitive region 110, a first isolation region 120, and a pinning layer 130 are formed on the front side of the semiconductor substrate 100 wafer, wherein the first photosensitive region 110 and the first isolation region 120 form the lateral PN junction;
[0063] Step S200: Perform the first bonding on the front side of the semiconductor substrate 100 wafer;
[0064] Step S300: A second photosensitive region 210, a second isolation region 220, and the logic circuit region 230 are formed on the back side of the semiconductor substrate 100 wafer;
[0065] Step S400: Perform a second bonding on the back side of the semiconductor substrate 100 wafer;
[0066] Step S500: Thin the front side of the semiconductor substrate 100 wafer and complete the subsequent processes of the image sensor.
[0067] In step S100, a semiconductor substrate 100 is provided, and a first photosensitive region 110, a first isolation region 120, and a pinning layer 130 are formed on its front side. Specifically, in a preferred embodiment, the front side of the semiconductor substrate 100 wafer has a first hard mask layer 140, and the method for forming the first photosensitive region 110 and the first isolation region 120 includes:
[0068] Step S111: Based on the first hard mask layer 140, the semiconductor substrate 100 is etched to form a first trench 111, such as... Figure 2 As shown;
[0069] Step S112: Perform a first epitaxial layer 112 on the surface of the first trench 111, such as... Figure 3 As shown;
[0070] Preferably, in a typical implementation, the semiconductor substrate 100 can be a P-type semiconductor, while an N-type semiconductor is grown during the first epitaxy to subsequently form the photosensitive region. In practice, the doping concentration of the first epitaxy is preferably not less than 2 × 10⁻⁶. 16 cm -3 That is, using high-concentration epitaxy.
[0071] Step S113: Perform self-aligned etching on the first epitaxial layer 112 and the semiconductor substrate 100 to form the second trench 113, such as... Figure 4 As shown;
[0072] The second trench 113 extends downward from the first trench 111, as shown in the figure. Since the first hard mask layer 140 is still retained, this etching does not require photolithography and can be self-aligned. The second trench 113 forms a stepped bottom trench based on the first trench 111.
[0073] Step S114: Perform at least one second epitaxy on the surfaces of the first epitaxial layer 112 and the second trench 113 to form a second epitaxial layer 114. The second epitaxial layer 114, the first epitaxial layer 112, and the semiconductor substrate 100 form the first photosensitive region 110.
[0074] In a preferred embodiment, the second epitaxial layer 114 includes an intrinsic semiconductor layer 115 and / or a fourth epitaxial layer 116 with a conductivity type opposite to that of the first epitaxial layer. Optionally, when forming the second epitaxial layer 114, undoped and / or doped semiconductors can be epitaxially grown on the surfaces of the first epitaxial layer 112 and the second trench 113 to form the intrinsic semiconductor layer 115 and / or the fourth epitaxial layer 116, such as... Figure 5 As shown.
[0075] Step S115: An oxide layer 121 is deposited on the surface of the second epitaxial layer; one function of the oxide layer 121 is to electrically isolate the polycrystalline semiconductor 122 to be filled later, and another function is to serve as a total reflection layer to form optical isolation of the first photosensitive area 110.
[0076] Step S116: Fill the surface of the oxide layer 121 with a polycrystalline semiconductor 122, such as polycrystalline silicon, to form the first isolation region 120, such as... Figure 6 As shown, the polycrystalline semiconductor is adapted to be connected to different potentials to induce charges at the interface between the deep trench and the semiconductor, thereby reducing dark current and thermal noise and improving the depletion of doped ions in the first photosensitive region.
[0077] Preferably, after filling the polycrystalline semiconductor 122, the polycrystalline semiconductor and oxide layer on the front surface of the semiconductor substrate 100 can be removed to allow for subsequent steps.
[0078] Furthermore, in an optional implementation, the pinning layer 130 can be formed in step S100 using the following method:
[0079] Step S121: Form a second hard mask layer 131 on the surface of the first photosensitive area 110 and the first isolation area 120;
[0080] Specifically, after forming the first isolation region 120 in step S116, the surfaces of the first photosensitive region 110 and the first isolation region 120 can be planarized to remove excess polycrystalline semiconductor and the first hard mask layer 140, forming a plane. Then, a dielectric layer is deposited on the surfaces of the first photosensitive region 110 and the first isolation region 120 to form the second hard mask layer 131. Next, based on the second photoresist pattern determined by the second hard mask layer 131, the first photosensitive region 110 is etched to form a third trench 132, such as... Figure 7 As shown;
[0081] Step S122: Perform a third epitaxy on the second hard mask layer 131 and the third trench surface 132, forming the pinning layer 130 within the third trench 132. The pinning layer 130 has the opposite conductivity type to the first photosensitive region 110. That is, if the first photosensitive region 110 is predominantly N-type doped, the pinning layer 130 is P-type doped, and vice versa.
[0082] Specifically, in an optional embodiment, the third epitaxy in step S122 uses a polycrystalline semiconductor material, and a polycrystalline semiconductor is grown in the third trench 132 to form the pinning layer 130; the third epitaxy continues to form a third epitaxial layer 133, which includes a polycrystalline semiconductor layer grown on the surface of the second hard mask layer 131, and a semiconductor layer with gradually increasing doping concentration formed on the surface of the pinning layer. During the epitaxial growth of the polycrystalline semiconductor, polycrystalline semiconductor material is grown on the oxide interface, and single-crystal semiconductor material is grown on the single-crystal semiconductor interface. After a certain thickness, adjusting the epitaxial growth parameters can make all the grown materials polycrystalline semiconductor layers, and the doping concentration gradually increases to enhance the impurity adsorption capacity. Generally, the doping concentration can be higher in areas farther away from the photosensitive area, such as... Figure 8 As shown.
[0083] In step S200, the first bonding is performed on the front side of the semiconductor substrate 100 wafer. Specifically, in an optional embodiment, after the formation of the third epitaxial layer 133, the first bonding process can refer to the following steps:
[0084] Step S210: The surface of the third epitaxial layer 133 is planarized;
[0085] Step S220: Bond the third epitaxial layer 133 to the first carrier wafer 300. During bonding, a bonding oxide can be used to bond the semiconductor substrate 100 to the first carrier wafer 300, such as... Figure 9 As shown, they are fixed together so that they can be flipped to operate on the other side.
[0086] After the first bonding process is completed, subsequent processes are performed on the back side of the semiconductor substrate 100 wafer. For example, in step S300, a second photosensitive region 210, a second isolation region 220, and the logic circuit region 230 are formed on the back side of the semiconductor substrate 100.
[0087] Specifically, the formation of the second photosensitive area 210, the second isolation area 220, and the logic circuit area 230 can be performed according to the following steps:
[0088] Step S310: The second photosensitive region 210 and the second isolation region 220 are formed on the back side of the semiconductor substrate wafer 100, and are electrically connected to the first photosensitive region 110 and the first isolation region 120, respectively; In a preferred embodiment, the second photosensitive region 210 and / or the second isolation region 220 can be formed by ion implantation.
[0089] The second photosensitive area 210 and the second isolation area 220 can be designed in the form of three-dimensional pixels according to actual needs, such as... Figure 10 As shown.
[0090] Step S320: The logic circuit region 230 is formed on the second photosensitive region 210 and the second isolation region 220. The logic circuit region 230 is used to arrange various electronic devices.
[0091] Then, a second bonding process is performed in step S400, such as... Figure 11 As shown. Preferably, the second bonding includes the following steps:
[0092] Step S410: Form a metal interconnect structure on the back side of the semiconductor substrate 100 wafer and perform surface passivation;
[0093] Step S420: Bond the back side of the semiconductor substrate wafer 100 to the second carrier wafer 400.
[0094] Between the first and second bonding, a device layer is formed mainly on the back side of the semiconductor substrate 100. After the second photosensitive region 210, the second isolation region 220 and the logic circuit layer 230 are formed, the back side of the semiconductor substrate 100 can be bonded to the second carrier wafer 400 by bonding oxide, so as to thin the front side of the semiconductor substrate 100.
[0095] Based on this, in step S500, the front side of the semiconductor substrate 100 is thinned to remove the first carrier wafer 300 and materials such as bonding oxides in the preferred embodiment. Specifically, in the preferred embodiment, after step S420, the thinning of the front side of the semiconductor substrate 100 wafer includes the following steps:
[0096] Step S511: Thin down to the second hard mask layer 131; in this step, selective etching or other methods can be used until the second hard mask layer 131 is exposed.
[0097] Step S512: Perform chemical mechanical polishing to remove the second hard mask layer 131; expose the pinning layer 130 and the first isolation region 120, and at least expose the polysilicon material in the first isolation region 120, such as... Figure 12As shown. Compared to step S511, a non-selective grinding method can be selected in step S512.
[0098] Furthermore, in step S500, in a preferred embodiment, the subsequent process further includes:
[0099] Step S521: A high dielectric constant material layer 150 is formed on the front side of the semiconductor substrate 100 wafer; preferably, the high dielectric constant material layer includes one or more combinations of aluminum oxide, tantalum oxide, hafnium oxide, hafnium silicon oxide, alumina hafnium oxide, or hafnium tantalum oxide.
[0100] Step S522: Sequentially arrange an isolation grid 160, a color filter 170, and a microlens 180 on the surface of the high dielectric constant material 150 layer, such as... Figure 13 As shown, this ultimately forms an image sensor. Preferably, the isolation grid 160 can correspond to the polysilicon positions in the first isolation region 120, dividing the area to form a pixel array. The color filter 170 and microlens 180 can be configured according to the actual image sensor functions and application requirements.
[0101] Based on the aforementioned implementation methods, in this invention, a deep trench isolation region is first formed on the front side of the image sensor fabrication process through a two-step bonding process. Then, a portion of the photosensitive region is epitaxially grown within the deep trench, increasing the full-well capacity of the photosensitive region by raising the doping concentration. In subsequent processes, polysilicon can be grown within the deep trench, allowing for control via contact circuitry. The technology in this invention is highly feasible due to its simple process, high full-well capacity, and self-alignment process, which is not limited by temperature.
[0102] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.
Claims
1. A method for forming an image sensor, characterized in that, The formation process of the image sensor includes at least two bonding processes on the semiconductor substrate wafer; wherein, Before the first bonding, a lateral PN junction and a pinning layer are formed in the semiconductor substrate wafer, and a logic circuit region is formed after the first bonding and before the second bonding. The method includes: A first photosensitive region, a first isolation region, and a pinning layer are formed on the front side of the semiconductor substrate wafer, and the first photosensitive region and the first isolation region form the lateral PN junction; The first bonding is performed on the front side of the semiconductor substrate wafer; A second photosensitive region, a second isolation region, and the logic circuit region are formed on the back side of the semiconductor substrate wafer; A second bonding is performed on the back side of the semiconductor substrate wafer; The front side of the semiconductor substrate wafer is thinned, and subsequent processes for the image sensor are completed.
2. The image sensor forming method according to claim 1, wherein The semiconductor substrate wafer has a first hard mask layer on its front side, and the method for forming the first photosensitive area and the first isolation area includes: Based on the first hard mask layer, the semiconductor substrate is etched to form a first trench; A first epitaxial layer is formed on the surface of the first trench. Self-aligned etching is performed on the first epitaxial layer and the semiconductor substrate to form a second trench; At least one second epitaxial layer is formed on the surface of the first epitaxial layer and the second trench to form a second epitaxial layer. The second epitaxial layer, the first epitaxial layer, and the semiconductor substrate form the first photosensitive region. An oxide layer is deposited on the surface of the second epitaxial layer; A polycrystalline semiconductor is filled on the surface of the oxide layer to form the first isolation region. The polycrystalline semiconductor is adapted to be connected to different potentials to improve the depletion of doped ions in the first photosensitive region.
3. The method of forming an image sensor according to claim 1, wherein The method for forming the pinning layer includes: A second hard mask layer is formed on the surfaces of the first photosensitive area and the first isolation area; Based on the second photoresist pattern, the first photosensitive area is etched to form the third trench; A third epitaxy is performed on the surfaces of the second hard mask layer and the third trench, and the pinning layer is formed in the third trench, the pinning layer having the opposite conductivity type to the first photosensitive region.
4. The method for forming an image sensor according to claim 3, wherein The step of performing a third epitaxy on the surfaces of the second hard mask layer and the third trench, and forming the pinning layer within the third trench, includes: The third epitaxial layer is made of polycrystalline semiconductor material, and the polycrystalline semiconductor is grown in the third trench to form the pinning layer. The third epitaxial layer is formed by continuing the third epitaxial process. The third epitaxial layer includes a polycrystalline semiconductor layer grown on the surface of the second hard mask layer and a semiconductor layer with gradually increasing doping concentration formed on the surface of the pinned layer.
5. The method for forming an image sensor according to claim 3, wherein The step of forming a second hard mask layer on the surfaces of the first photosensitive area and the first isolation area includes: The surfaces of the first photosensitive area and the first isolation area are smoothed; A second hard mask layer is formed by depositing a medium layer on the surfaces of the first photosensitive area and the first isolation area.
6. The method for forming an image sensor according to claim 4, wherein The first bonding process includes: The surface of the third epitaxial layer is planarized. The third epitaxial layer is bonded to the first carrier wafer.
7. The method for forming an image sensor according to claim 2, wherein The second epitaxial layer includes an intrinsic semiconductor layer and / or a fourth epitaxial layer with a conductivity type opposite to that of the first epitaxial layer.
8. The method for forming an image sensor according to claim 7, wherein The second extension includes: Undoped and / or doped semiconductors are epitaxially grown on the surfaces of the first epitaxial layer and the second trench to form an intrinsic semiconductor layer and / or the fourth epitaxial layer.
9. The method for forming an image sensor according to claim 2, wherein After the polycrystalline semiconductor is filled, the polycrystalline semiconductor and oxide layer on the front surface of the semiconductor substrate are removed.
10. The method for forming an image sensor according to claim 2, wherein The first epitaxy has a doping concentration of no less than 2x10 16 cm -3 .
11. The method for forming an image sensor according to claim 1, wherein The formation of the second photosensitive region, the second isolation region, and the logic circuit region on the back side of the semiconductor substrate wafer on the semiconductor substrate includes: A second photosensitive region and a second isolation region are formed on the back side of the semiconductor substrate wafer, and are electrically connected to the first photosensitive region and the first isolation region, respectively; The logic circuit region is formed on the second photosensitive region and the second isolation region.
12. The method for forming an image sensor according to claim 11, wherein The second photosensitive region and / or the second isolation region are formed by ion implantation.
13. The method for forming an image sensor according to claim 1, wherein The second bonding includes: A metal interconnect structure is formed on the back side of the semiconductor substrate wafer, and surface passivation is performed. The back side of the semiconductor substrate wafer is bonded to the second carrier wafer.
14. The method of forming an image sensor of claim 3, wherein, The thinning of the front side of the semiconductor substrate wafer includes: Thinning to the second hard mask layer; The second hard mask layer is removed by chemical mechanical polishing. The subsequent processes include: A high dielectric constant material layer is formed on the front side of the semiconductor substrate wafer; An image sensor is formed by sequentially setting an isolation grid, a color filter, and a microlens on the surface of the high dielectric constant material layer.
15. The method for forming an image sensor according to claim 14, wherein The high dielectric constant material layer includes one or more combinations of aluminum oxide, tantalum oxide, hafnium oxide, hafnium silicon oxide, hafnium alumina, or hafnium tantalum oxide.
16. An image sensor, comprising: It is formed using the image sensor forming method as described in any one of claims 1 to 15.