Annealing method, preparation method and application of passivation layer on surface of mercury cadmium telluride infrared detector chip

Abstract

This invention relates to a method, preparation method, and application of annealing for a passivation layer on a mercury cadmium telluride (HCd) infrared detector chip. The method includes: performing a three-stage annealing treatment on the HCd chip in a nitrogen atmosphere (low-high-low temperature range); a first low-temperature stage for initial stabilization of the material interface state; a subsequent high-temperature stage to promote the interdiffusion of Cd and Hg at the HCd interface and suppress surface leakage current; and a third low-temperature stage specifically for "freezing" and stabilizing the electrical state optimized by high temperature, resulting in an improved passivation layer and the fabrication of a long-wavelength HCd infrared detector chip. This invention introduces a third low-temperature stage, which significantly reduces the dark current density of the material by promoting the rebalancing of point defects and suppressing the oversaturation of mercury interstitial atoms after the high-temperature stage and the resulting secondary defect regeneration. This results in highly stable key electrical parameters such as carrier concentration and mobility, avoiding performance fluctuations and thus significantly improving the detectivity, uniformity, and long-term reliability of the long-wavelength HCd detector.

Description

Technical Field

[0001] This invention belongs to the field of mercury cadmium telluride infrared focal plane detectors, and more specifically, relates to the annealing method, preparation method and application of the passivation layer on the surface of mercury cadmium telluride infrared detector chip. Background Technology

[0002] With the continuous development of mercury cadmium telluride (HCd) infrared detectors, the wavelength of HCd has gradually shifted from mid-wave to long / very long-wave, placing higher demands on the resolution, reliability, and sensitivity of the devices. As a narrow bandgap semiconductor device, the fixed charges introduced to the surface of HCd infrared focal plane detector chips by contamination or dangling bonds can easily cause band bending of one or several orders of magnitude in bandgap, leading to accumulation, depletion, or inversion on the surface of the HCd material. This increases the leakage current on the detector surface and seriously affects the performance of the device. In addition, the Hg atoms in the material are highly reactive, and the Te-Hg bond energy is low, which easily causes Hg to escape, resulting in Te enrichment on the material surface and affecting the performance of the device. Therefore, surface passivation of HCd photovoltaic infrared focal plane detectors is a very critical step in the manufacturing process.

[0003] CdTe is widely used in the surface passivation of HgCdTe infrared devices due to its good lattice constant matching with that of HgCdTe. After heat treatment, atomic diffusion occurs at the HgCdTe / CdTe interface, with cadmium in CdTe diffusing into HgCdTe. This forms a gradient-distributed high-concentration layer on the HgCdTe surface, which effectively reduces the density of dangling bonds and lattice defects on the HgCdTe / CdTe surface. This makes the band structure at the HgCdTe / CdTe interface close to a flat band structure, thereby effectively reducing surface leakage current and recombination rate, and improving the stability and consistency of HgCdTe infrared devices.

[0004] CN118136726A discloses a passivation layer for mercury cadmium telluride (HCDT) APD, its preparation method, and its application. By forming a high-component transition layer through tube sealing and annealing, the leakage current on the device surface is improved. Furthermore, after tube sealing and annealing, a CdTe passivation layer is deposited to control the electrical parameters of the material and improve the compactness of the film. This solves the problem of high leakage current in current HCDT APD devices. However, saturated mercury is toxic and requires sealed vacuum annealing, which is inefficient and costly.

[0005] CN118136727A discloses an improved mercury cadmium telluride (HCDT) APD passivation layer, its preparation method, and its application. By using a low-temperature-high-temperature annealing method under a nitrogen atmosphere, the problem of poor film density of current magnetron sputtered CdTe passivation layers is solved. Although high-temperature annealing is beneficial to atomic diffusion, it can lead to excessively high doping concentration of HCDT material due to the escape of a large number of mercury atoms, which reduces the minority carrier lifetime of the material and thus increases the insufficiency of dark current in the device.

[0006] Currently, the annealing process for CdTe passivation layers mainly involves tube-sealing annealing in a saturated mercury atmosphere. However, mercury and Te are toxic, and sealed vacuum annealing requires significantly more time and money. Nitrogen is inert and reacts almost entirely with the mercury cadmium telluride material during annealing. Although nitrogen annealing is cheaper and more convenient, it suffers from limitations such as poor film quality after high-temperature annealing, high carrier concentration, and low minority carrier lifetime. Summary of the Invention

[0007] To address the shortcomings in the aforementioned background technology, this invention has made improvements and innovations. The aim is to improve the passivation layer quality, reduce the dangling bond and defect state density on the surface of long-wavelength mercury cadmium telluride (HCDT) materials, and increase the minority carrier lifetime of the materials through a three-temperature annealing process under a nitrogen atmosphere, thereby solving the problem of large leakage current on the surface of current long-wavelength HCDT devices.

[0008] Specifically, the present invention is implemented as follows:

[0009] A method for annealing the passivation layer on the surface of a mercury cadmium telluride (HCdTe) chip, wherein the HCdTe chip comprises an HgCdTe substrate layer and an HgCdTe layer, and a CdTe passivation layer and a ZnS passivation layer are further deposited on the HgCdTe layer; the HCdTe chip is subjected to a low-high-low three-temperature-segment annealing treatment in a nitrogen atmosphere; the low-high-low three-temperature-segment annealing treatment includes:

[0010] The first step is to use a low temperature of 100-200℃;

[0011] The second step involves a high-temperature setting of 300-380℃.

[0012] The third step is to maintain a low temperature of 200-280℃.

[0013] Furthermore, the heating rate in the first step is 5℃ / s-15℃ / s, and the duration is 1-3h, which is used to promote the migration and fusion of CdTe atomic grain boundaries, improve the crystal quality, and obtain a denser passivation layer.

[0014] Furthermore, the second step involves a heating rate of 5℃ / s-15℃ / s and a duration of 3-8h, which is used to promote the interdiffusion of Cd and Hg at the mercury cadmium telluride interface and suppress surface leakage current.

[0015] Furthermore, the cooling rate in the third step is 1℃ / s-2℃ / s, and the duration is 5-10h. This is to provide a temperature environment with moderate migration ability for the supersaturated mercury interstitial atoms formed after the high-temperature stage, so that they can diffuse in an orderly manner and reach a local equilibrium with the residual point defects, while avoiding the formation of high-concentration defect clusters. This enables the material's electrical properties to transition from a non-equilibrium state to a stable state, resulting in suitable electrical parameters and a higher minority carrier lifetime.

[0016] A method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip includes the following steps:

[0017] S1. Provide a mercury cadmium telluride chip, wherein the mercury cadmium telluride chip is composed of a cadmium zinc telluride substrate layer and a mercury cadmium telluride layer, wherein the thickness of the cadmium zinc telluride substrate layer is 700μm-900μm and the thickness of the mercury cadmium telluride layer is 10μm-14μm;

[0018] S2. The mercury cadmium telluride chip in S1 is subjected to bromoethanol wet chemical etching, and then immersed in methanol solution;

[0019] S3. A CdTe passivation layer and a ZnS passivation layer are deposited on the surface of the mercury cadmium telluride chip in S2 by thermal evaporation. The CdTe passivation layer has a thickness of 50nm-400nm, and the ZnS passivation layer has a thickness of 200-400nm.

[0020] S4. The passivation layer obtained in S3 is subjected to a low-high-low three-temperature annealing treatment in a nitrogen atmosphere as described in a mercury cadmium telluride chip surface passivation layer annealing method, to obtain a high-quality surface passivation layer.

[0021] One method for annealing the passivation layer on the surface of a mercury cadmium telluride (MCH) chip includes: performing a low-high-low three-temperature-segment annealing treatment on the MCH chip in a nitrogen atmosphere; the low-high-low three-temperature-segment annealing treatment includes:

[0022] The first step is to use a low temperature of 100-200℃;

[0023] The second step involves a high-temperature setting of 300-380℃.

[0024] The third step involves maintaining a low temperature of 200-280℃.

[0025] The heating rate in the first step is 5℃ / s-15℃ / s, and the duration is 1-3h. This is used to promote the migration and fusion of CdTe atomic grain boundaries, improve the crystal quality, and obtain a denser passivation layer.

[0026] The second step involves a heating rate of 5℃ / s-15℃ / s and a duration of 3-8h, which is used to promote the interdiffusion of Cd and Hg at the mercury cadmium telluride interface and suppress surface leakage current.

[0027] The third step involves a cooling rate of 1℃ / s-2℃ / s and a duration of 5-10 hours. This is used to provide a temperature environment with moderate migration capability for the supersaturated mercury interstitial atoms formed after the high-temperature stage, enabling them to diffuse in an orderly manner and achieve local equilibrium with the residual point defects. At the same time, it avoids the formation of high-concentration defect clusters, thereby realizing the transformation of the material's electrical properties from a non-equilibrium state to a stable state, and obtaining suitable electrical parameters and a higher minority carrier lifetime.

[0028] Furthermore, the composition and ratio of the bromomethanol corrosion solution are 1-4 mL of Br2 and 50-200 mL of methanol.

[0029] Furthermore, CdTe and ZnS passivation layers were grown using thermal evaporation, with the chamber vacuum level maintained at 10°C before growth. -5 -10 -6 mbar, deposition temperature of 30-60℃, deposition rate of 1-3 Å / s.

[0030] A long-wavelength mercury cadmium telluride (MCH) surface passivation layer prepared by an annealing method for a MCH infrared detector chip.

[0031] A method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip.

[0032] Application of a long-wavelength mercury cadmium telluride infrared detector chip in the fabrication of long-wavelength mercury cadmium telluride infrared detectors.

[0033] Working principle:

[0034] This invention employs a "low temperature-high temperature-low temperature" annealing method, i.e., T1-T2-T3, which is superior to traditional single-stage or "low-high" two-stage annealing. The fundamental reason is that this path simulates and precisely controls a complete defect "repair-stabilization" dynamic process, with each temperature segment playing an irreplaceable synergistic role, forming a progressive optimization mechanism.

[0035] Gradual defect control (the foundational role of T1): The initial low-temperature stage T1 is not simply preheating, but rather provides a suitable temperature to promote the migration and fusion of CdTe atomic grain boundaries and release shallow stress, preventing abnormal surface diffusion or stress concentration from becoming new sources of defects when directly entering the high-temperature stage T2. This ensures that the mercury atoms and energy input in the T2 stage can be used more efficiently for the repair of intrinsic defects in the bulk.

[0036] Activating Cd / Hg interdiffusion (the key role of T2): The high-temperature stage T2 is crucial for the synergistic effect of surface interface engineering and bulk defect repair. High temperatures significantly enhance the interdiffusion kinetics between Cd and Hg atoms. Cd atoms diffuse from the interior of the cadmium telluride passivation layer to the surface / interface region of the mercury cadmium telluride. This interdiffusion process typically forms a high-Cd content layer (Hg) with a gradient change and an average Cd composition (x value) higher than that of the bulk material in the near-surface region of the material, typically at a depth of tens to hundreds of nanometers. 1-x Cd x (Te, x value increases). Due to its wider band gap, the high Cd composition layer forms an electronic barrier at the surface, which can effectively block the transport of minority carriers to surface defect states, thereby significantly reducing the surface recombination rate and surface leakage current. This is a key step in suppressing the dark current of the device.

[0037] The decisive role of stabilizing the surface composition gradient and locking the electrical parameters of the material (T3): This is precisely the value of the third low-temperature segment, T3, and the core reason why the "low-high-low" structure is superior to the "low-high" structure. The high Cd composition gradient on the surface formed by high-temperature interdiffusion is thermodynamically in a non-equilibrium state. The mild temperature environment of the T3 segment allows for limited local adjustments by atoms, but suppresses long-range diffusion. This causes the formed composition gradient to relax to a more stable metastable state, making it less prone to degradation in subsequent processes and device operation, thus maintaining excellent surface passivation effects over a long period.

[0038] As previously stated, at this temperature, supersaturated mercury interstitial atoms (Hg) i This allows for controlled short-range migration, which combines with residual point defects to achieve a more stable local equilibrium, locking in the bulk material electrical properties optimized by the T2 segment, such as carrier concentration and mobility.

[0039] In contrast, the specially designed T3 segment in this invention, with a temperature slightly higher than T1, is used to stabilize the material interface state and adjust the material's electrical parameters. It provides an environment with moderate kinetic energy: the temperature is low enough to slow down overall atomic diffusion and prevent drastic structural changes; yet it allows Hg in the material to diffuse more readily. i Limited, controlled short-range migration of point defects can fill Hg vacancies and improve the minority carrier lifetime of long-wavelength mercury cadmium telluride materials.

[0040] The "low-high-low" three-temperature annealing described in this invention achieves a synergistic effect of "1+1>2" through the precise connection and functional superposition of the physical mechanisms at each stage:

[0041] T1 foundation: Provides a suitable temperature for interdiffusion in the T2 stage, promotes the migration and fusion of CdTe atomic grain boundaries and releases shallow stress.

[0042] T2 Construction and Repair: The core innovation lies in simultaneously completing the "active construction of a wide surface bandgap passivation layer" and the "deep filling of mercury vacancies in the bulk material" in the same high-temperature step. This breaks through the limitations of traditional annealing, which only focuses on bulk defects or relies on subsequent epitaxial passivation layers, and improves device performance from the material perspective.

[0043] T3 Stabilization: Specifically designed to consolidate the results of T2, while stabilizing the surface composition structure and bulk electrical parameters, ensuring the reliability and repeatability of the technical results.

[0044] Final Results: The long-wavelength mercury cadmium telluride material treated with this process exhibits a significant reduction in surface leakage current due to the stable high-Cd composition passivation layer formed in situ. Simultaneously, the bulk dark current is suppressed due to optimized defect states, ultimately resulting in a high-performance infrared detector material with extremely low dark current density, high detectivity, and excellent parameter stability. Compared with existing technologies, the beneficial effects of this invention are:

[0045] 1. This invention achieves high-quality passivation layers, low defect density, and high minority carrier lifetime through three-temperature annealing, thereby reducing leakage current in long-wavelength devices and improving device stability.

[0046] 2. The present invention uses nitrogen atmosphere for annealing. Compared with saturated mercury pressure annealing, nitrogen atmosphere annealing is non-toxic, simple to operate and low in cost. Attached Figure Description

[0047] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0048] Figure 1 This is a schematic diagram of the long-wavelength mercury cadmium telluride device of the present invention. In the figure: 1-zinc cadmium telluride substrate, 2-mercury cadmium telluride epitaxial material, 3-evaporated CdTe layer, 4-evaporated ZnS layer, 5-n-region metal electrode, 6-p-region metal electrode;

[0049] Figure 2 This is a schematic diagram of the formation of high-component layers before and after three-temperature annealing according to the present invention. The dashed lines represent the interfaces of the high-component layers formed after annealing.

[0050] Figure 3 This is a low-high-low three-temperature annealing treatment curve diagram of the present invention;

[0051] Figure 4 These are scanning electron microscope cross-sectional images of the passivation layers at different annealing process temperatures in Embodiment 1 and Comparative Example 1 of the present invention;

[0052] Figure 5 These are secondary ion mass spectra of the passivation layer under different annealing processes in Example 2 and Comparative Example 2 of the present invention;

[0053] Figure 6 These are scanning electron microscope cross-sectional images of the passivation layers under different annealing processes in Embodiment 2 and Comparative Example 2 of the present invention;

[0054] Figure 7 These are transmission electron microscope images of the passivation layers under different annealing processes in Embodiment 3 and Comparative Example 3 of the present invention;

[0055] Figure 8 The figures show the IV and RV curves of the long-wavelength mercury cadmium telluride infrared detector under different annealing processes according to the present invention. Detailed Implementation

[0056] To make the technical means, features, objectives and effects of the present invention easier to understand, the technical solution of the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0057] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0058] Example 1

[0059] This embodiment 1 describes an annealing method for the passivation layer on the surface of a mercury cadmium telluride (HCdTe) chip. The HCdTe chip consists of an HgCdTe substrate and an HgCdTe layer. A CdTe passivation layer and a ZnS passivation layer are also deposited on the HgCdTe layer. The HCdTe chip is subjected to a low-high-low three-temperature annealing treatment in a nitrogen atmosphere. The low-high-low three-temperature annealing treatment includes:

[0060] The first step is to use a low temperature of 100-200℃;

[0061] The second step involves a high-temperature setting of 300-380℃.

[0062] The third step involves maintaining a low temperature of 200-280℃.

[0063] The first heating step has a heating rate of 5℃ / s-15℃ / s and a duration of 1-3h, which is used to promote the migration and fusion of CdTe atomic grain boundaries and improve crystal quality. The second heating step has a heating rate of 5℃ / s-15℃ / s and a duration of 3-8h, which is used to promote the interdiffusion of Cd and Hg at the mercury cadmium telluride interface and suppress surface leakage current. The third cooling step has a cooling rate of 1℃ / s-2℃ / s and a duration of 5-10h, which is used to avoid the formation of high-concentration defect clusters, thereby realizing the transformation of the material's electrical properties from a non-equilibrium state to a stable state.

[0064] By optimizing and comparing the film quality at different temperatures, the final three-stage annealing temperature was determined to be "150℃-370℃-240℃", and the specific annealing temperature curves are as follows: Figure 3 As shown.

[0065] Comparative Example 1

[0066] To systematically evaluate the effect of annealing path on passivation layer quality, this experiment compared several three-stage temperature methods, namely T1-T2-T3, using three-stage annealing methods: "300℃-220℃-320℃" (high-low-high), "100℃-300℃-200℃" (low-high-low), and "200℃-370℃-280℃" (low-high-low). Figure 4The images shown in Figures 1 and 2 are SEM cross-sectional images of the CdTe passivation layers prepared in Comparative Example 1 and Example 1 after annealing. Figure 4 As shown, "150℃-370℃-240℃" Figure 4 (b) Annealed film quality is better than "100℃-300℃-200℃" (low-high-low) Figure 4 (c) and “200℃-370℃-280℃” (low-high-low) Figure 4 (d) Furthermore, annealing at "300℃-220℃-320℃" (high-low-high) resulted in the worst film quality, with numerous pores and poor density. SEM results directly demonstrate that the "high-low-high" path leads to film structure deterioration due to a contradiction in the physical mechanism; while the "low-high-low" path, although mechanistically reasonable, is highly dependent on the precise design of temperature parameters. The "150℃-370℃-240℃" combination proposed in this invention, through precise matching of three temperature segments, achieves optimal control of the entire process from surface pretreatment, main body repair to final stabilization, thereby obtaining a passivation layer structure with the highest crystal quality and best density.

[0067] Example 2

[0068] This embodiment provides a method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip, including the following steps:

[0069] S1. Provide a mercury cadmium telluride chip, wherein the mercury cadmium telluride chip is composed of a cadmium zinc telluride substrate layer and a mercury cadmium telluride layer, wherein the thickness of the cadmium zinc telluride layer is 700μm-900μm and the thickness of the mercury cadmium telluride layer is 10μm-14μm;

[0070] S2. The mercury cadmium telluride chip in S1 is subjected to bromoethanol wet chemical etching, and then immersed in methanol solution;

[0071] S3. A CdTe passivation layer and a ZnS passivation layer are deposited on the surface of the mercury cadmium telluride chip in S2 by thermal evaporation. The thickness of the CdTe passivation layer is 50nm-400nm and the thickness of the ZnS passivation layer is 200-400nm.

[0072] S4. The passivation layer obtained in S3 is subjected to a three-temperature annealing treatment in a nitrogen atmosphere as described in Example 1, in the form of a low-high-low temperature range, to obtain a high-quality surface passivation layer.

[0073] Provide a mercury cadmium telluride (MDT) chip. Prepare a bromomethanol solution using 1-4 mL of Br2 and 50-200 mL of methanol. Immerse the MDT chip in the bromomethanol solution for chemical etching. After soaking in the methanol solution, remove the chip. Then, grow a CdTe passivation layer and a ZnS passivation layer using thermal evaporation. Maintain a chamber vacuum of 10°C before growth. -5 -10 -6The deposition temperature was 30-60℃, the deposition rate was 1-3 Å / s, and then the mercury cadmium telluride chip was subjected to three-temperature annealing heat treatment.

[0074] In three-temperature annealing, the heat treatment conditions are as follows:

[0075] The first step involves annealing under nitrogen inert gas protection at a low temperature of 150℃, with a heating rate of 5℃ / s-15℃ / s and a duration of 2 hours. The purpose of this first stage of low-temperature annealing is to promote the migration and fusion of CdTe atomic grain boundaries, improve the crystal quality, and obtain a denser passivation layer.

[0076] The second step involves a high-temperature annealing process under nitrogen inert gas protection. The temperature is 370℃, the heating rate is 5℃ / s-15℃ / s, and the duration is 4h. The second stage of high-temperature annealing is used to promote the mutual diffusion of Cd and Hg at the mercury cadmium telluride interface and suppress surface leakage current.

[0077] The third step involves annealing at a low temperature of 240°C for 7 hours under nitrogen inert gas protection. This third stage of low-temperature annealing provides a temperature environment with moderate migration capability for the supersaturated mercury interstitial atoms formed after the high-temperature stage, enabling them to diffuse in an orderly manner and achieve local equilibrium with residual point defects. At the same time, it avoids the formation of high-concentration defect clusters, thereby realizing the transformation of the material's electrical properties from a non-equilibrium state to a stable state, resulting in suitable electrical parameters and a higher minority carrier lifetime.

[0078] Comparative Example 2

[0079] This comparative example provides a conventional method for fabricating long-wavelength mercury cadmium telluride infrared detector chips, employing a "low-high" dual-temperature annealing process.

[0080] Includes the following steps:

[0081] S1. Provide a mercury cadmium telluride chip, wherein the mercury cadmium telluride chip is composed of a cadmium zinc telluride substrate layer and a mercury cadmium telluride layer, wherein the thickness of the cadmium zinc telluride layer is 700μm-900μm and the thickness of the mercury cadmium telluride layer is 10μm-14μm;

[0082] S2. The mercury cadmium telluride chip in S1 is subjected to bromoethanol wet chemical etching, and then immersed in methanol solution;

[0083] S3. A CdTe passivation layer and a ZnS passivation layer are deposited on the surface of the mercury cadmium telluride chip in S2 by thermal evaporation. The thickness of the CdTe passivation layer is 50nm-400nm and the thickness of the ZnS passivation layer is 200-400nm.

[0084] S4. The passivation layer obtained in S3 is subjected to "low-high" dual-temperature annealing under a nitrogen atmosphere to obtain a surface passivation layer.

[0085] During low-high dual-temperature annealing:

[0086] The first step involves a process under nitrogen inert gas protection, with a low temperature of 150℃, a heating rate of 5℃ / s-15℃ / s, and a duration of 2 hours.

[0087] The second part involves a process under nitrogen inert gas protection, with a low temperature of 290℃, a heating rate of 5℃ / s-15℃ / s, and a duration of 3 hours.

[0088] This comparative example uses the same preparation method as Example 2, except that in step S4, a "low-high" dual-temperature annealing is adopted, and the high-temperature section temperature is 290°C for 3 hours. This temperature setting is about 80°C lower than the high-temperature section temperature in Example 2, which is about 370°C. This design is based on a key physical mechanism trade-off: in the absence of a subsequent stabilization low-temperature section, i.e., the T3 section, although an excessively high annealing temperature is beneficial to the diffusion of Cd / Hg atoms, it will lead to an excessively high doping concentration of the mercury cadmium telluride material due to the escape of a large number of mercury atoms, which will significantly reduce the minority carrier lifetime of the material and thus increase the dark current of the device.

[0089] See Figure 5 (a) and (b) Figure 5 In Figures (a) and (b), secondary ion mass spectra (SIMS) of the CdTe passivated mercury cadmium telluride samples prepared in Comparative Example 2 and Example 2, respectively, after thermal annealing. Figure 5 As shown, the thickness of the high-component layer after conventional annealing is 0.10µm-0.12µm. In Example 2, after the passivation layer underwent three-temperature annealing, the thickness of the high-component layer increased significantly to 0.22µm-0.25µm. This indicates that three-temperature annealing can increase the thickness of the high-component layer at the mercury cadmium telluride (HCDT) interface, which is beneficial for reducing leakage current caused by surface dangling bonds and defect density, while also enhancing the breakdown characteristics of HCDT APD devices.

[0090] See Figure 6 (a) and (b) Figure 6 In Figures (a) and (b), SEM cross-sectional images of the CdTe passivated mercury cadmium telluride samples prepared in Comparative Example 2 and Example 2 after different thermal annealing are shown. Figure 6 As shown, the passivation layer under traditional hot annealing has many pores. In Example 2, the passivation layer underwent three-temperature annealing, which not only promoted the moderate migration of CdTe grain boundaries but also avoided the migration process being too violent, thereby effectively improving the compactness of the passivation layer and reducing the defect density.

[0091] Example 3

[0092] Example 3 describes a method for fabricating a long-wavelength mercury cadmium telluride detector based on an improved three-temperature-range annealing passivation layer. The specific method is as follows:

[0093] (1) Fabrication of long-wavelength mercury cadmium telluride infrared detector: Based on Example 2, a photolithographic mask was applied to the surface of the mercury cadmium telluride material, followed by boron ion implantation at a dose of 280 keV and a dose of 3*e15 / cm. 2 The implanted mercury cadmium telluride (MCH) material was subjected to driven annealing heat treatment at 200℃ for 1.5h. The purpose of this driven annealing was to form an n-region, thereby keeping the pn junction depletion region away from the implantation damage region, reducing device tunneling, generating recombination current, improving device performance, and enhancing device stability. Finally, the long-wavelength MCH material that had undergone driven annealing was processed using photolithography, ICP etching, metal deposition, and metal lift-off to fabricate ohmic contact electrodes and ground lines.

[0094] Comparative Example 3

[0095] The fabrication method of a long-wavelength mercury cadmium telluride detector based on a conventional annealed passivation layer is as follows:

[0096] The fabrication method of the long-wavelength mercury cadmium telluride infrared detector is the same as that in Example 3, except that the passivation layer annealing process adopts the method described in Comparative Example 2.

[0097] TEM images of the passivation layers prepared in Example 3 and Comparative Example 3 are shown below. Figure 7 As shown in (a) and (b), the test results show that, Figure 7 As shown in (a), the interface between conventionally annealed CdTe and HgCdTe is poorly integrated; CdTe is almost simply stacked on the HgCdTe surface. In contrast, as shown in (a), Figure 7 As shown in (b), the CdTe with improved three-temperature annealing exhibits clear lattice stripes, and the interface fusion between CdTe and HgCdTe is high, indicating that the passivation layer after three-temperature annealing has better crystal quality and the passivation effect of the mercury cadmium telluride surface is significantly improved. This means that the surface defect state density and dangling bonds are greatly reduced, which is beneficial to improving the performance of long-wavelength mercury cadmium telluride devices.

[0098] The IV curve corresponding to the long-wavelength mercury cadmium telluride infrared detector is as follows: Figure 8 As shown in (a) and (b),

[0099] The comparative results show that the long-wavelength device prepared by the high-temperature three-temperature annealing process described in this invention has significantly better electrical performance under reverse bias than the device prepared by the traditional two-temperature annealing process, especially in the operating range where the reverse bias exceeds 150 mV, the performance advantage is even more prominent.

[0100] This superior electrical property is directly attributed to the higher high-temperature stage (370°C) in the high-temperature three-stage annealing process, and the resulting material and interface optimization. The higher annealing temperature effectively enhances the interdiffusion kinetics of Cd and Hg atoms, thereby forming a higher Cd composition (wide bandgap) transition layer with better crystal quality and greater thickness on the material surface. This optimized layer achieves two key physical improvements:

[0101] 1. Significantly reduced the fixed charge density and interface state density at the surface / interface, effectively suppressing surface leakage channels;

[0102] 2. Improved the bulk quality of materials near the pn junction and the minority carrier lifetime.

[0103] These fundamental improvements at the material level directly translate into enhancements in key electrical parameters at the device level: the zero-bias impedance (R0A) of the device is significantly improved, and the dark current density under higher reverse bias is effectively suppressed. In contrast, traditional annealing processes, due to their lower high-temperature range (290℃), result in insufficient Cd / Hg interdiffusion, making it difficult to achieve the same high-quality surface passivation and bulk defect repair. This leads to greater interface leakage current in the devices and more pronounced performance degradation under reverse bias.

[0104] This invention can significantly reduce surface leakage current and generation of recombination current in devices, improve the breakdown resistance and baking resistance of long-wavelength mercury cadmium telluride devices, and enhance device stability, thus having broad application prospects in the field of long-wavelength mercury cadmium telluride infrared detectors.

[0105] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A method for annealing the passivation layer on the surface of a mercury cadmium telluride (HCdTe) chip, wherein the HCdTe chip comprises an HgCdTe substrate layer and an HgCdTe layer, and a CdTe passivation layer and a ZnS passivation layer are further deposited on the HgCdTe layer; characterized in that, The mercury cadmium telluride chip was subjected to a three-temperature annealing process in a nitrogen atmosphere, consisting of low, high, and low temperatures. The low-high-low three-temperature annealing process includes: The first step is to use a low temperature of 100-200℃; The second step involves a high-temperature setting of 300-380℃. The third step is to maintain a low temperature of 200-280℃.

2. The annealing method for the passivation layer on the surface of a mercury cadmium telluride chip as described in claim 1, characterized in that, The heating rate in the first step is 5℃ / s-15℃ / s, and the duration is 1-3h. This is used to promote the migration and fusion of CdTe atomic grain boundaries, improve the crystal quality, and obtain a denser passivation layer.

3. The annealing method for the passivation layer on the surface of a mercury cadmium telluride chip as described in claim 1, characterized in that, The second step involves a heating rate of 5℃ / s-15℃ / s and a duration of 3-8h, which is used to promote the interdiffusion of Cd and Hg at the mercury cadmium telluride interface and suppress surface leakage current.

4. The annealing method for the passivation layer on the surface of a mercury cadmium telluride chip as described in claim 1, characterized in that, The cooling rate in the third step is 1℃ / s-2℃ / s, and the duration is 5-10h. This is to provide a temperature environment with moderate migration ability for the supersaturated mercury interstitial atoms formed after the high-temperature stage, so that they can diffuse in an orderly manner and reach a local equilibrium with the residual point defects. At the same time, it avoids the formation of high-concentration defect clusters, thereby realizing the transformation of the material's electrical properties from a non-equilibrium state to a stable state, and obtaining suitable electrical parameters and a higher minority carrier lifetime.

5. A method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip, characterized in that, Includes the following steps: S1. Provide a mercury cadmium telluride chip, wherein the mercury cadmium telluride chip is composed of a cadmium zinc telluride substrate layer and a mercury cadmium telluride layer, wherein the thickness of the cadmium zinc telluride substrate layer is 700μm-900μm and the thickness of the mercury cadmium telluride layer is 10μm-14μm; S2. The mercury cadmium telluride chip in S1 is subjected to bromoethanol wet chemical etching, and then immersed in methanol solution; S3. A CdTe passivation layer and a ZnS passivation layer are deposited on the surface of the mercury cadmium telluride chip in S2 by thermal evaporation. The CdTe passivation layer has a thickness of 50nm-400nm, and the ZnS passivation layer has a thickness of 200-400nm. S4. The passivation layer obtained in S3 is subjected to the low-high-low three-temperature annealing treatment described in the annealing method for the surface passivation layer of a mercury cadmium telluride chip as described in any one of claims 1-4 in a nitrogen atmosphere to obtain a high-quality surface passivation layer.

6. The method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip as described in claim 5, characterized in that, The composition and ratio of the bromomethanol corrosion solution are 1-4 mL of Br2 and 50-200 mL of methanol.

7. The method for fabricating a long-wavelength mercury cadmium telluride infrared detector chip as described in claim 5, characterized in that, CdTe and ZnS passivation layers were grown using thermal evaporation, with the chamber vacuum level maintained at 10°C before growth. -5 -10 -6 mbar, deposition temperature of 30-60℃, deposition rate of 1-3 Å / s.

8. A long-wavelength mercury cadmium telluride surface passivation layer prepared by an annealing method for a mercury cadmium telluride infrared detector chip as described in any one of claims 1-4.

9. A long-wavelength mercury cadmium telluride infrared detector chip prepared by the method described in any one of claims 5-7.

10. The application of a long-wavelength mercury cadmium telluride surface passivation layer as described in claim 8 or a long-wavelength mercury cadmium telluride infrared detector chip as described in claim 9 in the fabrication of a long-wavelength mercury cadmium telluride infrared detector.

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