LED light source module, display device, and manufacturing method thereof

Abstract

A display device may include a semiconductor stack comprising: a first conductivity type semiconductor substrate; and light-emitting diode (LED) units on a lower surface of the first conductivity type semiconductor substrate. The display device may further include: spacers on the side and lower surfaces of the LED units, the spacers including inclined outer sidewalls; reflective electrodes on the spacers and connected to a region of the first conductivity type semiconductor substrate between the LED units; a gap-filling insulating layer on the lower surface of the semiconductor stack and on at least one reflective electrode; connecting electrodes connected to a second conductivity type semiconductor layer through contact holes penetrating the gap-filling insulating layer, the reflective electrode, and the spacers; and an insulating liner disposed along the inner sidewall of the contact holes and electrically insulating the connecting electrode and the reflective electrode.

Description

Cross-references to related applications

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0176298, filed with the Korean Intellectual Property Office on December 2, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Some embodiments of this disclosure relate to a miniature light-emitting diode (LED) light source module, a display device equipped with the LED light source module, and a method of manufacturing the same. Background Technology

[0003] Semiconductor LEDs can be used as light sources for lighting devices and various electronic products. Specifically, LEDs are widely used as light sources for various display devices (such as TVs, mobile phones, PCs, laptops, PDAs, etc.).

[0004] Some display devices may consist primarily of a display panel including a liquid crystal display (LCD) and a backlight; however, recently, LEDs have been developed that use LEDs as pixels, eliminating the need for a separate backlight. Compared to LCDs, such display devices can be miniaturized and can achieve high-brightness displays with excellent luminous efficiency. Summary of the Invention

[0005] According to some embodiments of this disclosure, a display device with excellent luminous efficiency can be provided.

[0006] According to some embodiments of this disclosure, an LED module light source with excellent luminous efficiency can be provided.

[0007] According to some embodiments of this disclosure, a method for manufacturing an LED module light source with excellent luminous efficiency can be provided.

[0008] According to some embodiments of this disclosure, a display device may be provided, and the display device includes: a semiconductor stack comprising: a first conductivity type semiconductor substrate including an upper surface configured as a light-emitting surface; and a light-emitting diode (LED) unit on a lower surface of the first conductivity type semiconductor substrate, the LED unit including an active layer and a second conductivity type semiconductor layer sequentially stacked on the lower surface of the first conductivity type semiconductor substrate; a spacer on a side surface and a lower surface of the LED unit, the spacer including an inclined outer sidewall; a reflective electrode on the spacer and connected to the first conductivity type semiconductor substrate; a gap-filling insulating layer on the lower surface of the semiconductor stack and on the reflective electrode; a connecting electrode connected to the second conductivity type semiconductor layer of the LED unit through a contact hole penetrating the gap-filling insulating layer, the reflective electrode and the spacer; and an insulating liner disposed along the inner sidewall of the contact hole and electrically insulating the connecting electrode and the reflective electrode.

[0009] According to some embodiments of this disclosure, a display device can be provided, and the display device includes: a pixel array of a plurality of pixel units, each of the plurality of pixel units including a plurality of sub-pixels, wherein the pixel array includes: a semiconductor stack comprising: a first conductivity type semiconductor substrate including an upper surface configured as a light-emitting surface; and a light-emitting diode (LED) unit on a lower surface of the first conductivity type semiconductor substrate, the LED unit including an active layer and a second conductivity type semiconductor layer; a spacer on a side surface of the LED unit and on the lower surface of each of the LED units, the spacer including an inclined outer sidewall; and a reflective electrode on the spacer and The system comprises: a region connected to a first conductivity type semiconductor substrate; a gap-filling insulating layer on the lower surface of the semiconductor stack and on a reflective electrode; a connecting electrode that passes through a contact hole penetrating the gap-filling insulating layer, the reflective electrode, and the spacer to a second conductivity type semiconductor layer of the LED unit; and an insulating liner that extends along the inner sidewall of the contact hole from the upper end of the contact hole to the lower surface of the LED unit, wherein the region of the lower surface of the first conductivity type semiconductor substrate between the LED units includes: a first region in which the spacer is located; and a second region recessed between the first regions, wherein the reflective electrode is connected to the second region along the outer sidewall of the spacer.

[0010] According to some embodiments of this disclosure, a display device may be provided, and the display device includes: a pixel array of a plurality of pixel units, each of the plurality of pixel units including a plurality of sub-pixels, wherein the pixel array includes: a semiconductor stack comprising: a first conductivity type semiconductor substrate including an upper surface configured as a light-emitting surface, and a light-emitting diode (LED) unit on a lower surface of the first conductivity type semiconductor substrate, and the LED unit including an active layer and a second conductivity type semiconductor layer; a spacer on a side surface and a lower surface of the LED unit, the spacer including an inclined outer sidewall; a reflective electrode on the spacer and connected to a region of the first conductivity type semiconductor substrate; a gap-filling insulating layer on the lower surface of the semiconductor stack and on the reflective electrode; a connecting electrode through a contact hole penetrating the gap-filling insulating layer, the reflective electrode and the spacer and connected to the second conductivity type semiconductor layer of the LED unit; and an insulating liner extending from the upper end of the contact hole along the inner sidewall of the contact hole, the insulating liner being separated from the lower surface of each of the LED units by the spacer.

[0011] According to some embodiments of this disclosure, an LED light source module can be provided, comprising: a semiconductor stack including a first conductivity type semiconductor substrate and a plurality of LED units on a lower surface of the first conductivity type semiconductor substrate, the first conductivity type semiconductor substrate including an upper surface configured as a light-emitting surface, wherein each of the plurality of LED units includes at least an active layer and a second conductivity type semiconductor layer sequentially stacked on the lower surface of the first conductivity type semiconductor substrate. The LED light source module may further include: at least one spacer on the side and lower surfaces of each of the plurality of LED units, and including an inclined outer sidewall; at least one reflective electrode on the at least one spacer and connected to a region of the first conductivity type semiconductor substrate between the plurality of LED units; at least one gap-filling insulating layer on the lower surface of the semiconductor stack and on the at least one reflective electrode; at least one connecting electrode connected to the second conductivity type semiconductor layer of each of the plurality of LED units through at least one contact hole penetrating the at least one gap-filling insulating layer, the at least one reflective electrode, and the at least one spacer; and at least one insulating liner disposed along the inner sidewall of the at least one contact hole, insulating the at least one connecting electrode and the at least one reflective electrode.

[0012] According to one aspect of this disclosure, a method for manufacturing an LED light source module includes: sequentially growing a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a substrate to form a semiconductor stack; etching a portion of the second conductivity type semiconductor layer, a portion of the active layer, and a portion of the first conductivity type semiconductor layer to form a plurality of LED units; forming at least one spacer on a side surface and a lower surface of each of the plurality of LED units, the spacer including inclined sidewalls, wherein a region of the first conductivity type semiconductor layer between the plurality of LED units is exposed; forming at least one reflective electrode on the at least one spacer, the at least one reflective electrode being connected to the first conductivity type semiconductor layer in the plurality of LED units. The exposed area between the elements; forming at least one gap-filling insulating layer on at least one reflective electrode on the lower surface of the semiconductor stack; forming at least one contact hole penetrating at least one gap-filling insulating layer, at least one reflective electrode and at least one spacer; conformally forming a liner material layer on the upper surface of at least one gap-filling insulating layer and the inner surface of at least one contact hole; removing a portion of the liner material layer on the upper surface of at least one gap-filling insulating layer and the bottom of at least one contact hole using an etching process to form at least one insulating liner on the inner sidewall of at least one contact hole; and forming at least one connection electrode in at least one contact hole that is connected to a second conductivity type semiconductor layer for each of the plurality of LED elements. Attached Figure Description

[0013] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a display device according to an embodiment. Figure 2 It is shown Figure 1 A partial plan view of the magnified portion of part "A" of the display device shown. Figure 3 This is a schematic cross-sectional view illustrating a display device according to an embodiment. Figure 4 It is shown Figure 3 A partial enlarged view of part "B" of the display device shown. Figure 5 A driving circuit implemented in a display device according to an embodiment is shown. Figure 6 This is a cross-sectional view showing an LED light source module used in a display device according to an embodiment. Figure 7 This is a cross-sectional view showing an LED light source module used in a display device according to an embodiment. Figure 8This is a schematic cross-sectional view illustrating a display device according to an embodiment. Figure 9 It is shown Figure 8 A partial enlarged view of part "B3" of the display device shown. Figures 10A to 10E This is a cross-sectional view illustrating some processes of a method for manufacturing a display device according to an embodiment. Figures 11A to 11C It is shown Figure 10A A cross-sectional view of an example of the process (specifically, forming an LED unit). Figures 12A to 12D It is shown Figure 10B A cross-sectional view of an example of the process (specifically, forming spacers). Figures 13A to 13D This is a cross-sectional view illustrating an example of a spacer forming process employed in a manufacturing method according to an embodiment. Figure 14A and Figure 14B It is shown Figure 10C A cross-sectional view of an example of the process. Figures 15A to 15D It is shown Figure 10D A cross-sectional view of an example of the process (specifically, forming connecting electrodes). Figures 16A to 16D This is a cross-sectional view illustrating an example of a connection electrode forming process used in a manufacturing method according to an embodiment. Figures 17A to 17C This is a cross-sectional view illustrating other processes of a method for manufacturing a display device according to an embodiment. Figure 18 This is a schematic diagram of an electronic device including a display device according to an embodiment. Detailed Implementation

[0014] In the following, non-limiting exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0015] It will be understood that when a component or layer is referred to as being "on" another component or layer, "connected" to another component or layer, or "coupled" to another component or layer, the component or layer may be directly on, directly connected to, or directly coupled to the other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on" another component or layer, "directly connected" to another component or layer, or "directly coupled" to another component or layer, there are no intermediate components or layers.

[0016] Figure 1 This is a schematic perspective view of a display device according to an embodiment, and Figure 2 It can be Figure 1A cross-sectional view of part "A" of the display device taken along the XY plane.

[0017] Reference Figure 1 and Figure 2 The display device 10 according to this embodiment may include: a circuit board 200 including a driving circuit; and a pixel array 100 disposed on the circuit board 200 and having a plurality of pixels PX disposed therein. Furthermore, the display device 10 may also include a frame 11 surrounding the circuit board 200 and the pixel array 100.

[0018] The driving circuitry of circuit board 200 may include thin-film transistor (TFT) units. In some embodiments, in addition to the driving circuitry for display device 10, circuit board 200 may also include other circuitry. In some embodiments, circuit board 200 may include a flexible board, and display device 10 may be implemented as a display device with a curved profile.

[0019] Pixel array 100 may include a display area DA and a peripheral area PA located on at least one side of the display area DA. The display area DA may include an LED light source module for display. Pixel array 100 may include a display area DA in which a plurality of pixels PX are arranged. The peripheral area PA may include a pad area PAD, a connection area CR connecting the plurality of pixels PX and the pad area PAD, and an edge area ISO.

[0020] Each of the plurality of pixels PX may include a first subpixel to a third subpixel SP1, SP2, and SP3, which are configured to emit light of different colors to provide a color image. For example, the first subpixel to the third subpixel SP1, SP2, and SP3 may be configured to emit red (R), green (G), and blue (B) light, respectively.

[0021] In some embodiments, in each of pixels PX (also referred to as "pixel units"), the first to third sub-pixels SP1, SP2, and SP3 may be arranged in a Bayer pattern. Figure 2As shown, each of the pixels PX may include a first sub-pixel SP1 and a third sub-pixel SP3 (e.g., red (R) and blue (B)) arranged along a first diagonal direction, and two second sub-pixels SP2 (e.g., green (G)) arranged along a second diagonal direction intersecting the first diagonal direction. In this embodiment, each of the pixels PX is shown as having the first to third sub-pixels SP1, SP2, and SP3 arranged in a 2×2 Bayer pattern. However, embodiments of this disclosure are not limited thereto, and in other embodiments, each of the pixels PX may be constructed in a different arrangement (e.g., 3×3 or 4×4). In some embodiments, each of the pixels PX may include a sub-pixel configured to emit a color other than the colors shown (R, G, B) (e.g., yellow light).

[0022] exist Figure 1 In the pixel array 100, multiple pixels PX are shown in a 15×15 configuration, but the number of rows and columns can be implemented in any suitable number, such as, for example, 1024×768 or 1800×1350. For example, depending on the desired resolution, the multiple pixels PX can be arranged differently.

[0023] Frame 11 may be a guiding structure surrounding pixel array 100. Frame 11 may include at least one material such as polymer, ceramic, semiconductor, or metal. For example, frame 11 may include a black matrix. Frame 11 is not limited to a black matrix and may include a white matrix or structures of different colors depending on the purpose of display device 10. For example, a white matrix may include a reflective or scattering material. Figure 1 The display device 10 is shown as having a rectangular planar structure, but in some embodiments it may have a different shape.

[0024] Multiple LED units LC1, LC2 and LC3 can be provided (see...) Figure 3 Multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) can each be a micro-LED structure and can be configured to correspond to first to third sub-pixels SP1, SP2, and SP3, respectively. Multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) can be arranged in multiple rows and columns in a planar diagram (see...). Figure 2 ).

[0025] Multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) can be provided as a light source for first sub-pixels to third sub-pixels SP1, SP2, and SP3. As described above, first sub-pixels to third sub-pixels SP1, SP2, and SP3 can be configured to emit light of different colors. In this embodiment, reference is made to... Figure 3 Multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) may include active layers (e.g., first active layer 115R, second active layer 115G, and third active layer 115B) that emit light of different wavelengths from each other. Each of the LED units LC1 (e.g., the first LED unit) may include a first active layer 115R configured to emit red light (e.g., light with a wavelength of 620 nm to 660 nm) and may be provided as a red sub-pixel (e.g., first sub-pixel SP1). Each of the LED units LC2 (e.g., the second LED unit) may include a second active layer 115G configured to emit green light (e.g., light with a wavelength of 510 nm to 550 nm) and may be provided as a green sub-pixel (e.g., second sub-pixel SP2). Each of the LED units LC3 (e.g., the third LED unit) may include a third active layer 115B configured to emit blue light (e.g., light having a wavelength of 430 nm to 480 nm) and may be provided as a blue sub-pixel (e.g., the third sub-pixel SP3).

[0026] The first to third active layers 115R, 115G, and 115B can have different luminous efficiencies depending on the emission wavelength. In order to smoothly reproduce the colors of the display device 10, the area of ​​the LED cells or the structure of the active layers (e.g., the number of quantum wells) can be changed, thereby reducing the deviation between the amount of light emitted from different sub-pixels (e.g., the first to third sub-pixels SP1, SP2, and SP3).

[0027] Figure 3 This may be a partially enlarged cross-sectional view of a display device according to an embodiment, showing... Figure 1 The local cross-section of the peripheral area PA of the display device along line I-I' and Figure 2 The local cross section of the display area DA of the display device along line II-II'.

[0028] As described above, the first to third LED units LC1, LC2, and LC3 can be portions of the semiconductor stack 110 configured to emit light of different wavelengths from each other, and can be provided as light sources for the first to third sub-pixels SP1, SP2, and SP3. The semiconductor stack 110 including the first to third LED units LC1, LC2, and LC3 used in this embodiment can include nitride epitaxial layers grown on the same substrate (see [link to documentation]). Figure 10A ).

[0029] like Figure 3 As shown, the semiconductor stack 110 may have a first surface (or lower surface) facing the circuit board 200 and a second surface (or upper surface) opposite to the first surface. In this embodiment, the semiconductor stack 110 may include: a first conductivity type semiconductor substrate 112B providing the second surface of the semiconductor stack 110, and a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) disposed on the lower surface of the first conductivity type semiconductor substrate 112B. In this case, the upper surface of the first conductivity type semiconductor substrate 112B may be provided as the second surface of the semiconductor stack 110 (e.g., a light-emitting surface).

[0030] Multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) may include at least an active layer (e.g., first active layer 115R, second active layer 115G, and third active layer 115B) and a second conductive type semiconductor layer 116 stacked on the lower surface of a first conductive type semiconductor substrate 112B. The first conductive type semiconductor substrate 112B may be a substrate shared by the first LED units to third LED units LC1, LC2, and LC3, and may provide contact regions (e.g., n-side contact regions) for driving the multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). Additionally, the first conductive type semiconductor substrate 112B may have a suitably small thickness to reduce light leakage effects. In some embodiments, the thickness of the first conductive type semiconductor substrate 112B may be in the range of 0.1 μm to 2 μm.

[0031] Each of the plurality of LED units employed in this embodiment (e.g., first LED units to third LED units LC1, LC2, and LC3) may further include a first conductivity type semiconductor layer 112, which is located between a first conductivity type semiconductor substrate 112B and an active layer (e.g., a first active layer 115R, a second active layer 115G, and a third active layer 115B). The first conductivity type semiconductor layer 112 may be a portion obtained by etching the first conductivity type semiconductor substrate 112B. The active layers (e.g., first active layer 115R, second active layer 115G, and third active layer 115B) of each of the first to third LED units LC1, LC2, and LC3 may be configured to emit light of different wavelengths (e.g., red, green, and blue). In this embodiment, the first to third active layers 115R, 115G, and 115B of each of the first to third LED units may include quantum well layers with different amounts of indium.

[0032] The first conductivity type semiconductor substrate 112B and the first conductivity type semiconductor layer 112 can each be n-type In x Al y Ga 1-x-y A nitride epitaxial layer with a composition of N (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the first conductivity type semiconductor layer 112 may be an n-type nitride (e.g., n-GaN) layer doped with silicon (Si), germanium (Ge), or carbon (C). In particular, the first conductivity type semiconductor base layer 112B may include a high concentration of n-type nitride (n-GaN) providing contact regions. + -GaN) layer. The second conductivity type semiconductor layer 116 can be a p-type In) layer. x Al y Ga 1-x-y A nitride semiconductor layer with a composition of N (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the second conductivity type semiconductor layer 116 may be a p-type nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). Each of the first conductivity type semiconductor layer 112 and the second conductivity type semiconductor layer 116 may be formed as a single layer, but may also include multiple layers with different characteristics such as doping concentration and composition.

[0033] Reference Figure 3 and Figure 4Multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) may include contact electrodes 152 located on a second conductivity type semiconductor layer 116. Contact electrodes 152 may include transparent electrodes. The transparent electrodes may be one of a transparent conductivity type oxide layer and a nitride layer. For example, the transparent electrodes may be selected from indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and In4Sn3O. 12 and Zn (1-x) Mg x At least one of O (zinc magnesium oxide, 0≤x≤1).

[0034] In this embodiment, the first to third LED units LC1, LC2, and LC3 may have side surfaces that are almost perpendicular to the lower surface of the first conductivity type semiconductor substrate 112B. For example, the side surfaces of the first to third LED units LC1, LC2, and LC3 may have a tilt angle in the range of 85° to 95°. The almost perpendicular side surfaces of the first to third LED units LC1, LC2, and LC3 can be formed by an etching process (see, for example, [reference needed]). Figure 11A and Figure 11B The etching process removes damaged areas on the side surface of the LED unit. This etching process can remove defective areas that cause leakage current. In some embodiments, the lower surface of the first conductivity type semiconductor substrate 112B (or substrate 101 (see...)) is... Figure 10A The upper surface of the LED unit can be a (0001) crystal plane, and the side surface of each of the first to third LED units LC1, LC2 and LC3 can be an m-plane. In some embodiments, by applying an additional etching process (see...) Figure 11C The side surfaces of the first to third LED units LC1, LC2, and LC3 may have an inclination angle of less than 90° relative to the lower surface of the first conductivity type semiconductor substrate 112B. As a result, the first to third LED units LC1, LC2, and LC3 may have a structure conducive to light extraction (see...). Figure 7 ).

[0035] Reference Figure 3 and Figure 4 The pixel array 100 may include a reflective structure configured to emit light onto the upper surfaces (e.g., light-emitting surfaces) of the first LED units to the third LED units LC1, LC2 and LC3.

[0036] The reflective structure employed in this embodiment may include a spacer 160 having an inclined outer sidewall (e.g., an inclined side surface 160S) and a reflective electrode 130 connected to a first conductivity type semiconductor substrate 112B. In a comparative embodiment, when the reflective electrode is formed along the vertical side surface of the LED unit, light may be trapped within the LED unit, and the light may not be effectively extracted at the desired narrow beam angle. According to an embodiment, spacers 160 having inclined side surfaces 160S may be introduced on the side and lower surfaces of multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) to improve light extraction efficiency via the reflective electrode 130 and further enhance light collection performance.

[0037] Reference Figure 4 In this embodiment, the spacer 160 may include a first portion 160a covering the side surface of each of a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), and a second portion 160b covering the lower surface of each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The first portion 160a of the spacer 160 may have a sloping side surface 160S based on the lower surface of a first conductivity type semiconductor substrate 112B. The first portion 160a may have a thickness d1 that increases toward the first conductivity type semiconductor substrate 112B. The sloping side surface 160S may have a curved portion. In some embodiments, the second portion 160b may have a region with a constant thickness d2, but the flat region of the second portion 160b may be barely visible in the final structure due to the contact hole CH.

[0038] Reference Figure 4 The thickness d3 of the portion of spacer 160 adjacent to the lower edge of each of the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3) may be less than the thickness d1 of the first portion 160a. In this embodiment, the thickness d3 of the adjacent portion may be less than the thickness d2 of the second portion 160b. For example, spacer 160 may include SiO2, SiOC, SiON, or SiOCN.

[0039] The reflective electrode 130 may be formed to cover the spacer 160. The reflective electrode 130 may have a reflective surface formed according to the surface shape of the spacer 160. The reflective electrode 130 may have a bowl-shaped or bell-shaped reflective structure to enhance the light-capturing effect.

[0040] The reflective electrode 130 may be provided as a first electrode for driving a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The reflective electrode 130 may have a contact portion 130C that is electrically connected between the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) and a contact region of a first conductivity type semiconductor substrate 112B. The contact region of the first conductivity type semiconductor substrate 112B may be provided as the region between the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3).

[0041] In this embodiment, the contact portion 130C of the reflective electrode 130 can be provided as a common electrode for multiple LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3). In a plan view, as shown... Figure 2 As shown, the reflective electrode 130 (specifically, the contact portion 130C) may have a grid structure or mesh structure extending and connected to each other in a first horizontal direction (e.g., the X direction) and a second horizontal direction intersecting the first horizontal direction (e.g., the Y direction). The side cross-section of the reflective electrode 130 may have an inverted U-shape between adjacent LED units in the first to third LED units LC1, LC2, and LC3. The reflective electrode 130 may include a reflective electrode material and may include at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some embodiments, the reflective electrode 130 may include a single-layer structure or a multi-layer structure.

[0042] In this embodiment, the contact area of ​​the first conductivity type semiconductor substrate 112B may have a recessed RS. Similar to the contact portion 130C of the reflective electrode 130, the recessed RS may have a grid structure or mesh structure extending and connected to each other in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction) in a plan view. The contact portion 130C of the reflective electrode 130 may be connected to the bottom of the recessed RS. The bottom of the recessed RS may be provided by a highly doped first conductivity type semiconductor layer (e.g., n+-GaN). In this embodiment, the recessed RS may be defined as the region between adjacent spacers 160. The contact area of ​​the first conductivity type semiconductor substrate 112B between multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) may include the region where the spacers 160 are located and the recessed RS between that region. The side surface of the spacer 160 may be continuously connected to the side surface of the recessed RS. The reflective electrode 130 may be connected to the bottom of the recessed RS along the side surface of the spacer 160.

[0043] In this way, in this embodiment, even if the height of the LED units (e.g., the first to third LED units LC1, LC2 and LC3) is relatively small, it can be achieved through additional etching for forming the recessed RS (see [reference]). Figure 12D The process involves exposing the contact area using a process called (e.g., first LED units to third LED units LC1, LC2, and LC3). As a result, multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) can be formed with a relatively small aspect ratio. For example, the aspect ratio of the multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) can be 1 or less.

[0044] The pixel array 100 may further include a gap-filling insulating layer 141 covering the reflective electrode 130 on the lower surface of the semiconductor stack 110. The gap-filling insulating layer 141 may include spin-coated hard mask (SOH), flowable oxide (FOX), Tonen silazane (TOSZ), undoped quartz glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable chemical vapor deposition (CVD) (FCVD) oxide, or combinations thereof. The gap-filling insulating layer 141 may be formed using chemical vapor deposition, flowable CVD, or spin-coating processes, respectively. The gap-filling insulating layer 141 may be formed with a flat upper surface. In some embodiments, even if the gap-filling insulating layer 141 may comprise the same material as the spacer 160 (e.g., silicon oxide), the spacer 160 may be formed to have a higher density than the gap-filling insulating layer 141. For example, such a spacer 160 (e.g., a high-density spacer) may be formed by a process such as atomic layer deposition (ALD).

[0045] The contact hole CH can penetrate the gap-filling insulating layer 141, the reflective electrode 130, and the spacer 160. Multiple contact holes CH can be formed to expose areas on the lower surfaces of multiple LED units (e.g., first to third LED units LC1, LC2, and LC3). In this embodiment, the contact hole CH can be formed to penetrate not only the gap-filling insulating layer 141 and the spacer 160, but also the reflective electrode 130. The reflective electrode 130 can be exposed on the sidewalls of the contact hole CH.

[0046] Reference Figure 4 The insulating liner 170 may be disposed on the sidewall of the contact hole CH. The insulating liner 170 may be present in the contact hole CH and may not be present on the lower surface of the gap-filling insulating layer 141. In this embodiment, the insulating liner 170 may extend from the upper end of the contact hole CH to the contact electrode 152. The insulating liner 170 may include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or combinations thereof.

[0047] The connecting electrode 155 can be connected through the contact hole CH to the contact electrodes 152 of multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). In this embodiment, the connecting electrode 155 can be used as another electrode for driving multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The connecting electrode 155 can drive multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) together with the reflective electrode 130, and unlike the reflective electrode 130, which may be a common electrode, the connecting electrode 155 can be provided as a separate electrode. In some embodiments, the connecting electrode 155 may include an electrode material similar to the electrode material of the reflective electrode 130. For example, the connecting electrode 155 may include at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some embodiments, the connecting electrode 155 may include a single-layer structure or a multi-layer structure.

[0048] In this embodiment, the reflective electrode 130 may be exposed from the inner wall of the contact hole CH, but the connecting electrode 155 may be electrically isolated from the reflective electrode 130 by an insulating liner 170. In this way, the insulating liner 170 can prevent unwanted short circuits between the reflective electrode 130 and the connecting electrode 155.

[0049] Furthermore, the reflective electrode 130 may be formed entirely on the covered portion of the spacer 160 except for the contact hole CH (e.g., the second portion 160b; see also...). Figure 9 As a result, the reflective electrode 130 introduced in this embodiment can be configured to minimize light leakage on the lower surface of each of the plurality of LED units (e.g., the first LED unit to the third LED unit LC1, LC2 and LC3).

[0050] In this embodiment, the insulating liner 170 can be formed using a self-aligned process of anisotropic etching without a separate mask (see [link]). Figure 15B and Figure 15C As a result, in the cross-sectional structure, the thickness of the two sides of the insulating liner 170 can be relatively consistent. For example... Figure 4 As shown, the insulating liner 170 may have two sides facing each other in the contact hole CH, and the thickness deviation (t1-t2) between the two sides is negligible. For example, the thickness deviation (t1-t2) between the two facing sides may be 10% or less.

[0051] In this embodiment, the connecting electrode 155 may include a through-hole 155V located in the contact hole CH, and a pad 155P connected to the through-hole 155V and located on the lower surface of the gap-filling insulating layer 141. The pad 155P of the connecting electrode 155 may have a width S2, which is greater than the width S1 of each of the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2 and LC3). In this way, the pad 155P of the connecting electrode 155 may be provided as a complementary reflection structure for a small amount of horizontally leaked light (e.g., light leaking through the insulating liner).

[0052] Reference Figure 3 The reflective electrode 130 may have an extension 130E extending from the display area DA to the peripheral area PA. In the connection area CR, a common electrode 145 may be disposed on the extension 130E of the reflective electrode 130. A pad electrode 147 may be located in the pad area PAD and, in a similar manner to the common electrode 145, on the gap-filling insulating layer 141, and may be connected to a bonding pad 199 on the pad electrode 147 for connection to external circuitry.

[0053] The upper bonding structure may include: an upper bonding insulating layer 191 disposed on the lower surface of the gap-filling insulating layer 141, and upper bonding electrodes 195A to 195D passing through the upper bonding insulating layer 191 and electrically connected to the reflective electrode 130 and the connecting electrode 155, respectively. The upper bonding electrodes 195A to 195D may be electrically connected to the reflective electrode 130 and the connecting electrode 155. The upper bonding electrodes 195A to 195D may have a pillar-like shape. The upper surface of the upper bonding electrodes 195A to 195D may be substantially coplanar with the upper surface of the upper bonding insulating layer 191. This coplanar surface may be provided as the lower surface of the pixel array 100 as a bonding surface for bonding to the circuit board 200. The upper bonding electrodes 195A to 195D may include a conductive material, such as, for example, copper (Cu). For example, the upper bonding insulating layer 191 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0054] As described above, the common electrode 145 and the pad electrode 147 can be respectively disposed in the connection region CR and the pad region PAD. The common electrode 145 can be provided together with the reflective electrode 130 as a common electrode structure for driving the first LED unit to the third LED unit LC1, LC2 and LC3. The pad electrode 147 can be disposed in the pad region PAD and can be connected to the bonding pad 199 on the pad electrode 147 for connecting to external circuitry.

[0055] The common electrode 145 and the pad electrode 147 may include at least one of a conductive material such as silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), or gold (Au). For example, the bonding pad 199 may include at least one of gold (Au), silver (Ag), and nickel (Ni).

[0056] In this embodiment, depending on the connection target, the upper bonding electrode may include a first upper bonding electrode (e.g., upper bonding electrode 195A) electrically connected to the reflective electrode 130, a second upper bonding electrode (e.g., upper bonding electrode 195B) electrically connected to the connection electrode 155, and a third upper bonding electrode (e.g., upper bonding electrode 195C) connected to the pad electrode 147.

[0057] Reference Figure 3 The first upper bonding electrode (e.g., upper bonding electrode 195A) can penetrate the upper bonding insulating layer 191 and the gap-filling insulating layer 141 to land on the common electrode 145 (e.g., contacting the common electrode 145), and can be connected to one side of each of the first to third LED units LC1, LC2, and LC3 (e.g., the first conductivity type semiconductor substrate 112B) through the common electrode 145 and the reflective electrode 130. The second upper bonding electrode 195B can penetrate the upper bonding insulating layer 191 to land on the connecting electrode 155 (e.g., contacting the connecting electrode 155), and can be individually connected to the other side of each of the first to third LED units LC1, LC2, and LC3 (e.g., the second conductivity type semiconductor layer 116) through the connecting electrode 155 and the contact electrode 152. Additionally, the third upper bonding electrode 195C can land on the pad electrode 147 (e.g., contact the pad electrode 147) by penetrating the upper bonding insulating layer 191 and the gap filling insulating layer 141, and can be connected to the bonding pad 199 for connecting to external circuitry via the pad electrode 147.

[0058] Reference Figure 3 In this embodiment, the circuit board 200 may include: a device board (e.g., a device substrate 201) on which elements 220 for driving circuitry are disposed, and a lower bonding structure disposed on the device board (e.g., the device substrate 201). The circuit board 200 may include an interlayer connection structure 230 located between the device substrate 201 and the lower bonding structure. The interlayer connection structure 230 may include an interconnect insulating layer 231 on the device substrate 201, and interconnect circuitry 235 electrically connected to elements 220 in the interconnect insulating layer 231. The elements 220 for driving circuitry may include thin-film transistor (TFT) cells.

[0059] Device substrate 201 may be a semiconductor substrate including impurity regions, which include source / drain regions 205. Device substrate 201 may include, for example, semiconductors (such as silicon (Si) or germanium (Ge)) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, or InP). Driving circuitry may include circuitry for controlling the driving of pixels (particularly sub-pixels). The source region in the source / drain region 205 of the TFT cell may be electrically connected to one side of the first to third LED cells LC1, LC2, and LC3 via interlayer interconnection structure 230 and lower bonding structure. For example, the drain region in the source / drain region 205 of the TFT cell may be connected to a data line via interconnection circuitry 235. The gate electrode of the TFT cell may be connected to a gate line via interconnection circuitry 235. Reference will be made below. Figure 5 The circuit's construction and operation are described in more detail.

[0060] The lower bonding structure may include a lower bonding insulating layer 291 and lower bonding electrodes 295A to 295D passing through the lower bonding insulating layer 291 and electrically connected to the driving circuit. The lower bonding electrodes 295A to 295D may be electrically connected to the driving circuit via interconnect circuitry 235. For example, the lower bonding electrodes 295A to 295D may be provided in a pillar structure. The upper surfaces of the lower bonding electrodes 295A to 295D may be substantially coplanar with the upper surface of the lower bonding insulating layer 291. This coplanar surface may be provided as the upper surface of the circuit board 200 as a bonding surface for bonding to the pixel array 100. The lower bonding electrodes 295A to 295D may include a conductive material, such as, for example, copper (Cu). For example, the lower bonding insulating layer 291 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0061] The lower bonding electrodes 295A to 295D of the circuit board 200 and the upper bonding electrodes 195A to 195D of the pixel array 100 can be bonded to each other to provide an electrical connection path between the circuit board 200 and the pixel array 100. In addition, the upper bonding insulating layer 191 of the pixel array 100 can be bonded to the lower bonding insulating layer 291 of the circuit board 200.

[0062] In this manner, the circuit board 200 and the pixel array 100 can be bonded to each other by bonding the lower bonding electrodes 295A to 295D and the upper bonding electrodes 195A to 195D, and by bonding the lower bonding insulating layer 291 and the upper bonding insulating layer 191. The bonding of the lower bonding electrodes 295A to 295D and the upper bonding electrodes 195A to 195D can be, for example, a copper (Cu)-copper (Cu) bonding, and the bonding of the lower bonding insulating layer 291 and the upper bonding insulating layer 191 can be a dielectric-dielectric bonding, for example, a dielectric-dielectric bonding such as a SiCN-SiCN bonding. The circuit board 200 and the pixel array 100 can be bonded by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding, and can be bonded without a separate adhesive layer.

[0063] Depending on the connection target, similar to the upper bonding electrodes 195A to 195C, the lower bonding electrodes 295A to 295C can be respectively divided into first lower bonding electrodes to third lower bonding electrodes (e.g., lower bonding electrodes 295A, 295B, and 295C). Specifically, the first lower bonding electrode (e.g., lower bonding electrode 295A) can be bonded to the first upper bonding electrode (e.g., upper bonding electrode 195A) to electrically connect the reflective electrode 130 to the drive circuit via the common electrode 145. The second lower bonding electrode (e.g., lower bonding electrode 295B) can be bonded to the second upper bonding electrode (e.g., upper bonding electrode 195B) to electrically connect the connection electrode 155, which may be a separate electrode, to the drive circuit.

[0064] In this manner, through the bonding of the first upper bonding electrode (e.g., upper bonding electrode 195A) and the first lower bonding electrode (e.g., lower bonding electrode 295A), and the bonding of the second upper bonding electrode (e.g., upper bonding electrode 195B) and the second lower bonding electrode (e.g., lower bonding electrode 295B), multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) can be individually driven and connected to the drive circuit. Furthermore, the third lower bonding electrode (e.g., lower bonding electrode 295C) can be bonded to the third upper bonding electrode (e.g., upper bonding electrode 195C) to electrically connect the bonding pad 199 to the drive circuit via the pad electrode 147.

[0065] In this embodiment, the lower bonding electrode may further include a lower dummy bonding electrode 295D that is not connected to the driving circuit. Similarly, the upper bonding electrode may further include an upper dummy bonding electrode 195D that is connected to the lower dummy bonding electrode 295D but not connected to the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3). Multiple upper dummy bonding electrodes 195D and lower dummy bonding electrodes 295D may be provided over the entire area and are arranged at equal intervals with other lower bonding electrodes and other upper bonding electrodes. In some embodiments, the upper dummy bonding electrode 195D may be formed on a dummy pad 155D that is not connected to the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3), and the dummy pad 155D may be formed together with the connection electrode 155.

[0066] Reference Figure 3 and Figure 4 Microlens 180 may be disposed on each of the first to third LED units LC1, LC2, and LC3 to collect light emitted from the first to third LED units LC1, LC2, and LC3. Microlens 180 may be configured to adjust the beam angle of the light emitted from the first to third LED units LC1, LC2, and LC3. In this embodiment, microlens 180 may be disposed on a first conductivity type semiconductor substrate 112B. For example, microlens 180 may have a diameter larger than the width of each of the plurality of LED units (e.g., the first to third LED units LC1, LC2, and LC3) in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction).

[0067] The microlens 180 may be formed of, for example, a transparent photoresist material or a transparent thermosetting resin film. In this embodiment, the microlenses 180 may be configured to have the same shape and size as each other, but in some embodiments, they may have different shapes and / or different sizes depending on the area of ​​the first LED unit to the third LED unit LC1, LC2 and LC3.

[0068] Figure 5 A driving circuit implemented in a display device according to an embodiment is shown.

[0069] Reference Figure 5 The diagram shows a circuit diagram of a display device 10 in which n×n sub-pixels are arranged. The first to third sub-pixels SP1, SP2, and SP3 can be connected via data lines D1 to D2. n Receive data signals, data lines D1 to D n This could be, for example, a vertical path in the column direction. The first sub-pixel to the third sub-pixels SP1, SP2, and SP3 can be connected via gate lines G1 to G...n Receive control signals (e.g., gate signals), gate lines G1 to G n This could be, for example, a horizontal path in the row direction.

[0070] A plurality of pixels PX, including first sub-pixels to third sub-pixels SP1, SP2, and SP3, can provide a display area DA, and the display area DA can be provided as an active area and can be a display area for a user. An active area NA (or peripheral area PA) can be formed along one or more edges of the display area DA. The active area NA can extend along the outer periphery of the panel of the display device 10.

[0071] The first driver circuit 12 and the second driver circuit 13 can be used to control the operation of pixels PX (e.g., first sub-pixels to third sub-pixels SP1, SP2, and SP3). Some or all of the first driver circuit 12 and the second driver circuit 13 can be implemented on the circuit board 200. The first driver circuit 12 and the second driver circuit 13 can be configured as integrated circuits, thin-film transistor panel circuits, or other suitable circuits, and can be disposed in the non-active region NA of the display device 10. The first driver circuit 12 and the second driver circuit 13 may include a microprocessor (such as, for example, processing circuitry and communication circuitry) and / or a memory (such as, a storage device).

[0072] In order to display an image via pixels PX, the first driver circuit 12 can supply image data to data lines D1 to D2. n Simultaneously, clock signals and other control signals are transmitted to a second driver circuit 13, which may be a gate driver circuit. The second driver circuit 13 may be implemented using integrated circuits and / or thin-film transistor circuits. Gate signals for controlling the first to third sub-pixels SP1, SP2, and SP3 positioned along the row direction can be transmitted via gate lines G1 to G2 of the display device 10. n transmission.

[0073] Figure 6 and Figure 7 These are cross-sectional views showing LED light source modules used in display devices according to various embodiments. Figure 6 and Figure 7 The LED light source module shown can be understood as being used as a reference. Figures 1 to 3 The display light source used in the pixel array of a portion of the described display device.

[0074] Reference Figure 6 It is understood that, apart from the structure of the contact hole CH' and the formation area of ​​the insulating liner 170' being different, the display device 10A according to this embodiment is similar to... Figures 1 to 5The display device 10 shown is similar. Additionally, unless otherwise specifically described, reference can be made to the... Figures 1 to 5 The components of this embodiment are understood by describing the same or similar components as the display device 10 shown.

[0075] In this embodiment, similar to the previous embodiment, the insulating liner 170' may extend from the upper end of the contact hole CH', but may be separated from the lower surface of each of the plurality of LED units (e.g., the first to third LED units LC1, LC2 and LC3) by a covering portion of the spacer 160 (e.g., the second portion 160b). The insulating liner 170' may also separate the reflective electrode and the connecting electrode.

[0076] The contact hole CH' according to this embodiment (see [reference]) can be formed by removing a portion of the spacer 160 from the bottom of the initial contact hole after forming the initial contact hole for exposing the spacer, during anisotropic etching for forming the insulating liner. Figures 16A to 16D The remaining portion of spacer 160 can protect the contact areas of multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) during anisotropic etching processes. This embodiment can be advantageously used when the lower surface of each of the multiple LED units (e.g., first to third LED units LC1, LC2, and LC3) is directly provided by a second conductivity type semiconductor layer 116, as in this embodiment.

[0077] Reference Figure 7 It can be understood that, in addition to adding a passivation layer 120 to the surface of multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) and having different tilt angles on the side surfaces of the multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), the display device 10B according to this embodiment and Figures 1 to 5 The display device 10 shown is similar. Additionally, unless otherwise specifically described, reference can be made to the... Figures 1 to 5 The components of this embodiment are understood by describing the same or similar components as the display device 10 shown.

[0078] In this embodiment, the lower surface of each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) may have a first width W1, which is greater than the second width W2 of each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) on the lower surface of the first conductivity type semiconductor substrate 112B. This is achieved by fully applying an etching process for removing damaged areas to the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) (see [link to documentation]). Figure 11C The side surfaces of the first to third LED units LC1, LC2, and LC3 may have an inclination angle of less than 90° relative to the lower surface of the first conductivity type semiconductor substrate 112B. Therefore, the first to third LED units LC1, LC2, and LC3 may have a structure that is conducive to light extraction.

[0079] In this embodiment, the passivation layer 120 may be disposed below the spacer 160 on the side and lower surfaces of each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The passivation layer 120 may be formed on the portion of the first conductivity type semiconductor substrate 112B between the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). Additionally, the passivation layer 120 may extend to the region of the first conductivity type semiconductor substrate 112B located in the peripheral region PA. Specifically, the passivation layer 120 may be configured to cover the lower surface of the first conductivity type semiconductor substrate 112B in the connection region CR and the pad region PAD (e.g., the peripheral region PA). For example, the passivation layer 120 may include an insulating material, such as, for example, SiO2, SiN, SiCN, SiOC, SiON, SiOCN, HfO. x AlO x ZrO x At least one of ZrO2, Al2O3, and HfO2. In some embodiments, the passivation layer 120 may include at least one of ZrO2, Al2O3, and HfO2.

[0080] Reference Figure 7The passivation layer 120 may include a first insulating layer 121 contacting the surfaces of a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), and a second insulating layer 125 on the first insulating layer 121. The first insulating layer 121 may be provided as a layer for curing defects on the surfaces of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), particularly on the side surfaces of the nitride epitaxial layer. For example, the first insulating layer 121 may include at least one of ZrO2, Al2O3, and HfO2. The first insulating layer 121 may be conformally formed along the surfaces of the first LED units to third LED units LC1, LC2, and LC3. For example, the first insulating layer 121 may be formed by an atomic layer deposition (ALD) process. In some embodiments, the first insulating layer 121 may have a multilayer structure having a first insulating film 121a and a second insulating film 121b. The first insulating layer 121 may include, for example, a ZrO2 / Al2O3 / ZrO2 multilayer structure. Each layer of the multilayer structure can have a thickness of 1 nm to 10 nm. Additionally, the second insulating layer 125 may include at least one of, for example, SiO2, SiN, SiCN, SiOC, SiON, and SiOCN.

[0081] Figure 8 This is a schematic cross-sectional view illustrating a display device according to an embodiment, and Figure 9 It is shown Figure 8 A partial enlarged view of part "B3" of the display device shown.

[0082] Reference Figure 8 and Figure 9 It can be understood that, except that the first conductivity type semiconductor substrate may not have recesses between multiple LED units (e.g., the first LED unit to the third LED unit LC1, LC2 and LC3) and the spacer 160 may have a double spacer structure, the display device 10C according to this embodiment and Figures 1 to 5 The display device 10 shown is similar. Additionally, unless otherwise specifically described, reference can be made to the... Figures 1 to 5 The components of this embodiment are understood by describing the same or similar components as the display device 10 shown.

[0083] The spacer 160 used in this embodiment may include: a first spacer 161 surrounding the side surface and lower surface of each of a plurality of LED units (e.g., first LED units to third LED units LC1, LC2 and LC3) and having an inclined first side surface, and a second spacer 162 disposed on the first spacer 161 and having an inclined second side surface.

[0084] In this embodiment, the second spacer 162 may be primarily disposed on the first side surface of the first spacer 161. The first and second side surfaces may have profiles that are inclined to each other. The second side surface of the second spacer 162 may further increase the amount of the inclined portion compared to the first side surface of the first spacer 161, and may provide an inclined side surface 160S. The first spacer 161 and the second spacer 162 may comprise SiO2, SiOC, SiON, or SiOCN. In some embodiments, the first spacer 161 and the second spacer 162 may comprise the same material as each other (e.g., SiO2). In this case, the interface between the first spacer 161 and the second spacer 162 may not be visually distinguishable.

[0085] Reference Figure 9 In this embodiment, the inclined side surface 160S of the spacer 160 may have an inclined portion H1, and the inclined portion H1 may extend upward from a covering portion (e.g., the second portion 160b) of the lower surface of the spacer 160 covering each of the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3). The portion of the inclined side surface 160S adjacent to the first conductivity type semiconductor substrate 112B may be retained as a substantially vertical (e.g., almost vertical) portion H2. The inclined portion H1 of the spacer 160 may extend from the covering portion (e.g., the second portion 160b) of the lower surface covering each of the plurality of LED units (e.g., the first LED units to the third LED units LC1, LC2, and LC3) to at least above the level of the active layers (e.g., the first active layer 115R, the second active layer 115G, and the third active layer 115B). In some embodiments, the inclined portion H1 may have 50% or more (e.g., 80% or more) of the total height H of the inclined side surface 160S of the spacer 160.

[0086] In this embodiment, the inclined portion H1 can be extended by introducing a spacer 160 as a dual spacer. For example, a spacer 160 with a dual structure can be obtained by repeatedly depositing and etching back the spacer material (see [link]). Figures 13A to 13D As a result, the light-capturing effect caused by the reflective electrode 130 formed on the spacer 160 can be further enhanced.

[0087] Figures 10A to 10E This is a cross-sectional view illustrating some processes of a method for manufacturing a display device according to an embodiment.

[0088] Reference Figure 10A An epitaxial layer having multiple LED units (e.g., first LED units to third LED units LC1, LC2 and LC3) can be formed on a substrate 101 used for growth.

[0089] In this process, a semiconductor substrate 111 and a first conductivity type semiconductor base layer 112B are sequentially formed on a substrate 101 for growth. Then, a first conductivity type semiconductor layer 112, first active layers to third active layers 115R, 115G, and 115B, and a second conductivity type semiconductor layer 116 are sequentially formed on the first conductivity type semiconductor base layer 112B to form a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) may include first active layers to third active layers 115R, 115G, and 115B configured to emit light of different wavelengths (e.g., colors). A contact electrode 152 may be formed on each of the second conductivity type semiconductor layers 116.

[0090] The substrate 101 used for growth can be a substrate used for nitride single crystal growth. For example, the substrate 101 may include at least one of sapphire, Si, SiC, MgAl2O4, MgO, LiAlO2, LiGaO2, and GaN. The semiconductor underlayer 111, the first conductivity type semiconductor base layer 112B, the first conductivity type semiconductor layer 112, the first active layer to the third active layer 115R, 115G, and 115B, and the second conductivity type semiconductor layer 116 can be formed, for example, using metal-organic chemical vapor deposition (MOCVD), hydrogen vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE) processes.

[0091] In some embodiments, the semiconductor substrate 111 may include a buffer layer and an undoped nitride layer (e.g., GaN). The buffer layer may be used to mitigate lattice defects in the first conductivity type semiconductor layer 112 and may include undoped nitride semiconductors such as undoped GaN, undoped AlN, and undoped InGaN. The first conductivity type semiconductor substrate 112B and the first conductivity type semiconductor layer 112 may be n-type nitride semiconductor layers such as n-type GaN. The first conductivity type semiconductor substrate 112B may include a high concentration of n-type GaN providing contact regions. The second conductivity type semiconductor layer 116 may be a p-type nitride semiconductor layer, such as p-type GaN / p-type AlGaN. The first to third active layers 115R, 115G, and 115B may be single-quantum-well structures or multi-quantum-well structures, such as InGaN / GaN. In some embodiments, multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3) may be formed individually using a selective deposition process, such that the first active layer to the third active layer 115R, 115G, and 115B are formed as epitaxial layers with different compositions. Contact electrode 152 may be formed on the second conductivity type semiconductor layer 116. Contact electrode 152 may include a transparent electrode or a high-reflectivity ohmic contact layer.

[0092] In selective deposition or dry etching processes used to form multiple LED units (e.g., first to third LED units LC1, LC2 and LC3), the side surfaces of the multiple LED units (e.g., first to third LED units LC1, LC2 and LC3) may have damaged regions DR, which have crystal defects.

[0093] Next, refer to Figure 10B The damaged area DR can be removed from the side surfaces of the first LED unit to the third LED units LC1, LC2 and LC3.

[0094] Damaged regions (DR) can cause nonradiative recombination, which may significantly reduce the luminous efficiency of the first to third LED units LC1, LC2, and LC3. In this process, the luminous efficiency of the first to third LED units LC1, LC2, and LC3 can be improved by removing the damaged regions (DR). Figures 11A to 11C As shown, the process of removing the damaged area DR can be performed by wet etching.

[0095] Figures 11A to 11C It is shown Figure 10A A cross-sectional view of an example of a process (e.g., forming an LED cell).

[0096] First, refer to Figure 11A , can Figure 10AA mask 165 is formed on the first to third LED units LC1, LC2 and LC3 shown. The mask 165 may be formed on the contact electrode 152. For example, the mask 165 may include SiO2, SiOC, SiON or SiOCN.

[0097] Then, refer to Figure 11B Mask 165 can be used to apply wet etching to remove the damaged region DR. For example, wet etching can use KOH solution or TMAH solution. After removing the damaged region DR, the cross-sections of the first to third LED units LC1, LC2, and LC3 can change from trapezoidal to rectangular. During the wet etching process, the damaged region DR can be removed, and the side surfaces of the first to third LED units LC1, LC2, and LC3 can have stable crystal planes. For example, the first to third LED units LC1, LC2, and LC3 can have almost vertical side surfaces (e.g., m-planes). As a result, Figure 10B As shown, multiple LED units, each with an almost rectangular cross-section, can be obtained.

[0098] Optionally, the side profiles of the first to third LED units LC1, LC2, and LC3 can be altered by additionally applying this wet etching process. For example... Figure 11C As shown, the cross-sections of the first to third LED units LC1, LC2, and LC3 can be etched from a rectangle into an inverted trapezoidal shape using additional wet etching. The tilt angle θ of the side surfaces of the inverted trapezoids of the first to third LED units LC1, LC2, and LC3 can be less than 90° relative to the lower surface of the first conductivity type semiconductor substrate 112B. This inverted trapezoidal unit structure can be combined with a reflective electrode 130 (e.g., a bowl-shaped reflective electrode) to further enhance the reflective effect (see [reference]). Figure 7 ).

[0099] Next, refer to Figure 10C It can form a spacer 160 that covers multiple LED units (e.g., the first LED unit to the third LED unit LC1, LC2 and LC3).

[0100] Spacers 160 can be formed around the side and top surfaces of multiple LED units (e.g., first to third LED units LC1, LC2, and LC3). As described with respect to the above embodiments, spacers 160 may have inclined side surfaces 160S. See also Figures 12A to 12D The process of forming the spacer 160 used in this embodiment will be described. Figures 12A to 12D It is shown Figure 10C A cross-sectional view of an example of a process (e.g., forming spacers).

[0101] Reference Figure 12A A spacer material layer 160L can be formed on a first conductivity type semiconductor substrate 112B to cover a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The spacer material layer 160L can be formed to cover the upper and side surfaces of the first LED units to third LED units LC1, LC2, and LC3, and can also be formed on the upper surface of the first conductivity type semiconductor substrate 112B. For example, the spacer 160L may include SiO2, SiOC, SiON, or SiOCN. In this embodiment, the spacer material layer 160L can be conformally formed along the surfaces of the first LED units to third LED units LC1, LC2, and LC3, which have rectangular cross-sections. Figure 12A In the cross-section shown, the spacer material layer 160L may also have a rectangular external shape. For example, the spacer material layer 160L can be obtained by repeatedly performing the ALD process until the desired thickness is achieved.

[0102] Then, refer to Figure 12B A mask pattern PR can be formed in each of the regions of the spacer material layer 160L corresponding to the upper surfaces of the first to third LED units LC1, LC2, and LC3. The mask pattern PR used in this process can have sloping side surfaces and can include a photoresist pattern. A portion of the spacer material layer 160L on the side surfaces of the first to third LED units LC1, LC2, and LC3 can be located below the sloping side surfaces of the mask pattern PR. This process can be performed simultaneously with the application of the mask pattern PR by anisotropic etching, such as reactive ion etching. In this etching process, the mask pattern PR can be removed together with the portion of the spacer material layer 160L between the first to third LED units LC1, LC2, and LC3. In the process of removing the mask pattern PR, the portion of the spacer material layer 160L below the sloping side surfaces of the mask pattern PR can be partially removed to have a sloping side surface 160S.

[0103] As a result, Figure 12C As shown, the spacer 160 may include a first portion 160a covering the side surface of each of a plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), and a second portion 160b covering the upper surface of each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). The first portion 160a may have a thickness that increases toward the first conductivity type semiconductor substrate 112B, and the second portion 160b may be a portion located below a flat portion of the mask pattern and may have a nearly constant thickness.

[0104] Optionally, refer to Figure 12D The spacer 160 can be used as a mask to additionally etch the first conductivity type semiconductor substrate 112B to form the recessed RS. In this embodiment, by additionally applying this process, a region of the first conductivity type semiconductor substrate 112B provided as the bottom of the recessed RS between the spacers 160 can be formed, which can be provided as a contact region for a reflective electrode to be formed in a subsequent process. Since the process for the recess can additionally etch to the depth reaching the contact region, the first LED unit to the third LED unit LC1, LC2, and LC3 can be formed with a relatively small height. For example, the aspect ratio of the first LED unit to the third LED unit LC1, LC2, and LC3 can be 1 or less to have a stable structure.

[0105] In some embodiments, the process of forming the spacer can be performed using other processes. For example, forming on Figure 8 and Figure 9 The dual-spacer process used in the display device 10C shown can be achieved through... Figures 13A to 13D The process shown is used to perform this.

[0106] Reference Figure 13A A first spacer material layer 161L can be formed on a first conductivity type semiconductor substrate 112B, such that the first spacer material layer 161L covers the upper and side surfaces of the first LED unit to the third LED units LC1, LC2 and LC3. Then, referring to... Figure 13B Anisotropic etching can be applied to the first spacer material layer 161L. For example, by applying back etching to the first spacer material layer 161L, a treated first spacer 161 with rounded corners on the upper surfaces of the first LED units to the third LED units LC1, LC2, and LC3 can be formed. In this process, the portion of the first spacer material layer 161L between the LED units can be removed. Finally, the first side surface 161S of the first spacer 161 may have a slightly inclined curved surface, at least in the upper region.

[0107] Next, refer to Figure 13C ,and Figure 13ASimilar to the process described above, a second spacer material layer 162L can be deposited on the first to third LED units LC1, LC2, and LC3 on which the first spacer 161 is formed. The second spacer material layer 162L can be formed to cover the upper and side surfaces of the first to third LED units LC1, LC2, and LC3, and can also be formed on the upper surface of the first conductivity type semiconductor substrate 112B. The second spacer material layer 162L can be disposed on the inclined first side surface of the first spacer 161, and can therefore have inclined sidewalls corresponding to the first side surface.

[0108] Next, refer to Figure 13D ,and Figure 13B Similar to the process, a second etch-back process can be applied to the second spacer material layer 162L. For example, by performing a second etch-back process until a portion of the second spacer material layer 162L located on the upper surface of the first conductivity type semiconductor substrate 112B is removed, the second spacer 162 can have a second side surface 162S that is more inclined than the first side surface 161S. As a result, the spacer 160 can have sufficiently inclined sidewalls.

[0109] Next, refer to Figure 10D A reflective electrode 130 may be formed on each of the plurality of LED units (e.g., first LED units to third LED units LC1, LC2, and LC3), and a common electrode 145 and a pad electrode 147 may be formed in the peripheral region of the pixel array 100. Next, a gap-filling insulating layer 141 may be formed on the first conductivity type semiconductor substrate 112B such that the gap-filling insulating layer 141 covers the first LED units to third LED units LC1, LC2, and LC3 and the reflective electrode 130.

[0110] First, a reflective electrode 130 can be formed on the spacer 160 and the region of the first conductivity type semiconductor substrate 112B located between the spacer 160 (see...). Figure 14A The reflective electrode 130 may have a bowl-shaped reflective structure based on the inclined side surface of the spacer 160. The reflective electrode 130 may be electrically connected to the region of the first conductivity type semiconductor substrate 112B between multiple LED units (e.g., the first LED unit to the third LED units LC1, LC2, and LC3). Next, a common electrode 145 and a pad electrode 147 may be formed on the connection region CR and the pad region PAD, respectively. The common electrode 145 may be connected to the first conductivity type semiconductor substrate 112B. The common electrode 145 may be formed on the extension portion 130E of the reflective electrode 130. The common electrode 145 and the pad electrode 147 may be formed together in the same process.

[0111] A portion of the reflective electrode 130 located on the upper surface of the plurality of LED units (e.g., the first to the third LED units LC1, LC2, and LC3) can be removed, and the gap-filling insulating layer 141 can be formed to cover the upper surface of the semiconductor stack 110 on which the reflective electrode 130 is formed (see [link to documentation]). Figure 14B The gap-filling insulating layer 141 may be formed to cover the upper surface of the semiconductor stack 110 on which the reflective electrode 130 is formed, and then a planarization process such as chemical mechanical polishing (CMP) or etching back process may be used to perform a planarization process for the gap-filling insulating layer 141. For example, as described above, the gap-filling insulating layer 141 may be formed of silicon oxide.

[0112] Next, refer to Figure 10E A contact hole CH can be formed that penetrates the gap to fill the insulating layer 141, the reflective electrode 130 and the spacer 160, and an insulating liner 170 can be formed on the inner wall of the contact hole CH, and then a connecting electrode 155 connected to the contact electrode 152 can be formed.

[0113] This process can be achieved through Figures 15A to 15D The self-alignment process shown is used to perform this.

[0114] First, refer to Figure 15A A contact hole CH can be formed that penetrates the gap to fill the insulating layer 141, the reflective electrode 130, and the spacer 160. In this embodiment, the contact hole CH can be formed such that a portion of the contact electrode 152 is exposed. The contact hole CH can be formed by an etching process. For example, depending on the material, the etching process can be performed by a combination of multiple etching processes or a single etching process. The reflective electrode 130 can be exposed from the inner sidewall of the contact hole CH. The exposed portion of the reflective electrode 130 can be configured to surround the contact hole CH.

[0115] Next, refer to Figure 15B A liner material layer 170L can be conformally formed on the upper surface of the gap-filling insulating layer 141 and the inner surface of the contact hole CH. Inside the contact hole CH, the liner material layer 170L can be formed to cover not only the inner sidewall of the contact hole CH but also the portion of the contact electrode 152 located at the bottom of the contact hole CH. For example, the liner material layer 170L may include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or combinations thereof. For example, this process can be performed by an ALD process.

[0116] Next, refer to Figure 15CAn insulating liner 170 can be formed on the inner wall of the contact hole CH by partially removing the liner material layer 170L. In this process, an anisotropic etching process can be used to remove portions of the liner material layer 170L on the upper surface of the gap-filling insulating layer 141 and on the bottom of the contact hole CH. As a result, a portion of the contact electrode 152 on the bottom of the contact hole CH can be exposed again, and the insulating liner 170 can self-align on the inner wall of the contact hole CH. In this embodiment, the insulating liner 170 can extend from the upper end of the contact hole CH to the contact electrode 152.

[0117] Next, refer to Figure 15D A connection electrode 155 can be formed in the contact hole CH, connecting to each of the contact electrodes 152 (e.g., first LED units to third LED units LC1, LC2, and LC3). The connection electrode 155 can be electrically connected to the second conductivity type semiconductor layer 116 via the contact electrode 152. The connection electrode 155 may include pads located on the upper surface of the gap-filling insulating layer 141. The width of the pads of the connection electrode 155 may be greater than the width of each of the multiple LED units (e.g., first LED units to third LED units LC1, LC2, and LC3). In this way, the pads of the connection electrode 155 can be provided as a complementary reflective structure for the small amount of light leaking through the insulating liner 170.

[0118] In some embodiments, the process for forming the connection electrodes can be performed using other processes. For example, forming on Figure 6 The process of the insulating liner 170' used in the display device 10A shown can be achieved through... Figures 16A to 16D The process shown is used to perform this.

[0119] First, refer to Figure 16A A contact hole CH' can be formed that penetrates the gap-filling insulating layer 141 and the reflective electrode 130. In this embodiment, the contact hole CH' can be formed such that a portion of the spacer 160 can be exposed. In this process, etching for removing the gap-filling insulating layer 141 and etching for removing the reflective electrode can be performed sequentially. Also in this embodiment, the reflective electrode 130 can be exposed on the inner sidewall of the contact hole CH'.

[0120] Next, refer to Figure 16B A lining material layer 170L' can be conformally formed on the upper surface of the gap-filling insulating layer 141 and the inner surface of the contact hole CH'. The lining material layer 170L' within the contact hole CH' can be formed to cover the inner sidewall of the contact hole CH' and the portion of the spacer 160 exposed at the bottom of the contact hole CH'.

[0121] Next, refer to Figure 16CAn insulating liner 170' can be formed on the inner wall of the contact hole CH' by partially removing the liner material layer 170L'. In this process, an anisotropic etching process can be used to remove portions of the liner material layer 170L' on the upper surface of the gap-filling insulating layer 141 and the bottom of the contact hole CH'. In this etching process, a portion of the spacer 160 can be exposed at the bottom of the contact hole CH', and the exposed portion of the spacer 160 can also be etched to open the contact area on the upper surface of the first LED unit to the third LED unit LC1, LC2 and LC3. The insulating liner 170' can extend from the upper end of the contact hole CH', but can be separated from the contact area on the upper surface of the first LED unit to the third LED unit LC1, LC2 and LC3 by the spacer 160.

[0122] Next, refer to Figure 16D A connection electrode 155 can be formed in the contact hole CH' to connect to each of the plurality of LED units (e.g., the first LED unit to the third LED units LC1, LC2 and LC3). In this embodiment, the connection electrode 155 can be electrically isolated from the reflective electrode 130 through the insulating liner 170'.

[0123] Figures 17A to 17C This is a cross-sectional view illustrating other processes of a method for manufacturing a display device according to an embodiment.

[0124] First, refer to Figure 17A A pixel array structure including first LED units to third LED units LC1, LC2 and LC3 can be bonded to circuit board 200 (see...). Figure 17C ).

[0125] The circuit board 200 can be fabricated using a separate process. The pixel array 100 can be bonded at the wafer level using wafer bonding methods such as, for example, the hybrid bonding described above (see...). Figure 17C The pixel array 100, including the first LED units to the third LED units LC1, LC2, and LC3, and the circuit board 200, as described above, may include a lower bonding structure having a lower bonding insulating layer 291 and lower bonding electrodes 295A to 295D. The lower bonding electrodes 295A to 295D may be bonded to the upper bonding electrodes 195A to 195D, and the lower bonding insulating layer 291 may be bonded to the upper bonding insulating layer 191. In this way, the pixel array 100 and the circuit board 200, including the first LED units to the third LED units LC1, LC2, and LC3, can be bonded without a separate adhesive layer.

[0126] Next, refer to Figure 17B The substrate 101 used for growth can be removed (see...) Figure 17A And a portion of the semiconductor stack 110 (e.g., semiconductor underlayer 111) can be removed.

[0127] The substrate 101 used for growth can be removed by various processes such as laser lift-off, mechanical polishing or mechanical-chemical polishing, and etching. The semiconductor substrate 111 can be partially removed and reduced to a predetermined thickness using a polishing process such as CMP. After removing the semiconductor substrate 111, a first conductivity type semiconductor base layer 112B can be exposed. Additionally, the first conductivity type semiconductor base layer 112B located in the pad region PAD can be removed.

[0128] Then, refer to Figure 17C It can be manufactured by additionally forming microlenses 180 and bonding pads. Figure 3 and Figure 4 The display device 10 shown is shown.

[0129] Figure 18 This is a schematic diagram of an electronic device including a display device according to an embodiment.

[0130] Reference Figure 18 The electronic device 1000 according to this embodiment can be an eyeglass display, which can be a wearable device. The electronic device 1000 may include a pair of temples 1100, a pair of optically coupled lenses 1200, and a bridge 1300. The electronic device 1000 may also include a display device (e.g., display devices 10, 10A, 10B, and 10C) that includes an image generation unit.

[0131] The electronic device 1000 may be a virtual reality (VR) device, augmented reality (AR) device, or mixed reality (MR) device with a head-mounted, glasses-style, or goggles-style design, which can provide virtual reality or can provide virtual images and real external scenery together.

[0132] Temples 1100 may extend in one direction. Temples 1100 may extend parallel to each other and be spaced apart. Temples 1100 may be folded toward beam 1300 using a hinge connection. Beam 1300 may be disposed between optically coupled lenses 1200 to connect the optically coupled lenses 1200 to each other. Optically coupled lenses 1200 may include light guide plates. Display devices 10, 10A, 10B, and 10C may be disposed in portions of temples 1100 adjacent to optically coupled lenses 1200, and may generate images on optically coupled lenses 1200. In some embodiments, display devices 10, 10A, 10B, and 10C may be disposed in regions of optically coupled lenses 1200.

[0133] A bowl-shaped reflective electrode can be formed on each miniature LED unit in a manner that minimizes light leakage while preventing unwanted contact with different electrodes. This reflective structure allows for adjustment of the beam angle of each LED unit to collect light and improves light efficiency in the desired region.

[0134] The various advantages and effects of the embodiments of this disclosure are not limited to those described above, and other advantages and effects of the embodiments of this disclosure will be understood based on the above description.

[0135] Although non-limiting example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A display device, comprising: Semiconductor stacks, comprising: A first conductivity type semiconductor substrate, comprising an upper surface configured as a light-emitting surface; and A light-emitting diode unit, located on the lower surface of a first conductivity type semiconductor substrate, the light-emitting diode unit comprising an active layer and a second conductivity type semiconductor layer sequentially stacked on the lower surface of the first conductivity type semiconductor substrate; A spacer, which is located on the side and lower surfaces of the light-emitting diode unit, the spacer including an inclined outer sidewall; A reflective electrode, which is located on the spacer and connected to the first type of conductive semiconductor substrate; An insulating layer is filled in the gaps on the lower surface of the semiconductor stack and on the reflective electrode; A connecting electrode, which passes through a contact hole penetrating the gap-filling insulating layer, the reflective electrode, and the spacer, and connects to the second conductivity type semiconductor layer of the light-emitting diode unit; and An insulating liner is provided along the inner sidewall of the contact hole and electrically insulates the connecting electrode and the reflecting electrode.

2. The display device according to claim 1, wherein, The insulating liner is located in the contact hole and does not extend to the lower surface of the gap-filling insulating layer.

3. The display device according to claim 1, wherein, In a cross-section taken along a plane extending in the thickness direction of the semiconductor stack, the insulating liner includes a first portion and a second portion facing each other on the inner sidewall of the contact hole, and the thickness deviation between the first portion and the second portion is 10% or less.

4. The display device according to claim 1, wherein, The insulating liner extends from the upper end of the contact hole to the lower surface of the light-emitting diode unit.

5. The display device according to claim 4, wherein, The light-emitting diode unit also includes a contact electrode on the lower surface of the semiconductor layer of the second conductivity type.

6. The display device according to claim 1, wherein, The insulating liner extends from the upper end of the contact hole toward the light-emitting diode unit and is separated from the light-emitting diode unit by the spacer.

7. The display device according to claim 6, wherein, The lower surface of the light-emitting diode unit is defined by a semiconductor layer of the second conductivity type, and the connection electrode is connected to the semiconductor layer of the second conductivity type.

8. The display device according to claim 1, wherein, The first type of conductive semiconductor substrate includes a recess between the light-emitting diode unit and an adjacent light-emitting diode unit, and The reflective electrode is connected to the area of ​​the first conductive type semiconductor substrate exposed at the bottom of the recess.

9. The display device according to claim 1, wherein, The side surface of the light-emitting diode unit is perpendicular to the lower surface of the first conductivity type semiconductor substrate.

10. The display device according to claim 1, wherein, The lower surface of the light-emitting diode unit has a second width, which is greater than the first width of the light-emitting diode unit on the lower surface of the first conductivity type semiconductor substrate.

11. The display device according to claim 1, wherein, The connecting electrode includes: Through member, which is in the contact hole; and A pad connected to the through-hole, the pad being on the lower surface of the gap-filling insulating layer.

12. The display device according to claim 11, wherein, The pad of the connecting electrode has a width greater than the width of the light-emitting diode unit.

13. The display device according to claim 1, wherein, At least one of the reflective electrode and the connecting electrode includes at least one of Ag, Cr, Ni, Ti, Al, Rh and Ru.

14. The display device according to claim 1, wherein, The spacer includes: The first portion on the side surface of the light-emitting diode unit; and The second portion on the lower surface of the light-emitting diode unit, The first portion has an increasing thickness toward the semiconductor substrate of the first conductivity type.

15. The display device according to claim 14, wherein, The portion of the spacer adjacent to the lower edge of the light-emitting diode unit has a thickness smaller than that of each of the first and second portions.

16. The display device according to claim 1, wherein, The spacer includes: A first spacer includes an inclined first side surface on the side surface and the lower surface of the light-emitting diode unit, and The second spacer includes an inclined second side surface on the first spacer.

17. The display device of claim 1, further comprising a passivation layer below the spacer on the side surface and the lower surface of the light-emitting diode unit.

18. The display device according to claim 17, wherein, The passivation layer includes at least one of ZrO2, Al2O3, and HfO2.

19. A display device, comprising: A pixel array comprising multiple pixel units, each of which includes multiple sub-pixels. The pixel array includes: Semiconductor stacks, comprising: A first conductivity type semiconductor substrate, comprising an upper surface configured as a light-emitting surface; and A light-emitting diode unit is located on the lower surface of a first type of conductive semiconductor substrate, the light-emitting diode unit comprising an active layer and a second type of conductive semiconductor layer; A spacer, which is located on the side surface of the light-emitting diode unit and on the lower surface of the light-emitting diode unit, the spacer including an inclined outer sidewall; A reflective electrode, which is located on the spacer and connected to the region of the first type of conductive semiconductor substrate; An insulating layer is filled in the gaps on the lower surface of the semiconductor stack and on the reflective electrode; A connecting electrode, which passes through a contact hole penetrating the gap-filling insulating layer, the reflective electrode, and the spacer, and connects to the second conductivity type semiconductor layer of the light-emitting diode unit; and An insulating liner extends along the inner wall of the contact hole from the upper end of the contact hole to the lower surface of the light-emitting diode unit. Wherein, the region of the lower surface of the first conductivity type semiconductor substrate between the light-emitting diode units includes: A first region, wherein the spacer is located in the first region; and The second region is recessed between the first regions, and The reflective electrode is connected to the second region along the outer wall of the spacer.

20. A display device, comprising: A pixel array comprising multiple pixel units, each of which includes multiple sub-pixels. The pixel array includes: Semiconductor stacks, comprising: A first conductivity type semiconductor substrate includes an upper surface configured as a light-emitting surface, and A light-emitting diode unit is located on the lower surface of a first conductivity type semiconductor substrate, and the light-emitting diode unit includes an active layer and a second conductivity type semiconductor layer. A spacer, which is located on the side surface of the light-emitting diode unit and on the lower surface of the light-emitting diode unit, the spacer including an inclined outer sidewall; A reflective electrode, which is located on the spacer and connected to the region of the first type of conductive semiconductor substrate; An insulating layer is filled in the gaps on the lower surface of the semiconductor stack and on the reflective electrode; A connecting electrode, which passes through a contact hole penetrating the gap-filling insulating layer, the reflective electrode, and the spacer, and connects to the second conductivity type semiconductor layer of the light-emitting diode unit; and An insulating liner extends from the upper end of the contact hole along the inner sidewall of the contact hole, and the insulating liner is separated from the lower surface of the light-emitting diode unit by the spacer.

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