Display panel, preparation method thereof and display device

Abstract

This application discloses a display panel and its fabrication method, as well as a display device, belonging to the field of display technology. The display panel includes an array substrate, a planarization layer, an anode, an auxiliary planarization layer, and a pixel definition layer. Located on the array substrate, the planarization layer has vias communicating with the array substrate; located on the planarization layer and electrically connected to the array substrate through the vias, the anode has a recessed portion formed on the side facing away from the planarization layer; located on the anode, at least a portion of the auxiliary planarization layer is located within the recessed portion; located on the auxiliary planarization layer; wherein, the pixel definition layer has pixel definition openings, and the orthographic projection of the pixel definition openings on the array substrate does not intersect with the orthographic projection of the auxiliary planarization layer on the array substrate. The display panel of this application can reduce the deformation of the pixel definition openings, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have become one of the mainstream display technologies and are widely used in various terminal devices. An OLED display panel typically includes an array substrate and, sequentially formed on it, a planarization layer, an anode, a pixel definition layer, an organic light-emitting layer, a cathode, and an encapsulation layer. The anode is connected to the array substrate through an opening in the planarization layer. The pixel definition layer has pixel openings that expose the underlying anode portion. The organic light-emitting layer and the cathode are formed sequentially within the pixel openings and on the pixel definition layer, respectively.

[0003] However, as the pixel density of display panels continues to increase, the distance between the openings on the planarization layer and the pixel openings also decreases. Because the openings in the planarization layer form recessed areas, and the pixel definition layer is typically made of a material with a certain degree of fluidity, the pixel definition layer tends to flow and accumulate towards the openings in the planarization layer. This causes deformation of the pixel openings in the pixel definition layer. This deformation leads to abnormal shapes and uneven sizes of the pixel light-emitting areas, resulting in problems such as uneven display brightness and color shift. Summary of the Invention

[0004] This application provides a display panel and its manufacturing method, as well as a display device, which can reduce the deformation of pixel definition openings to improve the display effect of the display panel.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0006] Array substrate; A planarization layer is located on the array substrate, and the planarization layer is provided with vias communicating with the array substrate; An anode is located on the planarization layer and is electrically connected to the array substrate through the via. A recess is formed on the side of the anode facing away from the planarization layer. An auxiliary planarization layer is located on the anode, and at least a portion of the auxiliary planarization layer is located within the recess. A pixel definition layer is located on the auxiliary planarization layer; The pixel definition layer is provided with a pixel definition opening, and the orthographic projection of the pixel definition opening on the array substrate does not intersect with the orthographic projection of the auxiliary planarization layer on the array substrate.

[0007] Optionally, the auxiliary planarization layer includes a first planarization portion and a second planarization portion, wherein the orthographic projection of the first planarization portion on the array substrate is outside the orthographic projection of the anode on the array substrate, and the orthographic projection of the second planarization portion on the array substrate is within the orthographic projection range of the anode on the array substrate.

[0008] Optionally, the top surface of the first flat portion facing away from the flat layer is flush with the top surface of the second flat portion facing away from the flat layer.

[0009] Optionally, the orthographic projection of the auxiliary planarization layer on the array substrate is located within the orthographic projection range of the anode on the array substrate.

[0010] Optionally, the auxiliary planarization layer is provided with a flat opening corresponding to the pixel definition opening, the flat opening exposing at least a portion of the anode, and the orthographic projection of the pixel definition opening on the array substrate lies within the orthographic projection range of the flat opening on the array substrate; or, The orthographic projection of the auxiliary planarization layer on the array substrate coincides with the orthographic projection of the recessed portion on the array substrate.

[0011] Optionally, the orthographic projection of the via on the array substrate does not intersect with the orthographic projection of the pixel defining opening on the array substrate; and / or, The material of the auxiliary planarization layer is the same as that of the planarization layer.

[0012] According to a second aspect of this application, a display device is provided, comprising a display panel as described in any one of the above.

[0013] According to a third aspect of this application, a method for manufacturing a display panel is provided, comprising: Provide array substrate; A planarization layer is formed on the array substrate, and a via is formed on the planarization layer to connect to the array substrate; An anode is formed on the planarization layer, and the anode is electrically connected to the array substrate through the via. A recess is formed on the side of the anode facing away from the planarization layer. An auxiliary planarization layer is formed on the anode, and at least a portion of the auxiliary planarization layer is located within the recess. A pixel definition layer is formed on the auxiliary planarization layer, and a pixel definition opening is formed on the pixel definition layer. The orthographic projection of the pixel definition opening on the array substrate does not intersect with the orthographic projection of the auxiliary planarization layer on the array substrate.

[0014] Optionally, the auxiliary planarization layer includes a first planarization portion and a second planarization portion. The orthographic projection of the first planarization portion on the array substrate is outside the orthographic projection of the anode on the array substrate, and the orthographic projection of the second planarization portion on the array substrate is within the orthographic projection range of the anode on the array substrate. The first planarization portion is provided with a planar opening corresponding to the pixel definition opening, and the orthographic projection of the pixel definition opening on the array substrate is within the orthographic projection range of the planar opening on the array substrate.

[0015] Optionally, the orthographic projection of the auxiliary planarization layer on the array substrate is located within the orthographic projection range of the anode on the array substrate; The auxiliary planarization layer is provided with a planar opening corresponding to the pixel definition opening, and the orthographic projection of the pixel definition opening on the array substrate is located within the orthographic projection range of the planar opening on the array substrate; or... The orthographic projection of the auxiliary planarization layer on the array substrate coincides with the orthographic projection of the recessed portion on the array substrate.

[0016] In the display panel and its preparation method and display device of the present application embodiments, by providing an auxiliary planarization layer on the anode, and at least part of the auxiliary planarization layer being located in the recess, the auxiliary planarization layer can fill the recess, thereby preventing the material of the pixel definition layer from flowing into the recess, thereby reducing or avoiding deformation of the pixel definition opening, and thus improving the display effect of the display panel.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a schematic diagram of a first type of display panel provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a second type of display panel provided in an exemplary embodiment of this disclosure; Figure 3This is a schematic diagram of a third type of display panel provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of a fourth type of display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of a fifth type of display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of a sixth type of display panel provided in an exemplary embodiment of this disclosure; Figure 7 This is a flowchart of a method for manufacturing a display panel provided in an exemplary embodiment of this disclosure.

[0021] Explanation of reference numerals in the attached figures: 1. Array substrate; 11. Substrate; 111. First substrate; 112. Buffer layer; 113. Second substrate; 12. Barrier layer; 13. Driving circuit; 131. Active layer; 132. Gate; 1321. First gate; 1322. Second gate; 133. Source; 134. Drain; 14. Gate insulating layer; 141. First gate insulating layer; 142. Second gate insulating layer; 15. Interlayer dielectric layer; 2. Planarization layer; 21. Via; 3. Anode; 31. Recess; 4. Auxiliary planarization layer; 41. First planarization portion; 42. Second planarization portion; 43. Planarization opening; 5. Pixel definition layer; 51. Pixel definition opening; 6. Light-emitting layer; 7. Cathode; 8. Encapsulation layer. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "up," "down," "left," and "right" generally refer to up, down, left, and right in the actual use or working state of the device, specifically the drawing directions in the accompanying drawings.

[0023] In this application, unless otherwise expressly specified and limited, the terms "connected," "linked," "stacked," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] This application provides a display panel, a method for manufacturing the same, and a display device, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0025] According to the first aspect of this application, referring to Figure 1 One embodiment of this application provides a display panel, which may include: an array substrate 1, a planarization layer 2, an anode 3, an auxiliary planarization layer 4, and a pixel definition layer 5.

[0026] Specifically, refer to Figure 1 The array substrate 1 may include a substrate 11, a barrier layer 12, a driving circuit 13, a gate insulating layer 14, and an interlayer dielectric layer 15. The barrier layer 12 may be disposed on the substrate 11, the gate insulating layer 14 may be disposed on the barrier layer 12, and the interlayer dielectric layer 15 may be disposed on the gate insulating layer 14.

[0027] The substrate 11 serves as the supporting base for the entire array substrate 1. The substrate 11 may include a first substrate 111, a buffer layer 112, and a second substrate 113. The buffer layer 112 may be disposed between the first substrate 111 and the second substrate 113, and the second substrate 113 may be disposed between the barrier layer 12 and the buffer layer 112.

[0028] The first substrate 111 can be a glass substrate, a flexible polymer substrate (such as a polyimide (PI) substrate), etc. Glass substrates have advantages such as high mechanical strength, good light transmittance, and good heat resistance, making them suitable for rigid display panels. Flexible polymer substrates have advantages such as good flexibility, bendability, and light weight, making them suitable for flexible display panels.

[0029] The buffer layer 112 can reduce the stress difference between the first substrate 111 and the second substrate 113, thereby improving the overall structural stability of the substrate 11. At the same time, it can also prevent impurity ions in the first substrate 111 from diffusing to subsequent functional layers, thus avoiding affecting the performance of the driving circuit 13. The material of the buffer layer 112 can be silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0030] The second substrate 113 may be made of the same or different material as the first substrate 111. The second substrate 113 can further enhance the mechanical strength and stability of the substrate 11, providing a flat and stable substrate for the fabrication of subsequent structural layers such as the barrier layer 12 and the driving circuit 13. In this embodiment, the second substrate 113 is made of the same material as the first substrate 111.

[0031] The barrier layer 12 can be disposed on the substrate 11, that is, the barrier layer 12 can be disposed on the side of the second substrate 113 opposite to the buffer layer 112. The barrier layer 12 can prevent harmful gases such as moisture and oxygen from entering the interior of the display panel, and prevent functional layers such as the driving circuit 13 and the light-emitting layer 6 from being oxidized or corroded, thereby improving the service life of the display panel. The material of the barrier layer 12 can be an inorganic insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx), which have good barrier properties and chemical stability.

[0032] The driving circuit 13 is used to drive each pixel unit to emit light independently. The driving circuit 13 may include an active layer 131, a gate 132, a source 133, and a drain 134. The active layer 131 can be disposed on the barrier layer 12, and the material of the active layer 131 can be low-temperature polycrystalline silicon (LTPS), amorphous silicon (a-Si), or oxide semiconductors (such as IGZO, IZO, etc.). Low-temperature polycrystalline silicon has the advantage of high carrier mobility, enabling high integration and high performance of the driving circuit 13. Oxide semiconductors have the characteristics of good light transmittance, simple fabrication process, and low cost, making them suitable for large-size, high-resolution display panels. In this embodiment, the active layer 131 can be made of low-temperature polycrystalline silicon to achieve high integration and high performance of the driving circuit 13.

[0033] A gate insulating layer 14 can be disposed on the barrier layer 12 and cover the active layer 131. The gate insulating layer 14 can achieve electrical insulation between the gate 132 and the active layer 131. In this embodiment, the gate insulating layer 14 may include a first gate insulating layer 141 and a second gate insulating layer 142 sequentially disposed along a direction away from the substrate 11. The use of a stacked structure can further improve the insulation performance and reliability of the gate insulating layer 14. The materials of the first gate insulating layer 141 and the second gate insulating layer 142 can be silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0034] Gate 132 can be disposed on gate insulating layer 14 and used to control the transport of charge carriers in active layer 131. In this embodiment, gate 132 may include a first gate 1321 and a second gate 1322. The first gate 1321 may be located on the first gate insulating layer 141, and the second gate 1322 may be located on the second gate insulating layer 142, forming a dual-gate 132 structure. The dual-gate 132 structure can enhance the control capability of charge carriers in active layer 131, improve the switching speed and stability of drive circuit 13, and reduce leakage current. The material of gate 132 can be a metal material, such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or their alloys, or a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0035] An interlayer dielectric layer 15 can be disposed on the gate insulating layer 14 and cover the gate 132. The interlayer dielectric layer 15 can achieve electrical insulation between the gate 132 and the source 133 and drain 134, while providing a flat surface for the fabrication of the source 133 and drain 134. The material of the interlayer dielectric layer 15 can be silicon oxide (SiOx), silicon nitride (SiNx), or organic insulating materials, such as polyimide (PI) or benzocyclobutene (BCB).

[0036] The source electrode 133 and drain electrode 134 can be disposed on the side of the interlayer dielectric layer 15 away from the gate insulating layer 14, and both the source electrode 133 and drain electrode 134 can pass through the interlayer dielectric layer 15 and the gate insulating layer 14 to connect to the active layer 131. The source electrode 133 and drain electrode 134 serve as the signal input and output terminals of the driving circuit 13, used to transmit external driving signals to the active layer 131 and transmit driving signals from the active layer 131 to the anode 3. The materials of the source electrode 133 and drain electrode 134 can be metal materials or alloys, or different material combinations can be used to optimize their conductivity and process compatibility. In this embodiment, both the source electrode 133 and drain electrode 134 can adopt a three-layer metal structure of titanium / aluminum / titanium (Ti / Al / Ti), which has both good conductivity and can improve the adhesion to the interlayer dielectric layer 15 and the active layer 131.

[0037] Reference Figure 1 The planarization layer 2 can be located on the array substrate 1, that is, the planarization layer 2 can be located on the side of the interlayer dielectric layer 15 facing away from the gate insulating layer 14. The planarization layer 2 can further planarize the surface of the array substrate 1, providing a flat substrate for the subsequent fabrication of the anode 3, and at the same time, it can also protect the driving circuit 13 in the array substrate 1 from damage in subsequent processes. The material of the planarization layer 2 can be an organic insulating material, such as photosensitive polyimide (PSPI), acrylic materials, siloxane materials, etc.

[0038] The planarization layer 2 may have vias 21 connecting to the array substrate 1, with at least a portion of the array substrate 1 exposed through the vias 21. As an example, the vias 21 may penetrate the planarization layer 2, allowing the drain 134 in the array substrate 1 to be exposed through the vias 21, so that the anode 3 can be electrically connected to the drain 134 via the vias 21. The number and location of the vias 21 may correspond to the number and location of the pixel units in the display panel, with each pixel unit corresponding to one via 21.

[0039] Reference Figure 1 The anode 3 can be located on the planarization layer 2 and electrically connected to the array substrate 1 through a via 21. A recess 31 can be formed on the side of the anode 3 facing away from the planarization layer 2. As an example, the anode 3 can cover at least a portion of the surface of the planarization layer 2 and the inner wall of the via 21, and is electrically connected to the drain 134 exposed in the via 21. The anode 3 serves as the anode electrode of the pixel unit and is used to inject holes into the light-emitting layer 6. In some embodiments, refer to... Figure 2 The planarization layer 2 can be a multi-layer structure, and at least part of the source 133 and / or at least part of the drain 134 can be located inside the planarization layer 2.

[0040] The anode 3 material can be a transparent conductive oxide (TCO), silver (Ag), etc. Examples of transparent conductive oxides (TCOs) include indium tin oxide (ITO), indium zinc oxide (IZO), and tin oxide (SnO2). Among these, ITO is widely used in the fabrication of the anode 3 in display panels due to its high conductivity, high light transmittance, and good process compatibility. In this embodiment, the anode 3 can be made of ITO material, with a thickness of, for example, 1 nm to 100 nm, which meets the requirements for conductivity and light transmittance.

[0041] Reference Figure 1 The auxiliary planarization layer 4 can be located on the anode 3, and at least part of the auxiliary planarization layer 4 can be located within the recess 31. The auxiliary planarization layer 4 is used to fill the recess 31 formed on the surface of the anode 3 by the via 21, providing a flat substrate for the subsequent fabrication of the pixel definition layer 5. The material of the auxiliary planarization layer 4 can be the same as that of the planarization layer 2, which can reduce the difficulty of material selection, simplify the process flow, reduce production costs, and ensure compatibility between the auxiliary planarization layer 4 and the planarization layer 2.

[0042] The thickness of the auxiliary leveling layer 4 can be adjusted according to the depth of the recess 31 and the thickness of the anode 3 to ensure that the recess 31 can be completely filled and the upper surface of the auxiliary leveling layer 4 remains flat.

[0043] Reference Figure 1The pixel definition layer 5 can be located on the auxiliary planarization layer 4. The pixel definition layer 5 defines the light-emitting area of ​​each pixel unit, preventing color mixing between the light-emitting materials of adjacent pixel units and ensuring the clarity and color purity of the displayed image. The material of the pixel definition layer 5 can be the same as that of the auxiliary planarization layer 4, which reduces the difficulty of material selection and manufacturing costs, while ensuring compatibility between the pixel definition layer 5 and the auxiliary planarization layer 4. Alternatively, the material of the pixel definition layer 5 can be different from that of the auxiliary planarization layer 4.

[0044] Among them, reference Figure 1 The pixel definition layer 5 may be provided with pixel definition openings 51. The orthographic projection of the pixel definition opening 51 on the array substrate 1 does not intersect with the orthographic projection of the auxiliary planarization layer 4 on the array substrate 1. The pixel definition openings 51 are the light-emitting areas of the pixel units, and their number and position can correspond to the number and position of the pixel units. Each pixel unit can correspond to one pixel definition opening 51. Since the auxiliary planarization layer 4 can fill the recess 31, it can reduce the flow and aggregation of material in the pixel definition layer 5 due to the difference in bottom morphology, and can prevent the pixel definition openings 51 from deforming. The shape of the pixel definition openings 51 can be a regular polygon (such as a square, rectangle, hexagon, etc.) or a circle, etc., and the shape of the pixel definition openings 51 can be selected according to the design requirements of the display panel.

[0045] In some embodiments, refer to Figure 1 The orthographic projection of via 21 on array substrate 1 does not intersect with the orthographic projection of pixel definition opening 51 on array substrate 1. This ensures that the area corresponding to via 21 is separated from the light-emitting area corresponding to pixel definition opening 51, avoiding the influence of the structure of via 21 area on the light-emitting effect of light-emitting layer 6, and further preventing the pixel definition layer 5 from deforming in the via 21 area.

[0046] In this application, by providing an auxiliary planarization layer 4 on the anode 3, with at least a portion of the auxiliary planarization layer 4 located within the recess 31, the auxiliary planarization layer 4 can fill the recess 31. This prevents the material of the pixel definition layer 5 from flowing into the recess 31, thereby reducing or preventing deformation of the pixel definition opening 51, improving the uniformity of the displayed image, and thus improving the display effect of the display panel. Simultaneously, this application eliminates the need to increase the distance between the via 21 and the pixel definition opening 51 to prevent deformation of the pixel definition opening 51, which is beneficial for the development of display panels towards higher pixel density and higher resolution. Furthermore, by improving the quality of the pixel definition layer 5, defects such as abnormal light emission and short circuits caused by deformation of the pixel definition layer 5 are reduced, thereby improving the production yield of the display panel and reducing production costs.

[0047] In some embodiments, refer to Figure 1 and Figure 3 The auxiliary planarization layer 4 may include a first planarization portion 41 and a second planarization portion 42. The orthographic projection of the first planarization portion 41 onto the array substrate 1 may be outside the orthographic projection of the anode 3 onto the array substrate 1, and the orthographic projection of the second planarization portion 42 onto the array substrate 1 may be within the orthographic projection range of the anode 3 onto the array substrate 1. That is, the first planarization portion 41 covers at least a portion of the surface of the planarization layer 2, and the second planarization portion 42 covers the surface of the anode 3 and the recess 31. This can further improve the coverage of the auxiliary planarization layer 4, which can not only prevent the pixel definition layer 5 from deforming in the via 21 area, but also prevent deformation in other areas of the pixel definition layer 5, while improving the connection stability between the auxiliary planarization layer 4 and the planarization layer 2.

[0048] In some embodiments, refer to Figure 1 The top surface of the first flat portion 41 facing away from the flattening layer 2 can be flush with the top surface of the second flat portion 42 facing away from the flattening layer 2. This can further improve the flatness of the side of the auxiliary flattening layer 4 facing the pixel definition layer 5, thereby preventing the pixel definition layer 5 from deforming and improving the display effect of the display panel.

[0049] In some embodiments, refer to Figures 4 to 6 The orthographic projection of the auxiliary planarization layer 4 onto the array substrate 1 can be located within the orthographic projection range of the anode 3 onto the array substrate 1. That is, the auxiliary planarization layer 4 only covers at least a portion of the surface and recess 31 of the anode 3, and does not extend to the surface of the planarization layer 2.

[0050] In some embodiments, refer to Figure 1 , Figure 3 and Figure 4 The auxiliary planarization layer 4 may have a flat opening 43 corresponding to the pixel definition opening 51. The flat opening 43 exposes at least a portion of the anode 3, and the orthographic projection of the pixel definition opening 51 onto the array substrate 1 may fall within the orthographic projection range of the flat opening 43 onto the array substrate 1. The flat opening 43 may penetrate the auxiliary planarization layer 4, allowing a portion of the anode 3 surface to be exposed through the flat opening 43, so that the subsequent light-emitting layer 6 can make electrical contact with the anode 3. The position of the flat opening 43 may correspond to the position of the pixel definition opening 51, with each pixel definition opening 51 corresponding to one flat opening 43. The size of the flat opening 43 needs to be greater than or equal to the size of the pixel definition opening 51 to ensure that the pixel definition opening 51 is completely within the range of the flat opening 43, preventing the auxiliary planarization layer 4 from obstructing the pixel definition opening 51 of the pixel definition layer 5, thus affecting the formation and light emission effect of the light-emitting layer 6. As an example, the side length of the flat opening 43 is 0.5 μm to 10 μm longer than the side length of the pixel definition opening 51.

[0051] Reference Figure 1When the auxiliary planarization layer 4 includes a first planarization portion 41 and a second planarization portion 42, the second planarization portion 42 may be provided with a planar opening 43. The planar opening 43 may be a closed annular structure and is provided around the pixel-defined opening 51. In some embodiments, the planar opening 43 may also be a non-closed annular structure.

[0052] Reference Figure 4 When the orthographic projection of the auxiliary planarization layer 4 onto the array substrate 1 is within the orthographic projection range of the anode 3 onto the array substrate 1, the auxiliary planarization layer 4 can be provided with a flat opening 43. This can reduce the influence of the auxiliary planarization layer 4 on other areas. For example, when the auxiliary planarization layer 4 uses a light-shielding material, reducing the coverage area of ​​the auxiliary planarization layer 4 can avoid the influence of the auxiliary planarization layer 4 on the light-transmitting area. In some embodiments, refer to Figure 6 The orthographic projection of the auxiliary planarization layer 4 onto the array substrate 1 can coincide with the orthographic projection of the recessed portion 31 onto the array substrate 1. That is, the auxiliary planarization layer 4 only fills the recessed portion 31, which makes the side of the anode 3 facing the pixel definition layer 5 more flat, while further reducing the influence of the auxiliary planarization layer 4 on other areas. At this time, the top surface of the auxiliary planarization layer 4 facing away from the planarization layer 2 is flush or approximately flush with the top surface of the anode 3 facing away from the planarization layer 2. This makes the top surface of the auxiliary planarization layer 4 facing away from the planarization layer 2 and the top surface of the anode 3 facing away from the planarization layer 2 in the same plane, thereby providing a flat substrate for the fabrication of the pixel definition layer 5.

[0053] In some embodiments, refer to Figure 1 The display panel may also include a light-emitting layer 6, a cathode 7, and an encapsulation layer 8.

[0054] The light-emitting layer 6 can be located on the anode 3, and at least a portion of the light-emitting layer 6 can be located within the pixel definition opening 51. The light-emitting layer 6 can also cover a portion of the pixel definition layer 5. The material of the light-emitting layer 6 can be organic light-emitting materials, etc., and the light-emitting layer 6 can emit light under the combined effect of holes injected into the anode 3 and electrons injected into the cathode 7. The material of the light-emitting layer 6 can be selected according to the light emission color requirements of the display panel, including red light-emitting materials, green light-emitting materials, blue light-emitting materials, etc. For color display panels, red, green, and blue light-emitting materials can be used to correspond to different pixel units, and full-color display can be achieved by combining the three colors of light. The light-emitting layer 6 can be implemented using vacuum evaporation or inkjet printing processes, etc. In this embodiment, the light-emitting layer 6 can be prepared using a vacuum evaporation process, which has advantages such as good film quality, high thickness uniformity, and high patterning accuracy.

[0055] The cathode 7 can be located on the light-emitting layer 6, and is used to inject electrons into the light-emitting layer 6. The material of the cathode 7 is, for example, a transparent conductive oxide (TCO), a magnesium-silver (Mg-Ag) alloy, etc. Examples of transparent conductive oxides (TCOs) include indium tin oxide (ITO), indium zinc oxide (IZO), and tin oxide (SnO2). The cathode 7 can be fabricated using processes such as vacuum evaporation, and its thickness ranges from, for example, 5 nm to 300 nm.

[0056] The encapsulation layer 8 can be located on the cathode 7 and the pixel definition layer 5. The encapsulation layer 8 can prevent harmful gases such as moisture and oxygen, as well as dust, from entering the display panel, preventing the functional layers such as the light-emitting layer 6 and the cathode 7 from being oxidized or corroded, thereby extending the lifespan of the display panel. As an example, the encapsulation layer 8 can include at least one of an inorganic encapsulation layer (not shown), an organic encapsulation layer (not shown), and an inorganic-organic stacked encapsulation structure (not shown). The inorganic encapsulation layer can use inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3), which have good barrier properties. The organic encapsulation layer can use organic materials such as polyimide (PI) and acrylic resin, which have good flexibility and planarization properties. The inorganic-organic stacked encapsulation structure combines the advantages of both inorganic and organic encapsulation layers, further improving the encapsulation effect.

[0057] According to a second aspect of this application, one embodiment provides a display device including a display panel as described above. The display device can be any electronic device with display functionality, such as a wearable device, mobile phone, e-book, electronic newspaper, television set, or personal portable computer. Wearable devices include, for example, smart bracelets, smartwatches, and VR (Virtual Reality) devices.

[0058] According to the third aspect of this application, referring to Figure 1 and Figure 7 An embodiment of this application also provides a method for preparing a display panel, comprising: steps S1-S5.

[0059] Step S1: Provide array substrate 1.

[0060] Step S2: A planarization layer 2 is formed on the array substrate 1, and a via 21 communicating with the array substrate 1 is formed on the planarization layer 2.

[0061] As an example, a planarization layer 2 material is deposited on an array substrate 1 and pre-baked (at a temperature of, for example, 90°C to 120°C, for a time of, for example, 1 minute to 3 minutes); then the planarization layer 2 material is exposed through a photomask (exposure dose of, for example, 100 mJ / cm² to 300 mJ / cm²), with the exposed area being the area corresponding to the via 21; next, a development process is performed (development time of, for example, 30 seconds to 90 seconds) to remove the planarization layer 2 material in the exposed area, forming the via 21; finally, a baking process is performed (at a temperature of, for example, 180°C to 300°C, for example, 30 minutes to 120 minutes) to completely solidify the planarization layer 2 material, thus obtaining the planarization layer 2.

[0062] Step S3: An anode 3 is formed on the planarization layer 2. The anode 3 is electrically connected to the array substrate 1 through a via 21. A recess 31 is formed on the side of the anode 3 facing away from the planarization layer 2.

[0063] As an example, the array substrate 1 is placed in a magnetron sputtering apparatus, and ITO is used as the target material. Sputtering deposition is performed in an inert gas (such as argon) atmosphere to form an ITO thin film. The thickness of the ITO thin film is, for example, 1 nm to 100 nm. Then, the ITO thin film is patterned by photolithography to obtain an anode 3 structure corresponding to the pixel unit. The anode 3 can be connected to the drain 134 of the array substrate 1 through a via 21. A recess 31 is formed on the side of the anode 3 facing away from the planarization layer 2.

[0064] Step S4: An auxiliary planarization layer 4 is formed on the anode 3, at least a portion of the auxiliary planarization layer 4 being located within the recess 31.

[0065] Reference Figure 1 The auxiliary planarization layer 4 may include a first planarization portion 41 whose orthogonal projection on the array substrate 1 is located outside the orthogonal projection of the anode 3 on the array substrate 1, and a second planarization portion 42 whose orthogonal projection on the array substrate 1 is located within the orthogonal projection range of the anode 3 on the array substrate 1. The first planarization portion 41 is provided with a planar opening 43 corresponding to the pixel definition opening 51, and the orthogonal projection of the pixel definition opening 51 on the array substrate 1 is located within the orthogonal projection range of the planar opening 43 on the array substrate 1.

[0066] As an example, an auxiliary planarization layer 4 material is disposed on at least a portion of the surfaces of the anode 3 and the planarization layer 2, and pre-baked (at a temperature of, for example, 90°C to 120°C, for a time of, for example, 1 minute to 3 minutes); then the auxiliary planarization layer 4 material is exposed through a photomask (exposure dose of, for example, 100 mJ / cm² to 300 mJ / cm²), with the exposed area being the region corresponding to the planar opening 43; next, a development process is performed (development time of, for example, 30 seconds to 90 seconds) to remove the auxiliary planarization layer 4 material in the exposed area, forming the planar opening 43; finally, baking is performed (at a temperature of, for example, 180°C to 300°C, for example, 30 minutes to 120 minutes) to completely solidify the auxiliary planarization layer 4 material, thereby obtaining the auxiliary planarization layer 4.

[0067] In some embodiments, refer to Figure 4 The orthographic projection of the auxiliary planarization layer 4 onto the array substrate 1 is located within the orthographic projection range of the anode 3 onto the array substrate 1. The auxiliary planarization layer 4 has a planar opening 43 corresponding to the pixel definition opening 51, and the orthographic projection of the pixel definition opening 51 onto the array substrate 1 is located within the orthographic projection range of the planar opening 43 onto the array substrate 1. As an example, the auxiliary planarization layer 4 material is deposited on at least a portion of the surface of the anode 3 and pre-baked (at a temperature of, for example, 90°C to 120°C, for a time of, for example, 1 minute to 3 minutes); then, the auxiliary planarization layer 4 material is exposed through a photomask (exposure dose of, for example, 100 mJ / cm² to 300 mJ / cm²), with the exposed area being the region corresponding to the planar opening 43; next, a development process is performed (development time of, for example, 30 seconds to 90 seconds) to remove the auxiliary planarization layer 4 material from the exposed area, forming the planar opening 43; finally, baking is performed (at a temperature of, for example, 180°C to 300°C, for example, 30 minutes to 120 minutes) to completely solidify the auxiliary planarization layer 4 material, resulting in the auxiliary planarization layer 4.

[0068] Or, refer to Figure 6 The orthographic projection of the auxiliary planarization layer 4 on the array substrate 1 coincides with the orthographic projection of the recess 31 on the array substrate 1. As an example, the auxiliary planarization layer 4 material is provided on the recess 31 and baked (at a temperature of, for example, 180°C to 300°C, for a time of, for example, 30 minutes to 120 minutes) to completely cure the auxiliary planarization layer 4 material, thereby obtaining the auxiliary planarization layer 4.

[0069] Step S5: A pixel definition layer 5 is formed on the auxiliary planarization layer 4, and a pixel definition opening 51 is formed on the pixel definition layer 5. The orthographic projection of the pixel definition opening 51 on the array substrate 1 does not intersect with the orthographic projection of the auxiliary planarization layer 4 on the array substrate 1.

[0070] As an example, the material of the pixel definition layer 5 is applied to the auxiliary planarization layer 4 and pre-baked (at a temperature of, for example, 90°C to 120°C, for a time of, for example, 1 minute to 3 minutes); then, the pixel definition layer 5 is patterned using a photolithography process to form a pixel definition opening 51; finally, it is baked (at a temperature of, for example, 180°C to 300°C, for a time of, for example, 30 minutes to 120 minutes) to completely solidify the pixel definition layer 5 material, thus obtaining the pixel definition layer 5. The orthographic projection of the pixel definition opening 51 onto the array substrate 1 does not intersect with the orthographic projection of the auxiliary planarization layer 4 onto the array substrate 1.

[0071] In some embodiments, refer to Figure 1 The method for preparing the display panel may also include steps S6-S8.

[0072] Step S6: Form the light-emitting layer 6.

[0073] As an example, an array substrate 1 with a pixel definition layer 5 is placed in a vacuum evaporation apparatus, and an organic light-emitting material is placed in an evaporation source; then, the vacuum evaporation apparatus is evacuated to a vacuum level of 10. -4 Pa to 10 - 6 Pa; then the evaporation source is heated to evaporate the organic light-emitting material into a gaseous state; finally, the gaseous organic light-emitting material is deposited in the pixel definition opening 51 region of the substrate 11 to form the light-emitting layer 6. The thickness of the light-emitting layer 6 is, for example, 50 nm to 300 nm.

[0074] Step S7: Form cathode 7.

[0075] As an example, a magnesium-silver alloy thin film is deposited on the light-emitting layer 6 by a vacuum evaporation process to form a cathode 7, the thickness of which is, for example, 5 nm to 300 nm.

[0076] Step S8: Form encapsulation layer 8.

[0077] As an example, an encapsulation layer 8 is formed on the cathode 7 and the pixel definition layer 5 to complete the fabrication of the display panel.

[0078] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0080] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0081] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Array substrate; A planarization layer is located on the array substrate, and the planarization layer is provided with vias communicating with the array substrate; An anode is located on the planarization layer and is electrically connected to the array substrate through the via. A recess is formed on the side of the anode facing away from the planarization layer. An auxiliary planarization layer is located on the anode, and at least a portion of the auxiliary planarization layer is located within the recess. A pixel definition layer is located on the auxiliary planarization layer; The pixel definition layer is provided with a pixel definition opening, and the orthographic projection of the pixel definition opening on the array substrate does not intersect with the orthographic projection of the auxiliary planarization layer on the array substrate.

2. The display panel according to claim 1, characterized in that, The auxiliary planarization layer includes a first planarization portion and a second planarization portion. The orthographic projection of the first planarization portion on the array substrate is outside the orthographic projection of the anode on the array substrate, and the orthographic projection of the second planarization portion on the array substrate is within the orthographic projection range of the anode on the array substrate.

3. The display panel according to claim 2, characterized in that, The top surface of the first flat portion facing away from the flat layer is flush with the top surface of the second flat portion facing away from the flat layer.

4. The display panel according to claim 1, characterized in that, The orthographic projection of the auxiliary planarization layer on the array substrate is located within the orthographic projection range of the anode on the array substrate.

5. The display panel according to claim 2 or 4, characterized in that, The auxiliary planarization layer is provided with a flat opening corresponding to the pixel definition opening, the flat opening exposing at least a portion of the anode, and the orthographic projection of the pixel definition opening on the array substrate lies within the orthographic projection range of the flat opening on the array substrate; or... The orthographic projection of the auxiliary planarization layer on the array substrate coincides with the orthographic projection of the recessed portion on the array substrate.

6. The display panel according to claim 1, characterized in that, The orthographic projection of the via on the array substrate does not intersect with the orthographic projection of the pixel-defined opening on the array substrate; and / or The material of the auxiliary planarization layer is the same as that of the planarization layer.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 6.

8. A method for manufacturing a display panel, characterized in that, include: Provide array substrate; A planarization layer is formed on the array substrate, and a via is formed on the planarization layer to connect to the array substrate; An anode is formed on the planarization layer, and the anode is electrically connected to the array substrate through the via. A recess is formed on the side of the anode facing away from the planarization layer. An auxiliary planarization layer is formed on the anode, and at least a portion of the auxiliary planarization layer is located within the recess. A pixel definition layer is formed on the auxiliary planarization layer, and a pixel definition opening is formed on the pixel definition layer. The orthographic projection of the pixel definition opening on the array substrate does not intersect with the orthographic projection of the auxiliary planarization layer on the array substrate.

9. The method for manufacturing a display panel according to claim 8, characterized in that, The auxiliary planarization layer includes a first planarization portion and a second planarization portion. The orthographic projection of the first planarization portion on the array substrate is outside the orthographic projection of the anode on the array substrate. The orthographic projection of the second planarization portion on the array substrate is within the orthographic projection range of the anode on the array substrate. The first planarization portion is provided with a planar opening corresponding to the pixel definition opening. The orthographic projection of the pixel definition opening on the array substrate is within the orthographic projection range of the planar opening on the array substrate.

10. The method for manufacturing a display panel according to claim 8, characterized in that, The orthographic projection of the auxiliary planarization layer on the array substrate is located within the orthographic projection range of the anode on the array substrate; The auxiliary planarization layer is provided with a planar opening corresponding to the pixel definition opening, and the orthographic projection of the pixel definition opening on the array substrate is located within the orthographic projection range of the planar opening on the array substrate; or... The orthographic projection of the auxiliary planarization layer on the array substrate coincides with the orthographic projection of the recessed portion on the array substrate.

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