A method for epitaxial growth of semiconductor thin films
By setting etched structural layers and porous structural layers in the epitaxial substrate, the problems of insufficient lattice mismatch stress and thermal stress release capability in the prior art are solved, realizing high-quality semiconductor thin film epitaxy, simplifying the process and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
- Filing Date
- 2026-01-20
- Publication Date
- 2026-06-02
AI Technical Summary
In the current semiconductor thin film epitaxy process, the monolayer patterned structure has limited ability to release lattice mismatch stress and thermal stress, and the hydrogen annealing process conditions are harsh, making it difficult to achieve high-quality thin film epitaxy.
An etched structure layer and a porous structure layer are formed in an epitaxial substrate. The etched structure layer retains a smooth surface for high-quality thin film epitaxy, while the porous structure layer releases lattice mismatch stress and thermal stress. A composite structure is formed by electrochemical etching, which simplifies the process and reduces the requirements for hydrogen annealing.
It significantly reduces process difficulty and cost, improves the quality and uniformity of epitaxial films, and meets the process requirements of thicker epitaxial films and larger wafers.
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Figure CN122138620A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor materials technology, and specifically relates to a semiconductor thin film epitaxy method. Background Technology
[0002] Semiconductor devices are typically fabricated on epitaxial material layers, which can have lower defect density, higher mobility, and higher breakdown voltage than substrate materials.
[0003] When performing material epitaxy, the following factors need to be considered:
[0004] (1) Reduce defects in the substrate material to extend into the epitaxial material layer;
[0005] (2) Reduce material defects and wafer warping caused by lattice mismatch and thermal stress mismatch between epitaxial material layer and substrate material.
[0006] To achieve the above objectives, a patterned epitaxial substrate can be used, with a certain depth of convex and concave structures on its upper surface. During epitaxy, the epitaxial material along the convex portions preferentially heals. As the epitaxial material along the convex portions heals, the epitaxial process along the concave portions gradually stops, forming a cavity within the healed structure. This cavity structure can release lattice mismatch stress, thermal stress, and terminate defect growth, thereby resulting in fewer material defects during epitaxial material healing. However, using only a single-layer patterned structure has limited ability to release lattice mismatch stress and thermal stress, and the degree of reduction in material defect density is also limited.
[0007] Canon of Japan developed Eltran-SOI technology, such as... Figure 1 As shown: (1) Low-porosity porous silicon and high-porosity porous silicon are sequentially prepared on the surface of single-crystal silicon. Figure 2 (1) The high porosity porous silicon layer is located below the low porosity porous silicon layer; (2) The low porosity porous silicon surface is hydrogen annealed to achieve surface smoothing and pore healing; (3) Single crystal silicon is epitaxially grown on the above substrate; (4) The epitaxial substrate is bonded to another support substrate; (5) The bonded substrate is cracked along the high porosity layer; (6) The high porosity layer and the low porosity layer are removed, and the epitaxial single crystal silicon layer is ground to the required thickness and roughness.
[0008] The drawback of Eltran-SOI technology is that, Figure 3 As shown: (1) The upper surface of the low porosity layer is a sponge-like rough structure, which cannot be directly used for high-quality thin film epitaxy. (2) The low porosity layer needs to be healed by hydrogen annealing. However, the hydrogen annealing process only has a healing and polishing effect on a few semiconductor materials, and the process conditions are harsh. Summary of the Invention
[0009] The technical problem to be solved by the present invention is to provide a semiconductor thin film epitaxy method. The method sets an etched structure layer in the epitaxial substrate, and the unetched area still retains a smooth material surface. It can be directly used for the epitaxy of high-quality semiconductor material thin films, eliminating or reducing the post-processing requirements such as hydrogen annealing and polishing, and significantly reducing the process difficulty and process cost.
[0010] This invention provides a method for semiconductor thin film epitaxy, comprising the following steps:
[0011] (1) Prepare the epitaxial substrate;
[0012] (2) An etched structure layer comprising several longitudinal etched structures is prepared on the surface of the epitaxial substrate;
[0013] (3) A porous structure layer is prepared below the etched structure layer;
[0014] (4) Epitaxial target semiconductor thin film above the etched structure layer.
[0015] The non-etched areas of the etched structure layer retain good lattice quality and low roughness, which helps to improve the quality of the epitaxial film. The porous structure layer is located below the etched structure layer and contains a rich network of pores. It has strong deformation capability and can better release lattice mismatch stress and thermal stress, meeting the process requirements of thicker epitaxial films, larger epitaxial wafers, and higher epitaxial quality.
[0016] Preferably, in step (2), the etching depth of the non-etched area of the etched structural layer is ≤1 nm, and the increase in surface roughness compared to before the etching process is ≤1 nm; the depth of the etched structural layer is 10 nm to 10 μm. Furthermore, when preparing the etched structural layer, an electrochemical etching process can be used. Since the chemical reaction barrier at material defects is usually lower than that in defect-free areas, under precise control of the electrochemical etching process parameters (controlling the bias voltage of the electrochemical etching interface below a certain value so that the corrosion rate of the reaction ions in the electrochemical etching solution at the defects is significantly higher than that at the non-defect areas), corrosion holes can be preferentially formed at the material defects. This can prevent the defects from extending into the epitaxial layer in subsequent epitaxial processes, further improving the quality of the epitaxial film.
[0017] Preferably, the longitudinal etching structure in step (2) is a drill hole or a specific pattern structure.
[0018] Preferably, the diameter of the drilled hole is ≤1μm; the diameter of the hole-like structure in the specific pattern structure is ≤1μm, and the width of the line segment structure in the specific pattern structure is ≤1μm.
[0019] Preferably, the ratio of the diameter of the drilled hole to the etching depth is ≤4; the ratio of the diameter of the hole structure to the etching depth in the specific pattern structure is ≤4; and the ratio of the width of the line segment structure to the etching depth in the specific pattern structure is ≤4.
[0020] Preferably, in step (2), when preparing the etched structure layer, an etching mask is prepared on the surface of the epitaxial substrate, and one or more of dry etching, wet etching, and electrochemical etching are performed along the etching mask to form the etched structure layer.
[0021] Preferably, the porous structure layer in step (3) includes a porous structure located below the etched structure layer.
[0022] Preferably, a porous structure is formed at the bottom of the etched structure by electrochemical etching; as the electrochemical etching process proceeds, the porous structure gradually extends laterally to the area below the non-etched region of the etched structure layer.
[0023] Preferably, the epitaxial target semiconductor thin film in step (4) includes: an epitaxial buffer layer, wherein an epitaxial semiconductor material is grown along the surface of the etched structure layer and gradually covers the longitudinal etched structure, and material closure occurs above the longitudinal etched structure; subsequently, a second material layer is epitaxially grown on the buffer layer, wherein the defect surface density of the second material layer is ≤10. 9 / cm 2 .
[0024] Preferably, the epitaxial process includes one or more of chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, atomic layer deposition, physical sublimation deposition, electron beam deposition, and thermal evaporation deposition.
[0025] The present invention also provides a substrate obtained by the above-described semiconductor thin film epitaxy method.
[0026] Beneficial effects
[0027] The present invention sets an etched structure layer in the epitaxial process, and the unetched area still retains a smooth material surface, which can be directly used for the epitaxy of high-quality semiconductor material thin films. It eliminates or reduces the post-processing requirements of hydrogen annealing, and significantly reduces the process difficulty and process cost. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the Eltran-SOI technology process.
[0029] Figure 2 This is a schematic diagram of the cross-sections of the low-porosity layer and the high-porosity layer.
[0030] Figure 3The images show electron microscope (EM) images of the low-porosity layer surface and the surface after hydrogen annealing.
[0031] Figure 4 This is a cross-sectional schematic diagram of the process flow of the present invention.
[0032] Figure 5 This is a 3D schematic diagram of the process flow of the present invention.
[0033] Figure 6 This is a photograph of the thin film obtained from the process flow of this invention. Detailed Implementation
[0034] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0035] Example 1
[0036] This embodiment provides a semiconductor thin film epitaxy method, including the following steps:
[0037] (1) Prepare the epitaxial substrate;
[0038] (2) An etched structure layer comprising several longitudinal etched structures is prepared on the surface of the epitaxial substrate;
[0039] like Figure 4 As shown:
[0040] First, an etched structure layer is prepared on the top of the epitaxial substrate. The etched structure layer contains several vertical etched structures with a certain depth. Then, the etched structure is used as the starting point for electrochemical etching to form a porous structure layer below. The porous structure layer penetrates or partially penetrates the area below the etched structure layer in the horizontal direction.
[0041] When the etched structure is a drilled hole, the diameter of the hole is ≤1μm; when the etched structure is a specific pattern structure, the diameter of the hole-like structure in the specific pattern structure is ≤1μm in the horizontal direction, and the width of the line segment structure in the horizontal direction is ≤1μm. The ratio of the diameter of the drilled hole to the etching depth is ≤4; the ratio of the diameter of the hole-like structure in the specific pattern structure to the etching depth is ≤4; the ratio of the width of the line segment structure in the specific pattern structure to the etching depth is ≤4.
[0042] The aspect ratio of the etched structure needs to be ≥0.25 to avoid the low-quality epitaxial layer formed at the bottom of the etched structure from affecting the good healing of the buffer layer and the high-quality epitaxial layer.
[0043] (3) A porous structure layer is prepared below the etched structure layer;
[0044] The porous structure layer includes a porous structure located below the etched structure layer.
[0045] Preferably, a porous structure is formed at the bottom of the etched structure by electrochemical etching; as the electrochemical etching process proceeds, the porous structure gradually extends laterally to the area below the non-etched region of the etched structure layer.
[0046] The etched structure in the etched structure layer can serve as the starting point for the etching process of the porous structure layer. By using plasma treatment of the material surface, surface epitaxy, surface doping concentration control, or selecting compound materials with specific polarities, the chemical reaction barrier inside the etched substrate is lower than that on the surface. The bias voltage of the electrochemical etching interface is controlled below a certain value, so that the corrosion rate of the reactive ions in the electrochemical etching solution of the substrate exposed at the etched structure is significantly higher at the defects than at the non-etched structure.
[0047] As an example, a composite substrate containing multiple different material layers is used as the epitaxial substrate. The surface of the substrate is a material layer with a high chemical reaction barrier, and the bottom layer is a material layer with a low chemical reaction barrier. The material to be etched is placed in an electrochemical etching solution containing fluoride ions or other ions with strong corrosive ability. A corrosion current with a certain current density is passed through the substrate to be etched. During the etching process, drill holes are first formed on the surface to be etched. Then, the ions in the etching solution come into contact with the material layer with a low chemical reaction barrier below. The subsequent electrochemical etching process is mainly concentrated inside the material rather than on the surface. It will naturally expand into a network of porous corrosion pathways inside the material being etched. The material layer with a high chemical reaction barrier at the top only forms a few drill holes. After that, the etching process in this material area slows down or stops. The area outside the drill holes is relatively complete and smooth.
[0048] As an example ( Figure 6 Using compound semiconductors, due to the differences in chemical reaction barriers on the surfaces of different elements in compound semiconductors, a specific surface to be etched can be selected so that its surface reaction barrier is slightly higher than that of the material's interior and bottom. The material to be etched is placed in an electrochemical etching solution containing fluoride ions or other highly corrosive ions, and an 1~100mA / cm current is applied to the electrochemically etched substrate. 2The etching process involves a high current density, which first creates boreholes on the surface to be etched. Then, the etchant ions contact the internal structure of the substrate material. Because the chemical reaction barrier is lower inside the internal structure, the subsequent electrochemical etching process is mainly concentrated inside the material rather than on the surface. This naturally expands into a network of porous etching pathways within the etched material, ultimately forming a substrate structure with boreholes on the surface and a porous material layer inside. The chemical reaction barrier at the bottom of the etched structure is lower than that of the unetched area, allowing the porous structure layer to extend from the bottom of the etched structure into the depth of the substrate and laterally extend below the unetched area. The upper surface of the unetched area is unaffected by the electrochemical etching process (or minimally affected). This process of first preparing the etched structure layer and then the porous structure layer forms a clever combination. The process is simple and low-cost. The resulting composite structure of the etched and porous structures can better release lattice mismatch stress and thermal stress, meeting the process requirements for thicker epitaxial films, larger epitaxial wafers, and higher epitaxial quality.
[0049] (4) Epitaxial target semiconductor thin film above the etched structure layer.
[0050] It includes: an epitaxial buffer layer, wherein an epitaxial semiconductor material is grown along the surface of the etched structure layer and gradually covers the longitudinal etched structure, and material closure occurs above the longitudinal etched structure; subsequently, a high-quality epitaxial layer is epitaxially grown on the buffer layer.
[0051] Optionally, an epitaxial buffer layer is added above the etched structural layer. When adding the buffer layer, a low-temperature epitaxial process or a high-quality epitaxial process such as MBE can be selected to promote defect healing, opening structure healing, and improve the lattice quality of the buffer layer. This avoids secondary damage to the etched structural layer and porous structural layer caused by temperature and specific process gases during high-temperature epitaxial processes.
[0052] As an example, homoepitaxial growth is first performed on the etched structure layer to promote gradual healing of the material growing along the etched structure as the epitaxial thickness increases. Homoepitaxial growth exhibits minimal lattice mismatch, the strongest healing ability, and the fewest material defects. Heteroepitaxial growth is then performed to prevent epitaxial defects caused by the etched structure from being inherited into the heteroepitaxial layer.
[0053] like Figure 5As shown, it illustrates the 3D structure of the above-described process. The etched structure on the etched structure layer can be a drilled hole or a custom etched pattern. To ensure that the chemical reaction barrier at the bottom of the etched structure is lower than that of the unetched area, a semiconductor thin film can be epitaxially grown on top of the etched structure. This semiconductor thin film differs from the original substrate surface material in one or more parameters such as material type, conductivity, and crystal quality. Alternatively, before fabricating the etched structure, a semiconductor thin film can be epitaxially grown on the substrate, and then the etched structure can be fabricated on the epitaxial semiconductor thin film. The depth of the etched structure in the vertical direction can be less than, equal to, or greater than that of the epitaxial semiconductor thin film.
[0054] Figure 6 The image shows a physical example of the material prepared in this embodiment. The left side is a top view, containing scattered drilled holes with a diameter of less than 70 nm. The densely packed black dots in the image represent the pores of the underlying porous structure layer. When the etched structure layer is thin, the underlying porous structure layer can be observed through the surface using SEM. The area outside the drilled holes retains good surface roughness (≤1 nm) and good single-crystal structure quality. The right image is a cross-sectional view, showing an etched structure layer of approximately 50 nm at the top, within which longitudinal drilled holes are scattered. Below the etched structure layer is the porous structure layer, which not only exists below the projection of the etched structure but also extends laterally below the unetched areas within the etched structure layer.
Claims
1. A semiconductor thin film epitaxy method, characterized in that, Includes the following steps: (1) Prepare the epitaxial substrate; (2) An etched structure layer comprising several longitudinal etched structures is prepared on the surface of the epitaxial substrate; (3) A porous structure layer is prepared below the etched structure layer; (4) Epitaxial target semiconductor thin film above the etched structure layer.
2. The semiconductor thin film epitaxy method according to claim 1, characterized in that, In step (2), the etching depth of the material surface in the non-etched area of the etched structural layer is ≤1nm, and the increase in surface roughness compared to before the etching process is ≤1nm; the depth of the etched structural layer is 10nm~10μm.
3. The semiconductor thin film epitaxy method according to claim 1, characterized in that, The longitudinal etching structure in step (2) is a drill hole or a specific pattern structure.
4. The semiconductor thin film epitaxy method according to claim 3, characterized in that, The diameter of the drilled hole is ≤1μm; the diameter of the hole-like structure in the specific pattern structure is ≤1μm, and the width of the line segment structure in the specific pattern structure is ≤1μm.
5. A semiconductor thin film epitaxy method according to claim 4, characterized in that, The ratio of the diameter to the etching depth of the drilled hole is ≤4; the ratio of the diameter to the etching depth of the hole structure in the specific pattern structure is ≤4; the ratio of the width to the etching depth of the line segment structure in the specific pattern structure is ≤4.
6. The semiconductor thin film epitaxy method according to claim 1, characterized in that, In step (2), when preparing the etched structure layer, an etching mask is prepared on the surface of the epitaxial substrate, and one or more of dry etching, wet etching, and electrochemical etching are performed along the etching mask to form the etched structure layer.
7. A semiconductor thin film epitaxy method according to claim 1, characterized in that, The porous structure layer in step (3) contains a porous structure located below the etched structure layer.
8. A semiconductor thin film epitaxy method according to claim 1, characterized in that, The epitaxial target semiconductor thin film in step (4) includes: an epitaxial buffer layer, wherein an epitaxial semiconductor material is grown along the surface of the etched structure layer and gradually covers the longitudinal etched structure, and material closure occurs above the longitudinal etched structure; subsequently, a second material layer is epitaxially grown on the buffer layer, wherein the defect surface density of the second material layer is ≤10. 9 / cm 2 .
9. A semiconductor thin film epitaxy method according to claim 8, characterized in that, The epitaxial process includes one or more of the following: chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, atomic layer deposition, physical sublimation deposition, electron beam deposition, and thermal evaporation deposition.
10. A substrate obtained by the semiconductor thin film epitaxy method according to any one of claims 1 to 9.