Method for manufacturing semiconductor wafers

Abstract

A method for manufacturing a semiconductor wafer includes: forming a plurality of mandrels on a hard mask layer on a substrate; forming a spacer layer covering the mandrels; applying a filler material to the spacer layer and filling the gaps between the mandrels; rotating the substrate, wherein the substrate rotation is performed at an environment above the glass transition temperature of the filler material; etching back the filler material to expose the spacer layer; performing a first etching process to remove a first portion of the spacer layer to expose the mandrels; performing a second etching process to remove a second portion of the mandrels, the filler material, and the spacer layer; and patterning the hard mask layer through the remaining portions of the spacer layer. The method for manufacturing a semiconductor wafer of the present invention effectively reduces the thickness difference of the filler material between high-density and low-density regions of the semiconductor wafer during the etching back process.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor wafers. Background Technology

[0002] In the layout of memory arrays, there are typically high-pattern-density regions and low-pattern-density regions. During the semiconductor wafer manufacturing process, after the filler material is coated and baked, a thickness deviation of the filler material coating occurs at the boundary between the high-pattern-density and low-pattern-density regions. This phenomenon leads to a critical dimension (CD) imbalance problem in the self-aligned double patterning (SADP) process. Therefore, there is an urgent need to establish a reliable semiconductor wafer manufacturing method. Summary of the Invention

[0003] This invention relates to a method for manufacturing a semiconductor wafer. The method includes: forming a plurality of mandrels on a hard mask layer on a substrate; forming a spacer layer covering the mandrels; applying a filler material to the spacer layer and filling the gaps between the mandrels; and rotating the substrate, wherein the substrate is rotated at a temperature higher than the glass transition temperature (T0) of the filler material. g The process is performed in the following environment: etching back the filler material to expose the spacer layer; performing a first etching process to remove a first portion of the spacer layer to expose the mandrel; performing a second etching process to remove the mandrel, filler material, and a second portion of the spacer layer; and patterning the hard mask layer through the remaining portion of the spacer layer.

[0004] In some implementations, rotating the substrate is performed to flatten the top surface of the filling material.

[0005] In some embodiments, rotating the substrate includes a first step and a second step following the first step. The rotation speed in the first step is different from the rotation speed in the second step.

[0006] In some embodiments, rotating the substrate includes a first step and a second step following the first step. The rotation direction of the first step is different from the rotation direction of the second step.

[0007] In some embodiments, rotating the substrate includes a first step and a second step following the first step. The temperature of the first step is different from the temperature of the second step.

[0008] In some embodiments, rotating the substrate includes a first step and a second step following the first step. The rotational acceleration in the first step is different from the rotational acceleration in the second step.

[0009] In some embodiments, the mandrel includes a plurality of first mandrels and second mandrels. The width of the first mandrel is smaller than the width of the second mandrel. After the filler material is applied, the filler material has a first top surface above the first mandrel and a second top surface above the second mandrel, with the first top surface being lower than the second top surface. After the substrate is rotated, the first top surface and the second top surface are substantially coplanar.

[0010] In some implementations, the first top surface is inclined after the filling material is applied.

[0011] In some implementations, after the filling material is applied, the height of the first top surface gradually decreases from that of the second top surface.

[0012] In some implementations, the spacer layer includes a plurality of overhang structures located at the apex of the mandrel, and the first etching process is performed to remove the overhang structures of the spacer layer.

[0013] The present invention also relates to a method for manufacturing a semiconductor wafer. The method includes: transferring the semiconductor wafer to a wafer stage; applying a filler material to a spacer layer and filling the gap between a first mandrel and a second mandrel by means of a nozzle above the wafer stage, the filler material comprising a first portion above the first mandrel and a second portion above the second mandrel, wherein the top surface of the first portion is lower than the top surface of the second portion; and rotating the semiconductor wafer by means of the wafer stage such that the top surface of the first portion is coplanar with the top surface of the second portion. The semiconductor wafer includes a substrate, a hard mask layer on the substrate, a plurality of first mandrels and second mandrels on the hard mask layer, and a spacer layer covering the first mandrels and second mandrels. The width of the first mandrel is smaller than the width of the second mandrel.

[0014] In some embodiments, the wafer stage is rotated at an environment above the glass transition temperature of the filler material.

[0015] In some embodiments, the rotating wafer stage includes a first step and a second step following the first step. The rotational speed of the first step is different from the rotational speed of the second step.

[0016] In some embodiments, the rotating wafer stage includes a first step and a second step following the first step. The rotation direction of the first step is different from the rotation direction of the second step.

[0017] In some implementations, the rotating wafer stage includes a first step and a second step following the first step. The temperature of the first step is different from the temperature of the second step.

[0018] In some embodiments, the rotating wafer stage includes a first step and a second step following the first step. The rotational acceleration of the first step is different from the rotational acceleration of the second step.

[0019] In some implementations, the top surface of the first part is inclined after the filling material is applied.

[0020] In some implementations, after the filling material is applied, the height of the top surface of the first part gradually decreases from the top surface of the second part.

[0021] In some embodiments, the method of manufacturing a semiconductor wafer further includes: etching back the filler material to expose the spacer layer; performing a first etching process to remove the top of the spacer layer to expose the first mandrel and the second mandrel; performing a second etching process to remove the first mandrel and the second mandrel, the filler material and the bottom of the spacer layer; and patterning a hard mask layer through the remaining portion of the spacer layer.

[0022] In some embodiments, the spacer layer includes a plurality of overhang structures located at the apex corners of the first and second mandrels, and the first etching process is performed to remove the overhang structures located on the first and second mandrels.

[0023] In summary, the method for manufacturing semiconductor wafers of the present invention improves the uniformity of the filler material by rotating and baking the semiconductor wafer in an environment higher than the glass transition temperature of the filler material after applying the filler material. This method can effectively reduce the thickness difference of the filler material between high-density and low-density regions of the semiconductor wafer during the etch-back process.

[0024] These and other features, aspects and advantages of the present invention will become clearer with reference to the following description, claims and drawings.

[0025] It should be understood that the above general description and the following detailed description are merely examples and are intended to further explain the claimed invention. Attached Figure Description

[0026] A more complete understanding of the invention can be achieved by referring to the following detailed description of the embodiments herein: Figure 1 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0027] Figure 2 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0028] Figure 3A This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0029] Figure 3B This is a schematic diagram of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0030] Figure 4AThis is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0031] Figure 4B This is a schematic diagram of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0032] Figure 5 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0033] Figure 6 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0034] Figure 7 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0035] Figure 8 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0036] Figure 9 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention.

[0037] Figure 10 This is a cross-sectional view of a method for manufacturing a semiconductor wafer according to some embodiments of the present invention. Detailed Implementation

[0038] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0039] The following disclosure provides numerous different embodiments or examples for achieving different functions of the provided subject matter. To simplify the content of the invention, specific examples of elements and arrangements are described below. These examples are, of course, merely illustrative and not intended to be limiting. For example, the description of a first feature formed on or on the surface of a second feature may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between the first and second features without direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples; such repetition is for simplicity and clarity and is not intended to indicate, in itself, a relationship between the various embodiments and / or configurations discussed.

[0040] Furthermore, for ease of description, spatially related terms such as "below," "below," "bottom," "above," and "top" may be used in this invention to describe the relationship of one element or feature relative to another, as shown in the accompanying drawings. These spatially related terms are intended to cover different orientations of the device during use or operation, and are not limited to the orientations shown in the drawings. For example, the device may operate in different orientations (such as rotating 90 degrees or other orientations), therefore the spatially related descriptive terms in this document should be interpreted accordingly.

[0041] The terms "about," "approximately," "approximately," or "substantially" as used in this specification generally indicate a range of 20%, 10%, or 5% error within a specific value or range. All values ​​listed in this invention are approximate, meaning that even if not explicitly stated, the terms "about," "approximately," "approximately," or "substantially" can be inferred to apply. However, those skilled in the art should understand that the values ​​or ranges mentioned in the specification are merely examples, and as integrated circuits shrink, their values ​​or ranges may decrease or change accordingly.

[0042] This invention describes embodiments with reference to cross-sectional schematic diagrams, which are simplified representations of idealized embodiments (and intermediate structures). Therefore, actual structures may differ from the schematic shape due to manufacturing techniques and / or tolerances. Thus, the illustrated embodiments should not be construed as limited to the specific shape of the illustrated areas, but should include shape deviations due to manufacturing factors. For example, the figures show rectangular doped regions whose edges typically exhibit rounded corners or curves, and whose doping concentration shows a gradual distribution, rather than a binary abrupt change between undoped and non-doped regions. Similarly, embedded regions formed by doping may result in dopant penetrating into the transition zone between the embedded region and the doped surface. Therefore, the areas in the figures are merely illustrative, and their shapes are not intended to represent the actual form of the device area, nor should they be considered as limiting the scope of this invention.

[0043] The embodiments will be described in detail below with reference to the accompanying drawings.

[0044] Please see Figure 1 , Figure 2 , Figure 3A , Figure 4A and Figures 5 to 10 . Figure 1 , Figure 2 , Figure 3A , Figure 4A and Figures 5 to 10 This is a cross-sectional view of a method for manufacturing a semiconductor wafer 100 according to some embodiments of the present invention.

[0045] exist Figure 1In this process, a method of manufacturing a semiconductor wafer 100 includes forming a plurality of mandrels 130 on a hard mask layer 120 of a substrate 110. In some embodiments, the mandrels 130 include a plurality of first mandrels 131 and second mandrels 132. The width of the first mandrels 131 is smaller than the width of the second mandrels 132. The semiconductor wafer 100 includes a high-density region 111 and a low-density region 112. The first mandrels 131 are located in the high-density region 111 and the second mandrels 132 are located in the low-density region 112. The material of the mandrels 130 may include carbon.

[0046] exist Figure 2 In this method of manufacturing a semiconductor wafer 100, a spacer layer 140 is formed covering a mandrel 130. In some embodiments, the spacer layer 140 may include a first portion 141, a second portion 142, a residual portion 143, and a dangling structure 144. The first portion 141 is located on the top surface of the mandrel 130. The second portion 142 is located between two adjacent mandrels 130 and covers the top surface of a hard mask layer 120. The residual portion 143 covers the two sidewalls of the mandrel 130. The dangling structure 144 is located at the apex corner of the mandrel 130. In other words, the first portion 141 is the top of the spacer layer 140. The second portion 142 is the bottom of the spacer layer 140.

[0047] exist Figure 3A In this method of manufacturing a semiconductor wafer 100, a filler material 150 is applied to a spacer layer 140 and fills a gap 133 between mandrels 130. The filler material 150 has a first portion 151 above a first mandrel 131, a second portion 152 above a second mandrel 132, and a top surface 1510. The first portion 151 of the filler material 150 has a first top surface 1511 above the first mandrel 131. The second portion 152 of the filler material 150 has a second top surface 1521 above the second mandrel 132. The top surface 1510 includes both the first top surface 1511 and the second top surface 1521. After the filler material 150 is applied, the first top surface 1511 is lower than the second top surface 1521. In other words, the top surface of the first portion 151 of the filler material 150 is lower than the top surface of the second portion 152 of the filler material 150. The material of the filler material 150 may contain carbon. For example, the material of the filler material 150 may be a bottom anti-reflective coating material. The filling material 150 can be a photoresist material.

[0048] In some embodiments, the first top surface 1511 may be inclined after the filler material 150 is applied. In some embodiments, the height of the first top surface 1511 may gradually decrease from the second top surface 1521 after the filler material 150 is applied. Because the number of first mandrels 131 in the high-density region 111 is greater than the number of second mandrels 132 in the low-density region 112, the filler material 150 fills more gaps 133 in the high-density region 111. This situation causes the filler material 150 to gradually develop thickness differences, resulting in uneven distribution of the top surface 1510 of the filler material 150.

[0049] Please also refer to Figure 3A and Figure 3B . Figure 3B A schematic diagram of a method for manufacturing a semiconductor wafer 100 according to some embodiments of the present invention is shown. In other words, the method for manufacturing a semiconductor wafer 100 includes transferring the semiconductor wafer 100 onto a wafer stage 210; applying a filler material 150 onto a spacer layer 140 and filling the gap 133 between mandrels 130 through a nozzle 240 above the wafer stage 210.

[0050] exist Figure 4A In this method of manufacturing a semiconductor wafer 100, a rotating substrate 110 is included. The rotating substrate 110 can increase the kinetic energy of the filler material 150 during reflow motion. The rotating substrate 110 can operate at a temperature higher than the glass transition temperature (Tg) of the filler material 150. g Performed under the following conditions: glass transition temperature (T) g The glass transition temperature (T0) refers to the temperature at which a dried thin film (such as a photoresist material) transitions from a solid to a semi-solid state. This is typically defined as a glass transition temperature (T0) that is 150°C higher than that of the filler material. g The baking temperature can improve its reflow capability, thereby minimizing thickness deviation. In some embodiments, the operation of rotating substrate 110 is intended to flatten the top surface 1510 of filler material 150. After the substrate 110 is rotated, the first top surface 1511 and the second top surface 1521 are substantially coplanar.

[0051] Please also refer to Figure 4A and Figure 4B . Figure 4B A schematic diagram of a method for manufacturing a semiconductor wafer 100 according to some embodiments of the present invention is shown. In other words, the method for manufacturing the semiconductor wafer 100 includes rotating a substrate 110 via a wafer stage 210 such that a first top surface 1511 of a first portion 151 of a filler material 150 is coplanar with a second top surface 1521 of a second portion 152 of the filler material 150. The wafer stage 210 can be rotated at a temperature higher than the glass transition temperature (Tg) of the filler material 150. g It is executed in an environment that allows it to run.

[0052] In some embodiments, wafer stage 210 may include a heating plate. Motor 230 is connected to wafer stage 210 via shaft 220. Controller 250 is electrically connected to wafer stage 210 and motor 230 to control the temperature and rotation parameters of the heating plate within wafer stage 210.

[0053] In some embodiments, the rotating semiconductor wafer 100 (i.e., the substrate 110 of the rotating semiconductor wafer 100) may include a first step and a second step following the first step. The rotational speed of the first step is different from the rotational speed of the second step. The rotational direction of the first step is different from the rotational direction of the second step. The temperature of the first step is different from the temperature of the second step. The rotational acceleration of the first step is different from the rotational acceleration of the second step.

[0054] In some embodiments, the rotating semiconductor wafer 100 may include multiple successive steps. For example, the rotating semiconductor wafer 100 may be performed as described in Table 1 below.

[0055] [Table 1]

[0056] In some embodiments, the rotation time (time 1, time 2, time 3, and time 4) of steps 1 to 4 can be from 0 seconds to 200 seconds. The rotation speeds S1, S2, S3, and S4 of steps 1 to 4 can be from 0 rpm to 2000 rpm. The rotation directions D1, D2, D3, and D4 of steps 1 to 4 can be clockwise (e.g., ...). Figure 4B (as shown by arrow 261 in the image), or in a counter-clockwise direction (as shown by arrow 261 in the image). Figure 4B (As indicated by arrow 262 in the diagram). The rotational accelerations Acce1, Acce2, Acce3, and Acce4 in steps 1 to 4 can be from 0 rpm / sec to 10,000 rpm / sec. The temperatures T1, T2, T3, and T4 in steps 1 to 4 can be from 50°C to 500°C. Temperatures T1, T2, T3, and T4 can be higher than the glass transition temperature (T0) of the filler material. g ).

[0057] In some implementations, alternating the rotation direction between clockwise and counterclockwise can increase the overall uniformity of the filler material 150.

[0058] In some embodiments, the method of manufacturing semiconductor wafer 100 includes sequentially performing steps 1 to 4 in Table 1. The rotation times 1, 2, 3, and 4 may be the same or different. Rotation speeds S1 and S2 may be greater than rotation speeds S3 and S4. Rotation speed S1 may be equal to S2, and rotation speed S3 may be equal to S4 (i.e., S1 = S2 > S3 = S4). Rotation directions D1 and D3 may be clockwise, and rotation directions D2 and D4 may be counterclockwise. Rotation accelerations Acce1 and Acce2 may be greater than rotation accelerations Acce3 and Acce4. Rotation acceleration Acce1 may be equal to Acce2, and rotation acceleration Acce3 may be equal to Acce4 (i.e., Acce1 = Acce2 > Acce3 = Acce4). Temperatures T1 and T2 may be higher than temperatures T3 and T4. Temperature T1 may be equal to T2, and temperature T3 may be equal to T4 (i.e., T1 = T2 > T3 = T4). Temperatures T1 and T2 can be higher than the glass transition temperature (T) of the filler material by 150°C. g Temperatures T3 and T4 can be 150°C lower than the glass transition temperature (T) of the filler material. g ).

[0059] exist Figure 5 In this process, a method of manufacturing a semiconductor wafer 100 includes etching back a filler material 150 to expose a spacer layer 140. After etching back the filler material 150, a first portion 141 of the spacer layer 140 and a dangling structure 144 are exposed.

[0060] exist Figure 6 In one embodiment, a method of manufacturing a semiconductor wafer 100 includes performing a first etching process to remove a first portion 141 of a spacer layer 140 to expose a mandrel 130. In some embodiments, the first etching process is performed to remove overhang structures 144 at the apex corners of the spacer layer 140 of the first mandrel 131 and the second mandrel 132. In other words, the first etching process is performed to remove the top of the spacer layer 140 to expose the first mandrel 131 and the second mandrel 132.

[0061] exist Figure 7 In this process, the method of manufacturing a semiconductor wafer 100 includes performing a second etching process to remove a second portion 142 of a mandrel 130, a filler material 150, and a spacer layer 140. In other words, the second etching process is performed to remove the first mandrel 131 and the second mandrel 132, the filler material 150, and the second portion 142 of the spacer layer 140, leaving a residual portion 143 on the hard mask layer 120 to form a spacer 160.

[0062] exist Figure 8In this method of manufacturing a semiconductor wafer 100, a hard mask layer 120 is patterned through a residual portion 143 of a spacer layer 140. The residual portion 143 forms a spacer 160. The spacer 160 is used as a first etch mask to form a patterned hard mask 170.

[0063] exist Figure 9 In this process, a method for manufacturing a semiconductor wafer 100 includes removing spacers 160. Figure 10 In the process of manufacturing a semiconductor wafer 100, the method includes patterning a substrate 110 by patterning a hard mask 170.

[0064] In summary, the method for manufacturing semiconductor wafers of the present invention improves the uniformity of the filler material by rotating and baking the semiconductor wafer in an environment higher than the glass transition temperature of the filler material after applying the filler material. This method can effectively reduce the thickness difference of the filler material between high-density and low-density regions of the semiconductor wafer during the etch-back process.

[0065] Although the invention has been described in detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0066] Those skilled in the art will understand that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover the modifications and variations within the scope of the appended claims.

[0067] [Symbol Explanation] 100: Semiconductor wafer 110: Substrate 111: High-density area 112: Low-density area 120: Hard mask layer 130: Mandrel 131: First mandrel 132: Second mandrel 133: Gap 140: Spare layer 141: Part One 142: Part Two 143: Residual portion 144: Overhang structure 150: Filler material 1510: Top surface 151: Part One 1511: First Top Surface 152: Part Two 1521: Second Top Surface 160: Spacer 170: Patterned Hard Mask 210: Wafer stage 220: Shaft 230: Motor 240: Nozzle 250: Controller 261: Arrow 262: Arrow.

Claims

1. A method for manufacturing semiconductor wafers, characterized in that, Include: Multiple mandrels are formed on a hard masking layer on a substrate; Forming a spacer layer covering the plurality of mandrels; The filling material is applied to the spacer layer and fills the gaps between the plurality of mandrels; The substrate is rotated, wherein the rotation is performed at an environment above the glass transition temperature of the filler material; Etching back the filler material to expose the spacer layer; A first etching process is performed to remove a first portion of the spacer layer to expose the plurality of mandrels; A second etching process is performed to remove the plurality of mandrels, the filler material, and a second portion of the spacer layer; as well as The hard mask layer is patterned using the remaining portion of the spacer layer.

2. The method according to claim 1, characterized in that, Rotating the substrate is performed to flatten the top surface of the filling material.

3. The method according to claim 1, characterized in that, Rotating the substrate includes a first step and a second step following the first step, wherein the rotation speed of the first step is different from the rotation speed of the second step.

4. The method according to claim 1, characterized in that, Rotating the substrate includes a first step and a second step following the first step, wherein the rotation direction of the first step is different from the rotation direction of the second step.

5. The method according to claim 1, characterized in that, Rotating the substrate includes a first step and a second step following the first step, wherein the temperature of the first step is different from the temperature of the second step.

6. The method according to claim 1, characterized in that, Rotating the substrate includes a first step and a second step following the first step, wherein the rotational acceleration of the first step is different from the rotational acceleration of the second step.

7. The method according to claim 1, characterized in that, The plurality of mandrels includes a plurality of first mandrels and a plurality of second mandrels, wherein the width of the plurality of first mandrels is smaller than the width of the second mandrels; After the filling material is applied, the filling material has a first top surface above the plurality of first mandrels and a second top surface above the second mandrel, wherein the first top surface is lower than the second top surface; and After the substrate is rotated, the first top surface and the second top surface are substantially coplanar.

8. The method according to claim 7, characterized in that, After the filling material is applied, the first top surface is inclined.

9. The method according to claim 7, characterized in that, After the filling material is applied, the height of the first top surface gradually decreases from that of the second top surface.

10. The method according to claim 1, characterized in that, The spacer layer includes a plurality of overhang structures located at the apex of the plurality of mandrels, and the first etching process is performed to remove the plurality of overhang structures of the spacer layer.

11. A method for manufacturing semiconductor wafers, characterized in that, Include: Transferring a semiconductor wafer to a wafer stage, wherein the semiconductor wafer comprises: substrate; A hard masking layer on the substrate; A plurality of first mandrels and a second mandrel on the hard mask layer, wherein the width of the plurality of first mandrels is smaller than the width of the second mandrel; as well as A spacer layer covering the plurality of first mandrels and second mandrels; A filler material is applied to the spacer layer by a nozzle above the wafer stage and fills the gap between the plurality of first mandrels and the second mandrel. The filler material is contained in a first portion above the plurality of first mandrels and a second portion above the second mandrels, wherein the top surface of the first portion is lower than the top surface of the second portion. as well as The semiconductor wafer is rotated by the wafer stage so that the top surface of the first portion is coplanar with the top surface of the second portion.

12. The method according to claim 11, characterized in that, The wafer stage is rotated in an environment above the glass transition temperature of the filler material.

13. The method according to claim 11, characterized in that, Rotating the wafer stage includes a first step and a second step following the first step, wherein the rotation speed of the first step is different from the rotation speed of the second step.

14. The method according to claim 11, characterized in that, Rotating the wafer stage includes a first step and a second step following the first step, wherein the rotation direction of the first step is different from the rotation direction of the second step.

15. The method according to claim 11, characterized in that, Rotating the wafer stage includes a first step and a second step following the first step, wherein the temperature of the first step is different from the temperature of the second step.

16. The method according to claim 11, characterized in that, Rotating the wafer stage includes a first step and a second step following the first step, wherein the rotational acceleration of the first step is different from the rotational acceleration of the second step.

17. The method according to claim 11, characterized in that, After the filling material is applied, the top surface of the first portion is inclined.

18. The method according to claim 11, characterized in that, After the filling material is applied, the height of the top surface of the first portion gradually decreases from the top surface of the second portion.

19. The method according to claim 11, characterized in that, Further includes: Etching back the filler material to expose the spacer layer; A first etching process is performed to remove the top of the spacer layer to expose the plurality of first mandrels and second mandrels; A second etching process is performed to remove the plurality of first mandrels and second mandrels, the filler material, and the bottom of the spacer layer; as well as The hard mask layer is patterned using the remaining portion of the spacer layer.

20. The method according to claim 19, characterized in that, The spacer layer includes a plurality of overhang structures located at the apex of the plurality of first mandrels and the second mandrel, and the first etching process is performed to remove the plurality of overhang structures located on the plurality of first mandrels and the second mandrel.

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