A method of optical injection to improve silicon carbide chip wafer yield

Abstract

This application relates to the field of semiconductor device technology and discloses a method for improving the yield of silicon carbide (SiC) chip wafers through photoinjection. The method includes: providing an undivided SiC chip wafer, wherein the SiC material layer of the SiC chip wafer has Shockley-type stacking faults; performing heat treatment on the SiC chip wafer and irradiating the SiC chip wafer with ultraviolet light of irradiation power equal to or less than 200 milliwatts; and dicing the SiC chip wafer to form a plurality of SiC chips, wherein the number of SiC chips with Shockley-type stacking faults is reduced. This application solves the problem in related technologies where the area of ​​Shockley-type stacking faults on SiC chip wafers is large, and the number of SiC chips with effective area is small, resulting in a low overall yield of SiC chip wafers, thereby achieving the effect of improving the yield of SiC chip wafers.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a method for improving the yield of silicon carbide chip wafers through light injection. Background Technology

[0002] Silicon carbide (SiC) devices possess advantages such as high breakdown field strength, high thermal conductivity, and excellent high-temperature stability, making them widely used in fields such as electronic power, high-frequency power supplies, and new energy. However, existing wafers used to fabricate SiC devices suffer from basal plane dislocation defects, leading to bipolar degradation during device conduction. This degradation occurs when electrons and holes recombine during device operation. Under the driving force of carrier recombination, basal plane dislocations slip, splitting into Si and C core partial dislocations. The Si core partial dislocations slip due to carrier recombination, transforming previously less active dislocations into more easily diffused defects (such as Shockley stacking faults), resulting in device degradation and a reduction in the active region area. Current techniques involve cutting away devices with Shockley stacking fault defects. This method results in the loss of many usable components, leading to a smaller number of SiC chips and consequently, lower SiC wafer yield.

[0003] There is currently no effective solution to the problem of low overall yield of silicon carbide chip wafers due to the large area of ​​Shockley stacking faults on silicon carbide chip wafers and the small number of silicon carbide chips with effective area. Summary of the Invention

[0004] The purpose of this application is to provide a method for improving the yield of silicon carbide chip wafers by light injection, in order to solve the problem in related technologies that the Shockley stacking fault area on silicon carbide chip wafers is large and the number of silicon carbide chips with effective area is small, resulting in a low overall yield of silicon carbide chip wafers.

[0005] To achieve the above objectives, one embodiment of this application provides a method for improving the yield of silicon carbide chip wafers through optical injection, the method comprising:

[0006] Provide undivided silicon carbide chip wafers, the silicon carbide material layers of the silicon carbide chip wafers having Shockley-type stacking faults; The silicon carbide chip wafer is heat-treated and then irradiated with ultraviolet light with an irradiation power of 200 mW or less. This reduces the shrinkage barrier of the Shockley stacking faults in the silicon carbide chip wafer, increases electron-hole recombination in the Shockley stacking faults, causes the Shockley stacking faults to shrink, reduces the area of ​​the Shockley stacking faults, and reduces the number of silicon carbide chips occupied by each Shockley stacking fault. The silicon carbide chip wafer is diced to form several silicon carbide chips, among which the number of silicon carbide chips with Shockley stacking faults is reduced.

[0007] In some embodiments, the basal plane dislocations in the silicon carbide material layer of the silicon carbide chip wafer slip under the action of carrier recombination driving force and split into two partial dislocations: the Si core and the C core. The region between the Si core partial dislocation and the C core partial dislocation is the Shockley stacking fault. By lowering the contraction barrier of the Shockley stacking fault, the Si core partial dislocation slips towards the C core partial dislocation, thereby achieving the contraction of the Shockley stacking fault.

[0008] In some embodiments, reducing the contraction barrier of Shockley-type stacking faults includes: Heat treatment is used to provide thermally excited charge carriers to overcome the activation energy barrier of dislocation slip, thereby reducing the energy of the activation energy barrier. By reducing the energy of the activation energy barrier, the overall energy of the silicon carbide chip wafer is reduced, thereby reducing the shrinkage barrier of Shockley stacking faults.

[0009] In some embodiments, the heat treatment temperature is below 300°C.

[0010] In some embodiments, after the silicon carbide chip wafer is irradiated with ultraviolet light and before dicing, the silicon carbide chip wafer is placed in a room temperature or low temperature environment.

[0011] In some embodiments, the wavelength of the ultraviolet light is less than 390 nm.

[0012] In some embodiments, the irradiation power of ultraviolet light is 100 milliwatts to 200 milliwatts.

[0013] In some embodiments, the silicon carbide chip wafer has a silicon carbide substrate or a silicon carbide epitaxial layer, wherein the silicon carbide substrate has Shockley stacking faults, or the silicon carbide epitaxial layer has Shockley stacking faults.

[0014] In some embodiments, the method further includes: after dicing to form a plurality of silicon carbide chips, testing the plurality of silicon carbide chips to sort out silicon carbide chips with Shockley stacking faults and silicon carbide chips without Shockley stacking faults.

[0015] The beneficial effects of this application are: This application employs the following steps: providing an undivided silicon carbide (SiC) chip wafer, wherein the SiC material layer of the SiC chip wafer has Shockley stacking faults; heat-treating the SiC chip wafer and irradiating it with ultraviolet light with an irradiation power equal to or less than 200 milliwatts to reduce the contraction barrier of the Shockley stacking faults in the SiC chip wafer, thereby increasing electron-hole recombination in the Shockley stacking faults and causing them to contract, reducing their area and thus decreasing the number of SiC chips occupied by a single Shockley stacking fault; and dicing the SiC chip wafer to form several SiC chips, wherein the number of SiC chips with Shockley stacking faults is reduced. This solves the problem in related technologies where the area of ​​Shockley stacking faults on SiC chip wafers is large, and the number of SiC chips with effective area is small, resulting in a low overall yield of SiC chip wafers. This, in turn, improves the yield of silicon carbide chip wafers. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0017] Figure 1 This is a flowchart of a method for improving silicon carbide chip wafer yield according to an embodiment of this application; Figure 2 This is a schematic diagram of two partial dislocations in the Si core and C core of this application embodiment; Figure 3 This is a schematic diagram of an undivided silicon carbide chip wafer and its Shockley-type stacking faults according to an embodiment of this application; Figure 4 A schematic diagram of the energy difference between a wafer with Shockley-type stacking faults and a perfect 4H-SiC lattice, and the energy curve of the activation barrier for dislocation slip under thermodynamic equilibrium conditions. Figure 5 This is a schematic diagram of the energy curve between a wafer with Shockley-type stacking faults and a 4H-SiC perfect lattice, only under heating conditions. Figure 6 This is a schematic diagram of the energy curves between a wafer with Shockley-type stacking faults only under low carrier injection conditions and a 4H-SiC perfect lattice. Figure 7This is a schematic diagram of the energy curve between a wafer with Shockley-type stacking faults in a high carrier injection state and a 4H-SiC perfect lattice. Figure 8 This is a schematic diagram of the energy curve between a wafer with Shockley-type stacking faults and a 4H-SiC perfect lattice under low carrier injection synergistic heating conditions. Detailed Implementation

[0018] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0019] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0020] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0022] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0023] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0024] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application: Shockley stacking faults refer to the situation where the atomic layers of silicon carbide are originally stacked one by one according to a predetermined rule, but a certain layer slips into the lattice site of an adjacent layer, causing a small-scale dislocation in the local stacking order. This small-scale dislocation is called a Shockley stacking fault.

[0025] According to an embodiment of this application, a method for improving the yield of silicon carbide chip wafers by light injection is provided.

[0026] Figure 1 This is a flowchart of a method for improving the yield of silicon carbide chip wafers according to embodiments of this application. Figure 1 As shown, the method includes the following steps: Step S101: Provide an undivided silicon carbide chip wafer, wherein the silicon carbide material layer of the silicon carbide chip wafer has Shockley stacking faults.

[0027] The silicon carbide chip wafer is a wafer with several square or rectangular independent chips arranged on it. Each independent chip has already been fabricated with transistors, diodes, and other device structures, as well as all front-end processes such as metal electrodes. The packaging in this step is wafer-level packaging. Dicing will only be performed after wafer-level packaging is completed. The method in this embodiment is used after silicon carbide chip wafer-level packaging and before wafer dicing.

[0028] In other embodiments, the silicon carbide chip wafer has been prepared with a complete chip structure, and then diced to form discrete silicon carbide chips to be packaged.

[0029] In this embodiment, the silicon carbide chip wafer has a silicon carbide substrate with Shockley stacking faults. The surface of the silicon carbide substrate is formed with device structures such as transistors and diodes, as well as all front-end processes such as metal electrodes.

[0030] In another embodiment, the silicon carbide chip wafer has a semiconductor substrate and a silicon carbide epitaxial layer located on the surface of the semiconductor substrate. The surface of the silicon carbide epitaxial layer is formed with device structures such as transistors and diodes, as well as all front-end processes such as metal electrodes. The silicon carbide epitaxial layer has Shockley stacking faults.

[0031] Step S102: The silicon carbide chip wafer is heat-treated and irradiated with ultraviolet light with an irradiation power equal to or less than 200 milliwatts to reduce the shrinkage barrier of the Shockley stacking faults in the silicon carbide chip wafer. This increases the electron-hole recombination of the Shockley stacking faults in the silicon carbide chip wafer, causing the Shockley stacking faults to shrink and reducing their area. Consequently, the number of silicon carbide chips occupied by each Shockley stacking fault is reduced.

[0032] Heat treatment and ultraviolet irradiation are used synergistically to process silicon carbide chip wafers. In this embodiment, the heat treatment temperature is below 300°C, which can reduce the shrinkage barrier of Shockley stacking faults. The silicon carbide chip wafer is then irradiated with ultraviolet light with an irradiation power below 200 milliwatts. This generates electron-hole pairs within the silicon carbide chip wafer. These electron-hole pairs recombine in the Shockley stacking faults after entering a non-equilibrium state, lowering the activation barrier for dislocation slip associated with the Shockley stacking faults. This drives the boundary of the Shockley stacking faults to migrate along the shrinkage direction, reducing the area of ​​the Shockley stacking faults.

[0033] Specifically, ultraviolet (UV) irradiation with a power equal to or less than 200 milliwatts and a wavelength less than 390 nm increases electron-hole recombination, effectively providing a driving force for the contraction of Shockley stacking faults. To increase electron-hole recombination, the energy of the UV light must be higher than the bandgap of the silicon carbide (SiC) chip wafer to excite electrons from the valence band to the conduction band. If the energy of the UV light is lower than the bandgap of the SiC chip wafer, the energy is insufficient for electrons to cross the bandgap, thus preventing the generation of electrons and holes and hindering electron-hole recombination. Therefore, this invention employs UV irradiation with a wavelength less than 390 nm, where the energy of the UV light is higher than the bandgap of the SiC chip wafer.

[0034] In this embodiment, the irradiation power of the ultraviolet light is equal to or less than 200 milliwatts, such as 100 milliwatts, 150 milliwatts, 180 milliwatts, 200 milliwatts, etc.

[0035] In this embodiment, the silicon carbide chip wafer is subjected to heat treatment at a temperature below 300°C, such as 100°C or 200°C. The above-mentioned low-temperature heat treatment will not damage the silicon carbide chip wafer and can effectively improve the driving force of Shockley-type stacking fault shrinkage.

[0036] In this embodiment, the basal plane dislocations in the silicon carbide material layer of the silicon carbide chip wafer slip under the action of carrier recombination driving force, splitting into two partial dislocations: Si core and C core. The region sandwiched between the Si core partial dislocations and the C core partial dislocations is a Shockley stacking fault. By lowering the contraction barrier of the Shockley stacking fault, the Si core partial dislocations slip towards the C core partial dislocations, such as... Figure 2 As shown, this achieves the shrinkage of Shockley-type stacking faults.

[0037] Figure 3 This is a schematic diagram of an undivided silicon carbide chip wafer according to an embodiment of this application, wherein the silicon carbide material layer of the silicon carbide chip wafer has Shockley-type stacking faults. Figure 3 The left figure shows the area occupied by Shockley stacking faults on a silicon carbide chip wafer before ultraviolet light irradiation. Assuming there are two Shockley stacking faults on this silicon carbide chip wafer, and the number of silicon carbide chips occupied by the two Shockley stacking faults is 6, the yield is (16-6) / 16. 100% = 62.5%; Figure 3 The right figure shows the area occupied by Shockley stacking faults after ultraviolet light irradiation of a silicon carbide chip wafer. The number of silicon carbide chips occupied by two Shockley stacking faults is reduced to three, and the yield is (16-3) / 16. 100% = 81.25%. From the results, it can be seen that the Shockley stacking fault shrinks, the area of ​​the Shockley stacking fault on the silicon carbide chip wafer decreases, and the number of silicon carbide chips occupied by each Shockley stacking fault is reduced.

[0038] Step S103: The silicon carbide chip wafer is diced to form a plurality of silicon carbide chips, wherein the number of silicon carbide chips with Shockley stacking faults is reduced.

[0039] Because the processing in step S102 reduces the area of ​​each Shockley stacking fault, the number of silicon carbide chips occupied by a Shockley stacking fault is reduced. By dicing the silicon carbide chip wafer to form several silicon carbide chips, the final number of silicon carbide chips with Shockley stacking faults is reduced. Even if the area of ​​the Shockley stacking fault in the silicon carbide chips with Shockley stacking faults expands again in the future, it will not exceed the area of ​​a single silicon carbide chip and will not affect other silicon carbide chips without Shockley stacking faults, thereby improving the overall yield of silicon carbide chip wafers.

[0040] Furthermore, in the embodiments of this application, a plurality of silicon carbide chips can be formed by dicing, and the plurality of silicon carbide chips can be tested to separate silicon carbide chips with Shockley-type stacking faults and silicon carbide chips without Shockley-type stacking faults.

[0041] The method for testing silicon carbide chips includes: irradiating the test surface of the silicon carbide chip with a laser; acquiring multiple fluorescence images of the test surface after laser irradiation using a CCD array camera; acquiring multiple fluorescence images separately using CCD cameras equipped with different wavelength pass filters; stitching the multiple fluorescence images together to obtain a panoramic fluorescence image of the wafer; determining whether the silicon carbide chip under test has a Shockley-type stacking fault region based on the bright and dark stripes in the panoramic fluorescence image of the wafer, and the difference between whether the Shockley-type stacking fault region is located in the silicon carbide substrate or the epitaxial layer, thereby distinguishing between silicon carbide chips with and without Shockley-type stacking faults.

[0042] In one embodiment, a two-photon photoluminescence microscope using a 780nm femtosecond laser is used to illuminate the test surface of the silicon carbide chip under test; a fluorescence image is obtained using the photoluminescence microscope, and based on the bright and dark stripes in the wafer fluorescence panoramic image, and the difference between the Shockley-type stacking fault region located in the silicon carbide substrate or the epitaxial layer, it is determined whether the silicon carbide chip under test has a Shockley-type stacking fault region.

[0043] Heat treatment is used to provide thermally excited charge carriers to overcome the activation barrier of dislocation slip, thereby reducing the energy of the activation barrier. By reducing the energy of the activation barrier, the overall energy of the silicon carbide chip wafer is reduced, thus lowering the Shockley stacking fault contraction barrier. In the embodiments of this application, heating the silicon carbide chip wafer to below 300°C can reduce the energy of the activation barrier.

[0044] Specifically, the activation barrier of basal dislocations in the silicon carbide material layer of a silicon carbide chip wafer is relatively high, ranging from 1.8 eV to 2.9 eV. For basal dislocations to slip, this inherent activation barrier must be overcome. Heat treatment provides thermally excited charge carriers to overcome the activation barrier. The principle is that heating the wafer excites electrons originally in the valence band, causing them to cross the band gap and transition to the conduction band, leaving holes in place. Effectively, this creates electron-hole pairs as charge carriers, lowering the energy of the activation barrier. Heat treatment effectively reduces the resistance to basal slip. This reduction in the activation barrier lowers the overall energy of the silicon carbide chip wafer, further reducing the shrinkage barrier of Shockley stacking faults, making it easier for the area of ​​Shockley stacking faults to shrink or disappear completely.

[0045] Furthermore, Shockley-type stacking faults are metastable under thermodynamic equilibrium, exhibiting a thermal stability of 14.7 mJ / m. 2 The formation energy of a Shockley-type stacking fault is higher than that of a perfect 4H-SiC (4H-type silicon carbide) lattice. A Shockley-type stacking fault also has a free energy, representing the energy state of the silicon carbide wafer at that point. Without external carrier injection, Shockley-type stacking faults tend to contract. Furthermore, the quantum well effect also lowers the formation energy, further contributing to their contraction. If the energy per unit area exceeds this formation energy, the Shockley-type stacking fault tends to expand. Calculations show that under normal conditions, insufficient electron carriers prevent the formation energy of the Shockley-type stacking fault from being lowered below that of a perfect lattice. Therefore, heating methods can only cause the Shockley-type stacking fault to contract a portion of its area, thus reducing only a portion of the overall energy of the silicon carbide wafer. When external carriers are injected, the activation barrier for dislocation slip is lowered (to 0~0.27 eV). If the injected carrier density is small, the free energy of the Shockley stacked fault will decrease. The decrease in free energy is limited, and the activation barrier also decreases along with the decrease in free energy, eventually causing the Shockley stacked fault to shrink. If the injected carrier density exceeds the critical value, the free energy of the Shockley stacked fault will decrease below the perfect lattice, at which point the Shockley stacked fault will expand.

[0046] Figures 4-7 This is a schematic diagram of the energy curves of a wafer with a Shockley-type stacking fault and a 4H-SiC complete lattice under different external conditions according to embodiments of this application.

[0047] Figure 4 This is a schematic diagram illustrating the energy difference between a wafer with a Shockley-type stacking fault and a perfect 4H-SiC lattice, and the energy curves representing the activation barrier for dislocation slip under thermodynamic equilibrium. The lower horizontal line on the left represents the energy of the perfect 4H-SiC lattice, and the peak of the energy curve represents the activation barrier that dislocation slip needs to overcome, i.e., E0. The higher horizontal line on the right represents the energy required to form a Shockley-type stacking fault, i.e., E0. SF .

[0048] Figure 5 This is a schematic diagram of the energy curves between a wafer with Shockley-type stacking faults and a perfect 4H-SiC lattice under heating conditions only. The black dashed line represents the reference energy level of the original dislocation slip activation barrier, and the black solid line represents the reference energy level of the new activation barrier after thermal excitation, i.e., E0. ΔE0 represents the difference in the activation energy barrier, ΔE SF This represents the change in the formation energy of a Shockley-type stacking fault.

[0049] Figure 6 This is a schematic diagram of the energy curves between a wafer with Shockley-type stacking faults and a perfect 4H-SiC lattice under low carrier injection conditions only. Figure 5 Similarly, the activation barrier of wafers with Shockley-type stacking faults is reduced.

[0050] Figure 7 This is a schematic diagram of the energy curves between a wafer with a Shockley-type stacking fault and a 4H-SiC perfect lattice under high carrier injection conditions. At this time, the wafer with the Shockley-type stacking fault tends to expand.

[0051] Therefore, we can conclude that: if ΔE SF When the change in the formation energy of a Shockley-type stacking fault decreases, the Shockley-type stacking fault tends to contract. If ΔE SF When the change in the formation energy of a Shockley-type stacking fault increases, the fault tends to expand. Shockley-type stacking faults can expand or contract; in this embodiment, it is necessary to reduce the area of ​​the Shockley-type stacking fault.

[0052] Specifically, Figure 8This is a schematic diagram of the energy curves between a wafer with Shockley-type stacking faults and a 4H-SiC perfect lattice under low carrier injection and synergistic heating conditions. Analysis of the stacking fault expansion and contraction mechanism revealed that since silicon carbide chip wafers cannot withstand excessively high temperatures, the temperature is set below 300°C. At this temperature, the slip barrier of the stacking faults is somewhat reduced, but due to the low temperature, the slip contraction efficiency is relatively low. Therefore, a small dose of carriers (obtained by using ultraviolet light with an irradiation power equal to or less than 200 milliwatts in this embodiment) is injected to further reduce the slip barrier without causing it to expand.

[0053] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0054] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for improving the yield of silicon carbide chip wafers through optical injection, characterized in that, include: Provided undivided silicon carbide chip wafers, wherein the silicon carbide material layer of the silicon carbide chip wafers has Shockley-type stacking faults; The silicon carbide chip wafer is heat-treated and then irradiated with ultraviolet light with an irradiation power equal to or less than 200 milliwatts. This reduces the contraction barrier of the Shockley stacking faults in the silicon carbide chip wafer, increases electron-hole recombination in the Shockley stacking faults, causes the Shockley stacking faults to contract, reduces the area of ​​the Shockley stacking faults, and reduces the number of silicon carbide chips occupied by each Shockley stacking fault. The silicon carbide chip wafer is diced to form a number of silicon carbide chips, wherein the number of silicon carbide chips with Shockley stacking faults is reduced.

2. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, The basal plane dislocations in the silicon carbide material layer of the silicon carbide chip wafer slip under the action of carrier recombination driving force, splitting into two partial dislocations: Si core and C core. The region sandwiched between the Si core partial dislocation and the C core partial dislocation is the Shockley stacking fault. By lowering the contraction barrier of the Shockley stacking fault, the Si core partial dislocation slips towards the C core partial dislocation, thereby achieving the contraction of the Shockley stacking fault.

3. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, Lowering the contraction barrier of the Shockley-type stacking fault also includes: Heat treatment is used to provide thermally excited charge carriers to overcome the activation barrier of dislocation slip, thereby reducing the energy of the activation barrier. By reducing the energy of the activation barrier, the overall energy of the silicon carbide chip wafer is reduced, thereby reducing the shrinkage barrier of the Shockley stacking fault.

4. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, The heat treatment temperature is below 300°C.

5. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, A complete chip structure has been fabricated on the surface of the silicon carbide chip wafer that has not yet been diced.

6. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, After the silicon carbide chip wafer is irradiated with ultraviolet light and before it is diced, the silicon carbide chip wafer is placed in a room temperature or low temperature environment.

7. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, The wavelength of the ultraviolet light is less than 390 nm.

8. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, The irradiation power of the ultraviolet light is 100 milliwatts to 200 milliwatts.

9. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, The silicon carbide chip wafer has a silicon carbide substrate or a silicon carbide epitaxial layer, wherein the silicon carbide substrate has Shockley stacking faults, or the silicon carbide epitaxial layer has Shockley stacking faults.

10. The method for improving silicon carbide chip wafer yield by optical injection according to claim 1, characterized in that, Also includes: After dicing to form several silicon carbide chips, the silicon carbide chips are tested and sorted to separate those with Shockley-type stacking faults and those without.

Images