Silicon carbide vdmos resistant to drain voltage impact
By constructing a near-semi-circular protective layer and designing a convex dielectric region in silicon carbide VDMOS devices, optimizing current distribution and gate control, the problems of drain voltage surge resistance and on-resistance of the devices are solved, achieving higher reliability and faster switching speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-05-07
- Publication Date
- 2026-06-05
AI Technical Summary
Existing silicon carbide VDMOS devices have insufficient reliability in terms of withstand drain voltage surges, and their on-resistance is relatively high, making it difficult to meet the requirements of special applications.
A near-semi-circular protective layer is constructed at the bottom of the insulating dielectric region of the device. The insulating dielectric region is designed as a convex shape. Combined with the structural design of the P-type well region and the Schottky metal layer, insulating dielectric layers and Schottky metal layers of different thicknesses are formed through thermal diffusion to optimize current distribution and gate control capability.
While ensuring the device's resistance to drain voltage surges, the on-resistance has been reduced, the switching speed and drain voltage surge resistance have been improved, and the loss during non-conducting freewheeling has been reduced.
Smart Images
Figure CN224329833U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a silicon carbide VDMOS that is resistant to drain voltage surges. Background Technology
[0002] Due to its wide bandgap, silicon carbide VDMOS devices possess high switching speed and high voltage withstand capability. The VDMOS structure can achieve the characteristics of Si IGBT devices, thus attracting much attention from researchers and industry. Against this backdrop, researchers focus on the reliability and conduction characteristics of the devices to meet the needs of special applications. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a silicon carbide VDMOS that is resistant to drain voltage surges, thereby reducing the on-resistance of the device while ensuring that the device is resistant to drain voltage surges.
[0004] This invention provides a silicon carbide VDMOS resistant to drain voltage surges, comprising:
[0005] silicon carbide substrate;
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has a buried layer and a protrusion; a protective layer is provided inside the protrusion;
[0007] P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer;
[0008] A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the P-type source region;
[0009] The P-type well region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, and its inner side connected to the outer side of the protrusion; an N-type source region is provided within the P-type well region.
[0010] An insulating dielectric region, the lower side of which is connected to the N-type source region, the P-type well region, the drift layer and the protective layer respectively;
[0011] A gate metal layer, the gate metal layer being connected to the insulating dielectric region;
[0012] A source metal layer, the lower side of which is connected to the N-type source region, the P-type well region, the Schottky metal layer and the P-type source region respectively;
[0013] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0014] The advantages of this utility model are:
[0015] I. This utility model constructs a nearly semi-circular protective layer at the bottom of the insulating dielectric region of the device by thermal diffusion, forming a structure that is thick in the middle of the insulating dielectric region and thin near the conductive channel. This structure allows electrons to move laterally from the N-type source region through the gate control region to the drain metal layer, and the N-type region area becomes larger and larger during the process, thereby reducing the on-resistance of the device while ensuring the device's resistance to drain voltage surges.
[0016] II. The insulating dielectric region of this utility model is designed in a convex shape. The first insulating dielectric layer is located in the vertical part of the gate metal layer and the P-type well region of the device. The first insulating dielectric layer is relatively thin, which can realize the gate control capability of the gate in this region. There is a second insulating dielectric layer and the first insulating dielectric layer above the P-type protective layer and above the non-P-type well region. The thickness is relatively thick, which can reduce the capacitor charge, improve the switching speed of the device, and improve the device's resistance to drain voltage surge.
[0017] Third, this utility model constructs a Schottky metal layer on the outside of the P-type well region and in the middle of the P-type source region. This Schottky metal layer can reduce the on-state voltage drop of the body diode of the device and reduce the loss when the device is not conducting freewheeling.
[0018] IV. This invention constructs a buried layer below the P-type well region and below the Schottky metal layer. The main function of this buried layer is to guide the current of normal device conduction and body diode freewheeling laterally into the device, thereby reducing the device's on-resistance. Attached Figure Description
[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0020] Figure 1 This is a schematic diagram of a silicon carbide VDMOS that is resistant to drain voltage surges according to this utility model.
[0021] Figure 2 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 1 .
[0022] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 2 .
[0023] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 3 .
[0024] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 4 .
[0025] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 5 .
[0026] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 6 .
[0027] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 7 .
[0028] Figure 9 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 8 .
[0029] Figure 10 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 9 .
[0030] Figure 11 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 10 .
[0031] Figure 12 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 10 one.
[0032] Figure 13 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 10 two.
[0033] Figure 14 This is a cross-sectional view of the process of a silicon carbide VDMOS resistant to drain voltage surges according to this utility model. Figure 10 three. Detailed Implementation
[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0039] like Figure 1 As shown, this application embodiment provides a silicon carbide VDMOS that is resistant to drain voltage surges, comprising:
[0040] Silicon carbide substrate 1;
[0041] A drift layer 2 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 1; a buried layer 21 and a protrusion 22 are provided on the drift layer 2; a protective layer 221 is provided inside the protrusion 22;
[0042] P-type source region 3, the lower side of which is connected to the upper side of the drift layer 2;
[0043] Schottky metal layer 4, the lower side of which is connected to the upper side of the drift layer 2, and the outer side of which is connected to the inner side of the P-type source region 3;
[0044] P-type well region 5, the lower side of which is connected to the upper side of drift layer 2, the outer side of which is connected to the inner side of Schottky metal layer 4, and the inner side of which is connected to the outer side of protrusion 22; an N-type source region 51 is provided in the P-type well region 5;
[0045] An insulating dielectric region 6, the lower side of which is connected to the N-type source region 51, the P-type well region 5, the drift layer 2 and the protective layer 221 respectively;
[0046] A gate metal layer 7 is connected to the insulating dielectric region 6;
[0047] Source metal layer 8, the lower side of which is connected to the N-type source region 51, the P-type well region 5, the Schottky metal layer 4 and the P-type source region 3 respectively;
[0048] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0049] In this embodiment, preferably, the insulating dielectric region 6 includes a first insulating dielectric layer 61 and a second insulating dielectric layer 62. The width of the first insulating dielectric layer 61 is greater than the width of the second insulating dielectric layer 62. The first insulating dielectric layer 61 and the second insulating dielectric layer 62 form a convex shape. The gate metal layer 7 is an inverted concave shape and matches the insulating dielectric region 6.
[0050] In this embodiment, preferably, the width of the protective layer 221 is smaller than the width of the protrusion 22.
[0051] In this embodiment, preferably, the thicknesses of the N-type source region 51, the P-type well region 5, the Schottky metal layer 4, and the P-type source region 3 are all equal.
[0052] In this embodiment, preferably, the doping concentration of the buried layer 21 is greater than the doping concentration of the drift layer 2.
[0053] In this embodiment, preferably, the doping concentration of the P-type source region 3 is greater than or equal to the doping concentration of the P-type well region 5.
[0054] In this embodiment, preferably, the buried layer 21 is located directly below the P-type well region 5 and the Schottky metal layer 4, and the width of the buried layer 21 is less than the sum of the widths of the P-type well region 5 and the Schottky metal layer 4.
[0055] like Figures 1 to 14 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0056] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9, and epitaxially grow on the upper side of silicon carbide substrate 1 to form drift layer 2;
[0057] Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer 100 to form a via, and implant ions to form a buried layer 21;
[0058] Step 3: Remove the barrier layer from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type source region 3;
[0059] Step 4: Remove the barrier layer from Step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type well region 5 and a protrusion 22.
[0060] Step 5: Remove the barrier layer from Step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form an N-type source region 51.
[0061] Step 6: Remove the barrier layer from step 5, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the P-type well region 5 to form a trench 31, deposit metal, and form a Schottky metal layer 4.
[0062] Step 7: Remove the barrier layer from Step 6, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit P++ silicon carbide material 200, and perform thermal diffusion through a high-temperature process to form a protective layer 221.
[0063] Step 8: Remove the barrier layer from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form the first insulating dielectric layer 61; remove the barrier layer, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form the second insulating dielectric layer 62. The insulating dielectric region 6 includes the first insulating dielectric layer 61 and the second insulating dielectric layer 62.
[0064] Step 9: Remove the barrier layer from step 8, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal, and form the gate metal layer 7.
[0065] Step 10: Remove the barrier layer from step 9, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal to form the source metal layer 8, remove the barrier layer 100, and complete the fabrication.
[0066] Another embodiment of this utility model includes a drain metal layer 9, an N+ silicon carbide substrate 1, an N-type drift layer 2, an N-type buried layer 21, a P-type source region 3, a Schottky metal layer 4, a P-type well region 5, an N-type source region 51, a P-type protective layer 221, a first insulating dielectric layer 61, a second insulating dielectric layer 62, a gate metal layer 7, and a source metal layer 8. The doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 5-9e16cm. -3 The doping concentration of the N-type buried layer 21 is 1-5e17cm. -3 The doping concentration of P-type source region 3 is 0.8-5e19cm. -3 The doping concentration of P-type well region 5 is 5-8e18cm. -3 The doping concentration of the P-type protective layer 221 is 5-8e17cm. -3 The doping concentration of the N-type source region 51 is 2-8e18cm. -3 The insulating dielectric region can be made of silicon dioxide, and the gate metal layer 7, source metal layer 8 and drain metal layer 9 can be one or an alloy of several metals, namely Al, Cu and Ni.
[0067] The doping concentrations of the N-type silicon carbide substrate 1, N-type drift layer 2, P-type well region 5, and P-type source region 3 represent a trade-off between the on-resistance and breakdown voltage of the planar gate silicon carbide VDMOS device. The doping concentration of the N-type buried layer 21 represents a trade-off between the device's on-resistance, internal current sharing, and the distribution of the internal electric field. Too high a concentration can easily create a high electric field region inside the device structure, while too low a concentration does not have a lateral current sharing effect. The P-type protective layer 221 is designed to improve the device's drain voltage surge withstand capability, and its low doping concentration is to avoid the influence of the P-type region 3 on the device's on-resistance.
[0068] The width of the first insulating dielectric layer 61 is 2 μm, and the width of the second insulating dielectric layer 62 is 1.4 μm. The portion of the first insulating dielectric layer 61 that is wider than the second insulating dielectric layer 62 is equal on both sides, each being 0.3 μm. The width of the P-type well region 5 inside the N-type source region 51 is 0.3 μm. The maximum width of the P-type guard layer 221 is 1 μm. This is to control the diffusion of the space charge region of the P-type guard layer 221 and the N-type drift layer 2 into the conductive channel, thus affecting the conductivity characteristics of the device. The width of the N-type source region 51 is 1 μm, and the total width of the P-type well region 5 is 2 μm. This is to ensure the drain-source breakdown capability of the device when the drain is subjected to voltage. The width of the Schottky metal layer 4 is 500 nm, and the width of the P-type source region 3 is 500 nm. This is a compromise between the distribution of the Schottky body diode and the PN junction body diode. The width of the N-type buried layer 21 is 2 μm, and the edge of the buried layer 21 away from the gate metal layer 7 is located in the center of the Schottky metal layer 4.
[0069] The depth of the P-type well region 5 is 1 μm, the depth of the N-type source region 51 is 500 nm, the depth of the Schottky metal layer 4 is 1 μm, and the depth of the P-type source region 3 is 1 μm. This is to ensure that the contact depth between the Schottky diode and the PN junction diode and the N-type drift layer 2 is the same, improve interface consistency, and avoid non-ideal effects introduced by interface defects. The maximum depth of the P-type protective layer 221 is 800 nm, designed to withstand a drain voltage surge of 3000 V. The thickness of the N-type buried layer 21 is 600 nm, and the distance between its upper side and the lower side of the P-type well region 5 is 1 μm. This is to prevent the space charge region formed by the P-type well region 5 and the N-type drift layer 2 from spreading to the N-type buried layer 21 and affecting the current sharing effect. The thickness of the first insulating dielectric layer 61 is 50 nm, and the thickness of the second insulating dielectric layer 62 is 100 nm. This is the combined design of gate control capability and drain voltage surge resistance. The thickness of the source metal layer 8 is 300 nm, and the thickness of the gate metal layer 7 is 300 nm.
[0070] This invention constructs a nearly semi-circular protective layer 221 at the bottom of the insulating dielectric region 6 of the device by thermal diffusion, forming a structure that is thick in the middle region of the insulating dielectric region 6 and thin near the conductive channel. This structure allows electrons to move laterally from the N-type source region 51 through the gate control region to the drain metal layer 9, and the N-type region area becomes larger and larger during the process, thereby reducing the on-resistance of the device while ensuring the device's resistance to drain voltage surges.
[0071] The insulating dielectric region 6 is designed in a convex shape. The first insulating dielectric layer 61 is located in the vertical part of the device gate metal layer 7 and the P-type well region 5. The first insulating dielectric layer 61 is relatively thin, which can realize the gate control capability of the region. Above the P-type protective layer 221 and above the non-P-type well region 5, there is a second insulating dielectric layer 62 and the first insulating dielectric layer 61. The thickness is relatively thick, which can reduce the capacitor charge, improve the switching speed of the device, and improve the device's resistance to drain voltage surges.
[0072] A Schottky metal layer 4 is constructed between the outer side of the P-type well region 5 and the middle of the P-type source region 51 of the device. This Schottky metal layer 4 can reduce the on-state voltage drop of the body diode of the device and reduce the loss when the device is not conducting freewheeling.
[0073] An N-type buried layer 21 is constructed below the P-type well region 5 and the Schottky metal layer 4 of the device. The main function of the buried layer 21 is to guide the current of the device during normal conduction and the freewheeling current of the body diode laterally into the device, thereby reducing the on-resistance of the device.
[0074] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide VDMOS resistant to drain voltage surges, characterized in that: include: silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer has a buried layer and a protrusion; the protrusion has a protective layer inside; P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer; A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the P-type source region; The P-type well region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, and its inner side connected to the outer side of the protrusion; an N-type source region is provided within the P-type well region. An insulating dielectric region, the lower side of which is connected to the N-type source region, the P-type well region, the drift layer and the protective layer respectively; A gate metal layer, the gate metal layer being connected to the insulating dielectric region; A source metal layer, the lower side of which is connected to the N-type source region, the P-type well region, the Schottky metal layer and the P-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The silicon carbide VDMOS with resistance to drain voltage surges as described in claim 1, characterized in that: The insulating dielectric region includes a first insulating dielectric layer and a second insulating dielectric layer. The width of the first insulating dielectric layer is greater than the width of the second insulating dielectric layer. The first insulating dielectric layer and the second insulating dielectric layer form a convex shape. The gate metal layer is an inverted concave shape and matches the insulating dielectric region.
3. A silicon carbide VDMOS resistant to drain voltage surges as described in claim 1, characterized in that: The width of the protective layer is smaller than the width of the protrusion.
4. A silicon carbide VDMOS resistant to drain voltage surges as described in claim 1, characterized in that: The thicknesses of the N-type source region, P-type well region, Schottky metal layer, and P-type source region are all equal.
5. A silicon carbide VDMOS resistant to drain voltage surges as described in claim 1, characterized in that: The doping concentration of the buried layer is greater than that of the drift layer.
6. A silicon carbide VDMOS resistant to drain voltage surges as described in claim 1, characterized in that: The doping concentration of the P-type source region is greater than or equal to the doping concentration of the P-type well region.
7. A silicon carbide VDMOS resistant to drain voltage surges as described in claim 1, characterized in that: The buried layer is located directly below the P-type well region and the Schottky metal layer, and the width of the buried layer is less than the sum of the widths of the P-type well region and the Schottky metal layer.