Chip manufacturing method and apparatus

Abstract

A chip manufacturing method and apparatus. The chip manufacturing method includes: fabricating a plurality of predetermined chip sets on a wafer, wherein each predetermined chip set includes a plurality of individual chips; performing a conformity test on each individual chip in the plurality of predetermined chip sets; and dicing the wafer based on the test results, wherein, in response to each chip in a first predetermined chip set being conformable, the first predetermined chip set is diced as a whole, or in response to a portion of chips in a second predetermined chip set being conformable, the conformable and non-conforming individual chips in the second predetermined chip set are diced and separated. This chip manufacturing method dices the wafer in different ways based on the conformity of the individual chips formed on the wafer, thereby reducing manufacturing costs.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 202210871350.X, filed on July 22, 2022. Technical Field

[0002] The embodiments of this disclosure generally relate to a chip manufacturing method and apparatus. Background Technology

[0003] As semiconductor process dimensions continue to shrink, chiplet technology (or small chip technology) has been proposed to address challenges in integrated circuit (IC) manufacturing, such as yield and reticle size. This technology uses die-to-die (D2D) interconnection techniques to connect multiple functional dies together, enabling the packaging of multiple module chips with the underlying base chip to form a system-on-a-chip (SoC). Multiple SoCs can be further integrated into a multi-chip module (MCM) to create high-density and high-reliability microelectronic components.

[0004] Because of its advantages such as significantly improving the yield of large chips, reducing design complexity and design costs, and reducing chip manufacturing costs, chip assembly technology is widely used in today's semiconductor chip manufacturing. Summary of the Invention

[0005] This disclosure provides at least one embodiment of a chip manufacturing method. The chip manufacturing method includes: fabricating a plurality of predetermined chip sets on a wafer, wherein each predetermined chip set includes a plurality of single chips; performing a conformity test on each single chip in the plurality of predetermined chip sets; and dicing the wafer based on the test results, wherein, in response to each chip in a first predetermined chip set being conformable, the first predetermined chip set is diced as a whole, or in response to a portion of chips in a second predetermined chip set being conformable, the non-conforming single chips and conformable single chips in the second predetermined chip set are diced and separated. This chip manufacturing method dices the wafer in different ways based on the conformity of the single chips formed on the wafer, thereby reducing manufacturing costs.

[0006] For example, in at least one embodiment of the chip manufacturing method provided in this disclosure, after dicing the wafer based on test results, the method further includes packaging the intermediate products obtained from the dicing.

[0007] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, packaging the intermediate product obtained by dicing includes: packaging the first intermediate product obtained by dicing a first predetermined chip set as a whole; and packaging the second intermediate product obtained by dicing and separating the unqualified single chip and the qualified single chip in the second predetermined chip set, which includes at least one qualified single chip.

[0008] For example, in the chip manufacturing method provided in at least one embodiment of this disclosure, the second intermediate product including at least one qualified single chip includes at least two single chips interconnected with each other, and the second intermediate product including at least one qualified single chip obtained by cutting and separating the unqualified single chip and the qualified single chip in the second predetermined chip set includes: encapsulating the at least two interconnected single chips as a whole.

[0009] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, fabricating a plurality of predetermined chip sets on a wafer includes: a plurality of single chips in the same predetermined chip set located in the plurality of predetermined chip sets are formed by at least the same chip photomask.

[0010] In at least one embodiment of the chip manufacturing method provided in this disclosure, fabricating a plurality of predetermined chip sets on a wafer includes: fabricating conductive structures in the wafer to electrically connect two adjacent single chips within the same predetermined chip set.

[0011] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, fabricating a plurality of predetermined chip sets on a wafer further includes: forming a dicing region between two adjacent single chips within the same predetermined chip set; and wherein fabricating a conductive structure in the wafer to electrically connect two adjacent single chips within the same predetermined chip set includes: the two adjacent single chips being electrically connected via the dicing region through the conductive structure.

[0012] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, the preparation of a plurality of predetermined chip sets on a wafer further includes: setting sealing rings at both ends of the dicing region between two adjacent single chips.

[0013] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, a sealing ring is aligned with the chip edges of two single chips that are perpendicular to the extension direction of the dicing region.

[0014] In at least one embodiment of the chip manufacturing method provided in this disclosure, after testing each single chip in a plurality of predetermined chip sets, the method further includes: forming at least one redistribution layer on a wafer to electrically connect two adjacent qualified single chips in the same predetermined chip set based on the test results.

[0015] For example, in the chip manufacturing method provided in at least one embodiment of this disclosure, when the same predetermined chip set is a first predetermined chip set, the redistribution layer includes a first conductive structure for electrically connecting all qualified single chips in the first predetermined chip set; or, when the same predetermined chip set is a second predetermined chip set, if the second predetermined chip set includes two adjacent qualified single chips in the same row or column, the redistribution layer includes a second conductive structure for electrically connecting two adjacent qualified single chips in the same row or column in the second predetermined chip set; or if the second predetermined chip set does not include two adjacent qualified single chips in the same row or column, the redistribution layer is not formed on the second predetermined chip set, or the redistribution layer is formed on the second predetermined chip set but does not electrically connect two adjacent single chips.

[0016] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, the preparation of a plurality of predetermined chip sets on a wafer further includes: forming a dicing region between two adjacent single chips within the same predetermined chip set, wherein a redistribution layer is electrically connected to two adjacent qualified single chips within the same predetermined chip set via the dicing region between two adjacent qualified single chips within the same predetermined chip set.

[0017] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, forming at least one redistribution layer on a wafer to electrically connect two adjacent qualified single chips within the same predetermined chip set includes: for the case where the same predetermined chip set is a first predetermined chip set, forming a redistribution layer including a first conductive structure on the first predetermined chip set using a first photomask; or, for the case where the same predetermined chip set is a second predetermined chip set, forming a redistribution layer including a second conductive structure on the second predetermined chip set using a second photomask, or forming a redistribution layer on the second predetermined chip set that does not electrically connect two adjacent single chips using a third photomask, wherein the first photomask, the second photomask, and the third photomask are different from each other.

[0018] For example, in a chip manufacturing method provided in at least one embodiment of this disclosure, at least one redistribution layer includes at least one passivation layer, conductive traces formed on the surface of the passivation layer, and vias passing through the passivation layer.

[0019] At least one embodiment of this disclosure provides a chip manufacturing apparatus, which includes a processor and a memory including at least one computer program module; wherein the at least one computer program module is stored in the memory and configured to be executed by the processor to implement the chip manufacturing method provided in any embodiment of this disclosure.

[0020] At least one embodiment of this disclosure provides a computer-readable storage medium that non-temporarily stores computer-executable instructions, which, when executed by a computer, can implement the chip manufacturing method provided in any embodiment of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 This is a schematic diagram showing a wafer comprising multiple chip assemblies.

[0023] Figure 2 It is shown Figure 1 A schematic diagram of a chip assembly.

[0024] Figure 3 This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure.

[0025] Figure 4A This is a schematic diagram illustrating a plurality of exemplary pre-defined chip assemblies in a wafer.

[0026] Figure 4B The diagram illustrates the final product obtained by packaging intermediate products obtained from cutting different predetermined chip sets.

[0027] Figure 4C This is a structural diagram showing the example final product.

[0028] Figure 5A This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure.

[0029] Figure 5B It shows Figure 4A A schematic diagram of the predetermined chip set and its cross-sectional view along AA'.

[0030] Figure 6A This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure.

[0031] Figure 6B This is a schematic diagram illustrating the formation of a redistribution layer on a wafer using different photomasks according to at least one embodiment of the present disclosure.

[0032] Figure 6C It shows Figure 4A A schematic diagram of an example of a pre-defined chip set and its cross-sectional view along AA'.

[0033] Figure 7A schematic diagram of a chip manufacturing apparatus according to an embodiment of the present disclosure is shown.

[0034] Figure 8 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] Some embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of this disclosure appears in more than one drawing, that component is indicated by the same or similar reference numerals in each drawing.

[0038] As mentioned above, chiplet technology is widely used in modern semiconductor chip manufacturing. Generally, multiple chips are formed on a wafer, and the wafer is diced to form multiple individual chips. The qualified individual chips are then packaged to obtain the desired chip product. However, the size of the chips formed on the wafer affects the yield rate of the resulting chips. Therefore, as the area and density of chips formed on the wafer increase, the cost of testing to obtain qualified individual chips also increases.

[0039] To address at least the aforementioned problems, this disclosure provides at least one embodiment of a chip manufacturing method. The chip manufacturing method includes: fabricating a plurality of predetermined chip sets on a wafer, wherein each predetermined chip set includes a plurality of individual chips; performing a conformity test on each individual chip in the plurality of predetermined chip sets; and dicing the wafer based on the test results, wherein, in response to each chip in a first predetermined chip set being conforming, the first predetermined chip set is diced as a whole, or in response to some chips in a second predetermined chip set being conforming, the non-conforming individual chips and conforming individual chips in the second predetermined chip set are diced and separated. This embodiment's chip manufacturing method dices the wafer in different ways based on the conformity of the individual chips formed on the wafer, obtaining different chip set forms, thereby reducing manufacturing costs.

[0040] Figure 1 This is a schematic diagram showing a wafer 100 comprising multiple chip sets 110.

[0041] like Figure 1 As shown, wafer 100 includes a plurality of chip sets 110 arranged in a grid, wherein each chip set 110 further includes a plurality of individual chips (also referred to as dies) 120. For example, in Figure 1 In this embodiment, a chip assembly 110 may include four individual chips 120. For example, the four chips 120 may have the same function and / or structure, such as four processor cores of the same processor, or the four chips 120 may have different functions and / or structures, such as processor cores, image processing cores, AI acceleration cores, and memory units in the same system-on-a-chip (SoC), but this disclosure is not limited thereto. For example, multiple individual chips in the same chip assembly 110 may be combined to form a chiplet. As another example, individual chips from different chip assemblies may also be combined to form a chiplet.

[0042] In some embodiments, multiple individual chips located in the same chip set within multiple chip sets 110 may be processed as a whole during chip fabrication, and may be formed from at least the same chip fabrication mask. For example, the same mask may be used for at least one photolithography process in the chip fabrication process, followed by an etching process. Alternatively, the same multiple mask (e.g., the same batch of mask) may be used for multiple photolithography processes in the chip fabrication process, followed by separate etching processes. Typically, fabricating a chip requires dozens or even hundreds of photolithography processes. For example, in some examples, multiple individual chips located in each chip set within multiple chip sets 110 are formed from the same chip fabrication mask; or, in other examples, multiple individual chips located in different chip sets within multiple chip sets 110 may be formed from different chip fabrication masks. The following will refer to... Figure 2 Further description of chip assembly 110.

[0043] Figure 2 It is shown Figure 1 A schematic diagram of a chip assembly 110.

[0044] like Figure 2 As shown, chip assembly 110 includes four individual chips 120a, 120b, 120c, and 120d. Individual chips 120a, 120b, 120c, and 120d can be configured as follows: Figure 2 The arrangement shown is configured in the chip assembly 110. Furthermore, dicing regions 150 are formed between adjacent individual chips. That is, within the chip assembly 110, cross-shaped dicing regions 150 are formed between individual chips 120a and 120b, between individual chips 120a and 120c, between individual chips 120b and 120d, and between individual chips 120c and 120d; on the other hand, similar grid-shaped dicing regions are formed between the chip assemblies (see...). Figure 1 After fabrication, if the chip assembly is cut through the dicing channels between the chip assemblies, an independent chip assembly can be obtained; furthermore, if the chip assembly is cut entirely or partially through the dicing channels within the chip assembly, an independent single chip or a single chip assembly comprising two or more single chips can be obtained. For example, cutting can be performed using methods such as rotary saws, wire saws, and lasers.

[0045] Figure 3 This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure. The following will be combined with... Figure 1 and Figure 2 Detailed description Figure 3 The chip manufacturing method shown in the figure.

[0046] like Figure 3 As shown, the chip manufacturing method may include the following steps S310, S320 and S330.

[0047] Step S310: Fabricate a plurality of predetermined chip sets 110 on wafer 100, wherein each predetermined chip set 110 includes a plurality of single chips (e.g., Figure 1 single chip 120 or Figure 2 The single-chip 120a, 120b, 120c and 120d are collectively referred to here as single-chip 120.

[0048] Step S320: Perform a conformity test on each individual chip 120 in the plurality of predetermined chip sets 110.

[0049] Step S330: Cut wafer 100 based on the test results.

[0050] In different embodiments of this disclosure, examples of step S330 may further include the following steps S340, S350 and S360.

[0051] Step S340: For each of the multiple predetermined chip sets 110, determine whether each single chip 120 in the same predetermined chip set 110 is qualified.

[0052] Step S350: In response to the fact that each single chip 120 in the first predetermined chip set of a plurality of predetermined chip sets 110 is qualified, the first predetermined chip set is cut as a whole.

[0053] Step S360: In response to the fact that some single chips 120 in the second predetermined chip set of the plurality of predetermined chip sets 110 are qualified, the unqualified single chips and qualified single chips in the second predetermined chip set are cut and separated.

[0054] The terms "first predetermined chip set", "second predetermined chip set", etc., are used to refer to the chip set selected as the processing object among the multiple predetermined chip sets 110. It can be any chip set among the multiple predetermined chip sets 110 that conforms to the above description.

[0055] In some embodiments, such as Figure 1 A plurality of predetermined chip sets 110 are fabricated on the wafer 100 shown, the plurality of predetermined chip sets 110 being fabricated in a grid pattern on the wafer 100. Each predetermined chip set 110 may include a plurality (e.g., four) of individual chips 120. Each of the plurality of individual chips 120 is then subjected to conformity testing, for example, testing the electrical capabilities and circuit functions of the individual chip 120, or any chip performance testing well known to those skilled in the art, which is not limited herein. After the conformity testing of each individual chip 120 is completed, a dicing scheme is determined based on the test results, and the wafer 100 is diced according to the dicing scheme.

[0056] For example, according to at least one embodiment of this disclosure, each single chip 120 within one of the plurality of predetermined chip sets 110 (hereinafter referred to as the "first predetermined chip set") is qualified. Therefore, in response to the qualification of each single chip 120 within the first predetermined chip set, the first predetermined chip set can be diced as a whole. In other words, the first predetermined chip set can be directly diced from the wafer 100, and after dicing, the individual chips in the first predetermined chip set remain mechanically connected to each other, without first dicing the wafer 100 into a plurality of single chips 120 and then integrating a portion of the plurality of single chips 120 into a chip set.

[0057] For example, according to at least another embodiment of this disclosure, a portion of the individual chips 120 within one of the plurality of predetermined chip sets 110 (hereinafter referred to as the "second predetermined chip set") are qualified. Therefore, in response to the qualification of a portion of the individual chips 120 within the second predetermined chip set, the unqualified individual chips and qualified individual chips in the second predetermined chip set can be cut and separated. In other words, the predetermined chip set 110 that meets the aforementioned requirements will be further cut to separate the unqualified individual chips and qualified individual chips in the predetermined chip set 110. For example, after cutting, the plurality of qualified individual chips in the second predetermined chip set (if any) may remain mechanically connected to each other, or they may also be separated.

[0058] Reference Figure 4A In conjunction with the above steps S340, S350 and S360, the following will describe in detail how to implement step S330 of cutting wafer 100 based on the test results.

[0059] Figure 4A This is a schematic diagram showing a plurality of exemplary predetermined chip sets 410, 420 and 430 in wafer 100.

[0060] like Figure 4AAs shown, multiple chip assemblies are fabricated on wafer 100, including at least the predetermined chip assemblies 410, 420, and 430 discussed below. Each predetermined chip assembly 410, 420, and 430 includes four individual chips. Specifically, predetermined chip assembly 410 includes individual chips 412a, 412b, 412c, and 412d; predetermined chip assembly 420 includes individual chips 422a, 422b, 422c, and 422d; and predetermined chip assembly 430 includes individual chips 432a, 432b, 432c, and 432d. For example, in each photolithography process of the chip fabrication process, the above-mentioned multiple chip assemblies are fabricated by a step-through exposure process. Therefore, the multiple individual chips located in predetermined chip assemblies 410, 420, and 430 can be formed from the same chip fabrication mask.

[0061] like Figure 4A As shown in the predetermined chip set 410, four single chips 412a, 412b, 412c, and 412d are all qualified single chips. Therefore, based on the above... Figure 3 In steps S340 and S350, the predetermined chip set 410 can be cut as a whole. After cutting, the four individual chips in the predetermined chip set 410 remain mechanically connected to each other.

[0062] like Figure 4A As shown in the predetermined chip set 420, among the four single chips 422a, 422b, 422c, and 422d in the predetermined chip set 420, single chips 422b and 422c are defective single chips, while single chips 422a and 422d are qualified single chips. Therefore, based on the above... Figure 3 Steps S340 and S360 in the process can separate the defective single chips 422b and 422c from the qualified single chips 422a and 422d in the predetermined chip set 420. After cutting, the two qualified single chips in the predetermined chip set 420 are not only separated from each other, but also separated from the other defective single chips.

[0063] like Figure 4A As shown in the predetermined chip set 430, among the four single chips 432a, 432b, 432c, and 432d in the predetermined chip set 430, single chips 432a and 432b are defective single chips, while single chips 432c and 432d are qualified single chips. Therefore, similarly, based on the above... Figure 3In steps S340 and S360, the defective single chips 432a and 432b in the predetermined chip set 430 are cut and separated from the qualified single chips 432c and 432d. After cutting, the two qualified single chips in the predetermined chip set 410 remain mechanically connected to each other, but are separated from the other defective single chips.

[0064] In some embodiments, after dicing the wafer 100 based on test results, the process further includes packaging the intermediate products obtained from the dicing. For example, the intermediate products obtained from the dicing of the first predetermined chip set as a whole (e.g., the entire first predetermined chip set obtained from the dicing) can be packaged, or the intermediate products obtained from the dicing and separation of defective single chips and qualified single chips in the second predetermined chip set (e.g., qualified single chips obtained from the dicing and separation) can be packaged.

[0065] return Figure 3 The chip manufacturing method of this disclosure may further include steps S355 and S365.

[0066] S355: Package the first intermediate product obtained by cutting the first predetermined chip set as a whole.

[0067] S365: Package a second intermediate product, which includes at least one qualified single chip, obtained by cutting and separating the unqualified single chip and the qualified single chip in the second predetermined chip set.

[0068] The following will refer to Figure 4A Examples of steps S355 and S365 described above are further described below.

[0069] As mentioned earlier, due to Figure 4A The four single chips 412a, 412b, 412c and 412d in the predetermined chip set 410 are all qualified single chips. Therefore, the predetermined chip set 410 can be cut as a whole to obtain a first intermediate product 415, and then the first intermediate product 415 can be packaged as a whole, for example to obtain an intermediate product that can be used with other chip sets or to obtain a final product.

[0070] However, for Figure 4A The predetermined chip sets 420 and 430, since not all individual chips within them are qualified, can be packaged after separating the qualified and unqualified individual chips from the predetermined chip sets 420 and 430, resulting in a second intermediate product including at least one qualified individual chip. For example, for Figure 4AAfter separating the defective single chips 422b and 422c from the qualified single chips 422a and 422d in the predetermined chip set 420, the resulting intermediate product including at least one of the qualified single chips 422a and 422d can be packaged. For example, the intermediate product 425a including the qualified single chip 422a and the intermediate product 425b including the qualified single chip 422d can be packaged respectively to obtain an intermediate product for subsequent use with other chip sets or to obtain a final product.

[0071] Similarly, for Figure 4A After separating the defective individual chips 432a and 432b from the qualified individual chips 432c and 432d in the predetermined chip set 430, an intermediate product including at least one of the qualified individual chips 432c and 432d can be packaged. For example, an intermediate product including the qualified individual chip 432c (not shown) and an intermediate product including the qualified individual chip 432d (not shown) can be packaged separately. In this case, the qualified individual chips 432c and 432d in the predetermined chip set 430 are separated into individual chips 432c and 432d, for example, to obtain an intermediate product for subsequent use with other chip sets or to obtain a final product.

[0072] However, according to other embodiments of this disclosure, a second intermediate product including at least one qualified single chip may include at least two qualified single chips in the same row or column. Therefore, packaging the resulting second intermediate product including at least one qualified single chip may include packaging at least two qualified single chips in the same row or column as a whole.

[0073] like Figure 4A As shown, for Figure 4A The predetermined chip set 430, with qualified single chips 432c and 432d fabricated in the same row (or in the same column), therefore, according to at least one embodiment of the present disclosure, the intermediate product 435, which includes both qualified single chips 432c and 432d, can be packaged.

[0074] Figure 4B This illustrates further intermediate or final products obtained by packaging intermediate products obtained from cutting different predetermined chip sets.

[0075] like Figure 4BAs shown, for a predetermined set of chips 410 in which all individual chips (i.e., individual chips 412a, 412b, 412c and 412d) are qualified, the intermediate product 415 obtained by cutting is packaged to obtain the final product P1. For example, the final product P1 includes four qualified individual chips and all of the individual chips included therein have been interconnected by, for example, conductive structures prepared in the wafer or redistribution layers formed on the wafer (which will be described in detail later).

[0076] like Figure 4B As shown, not all individual chips in the predetermined chip set are qualified chips. For example, in predetermined chip set 420, the intermediate products 425a and 425b obtained by dicing them can be packaged to obtain two final products P2, each of which includes one qualified chip. Similarly, predetermined chip set 430 can also be diced and packaged to obtain two final products P2, which respectively include qualified chips 432c and 432d. However, unlike predetermined chip set 420, the two qualified chips in predetermined chip set 430 are two adjacent chips in the same row. Therefore, for predetermined chip set 430, as shown above, the intermediate product 435, which includes both qualified chips 432c and 432d, can also be packaged to obtain a final product P3. For example, the final product P3 may include two adjacent qualified chips interconnected by, for example, conductive structures prepared in the wafer or redistribution layers formed on the wafer (described in detail later).

[0077] The following will refer to Figure 4C Taking the final product P1 obtained by packaging the intermediate product 415 obtained by cutting the predetermined chip set 410 as an example, the structure of the final product is briefly described.

[0078] Figure 4C It is shown Figure 4B The structural diagram of the final product P1.

[0079] like Figure 4C As shown, the final product 400 includes a substrate 490 and a plurality of single chips 412 disposed on the substrate 490, wherein a dicing region 418 is formed between two adjacent single chips 412. A bump 480 is provided between the substrate 490 and the single chips 412 disposed thereon for fixing the single chips 412 to the substrate 490 and connecting them to conductive structures (such as leads, vias, or contact pads) in the substrate 490.

[0080] Furthermore, as will be described in detail below, according to at least one embodiment of the present invention, two adjacent single chips 412 are electrically connected to each other in the dicing region 418, avoiding problems such as high energy consumption, high cost, and complex process that may arise from, for example, setting traces in the substrate to connect adjacent single chips.

[0081] In yet another embodiment, the final product may be a chiplet consisting of a single single chip (e.g., Figure 4B The final product P2), or it can be a chip product composed of two adjacent single chips (e.g., Figure 4B The final product P3), and the aforementioned chiplets and / or chip products can then, for example, be disposed on a substrate and electrically connected to each other through interposers, redistribution layers (RDLs), or to other functional modules on the substrate to form a new chip assembly, or can be integrated into a multi-chip module to form a high-density and high-reliability microelectronics assembly.

[0082] The chip manufacturing method described above determines the wafer dicing based on whether each of the multiple single chips in a plurality of predetermined chip sets on the wafer is qualified. A complete chip set including multiple qualified single chips can be directly diced from the wafer, thereby reducing manufacturing costs. Furthermore, a small chip (or chip chip) including at least one qualified single chip can also be diced from the wafer, so that each qualified single chip can be fully utilized and packaged into a final product, thereby improving the wafer packaging yield and helping to solve problems such as high energy consumption, high cost, and complex process of at least some of the obtained products.

[0083] On the other hand, in traditional chip assembly technologies, interconnecting interface circuits, such as die-to-die (D2D) interfaces and high-bandwidth memory (HBM) physical interfaces, are typically required between the logic chips and input / output chips within the chip assembly. For artificial intelligence (AI) and high-performance computing (HP), multiple logic chips are usually needed to meet the enormous computing power requirements. Considering the limitations of chip yield and mask size, the aforementioned chip assembly technologies and die-to-die interconnect technologies are essential for the manufacture of chips suitable for AI and HP computing (e.g., multi-chip modules (MCMs)).

[0084] Currently, to achieve D2D interconnection in a chip assembly, bumps (or microbumps (uBump)) and substrate traces are typically used to connect the bare dies (also referred to as single chips in this paper) of the chip assembly within an MCM, or interconnection of the bare dies in the chip assembly is achieved through bumps (and / or microbumps) and traces in the interposer. However, regardless of which D2D interconnection method is used, additional connection components (e.g., bumps, traces) are required, making the fabrication process complex and costly. Furthermore, due to the connection characteristics of bumps and traces, achieving D2D interconnection also faces significant challenges in terms of bandwidth and power consumption.

[0085] At least in response to the above-mentioned problems, at least one embodiment of this disclosure also provides a chip manufacturing method. The method includes fabricating conductive structures in the wafer to electrically connect two adjacent single chips within the same predetermined chip set when fabricating a plurality of predetermined chip sets on a wafer, thereby achieving high-bandwidth and low-power D2D connectivity while reducing manufacturing costs.

[0086] Figure 5A This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure.

[0087] like Figure 5A As shown, Figure 3 Step S310 may further include the following step S3105.

[0088] Step S3105: Fabricate a conductive structure in the wafer to electrically connect two adjacent single chips within the same predetermined chip set.

[0089] For example, refer to Figure 4A After fabricating multiple predetermined chip sets 410, 420 and 430 on wafer 100, conductive structures are also fabricated in wafer 100 to electrically connect two adjacent single chips within the same predetermined chip set. For example, connecting two adjacent single chips within predetermined chip set 410 (such as single chips 412a and 412b, single chips 412a and 412c, single chips 412b and 412d, and single chips 412c and 412d); connecting two adjacent single chips within predetermined chip set 420 (such as single chips 422a and 422b, single chips 422a and 422c, single chips 422b and 422d, and single chips 422c and 422d); connecting two adjacent single chips within predetermined chip set 430 (such as single chips 432a and 432b, single chips 432a and 432c, single chips 432b and 432d, and single chips 432c and 432d).

[0090] As shown above, a cut-out region is formed between two adjacent single chips within the same predetermined chip set. Therefore, in some embodiments, two adjacent single chips can be electrically connected via the cut-out region through a conductive structure.

[0091] The following will refer to Figure 5B ,by Figure 4A Taking the pre-ordered chip set 410 as an example, we will elaborate further. Figure 5B Examples are shown Figure 4A A schematic diagram of the predetermined chip set 410 and its cross-sectional view along AA'.

[0092] like Figure 5B As shown, within the predetermined chip assembly 410, a dicing region 418 is formed between each adjacent single chip (i.e., between single chips 412a and 412b, between single chips 412a and 412c, between single chips 412b and 412d, and between single chips 412c and 412d). Adjacent single chips, for example, single chips 412c and 412d, can be further electrically connected via the dicing region 418 through a conductive structure 417. Similarly, single chips 412a and 412b, single chips 412a and 412c, and single chips 412b and 412d are all electrically connected via the dicing region 418 through a conductive structure identical or similar to the conductive structure 417.

[0093] return Figure 5A After multiple predetermined chip sets are fabricated on the wafer (step S310), and conductive structures are fabricated in the wafer to electrically connect two adjacent single chips in each of the multiple predetermined chip sets (step S310), the following can be performed: Figure 3 Steps S320 and S330, as described above, refer to... Figure 3 Similarly, steps S350 and S355 or steps S360 and S365 are performed as described above, which will not be repeated here.

[0094] In this embodiment, for example, no conductive structure is fabricated between adjacent single chips in a predetermined chip set as described above.

[0095] Furthermore, according to yet another embodiment of this disclosure, using Figure 5A When using chip manufacturing methods, such as Figure 5BAs shown, sealing rings 416 can be respectively provided at both ends of the dicing region between two adjacent single chips in a plurality of predetermined chip sets fabricated on a wafer. For example, the sealing rings 416 can be aligned with the chip edges of the two single chips perpendicular to the extension direction of the dicing region. The sealing rings are used to seal the dicing region to prevent moisture from entering, and the sealing rings 416 can also prevent the chips from being damaged by mechanical stress during dicing. In some cases, the sealing rings 416 can be grounded to shield against external interference and provide electrostatic discharge protection. In some implementations, the sealing rings 416 can be made of metal, but they do not provide electrical connection to adjacent single chips.

[0096] As mentioned above, by first fabricating conductive structures in the wafer to electrically connect adjacent single chips within the same predetermined chip set, the bandwidth and power consumption problems caused by using microbumps (or bumps) and substrate traces to connect adjacent single chips can be avoided. At the same time, since the conductive structures are fabricated directly in the wafer to electrically connect the single chips in the chip set, the process flow of chip set fabrication is simplified and the additional cost required to connect the single chips in the chip set is reduced.

[0097] At least one embodiment of this disclosure also provides a chip manufacturing method. The method includes, after testing each single chip in a plurality of predetermined chip sets on a wafer, forming at least one redistribution layer on the wafer based on the test results to electrically connect two adjacent qualified single chips within the same predetermined chip set, thereby achieving high-bandwidth and low-power D2D connectivity while reducing manufacturing costs.

[0098] Figure 6A This is a flowchart illustrating a chip manufacturing method according to at least one embodiment of the present disclosure.

[0099] like Figure 6A As shown, Figure 3 The step S3205 may be further included after step S320 and before step S330.

[0100] Step S3205: Based on the test results, form at least one redistribution layer on the wafer to electrically connect two adjacent qualified single chips within the same predetermined chip set.

[0101] In some embodiments, for cases where the same predetermined chip set is a first predetermined chip set (as described above, each individual chip within the predetermined chip set is qualified), the redistribution layer may include a first conductive structure for electrically connecting all qualified individual chips within the first predetermined chip set. For example, a redistribution layer including the first conductive structure may be formed on the first predetermined chip set using a first photomask.

[0102] In some other embodiments, for the case where the same predetermined chip set is a second predetermined chip set (as mentioned above, some individual chips 120 within the predetermined chip set are qualified), if the second predetermined chip set includes two adjacent qualified individual chips in the same row or column (e.g., Figure 4A In the predetermined chip set 430), the redistribution layer may include a second conductive structure for electrically connecting two adjacent qualified single chips in the same row or column on the second predetermined chip set, wherein the redistribution layer including the second conductive structure can be formed on the second predetermined chip set using a second photomask; or, if the second predetermined chip set does not include two adjacent qualified single chips in the same row or column (e.g., Figure 4A In the predetermined chip set 420, the redistribution layer may not be formed on the second predetermined chip set, or the redistribution layer may be formed on the second predetermined chip set but not electrically connected to two adjacent single chips. When the redistribution layer is formed on the second predetermined chip set but not electrically connected to two adjacent single chips, a third photomask can be used to form a redistribution layer on the second predetermined chip set that does not electrically connect two adjacent single chips.

[0103] It should be noted that the first, second, and third photomasks here are completely different from the chip fabrication photomasks mentioned above. For example, the first, second, and third photomasks can be used in the same photolithography process for fabricating the redistribution layer. After using the first, second, and third photomasks to expose the photoresist to obtain a photoresist mask, this photoresist mask is then used for etching. After the redistribution layer is formed, structures such as bumps can be subsequently formed on it.

[0104] Figure 6B This is a schematic diagram illustrating the formation of a redistribution layer on wafer 100 using different photomasks (610a, 610b and 610c) according to at least one embodiment of the present disclosure.

[0105] As described above, based on the results of conformity tests for each individual chip within the same predetermined chip set, different photomasks can be used to form a redistribution layer including conductive structures within that same predetermined chip set. Figure 6B In this context, "G" (Good) indicates a single chip that passes the qualification test, while "NG" (Not Good) indicates a single chip that fails the qualification test.

[0106] like Figure 6BAs shown, if each single chip in the same predetermined chip set is qualified, that is, if all single chips in a predetermined chip set are qualified single chips "G", then a redistribution layer including a first conductive structure can be formed in the predetermined chip set using a first photomask 610a. The redistribution layer including the first conductive structure can electrically connect two adjacent qualified single chips "G" in the predetermined chip set.

[0107] When not all individual chips within the same predetermined chip set are qualified, i.e., the same predetermined chip set includes both qualified single chips "G" and unqualified single chips "NG", it can be further divided into the following two cases. In some embodiments, a predetermined chip set may include two adjacent qualified single chips "G" in the same row or column. Therefore, in this case, a redistribution layer including a second conductive structure can be formed on the predetermined chip set using a second photomask 610b. This redistribution layer including the second conductive structure can electrically connect the two adjacent qualified single chips "G" within the predetermined chip set, and can prevent the unqualified single chip "NG" from being electrically connected to its adjacent single chip (either a qualified single chip "G" or an unqualified single chip "NG"). It should be noted that the second photomask 610b is not fixed here; specifically, the shape of the second photomask 610b can vary according to the distribution of the qualified single chips "G". For example, in Figure 6B In the example shown, because the distribution of qualified single chips "G" within the predetermined chip set covered by the second photomask 610b-1 and the second photomask 610b-2 is different, the second photomask 610b-1 and the second photomask 610b-2 are correspondingly different. Figure 6B As shown, within the predetermined chip set covered by the second photomask 610b-1, only two adjacent single chips are qualified single chips "G". Therefore, the redistribution layer formed by the second photomask 610b-1 on the predetermined chip set it covers can electrically connect two adjacent qualified single chips "G". In contrast, within the predetermined chip set covered by the second photomask 610b-2, three adjacent single chips in an "L" shape are qualified single chips "G". Therefore, the redistribution layer formed by the second photomask 610b-2 on the predetermined chip set it covers can electrically connect three adjacent qualified single chips "G" in an "L" shape. In some other embodiments, the plurality of qualified single chips “G” included in the predetermined chip set are not adjacent to each other or include only one qualified single chip “G”, or all single chips included in the predetermined chip set are unqualified single chips “NG”. In this case, a redistribution layer that does not electrically connect two adjacent single chips can be formed on the predetermined chip set using a third photomask 610c. That is, the redistribution layer formed on the predetermined chip set using the third photomask 610c does not include conductive structures.

[0108] According to some embodiments of this disclosure, the first photomask 610a, the second photomask 610b, and the third photomask 610c are different from each other, and the second photomask 610b may include multiple second photomasks of different shapes (e.g., second photomask 610b-1 and second photomask 610b-2), thereby allowing for the targeted formation of redistribution layers with different conductive structures (or without conductive structures). Furthermore, for redistribution layers that can be formed using photomasks and include conductive structures (e.g., a redistribution layer with a first conductive structure formed using the first photomask 610a, or a redistribution layer with a second conductive structure formed using the second photomask 610b), for example, the redistribution layer may include at least one passivation layer, conductive traces formed on the surface of the passivation layer, and vias passing through the passivation layer, the vias being filled with conductive material. However, this disclosure is not limited to this; the redistribution layer may include any suitable conductive structure.

[0109] As shown above, a cleavage region is formed between two adjacent single chips within the same predetermined chip set. Therefore, in some embodiments, the redistribution layer is electrically connected to two adjacent qualified single chips within the same predetermined chip set via the cleavage region between them. The following will refer to... Figure 6C still with Figure 4A Taking the pre-ordered chip set 410 as an example, we will elaborate further.

[0110] Figure 6C It shows Figure 4A A schematic diagram of an example of a pre-defined chip set 410 and its cross-sectional view along AA'.

[0111] like Figure 6C As shown, dicing regions 418 are formed between adjacent single chips within the predetermined chip set 410 (i.e., between single chips 412a and 412b, between single chips 412a and 412c, between single chips 412b and 412d, and between single chips 412c and 412d). As described above, since all single chips 412a, 412b, 412c, and 412d within the predetermined chip set 410 are qualified single chips, a photomask ( Figure 6BA first photomask 610a) forms a redistribution layer including a first conductive structure 617 on a predetermined chip assembly 410. This redistribution layer including the first conductive structure 617 electrically connects individual chips 412c and 412d via a dicing region 418. Similarly, individual chips 412a and 412b, 412a and 412c, and 412b and 412d within the predetermined chip assembly 410 are electrically connected via the redistribution layer including the first conductive structure 617 through the dicing region 418. In some embodiments, the redistribution layer including the first conductive structure 617 may include at least one passivation layer, conductive traces formed on the surface of the passivation layer, and vias passing through the passivation layer.

[0112] Similar to Figure 5B As described, in some examples, sealing rings 616 may also be provided at both ends of the dicing region between two adjacent single chips in a plurality of predetermined chip sets fabricated on a wafer. The arrangement and characteristics of the sealing rings 616 are as described above. Figure 5B The sealing ring 416 is similar, so it will not be described in detail here.

[0113] As described above, after testing each single chip in a plurality of predetermined chip sets on a wafer, at least one redistribution layer is formed on the wafer based on the test results to electrically connect two adjacent qualified single chips within the same predetermined chip set. Only adjacent qualified single chips can be electrically connected, avoiding redundant electrical connections (e.g., electrical connections with adjacent unqualified single chips), thereby reducing the additional cost required to connect single chips in the chip set and thus reducing manufacturing costs.

[0114] At least one embodiment of this disclosure also provides a chip manufacturing apparatus, which includes a processor; a memory including at least one computer program module; wherein, when the at least one computer program module is stored in the memory and configured to be executed by the processor, it can implement the chip manufacturing method provided in any embodiment of this disclosure.

[0115] Figure 7 A schematic diagram of a chip manufacturing apparatus 700 according to an embodiment of the present disclosure is shown. For example... Figure 7 As shown, the chip manufacturing apparatus 700 includes a processor 710 and a memory 720. The memory 720 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 executes the non-transitory computer-readable instructions, which, when executed by the processor 710, can perform one or more steps in the chip manufacturing method described above. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0116] For example, processor 710 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. For example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 710 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in chip manufacturing equipment 700 to perform desired functions.

[0117] For example, memory 720 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include random access memory (RAM) and / or cache memory. Non-volatile memory may include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 710 may run one or more computer program modules to implement various functions of chip manufacturing apparatus 700. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0118] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the chip manufacturing equipment 700 can be referred to the description of the chip manufacturing method above, and will not be repeated here.

[0119] At least one embodiment of this disclosure also provides a computer-readable storage medium that non-temporarily stores computer-executable instructions, which, when executed by a computer, can implement the chip manufacturing method provided in any embodiment of this disclosure.

[0120] Figure 8 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. Figure 8 As shown, the storage medium 800 is used to store non-transitory computer-readable instructions 810. For example, when the non-transitory computer-readable instructions 810 are executed by a computer, one or more steps in the chip manufacturing method described above can be performed.

[0121] For example, the storage medium 800 can be used in the chip manufacturing equipment 700 described above. For example, the storage medium 800 can be... Figure 7 The memory 720 in the chip manufacturing apparatus 700 shown. For example, a description of the storage medium 800 can be found here. Figure 7The corresponding description of the memory 720 in the chip manufacturing equipment 700 shown will not be repeated here.

[0122] The following points should be noted regarding this disclosure:

[0123] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0124] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0125] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip manufacturing method, comprising: Multiple predetermined chip assemblies are fabricated on a wafer, wherein each predetermined chip assembly includes multiple single chips; Perform a qualification test on each individual chip in the plurality of predetermined chip sets; The wafer is diced based on the test results, wherein... In response to the fact that each individual chip in the first predetermined chip set of the plurality of predetermined chip sets is qualified, the first predetermined chip set is cut as a whole, or In response to the fact that some individual chips in the second predetermined chip set of the plurality of predetermined chip sets are qualified, the unqualified individual chips and qualified individual chips in the second predetermined chip set are cut and separated.

2. The method according to claim 1, further comprising, after dicing the wafer based on the test results: The intermediate products obtained from the cutting process are then packaged.

3. The method according to claim 2, wherein, The packaging of the intermediate products obtained from the cutting process includes: The first intermediate product obtained by cutting the first predetermined chip set as a whole is packaged as a whole; The second intermediate product, which includes at least one of the qualified single chips, obtained by cutting and separating the unqualified single chips and qualified single chips from the second predetermined chip set, is packaged.

4. The method according to claim 3, wherein, The second intermediate product, which includes at least one of the qualified single chips, comprises at least two single chips interconnected with each other. The process of packaging the second intermediate product, which includes at least one of the qualified single chips, obtained by cutting and separating the unqualified single chips and qualified single chips from the second predetermined chip set, includes: The at least two interconnected single chips are packaged together.

5. The method according to any one of claims 1-4, wherein, The fabrication of the plurality of predetermined chip assemblies on a wafer includes: Multiple single chips located in the same predetermined chip set within the plurality of predetermined chip sets are formed by photomasks fabricated from at least the same chip.

6. The method according to claim 1, wherein, The fabrication of the plurality of predetermined chip assemblies on a wafer includes: Conductive structures are fabricated in the wafer to electrically connect two adjacent single chips within the same predetermined chip set.

7. The method according to claim 6, wherein, The fabrication of the plurality of predetermined chip sets on the wafer further includes: A dicing region is formed between two adjacent individual chips within the same predetermined chip set. The process of fabricating the conductive structure in the wafer to electrically connect two adjacent single chips within the same predetermined chip set includes: The two adjacent single chips are electrically connected through the conductive structure via the dicing region.

8. The method according to claim 7, wherein, The fabrication of the plurality of predetermined chip sets on the wafer further includes: Sealing rings are provided at both ends of the dicing area between two adjacent single chips.

9. The method according to claim 8, wherein, The sealing ring is aligned with the chip edges of the two single chips that are perpendicular to the extension direction of the cut channel region.

10. A chip manufacturing apparatus, comprising: Memory; and A processor, including at least one computer program module; The at least one computer program module is stored in the memory and configured to implement the chip manufacturing method as described in any one of claims 1-9 when executed by the processor.

11. A computer-readable storage medium that non-transitorily stores computer-executable instructions, which, when executed by a computer, are used to implement the chip manufacturing method according to any one of claims 1-9.

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