Semiconductor structure and manufacturing method

Abstract

This invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate having a first conductivity type; at least one epitaxial layer disposed above the substrate; a deep trench isolation structure penetrating the at least one epitaxial layer and the substrate, the deep trench isolation structure surrounding a first region and including a second region outside the deep trench isolation structure; a patterned isolation layer disposed on a bottom surface of the substrate, having an opening to expose the second region of the substrate; and a conductive layer disposed below the patterned isolation layer and electrically connected to the substrate via the opening.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure including a local isolation region and a method for manufacturing the same. Background Technology

[0002] With the evolution of integrated circuit manufacturing technology, various components can be integrated onto a single chip, including lateral components where current flows horizontally, such as complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs), and vertical components where current flows vertically, such as dynamic random-access memory (DRAM). Local isolation structures need to be formed within the single substrate to isolate lateral and vertical components. Junction isolation regions or partial silicon on insulator (SOI) regions are typically used as local isolation structures. However, the depth of junction isolation regions is limited by the implantation energy of the ion implantation machine. Furthermore, the process for forming SOI regions mainly includes separation by implantation of oxygen (SIMOX) and smart cut processes; however, many problems still need to be overcome when using SIMOX and smart cut processes to form local isolation structures. Summary of the Invention

[0003] In view of this, the present invention proposes a semiconductor structure and its manufacturing method, which uses a deep trench isolation structure and a patterned isolation layer located on the back side of the substrate to form a local isolation region to isolate lateral and vertical components integrated in a single chip. Besides avoiding the problems encountered with conventional methods of forming junction isolation regions and partially overlaid silicon regions on insulating layers, it also effectively prevents lateral components from being subjected to high-potential surges from vertical components, making it more suitable for high-voltage applications (e.g., above 80 volts).

[0004] According to an embodiment of the present invention, a semiconductor structure is provided, comprising: a substrate having a first conductivity type; at least one epitaxial layer disposed above the substrate; a deep trench isolation structure penetrating the at least one epitaxial layer and the substrate, the deep trench isolation structure surrounding a first region and including a second region outside the deep trench isolation structure; a patterned isolation layer disposed on a bottom surface of the substrate, having an opening exposing the second region of the substrate; and a conductive layer disposed below the patterned isolation layer and electrically connected to the substrate via the opening.

[0005] According to another embodiment of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate having a first conductivity type, including a first surface and a second surface on opposite sides; forming an epitaxial layer on the first surface of the substrate; forming a deep trench isolation structure in the epitaxial layer and the substrate, the deep trench isolation structure surrounding a first region and including a second region outside the deep trench isolation structure; performing a polishing process on the second surface of the substrate to thin the substrate and expose the deep trench isolation structure; depositing an isolation material layer on the thinned second surface of the substrate and contacting the bottom surface of the deep trench isolation structure; patterning the isolation material layer to form a patterned isolation layer having an opening to expose the second region of the substrate; and forming a conductive layer below the patterned isolation layer, the conductive layer being electrically connected to the substrate via the opening. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

[0008] Figures 3 to 9 This is a cross-sectional schematic diagram illustrating some stages of a semiconductor structure manufacturing method according to an embodiment of the present invention.

[0009] Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage of a semiconductor structure manufacturing method according to another embodiment of the present invention.

[0010] Explanation of reference numerals in the attached figures:

[0011] 100… Semiconductor Structure

[0012] 100-1…First District

[0013] 100-2…Second District

[0014] 101…base

[0015] 101F…First Surface

[0016] 101B…Second Surface

[0017] 103… epitaxial layer

[0018] 103-1…First epitaxial layer

[0019] 103-2…Second epitaxial layer

[0020] 105…Deep trench isolation structure

[0021] 106…Insulation material layer

[0022] 107… Patterned isolation layer

[0023] 108…opening

[0024] 109…conductive layer

[0025] 111…N-LDMOS transistor

[0026] 113…P-LDMOS transistor

[0027] 115…CMOS transistors

[0028] 117…VDMOS transistor

[0029] 121, 144… Dielectric layers

[0030] 122…gate

[0031] 123, 145…field boards

[0032] 125…Matrix area

[0033] 127…Source Region

[0034] 129…doped region

[0035] 131…First Buried Layer

[0036] 132…First sub-deep trench isolation structure

[0037] 133…Second Buried Layer

[0038] 134…Second sub-deep trench isolation structure

[0039] 135…Third Buried Layer

[0040] 136…Third sub-deep trench isolation structure

[0041] 141… trench

[0042] 142…Dielectric sheath

[0043] 143…Semiconductor Materials

[0044] 150… Shallow trench isolation zone

[0045] 151…Deep trench

[0046] 152…filling material

[0047] Well areas 161, 162, 163, 164, 165, 166, 167…

[0048] 168, 169... doped regions

[0049] 171···Dielectric layer

[0050] 173··· Gate

[0051] 180··· Interlayer dielectric layer

[0052] 181, 182···Contact

[0053] T1···Initial Thickness

[0054] T2, T4...thickness

[0055] T3, T5... depth

[0056] S···Source potential

[0057] D···Drain potential

[0058] G··· Gate potential

[0059] B···Base potential

[0060] Subbasal potential

[0061] SB... Single substrate

[0062] Steps S101A, S101B, S103A, S103B, S105A, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125... Detailed Implementation

[0063] This invention provides several different embodiments for implementing various features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact," or it may mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and not to indicate any correlation between different embodiments and / or configurations.

[0064] Furthermore, regarding spatially related descriptive terms used in this invention, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the accompanying drawings. In addition to the orientations shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor structure during use and operation. As the orientation of the semiconductor structure varies (rotation by 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0065] Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the order of arrangement or manufacturing process of one element with another. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section, etc.

[0066] The terms "about" or "substantially" used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0067] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0068] Although the invention is described below with reference to specific embodiments, the principles of the invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0069] Embodiments of the present invention utilize a deep trench isolation structure and a patterned isolation layer on the back side of the substrate to form a local isolation region, thereby isolating lateral and vertical components integrated in a monolithic chip. The deep trench isolation structure and the patterned isolation layer surround the lateral components without obstructing the electron flow from the vertical components to the substrate. In the off-state, the lateral components are not subjected to high-potential surges from the vertical components, making it suitable for applications on higher voltage platforms (e.g., above 80 volts). Furthermore, the semiconductor structure and manufacturing method according to the present invention avoids the problem of forming only a junction isolation region, the depth of which is limited by ion implantation energy, and also avoids the epitaxial defects and surface height differences caused by forming a partial insulating layer overlaid with silicon in the prior art.

[0070] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure 100 according to an embodiment of the present invention. The semiconductor structure 100 includes a substrate 101 having a first conductivity type, such as an N-type heavily doped silicon substrate. The substrate 101 includes a first surface 101F (also referred to as the upper surface) and a second surface 101B (also referred to as the bottom surface) on opposite sides. An epitaxial layer 103 is disposed on the first surface 101F of the substrate 101. The epitaxial layer 103 also has a first conductivity type, such as an N-type silicon epitaxial layer. The substrate 101 and the epitaxial layer 103 constitute a monolithic substrate SB. In one embodiment, the epitaxial layer 103 includes a first epitaxial layer 103-1 and a second epitaxial layer 103-2, stacked on the substrate 101 from bottom to top. However, it is not limited to this, and the epitaxial layer 103 may include one, three, or more epitaxial layers. Furthermore, the composition of the first epitaxial layer 103-1 and the second epitaxial layer 103-2, the doping concentration of the first conductivity type dopant, and / or the thickness may be different. In some embodiments, the substrate 101 is composed of, for example, silicon (Si), silicon carbide (SiC) or other suitable semiconductor materials, and the epitaxial layer 103 is composed of, for example, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP) or other suitable semiconductor materials.

[0071] According to an embodiment of the present invention, the semiconductor structure 100 includes a deep trench isolation (DTI) structure 105 that penetrates the epitaxial layer 103 and the substrate 101, extending downward from the top surface of the epitaxial layer 103 to the second surface 101B of the substrate 101. The deep trench isolation structure 105 surrounds a first region 100-1 of the semiconductor structure 100, and outside the deep trench isolation structure 105, it includes a second region 100-2 of the semiconductor structure 100. Figure 1 The cross-sectional view only shows the deep trench isolation structure 105 located to the right of the first region 100-1 for top view. The deep trench isolation structure 105 surrounds the first region 100-1, and the second region 100-2 is located in the region to the right of the deep trench isolation structure 105. Lateral devices are set in the epitaxial layer 103 of the first region 100-1, such as N-type lateral double-diffused metal-oxide-semiconductor (N-LDMOS) transistor 111, P-type lateral double-diffused metal-oxide-semiconductor (P-LDMOS) transistor 113, and complementary metal-oxide-semiconductor (CMOS) transistor 115. However, it is not limited to these. Other lateral devices, such as bipolar transistors, can also be set in the epitaxial layer 103 of the first region 100-1. These lateral devices in the first region 100-1 can form a bipolar-CMOS-DMOS integrated architecture, abbreviated as BCD architecture.

[0072] Vertical devices, such as vertical double-diffused metal-oxide-semiconductor (VDMOS) transistors 117, insulated-gate bipolar transistors (IGBTs), trench MOS transistors, and / or other vertical devices, are disposed in the epitaxial layer 103 of the second region 100-2. The VDMOS transistor 117 includes multiple trenches 141 formed in the epitaxial layer 103 of the second region 100-2. A gate 122, a field plate 123, and a dielectric layer 121 are disposed within the trenches 141 of the active region. The gate 122 is located directly above the field plate 123, and the dielectric layer 121 surrounds the gate 122 and the field plate 123, longitudinally separating the gate 122 from the field plate 123. A body region 125 is disposed on both sides of the trench 141 of the active region. The body region 125 is, for example, a P-type well region. A source region 127 is disposed within the body region 125. The source region 127 is, for example, a heavily doped N-type region. Furthermore, a field plate 145 and a dielectric layer 144 are disposed within the trench 141 outside the active region, wherein the dielectric layer 144 surrounds the field plate 145. The substrate 101 is, for example, a heavily doped N-type silicon substrate. The substrate 101 of the second region 100-2 constitutes the drain region of the VDMOS transistor 117. Electron flow is perpendicular from the source region 127 to the substrate 101 of the second region 100-2.

[0073] Furthermore, the semiconductor structure 100 also includes a patterned isolation layer 107 disposed on a second surface (bottom surface) 101B of the substrate 101. The patterned isolation layer 107 has an opening 108 to expose the substrate 101 of the second region 100-2. In some embodiments, viewed from above, the area of ​​the opening 108 and the area of ​​the VDMOS transistor 117 may be substantially the same, or the area of ​​the opening 108 may be smaller than the area of ​​the VDMOS transistor 117. The semiconductor structure 100 also includes a conductive layer 109 disposed below the patterned isolation layer 107. The conductive layer 109 is electrically connected to the substrate 101 of the second region 100-2 via the opening 108, and the conductive layer 109 may serve as the drain electrode of the VDMOS transistor 117. In one embodiment, the conductive layer 109 is a metal layer, the composition of which may include gold, titanium, silver, copper, aluminum copper, other suitable metals or alloys. The conductive layer 109 covers the bottom and sides of the patterned isolation layer 107 and directly contacts the substrate 101 of the second region 100-2.

[0074] like Figure 1As shown, the bottom surface of the deep trench isolation structure 105 contacts the top surface of the patterned isolation layer 107. Viewed from above, the boundary of the patterned isolation layer 107 extends beyond the boundary of the deep trench isolation structure 105. According to an embodiment of the present invention, the deep trench isolation structure 105 and the patterned isolation layer 107 can completely surround a plurality of lateral elements in the first region 100-1, including N-LDMOS transistors 111, P-LDMOS transistors 113, CMOS transistors 115, and other horizontal elements. Simultaneously, the local isolation region formed by the deep trench isolation structure 105 and the patterned isolation layer 107 does not impede the vertical electron flow of vertical elements in the second region 100-2, such as VDMOS transistors 117, towards the substrate 101. VDMOS transistor 117 can be used as a power integrated circuit (power IC) component, suitable for high voltage and high current operating conditions. The use of deep trench isolation structure 105 and patterned isolation layer 107 can effectively prevent the lateral components of the first region 100-1 from being subjected to high potential surges from the vertical components of the second region 100-2, and can also avoid electrostatic discharge (ESD) latch-up caused by current noise from the vertical components. Therefore, the semiconductor structure 100 of this embodiment is suitable for applications with higher voltage (e.g., above 80 volts).

[0075] In addition, Figure 1 In the embodiments, a first buried layer 131, a second buried layer 133, and a third buried layer 135 may also be disposed in the epitaxial layer 103 of the first region 100-1, respectively located directly below the N-LDMOS transistor 111, the P-LDMOS transistor 113, and the CMOS transistor 115. The first buried layer 131, the second buried layer 133, and the third buried layer 135 all have a second conductivity type different from the first conductivity type of the epitaxial layer 103, for example, they are all P-type buried layers. The P-type first buried layer 131, the second buried layer 133, and the third buried layer 135 can generate a junction isolation effect with the N-type epitaxial layer 103, thereby providing junction isolation regions for the N-LDMOS transistor 111, the P-LDMOS transistor 113, and the CMOS transistor 115 respectively.

[0076] In one embodiment, the deep trenches of the deep trench isolation structure 105 may be completely filled with an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable organic insulating materials, or combinations thereof. The patterned isolation layer 107 may be composed of the same insulating material as the deep trench isolation structure 105. For example, the deep trenches of the deep trench isolation structure 105 may be filled with silicon oxide, and the patterned isolation layer 107 may be a silicon oxide layer. However, it is not limited to this, and the patterned isolation layer 107 may also be composed of other insulating materials different from those of the deep trench isolation structure 105. In addition, the thickness of the patterned isolation layer 107 can be adjusted according to the voltage rating of the vertical element in the second region 100-2. When the operating voltage of the VDMOS transistor 117 is higher, the thickness of the patterned isolation layer 107 can be increased accordingly. For example, when the operating voltage of the VDMOS transistor 117 is 80V or above, the thickness of the patterned isolation layer 107 can be adjusted to 0.3 micrometers (μm) or greater than 0.3 μm.

[0077] In another embodiment, a dielectric layer and a semiconductor material may be filled within the deep trench isolation structure 105, wherein the dielectric layer conformally lining the sidewalls of the deep trench, and the semiconductor material filling the deep trench. The dielectric layer may be composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the semiconductor material may be, for example, polysilicon. For deep trenches with high aspect ratios, the semiconductor material has better hole-filling capability than the material used for the dielectric layer, and can fill the deep trench with little or no voids. Furthermore, when the deep trench isolation structure 105 is filled with semiconductor material, the bias voltage of the deep trench isolation structure 105 may be a floating potential or electrically coupled to a ground terminal to further prevent mutual interference between the lateral elements of the first region 100-1 and the vertical elements of the second region 100-2.

[0078] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure 100 according to another embodiment of the present invention. In this embodiment, the semiconductor structure 100 further includes a first sub-deep trench isolation structure 132, a second sub-deep trench isolation structure 134, and a third sub-deep trench isolation structure 136 disposed in a first region 100-1. These sub-deep trench isolation structures all penetrate the epitaxial layer 103 and the substrate 101, and the bottom surfaces of these sub-deep trench isolation structures all contact the top surface of the patterned isolation layer 107. Specifically, the first sub-deep trench isolation structure 132 is disposed between an N-LDMOS transistor 111 and a P-LDMOS transistor 113, the second sub-deep trench isolation structure 134 is disposed between a P-LDMOS transistor 113 and a CMOS transistor 115, and the third sub-deep trench isolation structure 136 isolates the N-LDMOS transistor 111 from other components in the first region 100-1.

[0079] In one embodiment, the sub-deep trench isolation structures of the first region 100-1 may have the same composition, the same depth, and the same width as the deep trench isolation structure 105. In another embodiment, the sub-deep trench isolation structures of the first region 100-1 all have the same composition, depth, and width, and the composition and width of these sub-deep trench isolation structures may differ from the composition and width of the deep trench isolation structure 105. For example, insulating material may be filled within these sub-deep trench isolation structures, while a dielectric layer and semiconductor material may be lined within the deep trench isolation structure 105, and the width of these sub-deep trench isolation structures may be smaller than the width of the deep trench isolation structure 105. Furthermore, in Figure 2 In the semiconductor structure 100, a junction isolation region may not be provided directly below the lateral elements in the first region 100-1. For example, a P-type buried layer may not be provided directly below the N-LDMOS transistor 111, P-LDMOS transistor 113, and CMOS transistor 115. Good isolation can be provided between the N-LDMOS transistor 111, P-LDMOS transistor 113, and CMOS transistor 115 by means of the first sub-deep trench isolation structure 132, the second sub-deep trench isolation structure 134, and the third sub-deep trench isolation structure 136. Figure 2 Details of other features of the semiconductor structure 100 can be found in the foregoing. Figure 1 The relevant descriptions of the semiconductor structure 100 will not be repeated here.

[0080] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional schematic diagram of some stages of a semiconductor structure 100 manufacturing method according to an embodiment of the present invention. For example... Figure 3In step S101A, a substrate 101 having a first conductivity type, such as an N-type heavily doped silicon substrate, is first provided. The substrate 101 has a first surface 101F and a second surface 101B on opposite sides, and in step S101A, the substrate 101 has an initial thickness T1. Then, a first epitaxial layer 103-1 and a second epitaxial layer 103-2 are sequentially epitaxially grown on the first surface 101F of the substrate 101. These epitaxial layers all have the first conductivity type, for example, both are N-type silicon epitaxial layers. The first epitaxial layer 103-1 and the second epitaxial layer 103-2 constitute epitaxial layer 103, which has a thickness T2. Next, a deep trench 151 with a high aspect ratio is formed in the epitaxial layer 103 and the substrate 101 using an etching process such as deep reactive ion etching (DRIE). The aspect ratio can be, for example, greater than 50. A deep trench 151 extends downward from the top surface of the epitaxial layer 103, penetrates the epitaxial layer 103 to reach the substrate 101, and the bottom surface of the deep trench 151 is located in the substrate 101. Subsequently, using deposition and chemical mechanical planarization (CMP) processes, the deep trench 151 is filled with filler material 152 to form a deep trench isolation structure 105. The deep trench isolation structure 105 surrounds a first region 100-1, and a second region 100-2 is contained outside the deep trench isolation structure 105.

[0081] In one embodiment, the filling material 152 is an insulating material, such as silicon oxide. In another embodiment, the filling material 152 comprises a dielectric layer and a semiconductor material, wherein the dielectric layer, for example, is a silicon oxide layer, deposited oriented on the inner sidewalls and bottom surface of the deep trench 151, and the semiconductor material, for example, is polysilicon, filling the deep trench 151, with the dielectric layer surrounding the semiconductor material. In step S101A, the deep trench 151 of the deep trench isolation structure 105 has a depth T3, and the depth T3 can be adjusted according to the target depth of the deep trench isolation structure 105 in the semiconductor structure. For example, when the target depth of the deep trench isolation structure 105 is 100 μm, the depth T3 of the deep trench 151 can be 120 μm to 150 μm, and the initial thickness T1 of the substrate 101 can be 750 μm, and the thickness T2 of the epitaxial layer 103 can be 10 μm. In addition, the width of the deep trench 151 is determined by the aspect ratio achievable by the etching process and the depth T3.

[0082] Continue reading Figure 3 In step S103A, a plurality of trenches 141 of VDMOS transistors are etched in the epitaxial layer 103 of the second region 100-2. Then, using deposition and chemical mechanical planarization processes, a dielectric substrate 142 is formed in the orientation within each trench 141, and a semiconductor material 143, such as polysilicon, is filled within each trench 141, wherein the dielectric substrate 142 surrounds the semiconductor material 143.

[0083] See next Figure 4 In step S105A, using an ion implantation process and patterned shielding, a first buried layer 131, a second buried layer 133, and a third buried layer 135, which are laterally separated, are simultaneously formed within the epitaxial layer 103 of the first region 100-1. These buried layers all have a second conductivity type, such as P-type buried layers (PBL), and these buried layers have the same doping concentration and the same depth. In step S107, using an etching, deposition, and chemical mechanical planarization process, multiple shallow trench isolation (STI) regions 150 are formed on the top surface of the epitaxial layer 103 of the first region 100-1 and on the deep trench isolation structure 105. These STI regions 150 can separate multiple doped regions of different conductivity types of multiple lateral elements subsequently formed in the first region 100-1.

[0084] Then, refer to Figure 5 In step S109, using an ion implantation process and patterned shielding, three well regions 161 are formed within the first buried layer 131, and corresponding well regions 162 are formed within the epitaxial layer 103 in the second buried layer 133. Well regions 161 and 162 both have a second conductivity type, such as a high-voltage P-type well region (HVPW). Subsequently, using another ion implantation process and another patterned shielding, two well regions 163 are formed within the first buried layer 131, each well region 163 located between two well regions 161. These well regions 163 both have a first conductivity type, such as a high-voltage N-type well region (HVNW).

[0085] Continue reading Figure 5 In step S111, in the second region 100-2, except for the outermost (outer active region) trench 141, a portion of the semiconductor material 143 within the plurality of trenches 141 in the active region is etched away to form a field plate 123. Then, a deposition process is used to fill the trenches 141 with dielectric material to cover the field plate 123. Next, the dielectric material above the field plate 123 within the plurality of trenches 141 is etched away to form a recess, and a gate dielectric layer is formed oriented within the recess using a deposition or thermal oxidation process. Afterwards, semiconductor material is filled within the recess to form a gate 122. The dielectric material within the trenches 141 of the active region constitutes a dielectric layer 121, surrounding the gate 122 and the field plate 123, and longitudinally separating the gate 122 and the field plate 123. The semiconductor material 143 in the trench 141 outside the active region constitutes the field plate 145, and the dielectric liner 142 in the trench 141 constitutes the dielectric layer 144 surrounding the field plate 145.

[0086] Next, refer to Figure 6In step S113, using an ion implantation process and patterned shielding, well region 164 is formed in well region 161 above the middle of the first buried layer 131, and well region 165 is formed in the third buried layer 135. Well regions 164 and 165 both have a second conductivity type, for example, both are P-type well regions (PW). Then, using another ion implantation process and another patterned shielding, well region 166 is formed in well region 162, and well region 167 is formed in the third buried layer 135, wherein well region 167 is adjacent to well region 165. Well regions 166 and 167 both have a first conductivity type, for example, both are N-type well regions (NW). Subsequently, a dielectric layer 171 is deposited all over the top surface of the epitaxial layer 103, wherein the dielectric layer 171 located in the first region 100-1 serves as the gate dielectric layer. Next, using deposition and patterning processes, a plurality of gates 173 are formed on the dielectric layer 171 of the first region 100-1, wherein two gates 173 are located on both sides of well region 164, two gates 173 are located on both sides of well region 166, and two gates 173 are located directly above well regions 165 and 167, respectively. Then, using ion implantation and patterning shielding processes, a substrate region 125, for example a P-type substrate region, is formed in the epitaxial layer 103 of the second region 100-2, located on both sides of the gate 122.

[0087] Continue reading Figure 6 In step S115, using an ion implantation process and patterned shielding, multiple doped regions 168 are formed in the epitaxial layer 103 of well regions 163, 164, 166, 165, 167, and the first region 100-1. Simultaneously, a source region 127 is formed in the substrate region 125. Both the doped regions 168 and the source regions 127 have a first conductivity type, for example, they are all heavily N-type doped regions. Then, using another ion implantation process and another patterned shielding, multiple doped regions 169 are formed in well regions 161, 164, 162, 166, 165, and 167. These doped regions 169 all have a second conductivity type, for example, they are all heavily P-type doped regions.

[0088] Next, refer to Figure 7In step S117, an interlayer dielectric layer 180 is deposited comprehensively on the top surface of the epitaxial layer 103 to cover multiple gates 173. Then, trenches for multiple contacts 181 are etched within the interlayer dielectric layer 180 of the second region 100-2. These trenches extend downward into the substrate region 125, with some trenches penetrating the source region 127. Using an ion implantation process, doped regions 129 are formed within the substrate region 125 via the trenches of the contacts 181, located directly below the trenches. The doped regions 129 have a second conductivity type, such as a heavily p-type doped region. Subsequently, conductive material is filled into the trenches of the contacts 181 to form multiple contacts 181 of the VDMOS transistor. Then, trenches for multiple contacts 182 are etched within the interlayer dielectric layer 180 of the first region 100-1. These trenches expose doped regions 168 and 169, respectively. Conductive material is then filled into these trenches to form multiple contacts 182 of N-LDMOS transistors, P-LDMOS transistors, and CMOS transistors. In step S117, all back-end processes from the front side of the semiconductor structure to the passivation layer are completed.

[0089] Continue reading Figure 7 In step S119, a carrier plate, such as a glass substrate, is bonded to the interlayer dielectric layer 180 of the structure from step S117, and the structure from step S117 is flipped over. A polishing process is performed on the second surface 101B of the substrate 101 to reduce the thickness of the substrate 101 and expose the deep trench isolation structure 105. Before the polishing process in step S119, N-LDMOS transistors, P-LDMOS transistors, and CMOS transistors have been formed in the epitaxial layer 103 of the first region 100-1, and VDMOS transistors have been formed in the epitaxial layer 103 of the second region 100-2. After the polishing process in step S119, the thickness of the substrate 101 is reduced from the initial thickness T1 to a thickness T4. In addition, the polishing process in step S119 also removes part of the filler material of the deep trench isolation structure 105. In one embodiment, this polishing process can remove the insulating material at the bottom of the deep trench isolation structure 105. In another embodiment, this polishing process removes the dielectric layer and semiconductor material at the bottom of the deep trench isolation structure 105, exposing the semiconductor material. The semiconductor material of the deep trench isolation structure 105 allows the bias voltage of the deep trench isolation structure 105 to be a floating potential or electrically coupled to ground. After the polishing process in step S119 is completed, the depth T5 of the deep trench isolation structure 105 is less than the depth T3 of the deep trench 151 in steps S101A to S117. In some embodiments, the depth T5 is, for example, approximately 100 μm to 110 μm, and the depth T3 is, for example, approximately 120 μm to 150 μm.

[0090] Next, refer to Figure 8In step S121, an isolation material layer 106, such as a silicon oxide layer, is deposited comprehensively on the second surface 101B of the thinned substrate 101. The isolation material layer 106 covers the deep trench isolation structure 105 and contacts the bottom surface of the deep trench isolation structure 105. In some embodiments, when the voltage rating of the VDMOS transistor is 80V, the thickness of the isolation material layer 106 can be approximately 0.3μm, and the thickness of the isolation material layer 106 can be increased as the voltage rating of the VDMOS transistor increases.

[0091] Continue reading Figure 8 In step S123, using an etching process and patterned hard shielding, the isolation material layer 106 is patterned to form a patterned isolation layer 107, which has an opening 108 exposing the substrate 101 of the second region 100-2. The thinned substrate 101 of the second region 100-2 constitutes the drain region of the VDMOS transistor, and the area of ​​the opening 108 of the patterned isolation layer 107 can be approximately equal to the area of ​​the VDMOS transistor, or the area of ​​the opening 108 can be smaller than the area of ​​the VDMOS transistor.

[0092] See next Figure 9 In step S125, backside metallization is performed on the second surface 101B of the substrate 101. A conductive layer 109 is formed beneath the patterned isolation layer 107 using an evaporation or sputtering deposition process. The conductive layer 109 is electrically connected to the substrate 101 of the second region 100-2 via an opening 108 in the patterned isolation layer 107. The conductive layer 109 can serve as the drain electrode of the VDMOS transistor 117 and is electrically connected to the substrate 101 of the second region 100-2, which is the drain region, to provide a drain potential D. In some embodiments, the conductive layer 109 is a metal layer, which may comprise titanium (Ti), nickel (Ni), silver (Ag), tin (Sn), copper (Cu), gold (Au), aluminum copper (AlCu), other metals, alloys, or multilayer metal stacks, such as Ti / Ni / Ag, Ti / Ni / Ti / Ag, Ti / Ni / Ag / Ni, or Ti / Ni / Ag / Sn metal stacks. Additionally, the metal layer of the conductive layer 109 may cover the bottom and sides of the patterned isolation layer 107 and fill the openings 108 to directly contact the substrate 101 of the second region 100-2.

[0093] like Figure 9As shown, some contacts in the interlayer dielectric layer 180 can provide source potential S, drain potential D, and gate potential G to N-LDMOS transistor 111, P-LDMOS transistor 113, and CMOS transistor 115, respectively. Other contacts can provide base potential Sub to the epitaxial layer 103 of the first region 100-1. Some contacts can provide base potential B to CMOS transistor 115, and other contacts can provide source potential S to VDMOS transistor 117. The contacts (not shown) providing gate potential G to VDMOS transistor 117 are also in the interlayer dielectric layer 180. The field plate in the trench of VDMOS transistor 117 can be electrically coupled to the source potential S.

[0094] Figure 10 According to another embodiment of the present invention, the following description is provided. Figure 2 A cross-sectional schematic diagram of an intermediate stage in the manufacturing method of the semiconductor structure 100. In step S101B, in the aforementioned... Figure 7 Before the polishing process in step S119, a first sub-deep trench isolation structure 132, a second sub-deep trench isolation structure 134, and a third sub-deep trench isolation structure 136 are formed in the epitaxial layer 103 and the substrate 101. The first sub-deep trench isolation structure 132 is located between the subsequently formed N-LDMOS transistor 111 and P-LDMOS transistor 113, the second sub-deep trench isolation structure 134 is located between the subsequently formed P-LDMOS transistor 113 and CMOS transistor 115, and the third sub-deep trench isolation structure 136 isolates the N-LDMOS transistor 111 from other components in the first region 100-1. In one embodiment, these sub-deep trench isolation structures and the deep trench isolation structure 105 are formed simultaneously. The deep trenches 151 of the sub-deep trench isolation structures and the deep trenches 151 of the deep trench isolation structure 105 may have the same depth T3 and the same width, and the filling materials 152 of the sub-deep trench isolation structures and the filling materials 152 of the deep trench isolation structure 105 may have the same composition. (Continuing to refer to...) Figure 10 In step S103B, a plurality of trenches 141 of VDMOS transistors are etched in the epitaxial layer 103 of the second region 100-2. Then, a dielectric substrate 142 is formed in each trench 141 in a forward orientation using a deposition and chemical mechanical planarization process, and a semiconductor material 143, such as polysilicon, is filled in each trench 141, wherein the dielectric substrate 142 surrounds the semiconductor material 143.

[0095] Afterwards, the aforementioned Figure 4 Step S107 to Figure 9 Step S125, to complete Figure 2 The semiconductor structure 100. In this embodiment, in Figure 7After performing the grinding process in step S119, the deep trench isolation structure 105, the first sub-deep trench isolation structure 132, the second sub-deep trench isolation structure 134, and the third sub-deep trench isolation structure 136 can be exposed simultaneously. Furthermore, in Figure 8 After the patterned isolation layer 107 is formed in steps S121 to S123, the bottom surfaces of the first sub-deep trench isolation structure 132, the second sub-deep trench isolation structure 134 and the third sub-deep trench isolation structure 136 are all in contact with the patterned isolation layer 107. When viewed from above, the boundary of the patterned isolation layer 107 extends beyond the boundary of the deep trench isolation structure 105.

[0096] According to embodiments of the present invention, a deep trench isolation structure is formed through the epitaxial layer and the substrate, and a patterned isolation layer is formed on the back side of the substrate. The deep trench isolation structure and the patterned isolation layer can form a local isolation region to surround the lateral elements of the first region, such as N-LDMOS transistors, P-LDMOS transistors, and CMOS transistors. In addition, an N-type heavily doped semiconductor substrate can be used as the drain region of the vertical elements of the second region, such as VDMOS transistors. The deep trench isolation structure and the patterned isolation layer can effectively prevent the current of the vertical elements from flowing through the substrate to the lateral elements, thereby providing good electrical isolation between the vertical and lateral elements in a single chip, so as to avoid the lateral elements being subjected to high potential impacts from the vertical elements, and also to avoid the electrostatic discharge latch-up effect caused by the current noise of the vertical elements.

[0097] Furthermore, compared to forming only a junction isolation region as a local isolation region in the epitaxial layer, increasing the thickness of the epitaxial layer is typically necessary to increase the breakdown voltage (BVon) of the parasitic bipolar junction transistor (BJT) to meet the breakdown voltage (BVceo) requirement of the LDMOS transistor. However, the depth of the junction isolation region formed in the epitaxial layer is limited by the implantation energy, necessitating a reduction in the epitaxial layer thickness. According to the semiconductor structure of the present invention, using a deep trench isolation structure and a patterned isolation layer as the local isolation region avoids the problem of failing to meet the breakdown voltage (BVceo) requirement of the LDMOS transistor, thus allowing for a reduction in the epitaxial layer thickness and simultaneously reducing the on-resistance (Ron) of the VDMOS transistor.

[0098] Furthermore, in the semiconductor structure of this invention, since the patterned isolation layer is formed on the back side of the substrate, it does not affect the epitaxial quality of the epitaxial layer, nor does it cause height differences in different regions of the epitaxial layer. Therefore, it is beneficial for subsequent multi-processing on the epitaxial layer, such as improving the accuracy of the exposure process and the uniformity of processes like grinding and etching. Compared to existing methods that use smart cut and etching processes to form localized oxide regions and then grow epitaxial layers on these regions, the semiconductor structure of this invention does not have epitaxial defects or height differences. Additionally, the semiconductor structure of this invention can increase the thickness of the patterned isolation layer according to the high voltage requirements of vertical power devices without causing height differences in the epitaxial layer, making it more suitable for higher voltage (e.g., above 80V) applications.

[0099] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, several equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and all such modifications, achieving the same performance or purpose, should be considered within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first conductivity type; At least one epitaxial layer is disposed above the substrate; A deep trench isolation structure extends through the at least one epitaxial layer and the substrate, the deep trench isolation structure surrounds a first region, and includes a second region outside the deep trench isolation structure; A patterned isolation layer is disposed on a bottom surface of the substrate, having an opening to expose the second region of the substrate; and A conductive layer is disposed below the patterned isolation layer and electrically connected to the substrate via the opening.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A lateral element is disposed in the epitaxial layer of the first region; and A vertical element is disposed in the epitaxial layer of the second region, wherein the substrate of the second region constitutes a drain region of the vertical element.

3. The semiconductor structure as described in claim 2, characterized in that, It also includes a buried layer having a second conductivity type, disposed in the epitaxial layer and located directly below the lateral element.

4. The semiconductor structure as described in claim 2, characterized in that, It also includes a sub-deep trench isolation structure disposed between the lateral element and another lateral element.

5. The semiconductor structure as described in claim 4, characterized in that, The sub-deep trench isolation structure penetrates the epitaxial layer and the substrate, and the bottom surface of the sub-deep trench isolation structure contacts the top surface of the patterned isolation layer.

6. The semiconductor structure as described in claim 1, characterized in that, The bottom surface of the deep trench isolation structure contacts the top surface of the patterned isolation layer. When viewed from above, the boundary of the patterned isolation layer extends beyond the boundary of the deep trench isolation structure.

7. The semiconductor structure as described in claim 1, characterized in that, The conductive layer includes a metal layer that covers the bottom and sides of the patterned isolation layer and directly contacts the substrate of the second region.

8. The semiconductor structure as described in claim 1, characterized in that, The substrate includes an N-type heavily doped semiconductor substrate.

9. The semiconductor structure as described in claim 1, characterized in that, The deep trench isolation structure includes an insulating material filling a deep trench, and the patterned isolation layer comprises the insulating material.

10. The semiconductor structure as claimed in claim 1, characterized in that, The deep trench isolation structure includes: A deep trench; A dielectric layer, lining the sidewalls of the deep trench; and A semiconductor material is used to fill the deep trench; The bias voltage of the deep trench isolation structure is a floating potential, or it is electrically coupled to the ground terminal.

11. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided having a first conductivity type, including a first surface and a second surface on opposite sides; An epitaxial layer is formed on the first surface of the substrate; A deep trench isolation structure is formed in the epitaxial layer and the substrate, the deep trench isolation structure surrounds a first region, and a second region is included outside the deep trench isolation structure; A polishing process is performed on the second surface of the substrate to reduce the thickness of the substrate and expose the deep trench isolation structure; A layer of insulating material is deposited on the second surface of the thinned substrate and contacts the bottom surface of the deep trench isolation structure; The insulating material layer is patterned to form a patterned insulating layer having an opening that exposes the substrate of the second region; as well as A conductive layer is formed beneath the patterned isolation layer, and the conductive layer is electrically connected to the substrate via the opening.

12. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Also includes: Prior to the grinding process, a lateral element is formed in the epitaxial layer of the first region; as well as Prior to the grinding process, a vertical element is formed in the epitaxial layer of the second region.

13. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, The thinned substrate in the second region constitutes a drain region of the vertical element.

14. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, It also includes forming a buried layer in the epitaxial layer by an ion implantation process, having a second conductivity type, and located directly below the lateral element.

15. The method for manufacturing a semiconductor structure as described in claim 12, characterized in that, It also includes forming a sub-deep trench isolation structure in the epitaxial layer and the substrate prior to the grinding process, wherein the sub-deep trench isolation structure is located between the lateral element and another lateral element.

16. The method for manufacturing a semiconductor structure as described in claim 15, characterized in that, The deep trench isolation structure and the sub-deep trench isolation structure are formed simultaneously, and the grinding process exposes the deep trench isolation structure and the sub-deep trench isolation structure.

17. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The deep trench isolation structure includes: A deep trench is formed by an etching process, penetrating the epitaxial layer, with the bottom surface of the deep trench located in the substrate; and An insulating material is filled into the deep trench; Wherein, the insulating material removed in the grinding process is such that, after the grinding process, the depth of the deep trench isolation structure is less than the depth of the deep trench.

18. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The deep trench isolation structure includes: A deep trench is formed by an etching process, penetrating the epitaxial layer, and the bottom surface of the deep trench is located in the substrate; A dielectric layer is deposited oriented in the deep trench; and A semiconductor material is filled within the deep trench, and the dielectric layer surrounds the semiconductor material. In the polishing process, a portion of the dielectric layer and a portion of the semiconductor material are removed. After the polishing process, the depth of the deep trench isolation structure is less than the depth of the deep trench, and the bias voltage of the deep trench isolation structure is a floating potential or electrically coupled to the ground terminal.

19. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Forming the conductive layer includes depositing a metal layer on the second surface of the substrate to cover the bottom and sides of the patterned isolation layer and fill the openings, the metal layer being in direct contact with the substrate in the second region.

20. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The patterned isolation layer contacts the bottom surface of the deep trench isolation structure. When viewed from above, the boundary of the patterned isolation layer extends beyond the boundary of the deep trench isolation structure.

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