Method of manufacturing a semiconductor device and semiconductor device

Abstract

This invention provides a semiconductor device comprising a substrate, a channel layer, a barrier layer, a gate structure, a dielectric layer, a gate plug, and a gate connection pad. The channel layer is disposed on the substrate; the barrier layer is disposed on the channel layer; the gate structure is disposed on a portion of the barrier layer; the dielectric layer is disposed on the barrier layer and the gate structure; the gate plug is disposed in the dielectric layer and contacts the gate structure; and the gate connection pad is disposed on the gate plug to significantly reduce gate resistance.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Power semiconductor devices continue to evolve and are widely used in fields such as wireless communication, electronic products, and electric vehicles. However, devices capable of handling high power require high breakdown voltage, and even better devices need high electron mobility and excellent thermal stability. Therefore, a new semiconductor device and its fabrication method are needed to continue the development of this field. Summary of the Invention

[0003] One embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer; forming a gate structure on a portion of the barrier layer; forming a dielectric layer on the barrier layer and the gate structure; forming a gate plug in the dielectric layer and in contact with the gate structure; and forming a gate connection pad on the gate plug.

[0004] Another embodiment of this disclosure provides a semiconductor device including a substrate, a channel layer, a barrier layer, a gate structure, a dielectric layer, and a gate plug for connection to a gate pad. The channel layer is disposed on the substrate; the barrier layer is disposed on the channel layer; the gate structure is disposed on a portion of the barrier layer; the dielectric layer is disposed on the barrier layer and the gate structure; the gate plug is disposed in the dielectric layer and contacts the gate structure; and the gate connection pad is disposed on the gate plug. Attached Figure Description

[0005] The various aspects of this disclosure will be most readily understood when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard operating procedures, the various features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the various features can be arbitrarily increased or decreased. To make the above and other objects, features, advantages, and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0006] Figure 1 A perspective view of a semiconductor device according to some embodiments disclosed herein is shown.

[0007] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to one embodiment of the present invention is shown.

[0008] Figures 3 to 5 These are cross-sectional views of different manufacturing stages of one embodiment of the semiconductor device disclosed herein.

[0009] Figure 6 A cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown. Detailed Implementation

[0010] Gallium nitride (GaN) semiconductor devices are increasingly widely used due to their ability to carry high current and support high voltage. To reduce gate resistance, existing GaN semiconductor devices use gate metal interconnects in the active region. However, this process requires creating openings in the dielectric layer before depositing the gate metal inside and on top of these openings, resulting in a cumbersome and complex process. Furthermore, due to the lack of planarization and dielectric layer recesses caused by gate metal etching, only 2–4 kA copper-aluminum (AlCu) materials can be used as gate metals.

[0011] In view of this, some embodiments disclosed herein provide a semiconductor device and a method for fabricating the same, in which a gate plug is directly contacted with the gate (including the gate electrode layer) and the gate bus line extending to the active region, for example using ME1 6-18KA copper-aluminum as the connecting wire, which can significantly reduce the gate resistance by approximately 65%. Furthermore, by directly contacting the gate plug with the gate structure (excluding the gate electrode layer), gate metal processing can be reduced, thereby saving photomask steps.

[0012] The following examples and experimental cases illustrate the method for manufacturing a semiconductor device and the semiconductor device disclosed herein in more detail. However, they are only illustrative and are not intended to limit the scope of the disclosure. The scope of protection of the disclosure shall be defined by the appended claims.

[0013] Although the methods disclosed herein are illustrated using a series of operations or steps, the order in which these operations or steps are shown should not be construed as a limitation of this disclosure. For example, some operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, it is not necessary to perform all illustrated operations, steps, and / or features to achieve the implementation of this disclosure. In addition, each operation or step described herein may comprise several sub-steps or actions.

[0014] For clarity, features and elements that are known in the domain and are not essential for understanding the principles described will be omitted.

[0015] Reference Figure 1This is a perspective view of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 100 includes a semiconductor substrate 110, which defines an active region A1 and isolation regions A2 located on both sides of the active region A1 (only one side is shown in the figure). The channel layer in the active region A1 is not destroyed, while the channel layer in the isolation region A2 is destroyed by ion bombardment. The semiconductor device 100 includes a gate structure 120, a drain electrode 130, and a source electrode 140 disposed on the active region A1. The gate structure 120, drain electrode 130, and source electrode 140 are arranged substantially parallel to each other, and the drain electrode 130 and source electrode 140 are disposed on both sides of the gate structure 120.

[0016] Semiconductor device 100 includes a gate bus 150 disposed on an isolation region A2 and a gate connection pad 152 connected to the gate bus 150 and extending into an active region A1, wherein the extending direction of the gate bus 150 is perpendicular to the extending direction of the gate connection pad 152. The gate connection pad 152 overlaps on a gate structure 120. Semiconductor device 100 also includes a plurality of gate plugs 154 disposed on the active region A1 and physically and electrically connected to the gate connection pad 152 and the gate structure 120.

[0017] The semiconductor device 100 further includes a drain bus (not shown) and a source bus (not shown) disposed on an isolation region A2 on the other side, a drain connection pad 162 connected to the drain bus and extending into the active region A1, and a source connection pad 172 connected to the source bus and extending into the active region A1. The extending directions of the drain connection pad 162 and the source connection pad 172 are parallel to the extending direction of the gate connection pad 152. The semiconductor device 100 also includes a plurality of drain plugs 164 and source plugs 174, which are disposed on the active region A1 and are physically and electrically connected to the drain connection pad 162 and the drain electrode 130, and the source connection pad 172 and the source electrode 140, respectively.

[0018] Cooperate Figures 3 to 5 See Figure 2 . Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to one embodiment of the present invention is shown. Figures 3 to 5 These are cross-sectional views at different stages of fabrication of an embodiment of the semiconductor device disclosed herein. Figure 2 As shown, method 10 includes steps S11 to S15.

[0019] In step S11, a substrate 110, a channel layer 112, and a barrier layer 114 are provided sequentially, such as... Figure 3 As shown, its cross-sectional location can be referenced. Figure 1Line segment AA in the diagram. Substrate 110 is a silicon substrate. A method for fabricating a semiconductor device includes forming a channel layer 112 on the semiconductor substrate 110 and forming a barrier layer 114 on the channel layer 112. The semiconductor substrate 110 may be a silicon substrate or a silicon carbide substrate, etc., and may contain semiconductor elements, compounds and / or alloys.

[0020] Channel layer 112 provides a channel for carrier flow between the source and drain. Barrier layer 114 helps to form a two-dimensional electron gas (2DEG) layer with high concentration, high electron mobility, and low resistance in channel layer 112 as a carrier flow channel. In some embodiments, the material of channel layer 112 includes epitaxial gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), etc. In some embodiments, the material of barrier layer 114 includes gallium nitride, aluminum nitride, aluminum gallium nitride, etc.

[0021] Next, in step S12, a gate structure 120 is formed on the barrier layer 114 to control the flow of charge carriers in the channel layer 112. In some embodiments, the gate structure 120 includes a patterned doped layer 122 and a gate metal layer 124 on the doped layer 122. For example, in some embodiments, the doped layer 122 includes gallium nitride doped with a p-type dopant. The material of the gate metal layer 124 may include a suitable metallic material, such as titanium nitride, etc.

[0022] Next, in step S13, a dielectric layer 180 is formed on the barrier layer 114 and the gate structure 120. A first dielectric layer 181 is conformally formed on the barrier layer 114 and the gate structure 120, extending continuously. The first dielectric layer 181 and the barrier layer 114 are in direct contact with the gate structure 120. In some embodiments, the first dielectric layer 181 covers the barrier layer 114 and continuously covers the upper surface and side surface of the gate structure 120.

[0023] Next, as Figure 4 As shown, drain electrode 130 and source electrode 140 are formed on both sides of gate structure 120 and respectively contact barrier layer 114. The materials of drain electrode 130 and source electrode 140 are ohmic contact metals, which can be selected to match the corresponding barrier layer 114. In some embodiments, the materials of the ohmic contact metals of drain electrode 130 and source electrode 140 may include titanium, aluminum, aluminum silicide, copper-aluminum alloy, titanium nitride, nickel, platinum, gold, etc. Drain electrode 130 and source electrode 140 contact the barrier layer 114 through the first dielectric layer 181.

[0024] Next, a dielectric layer 180 is formed on the barrier layer 114, drain electrode 130, source electrode 140, and gate structure 120. In some embodiments, a second dielectric layer 182 covers the drain electrode 130, source electrode 140, and first dielectric layer 181. In some embodiments, the materials of the first dielectric layer 181 and the second dielectric layer 182 include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. After the second dielectric layer 182 is formed, a patterned photoresist can be used to cover the semiconductor substrate 110 as the active region A1 (see...). Figure 2 This part will be used as quarantine zone A2 (see) Figure 2 The active region A1 and the isolation region A2 are defined by partially exposing the active region A1 and partially exposing the isolation region A2 by plasma bombardment, which destroys the channel layer 112 in the isolation region A2. Then the patterned photoresist is removed.

[0025] Next, as Figure 5 As shown, a third dielectric layer 183 is deposited on the second dielectric layer 182, and a planarization process is performed to provide a flat upper surface for the third dielectric layer 183. The first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183 can be collectively referred to as dielectric layer 180.

[0026] Next, in step S14, a gate plug 154 is formed in the dielectric layer 180 and contacts the gate structure 120. Further, a drain plug 164 and a source plug 174 are formed in the dielectric layer 180, and the drain plug 164 and source plug 174 contact the drain electrode 130 and the source electrode 140, respectively. In some embodiments, the dielectric layer 180 is etched to define a plurality of openings OP, and a metal material, such as tungsten, is deposited to fill the openings OP, thereby forming a plurality of gate plugs 154 connected to the gate structure 120, a plurality of drain plugs 164 connected to the drain electrode 130, and a plurality of source plugs 174 connected to the source electrode 140.

[0027] Next, in step S15, a gate connection pad 152 is formed on the gate plug 154. Further, a drain connection pad 162 and a source connection pad 172 are formed on the drain plug 164 and the source plug 174, respectively. In some embodiments, after the gate plug 154, drain plug 164, and source plug 174 are formed on the active region A1, a metal layer M1 is deposited on the dielectric layer 180 and patterned thereon to obtain the gate bus 150 (see...). Figure 2The gate metal layer M1 is connected to the gate connection pad 152, the drain bus (not shown) and the drain connection pad 162, and the source bus (not shown) and the source connection pad 172. In some embodiments, the metal layer M1 is made of a low-resistance metal material, such as copper-aluminum, aluminum, aluminum silicon (AlSi), copper, or other low-resistance metals. In some embodiments, the thickness of the metal layer M1 is greater than that of the gate metal layer 124 to achieve a significant reduction in gate resistance, thereby reducing switching losses and increasing the switching frequency when the gate control element is switched. For example, the thickness range of the gate metal layer 124 is... Thickness range of metal layer M1

[0028] In some embodiments, the gate connection pad 152, drain connection pad 162, and source connection pad 172 are arranged parallel to each other in the same direction within the same active region A1 of the substrate 110. Specifically, the semiconductor device 100 includes a gate structure 120, a drain electrode 130, and a source electrode 140 arranged parallel to each other on the active region A1, and gate connection pads 152, drain connection pads 162, and source connection pads 172 arranged parallel to each other in the vertical projection direction. A gate plug 154 of the semiconductor device 100 is disposed on the active region A1 and connects the gate connection pad 152 to the gate structure 120. A drain plug 164 of the semiconductor device 100 is disposed on the active region A1 and connects the drain connection pad 162 to the drain electrode 130. A source plug 174 of the semiconductor device 100 is disposed on the active region A1 and connects the source connection pad 172 to the source electrode 140.

[0029] In some embodiments, the gate plug 154, drain plug 164, and source plug 174 are disposed only in the active region A1, and not in the isolation region A2 (e.g., Figure 1 As shown in the figure.

[0030] Reference Figure 6 This is a cross-sectional view of some other embodiments of the semiconductor device disclosed herein, the cross-sectional position of which can be referenced. Figure 2 Line segment AA in the diagram. In some embodiments, such as semiconductor device 100A, gate structure 120A may further include a gate electrode layer 126 disposed on gate metal layer 124 and covered by dielectric layer 180, thereby reducing the resistance value of gate structure 120A. Gate electrode layer 126 may be a single layer or multiple layers of conductive material. In some embodiments, gate electrode layer 126 may include titanium nitride, titanium, aluminum copper, or combinations thereof.

[0031] In some embodiments, the gate electrode layer 126 may have a shape that is wider at the top and narrower at the bottom, such that the width W1 of the upper surface of the gate electrode layer 126 is greater than the width W2 of the gate metal layer 124, so as to further increase the contact area between the gate plug 154 and the gate structure 120A, thereby reducing the contact resistance between the gate plug 154 and the gate structure 120A.

[0032] In such Figure 6 In the illustrated embodiment, the gate electrode layer 126 is located on a different layer from the drain electrode 130 and the source electrode 140. Specifically, the lower surface of the gate electrode layer 126 is higher than the lower surfaces of the drain electrode 130 and the source electrode 140, and the lower surfaces of the gate connection pad 152, the drain connection pad 162, and the source connection pad 172 are higher than the upper surface of the gate electrode layer 126. In some embodiments, the horizontal plane P2 where the gate electrode layer 126 is located is higher than the horizontal plane P1 where the drain electrode 130 and the source electrode 140 are located, and the horizontal plane P3 where the gate connection pad 152, the drain connection pad 162, and the source connection pad 172 are located is higher than the horizontal plane P2 where the gate electrode layer 126 is located.

[0033] In summary, in some embodiments of the semiconductor device disclosed herein, the gate structure and the gate connection pad are connected by a gate plug in the active region. Since the gate connection pad extends from the gate bus, the same low-resistance metal material can be used as the connection wire, which greatly reduces the gate resistance.

[0034] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0035] [Symbol Explanation]

[0036] 10: Method

[0037] 100, 100A: Semiconductor devices

[0038] 110: Substrate

[0039] 112: Channel Layer

[0040] 114: Barrier Layer

[0041] 120, 120A: Gate structure

[0042] 122: Doped layer

[0043] 124: Gate metal layer

[0044] 126: Gate electrode layer

[0045] 130: Drain electrode

[0046] 140: Source electrode

[0047] 150: Gate bus

[0048] 152: Gate connection pad

[0049] 154: Gate plug

[0050] 162: Drain connection pad

[0051] 164: Drain plug

[0052] 172: Source Connector Pad

[0053] 174: Source Plug

[0054] 180: Dielectric layer

[0055] 181: First dielectric layer

[0056] 182: Second dielectric layer

[0057] 183: Third dielectric layer

[0058] AA: line segment

[0059] A1: Active Zone

[0060] A2: Isolation Zone

[0061] M1: Metal layer

[0062] OP: Opening

[0063] P1, P2, P3: Horizontal plane

[0064] W1, W2: Width

[0065] S11~S15: Steps.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Include: A substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer are provided; A gate structure is formed on a portion of the barrier layer; A dielectric layer is formed on the barrier layer and the gate structure; A gate plug is formed in the dielectric layer and contacts the gate structure; as well as A gate connection pad is formed on the gate plug.

2. The method according to claim 1, wherein the gate structure comprises: A doped layer is disposed on the gate structure; and A gate metal layer is disposed on the doped layer.

3. The method according to claim 1, wherein, Also includes: A drain electrode and a source electrode are formed and respectively contact the barrier layer, and are respectively disposed on both sides of the gate structure; The dielectric layer is formed on the barrier layer, the drain electrode, the source electrode, and the gate structure; A drain plug and a source plug are formed in the dielectric layer, and the drain plug and the source plug are respectively in contact with the drain electrode and the source electrode; as well as The drain connection pad and the source connection pad are respectively formed on the drain plug and the source plug.

4. The method of claim 3, wherein prior to depositing the dielectric layer, the method further comprises: forming a gate electrode layer on the gate structure, wherein, The lower surface of the gate electrode layer is higher than the lower surface of the drain electrode and the lower surface of the source electrode, and the lower surface of the gate connection pad, the lower surface of the source connection pad and the lower surface of the drain connection pad are higher than the lower surface of the gate electrode layer.

5. A semiconductor device, characterized in that, Include: substrate; The channel layer is disposed on the substrate; A barrier layer is disposed on the channel layer; The gate structure is disposed on a portion of the barrier layer; A dielectric layer is disposed on the barrier layer and the gate structure; A gate plug is disposed in the dielectric layer and in contact with the gate structure; as well as A gate connection pad is disposed on the gate plug.

6. The semiconductor device of claim 5, wherein the gate structure comprises: A doped layer is disposed on the gate structure; and A gate metal layer is disposed on the doped layer.

7. The semiconductor device according to claim 6, wherein, Also includes: The drain electrode and the source electrode are respectively in contact with the barrier layer, and the drain electrode and the source electrode are respectively disposed on both sides of the gate structure; The dielectric layer covers the barrier layer, the drain electrode, the source electrode, and the gate structure; The drain plug and the source plug are disposed in the dielectric layer, and the drain plug and the source plug are respectively in contact with the drain electrode and the source electrode; as well as The drain connection pad and the source connection pad are respectively disposed on the drain plug and the source plug.

8. The semiconductor device of claim 7, wherein, in plan view, the gate connection pad, the drain connection pad, and the source connection pad are arranged in parallel along the same direction in the same active region of the substrate.

9. The semiconductor device of claim 7, wherein the thickness of the gate connection pad, the drain connection pad and the source connection pad is greater than that of the gate metal layer.

10. The semiconductor device according to claim 7, wherein, Also includes: A gate electrode layer is disposed on the gate structure and is covered by the dielectric layer; wherein the gate electrode layer is located on a different layer from the drain electrode and the source electrode.

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