Semiconductor structure and method of manufacturing the same
By forming a second conductive plug covering the first conductive plug in the conductive plug hole, and using a less reactive metal material, the problem of metal contamination during the grinding process of the through-silicon via structure is solved, and the stability and high conductivity of the semiconductor structure are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-02
Smart Images
Figure CN122138694A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] With the development of semiconductor technology, the feature size of integrated circuits is constantly shrinking and the interconnection density of devices is constantly increasing. As a result, through-silicon via (TSV) structures are widely used in integrated circuits.
[0003] However, metal contamination can occur during the polishing process of through-silicon via (TSV) structures, leading to a decrease in device performance. Summary of the Invention
[0004] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:
[0005] Provide a base;
[0006] A conductive plug hole is formed in the substrate;
[0007] A first conductive plug and a second conductive plug are sequentially formed in the conductive plug hole. The second conductive plug is located on the first conductive plug and covers the top surface of the first conductive plug. The first conductive plug includes a first conductive metal, and the second conductive plug includes a second conductive metal.
[0008] A through-silicon via (TSV) structure is formed in the substrate, the TSV structure being located on one side of the conductive plug, the TSV structure comprising a third conductive metal;
[0009] The reactivity of the second conductive metal is less than or equal to that of the third conductive metal.
[0010] In some embodiments, the step of forming the first conductive plug includes:
[0011] The first conductive metal is deposited into the conductive plug hole to form a first conductive metal layer, the first conductive metal layer covering the top surface of the substrate;
[0012] The first conductive metal layer located on the substrate is ground to form the first conductive plug.
[0013] In some embodiments, during the grinding process of the first conductive metal layer located on the substrate, a recessed area is formed on the top of the first conductive plug so that the top surface of the first conductive plug is lower than the top surface of the substrate.
[0014] In some embodiments, the step of forming the second conductive plug includes:
[0015] The second conductive metal is deposited into the recessed area to form a second conductive metal layer, the second conductive metal layer covering the top surface of the substrate, wherein the reactivity of the first conductive metal is greater than that of the second conductive metal.
[0016] The second conductive metal layer located on the substrate is ground to form the second conductive plug, the top surface of the second conductive plug being flush with the top surface of the substrate.
[0017] In some embodiments, the step of forming the first conductive plug includes:
[0018] The first conductive metal is deposited into the conductive plug hole to form a first conductive metal layer;
[0019] The first conductive metal layer is etched to form the first conductive plug, the height of which is less than the depth of the conductive plug hole.
[0020] In some embodiments, the step of forming the second conductive plug includes:
[0021] The second conductive metal is formed in the conductive plug hole, and the second conductive metal covers the top surface of the substrate;
[0022] The second conductive metal located on the substrate is ground to form the second conductive plug, the top surface of the second conductive plug being flush with the top surface of the substrate.
[0023] In some embodiments, in the vertical direction, the height of the second conductive plug is less than the height of the first conductive plug, and the conductivity of the first conductive plug is less than the conductivity of the second conductive plug.
[0024] In some embodiments, after forming the first conductive plug, a barrier layer is further formed on the first conductive plug, the barrier layer being located between the first conductive plug and the second conductive plug.
[0025] In some embodiments, the step of forming the through-silicon via structure includes:
[0026] Through-silicon vias are formed in the substrate;
[0027] An insulating layer is formed inside the through-silicon via;
[0028] The third conductive metal is deposited in the through-silicon via to form a third conductive metal layer, which covers the top surface of the substrate;
[0029] The third conductive metal layer located on the substrate is polished to form the through-silicon via structure.
[0030] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising:
[0031] Base;
[0032] A conductive plug is located in the substrate. The conductive plug includes a first conductive plug and a second conductive plug located on the first conductive plug. The second conductive plug covers the first conductive plug. The first conductive plug includes a first conductive metal, and the second conductive plug includes a second conductive metal.
[0033] A through-silicon via (TSV) structure is located in the substrate, on one side of the conductive plug, and the TSV structure includes a third conductive metal.
[0034] The reactivity of the second conductive metal is less than or equal to that of the third conductive metal.
[0035] In some embodiments, the height of the first conductive plug is greater than the height of the second conductive plug in the vertical direction.
[0036] In some embodiments, a barrier layer is further included, the barrier layer being located between the first conductive plug and the second conductive plug.
[0037] In some embodiments, the reactivity of the second conductive metal is less than that of the first conductive metal.
[0038] In some embodiments, the conductivity of the second conductive metal is greater than that of the first conductive metal.
[0039] In some embodiments, the ratio of the height of the first conductive plug to the height of the second conductive plug is greater than the ratio of the height of the through-silicon via structure to the height of the first conductive plug.
[0040] In summary, this disclosure provides a semiconductor structure and its manufacturing method. First, a conductive plug hole is formed in a substrate. Then, a first conductive plug and a second conductive plug are sequentially formed within the conductive plug hole, thus forming a conductive plug. The second conductive plug is located on top of the first conductive plug and completely covers its top surface. Next, a through-silicon via (TSV) structure is formed on one side of the conductive plug. Since the first conductive plug includes a first conductive metal, the second conductive plug includes a second conductive metal, and the TSV structure includes a third conductive metal, and the reactivity of the second conductive metal is less than or equal to that of the third conductive metal, during the formation of the TSV structure, the third conductive metal reacts with the polishing slurry to form metal ions. Simultaneously, the second conductive plug prevents the first conductive plug from contacting the polishing slurry, thereby preventing the first conductive metal from reacting with the metal ions. Meanwhile, since the reactivity of the second conductive metal is less than or equal to that of the third conductive metal, the second conductive metal will not react with the metal ions even if it comes into contact with the polishing slurry. In other words, the metal ions in the polishing slurry will not be reduced to the third conductive metal. This can prevent the formation of the third conductive metal on the conductive plug, thereby preventing short circuits between adjacent conductive plugs and also preventing metal contamination. Attached Figure Description
[0041] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment;
[0042] Figure 2 This is a schematic diagram of a substrate according to an exemplary embodiment;
[0043] Figure 3 This is a schematic diagram of a conductive plug hole according to an exemplary embodiment;
[0044] Figure 4 This is illustrated according to an exemplary embodiment. Figure 3 A simplified top view;
[0045] Figure 5 This is a schematic diagram of a first conductive metal layer according to an exemplary embodiment;
[0046] Figure 6 This is a schematic diagram of a recessed area according to an exemplary embodiment;
[0047] Figure 7 This is a schematic diagram of a second conductive metal layer according to an exemplary embodiment;
[0048] Figure 8 This is a schematic diagram of a second conductive plug according to an exemplary embodiment;
[0049] Figure 9This is a schematic diagram of a through-silicon via according to an exemplary embodiment;
[0050] Figure 10 This is a schematic diagram of an insulating layer according to an exemplary embodiment;
[0051] Figure 11 This is a schematic diagram of a third conductive metal layer according to an exemplary embodiment;
[0052] Figure 12 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment;
[0053] Figure 13 This is a schematic diagram of a conductive plug according to an exemplary embodiment;
[0054] Figure 14 This is a schematic diagram of a first conductive plug according to an exemplary embodiment;
[0055] Figure 15 This is yet another schematic diagram of a second conductive metal layer according to an exemplary embodiment;
[0056] Figure 16 This is a schematic diagram of a second conductive plug according to an exemplary embodiment;
[0057] Figure 17 This is a simplified schematic diagram of a barrier layer according to an exemplary embodiment;
[0058] Figure 18 This is yet another schematic diagram of a semiconductor structure illustrated according to an exemplary embodiment. Detailed Implementation
[0059] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0060] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0061] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0062] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0063] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0064] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0065] Currently, through-silicon vias (TSVs) are widely used in semiconductor devices. The manufacturing process of TSVs generally includes: creating a filling hole in a substrate, depositing a metal material into the filling hole, which also covers the surface of the substrate, and then removing the metal material from the substrate surface through a grinding process, thereby forming the TSV.
[0066] However, the applicant discovered that a plug structure had already formed in the substrate before the through-silicon via (TSV) structure was fabricated. The material of this plug structure differed from that of the TSV structure. Typically, the plug structure is made of tungsten, while the TSV structure is made of copper. During the polishing of the TSV structure's metal material (copper), the copper first reacts with the polishing slurry (which contains an acidic cleaning solution). The acidic cleaning solution oxidizes the copper, forming copper ions, which then enter the polishing slurry. When the metal material on the substrate surface is polished away, the surface of the plug structure is exposed to the polishing slurry. At this point, both the plug structure and the TSV structure are simultaneously exposed to the slurry, creating an electrochemical reaction field. Therefore, the metal material (tungsten) in the plug structure reacts with the copper ions in the polishing slurry, reducing them to copper atoms. These copper atoms deposit on the tungsten, potentially causing a short circuit in the conductive plug. Simultaneously, copper atoms have a large diffusion coefficient in the dielectric layer, leading to copper diffusion and copper contamination, resulting in degraded device performance.
[0067] In view of the above-mentioned technical problems, this disclosure provides a method for manufacturing a semiconductor structure, which can be used to manufacture semiconductor devices including through-silicon via (TSV) structures. This method also prevents copper contamination. Figure 1 As shown, the manufacturing method includes:
[0068] S1: Provides a substrate with conductive plug holes in it;
[0069] S2: A first conductive plug and a second conductive plug are sequentially formed in the conductive plug hole. The second conductive plug is located on the first conductive plug and covers the top surface of the first conductive plug. The first conductive plug includes a first conductive metal, and the second conductive plug includes a second conductive metal.
[0070] S3: A through-silicon via (TSV) structure is formed in the substrate, the TSV structure being located on one side of the first conductive plug, and the TSV structure including a third conductive metal. The reactivity of the second conductive metal is less than or equal to that of the third conductive metal.
[0071] like Figures 2-3As shown, in step S1, a substrate 101 is first provided. The substrate 101 may include a substrate 102 and a dielectric layer 103, with the dielectric layer 103 covering the substrate 102. The substrate 102 may be silicon, such as a silicon substrate with or without an epitaxial layer, or a silicon-on-insulator (SOI) substrate with a buried insulating layer. Alternatively, the substrate 102 may be a GaAs substrate, GaAsP substrate, InP substrate, GaAlAs substrate, or InGaP substrate. A device structure 104 is located in the substrate 102. The device structure 104 may include multiple independent circuit units, such as transistors, diodes, resistors, capacitors, inductors, or other active and passive semiconductor devices. For example, the device structure 104 may be a transistor with a gate and source / drain electrodes.
[0072] like Figures 2-3 As shown, dielectric layer 103 is located on the front side of substrate 102 and is used to isolate device structure 104 from subsequently formed interconnect structures. Dielectric layer 103 can be a single layer or a multilayer structure. Dielectric layer 103 can be a doped or undoped silicon oxide layer, formed by thermochemical vapor deposition or high-density plasma processing, such as undoped silicon glass, phosphorus-doped silicon glass, or borosilicate glass. In some embodiments, dielectric layer 103 can also be doped or phosphorus-doped spin-on glass (SOG), phosphorus-doped tetraethoxysilicate (PTEOS), or borosilicate-doped tetraethoxysilicate (BPTEOS). After forming dielectric layer 103, conductive plug vias 105 are formed in dielectric layer 103 using a dry etching process, thereby exposing a portion of device structure 104. In one embodiment, after planarization of dielectric layer 103, a dielectric antireflective coating (DARC) and / or a bottom antireflective coating (BARC) and a patterned photoresist layer are formed; these layers are not shown in the figure for simplification. Next, a dry etching process is performed to form conductive plug holes 105 through the dielectric layer 103, exposing the contact areas of the device structure 104, such as the silicide layer located on the source / drain regions. Then, the patterned photoresist layer and antireflective layer are stripped away.
[0073] like Figure 4 As shown, Figure 4 Displayed as Figure 3The top view shows the conductive plug hole 105 located above the device structure 104, allowing signals to be transmitted to the device structure 104 via the conductive plug. The projection area of the conductive plug hole 105 is entirely within the projection area of the device structure 104. Because the spacing between adjacent device structures 104 is relatively small, each conductive plug hole 105 is directly above each device structure 104, and the inner diameter of the conductive plug hole 105 is small, thereby increasing the spacing between adjacent conductive plug holes 105. This prevents one conductive plug hole 105 from exposing two device structures 104, thus preventing short circuits between the two device structures 104.
[0074] like Figure 5 As shown, in step S2, after forming the conductive plug hole 105, a first conductive metal is deposited on the dielectric layer 103 to form a first conductive metal layer 106. The first conductive metal layer 106 is also formed in the conductive contact hole 105, thereby electrically connecting to the device structure 104. This embodiment uses, for example, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other advanced deposition techniques to form the first conductive metal layer 106. The first conductive metal layer 106 includes a first conductive metal, such as nickel or tungsten. In some embodiments, the first conductive metal layer 106 can also be other metals such as molybdenum, titanium nitride, or copper.
[0075] like Figures 5-6As shown, after the first conductive metal layer 106 is formed, it is ground to remove the portion of the first conductive metal layer 106 located outside the conductive plug hole 105 and above the dielectric layer 103, thus retaining the portion of the first conductive metal layer 106 located in the conductive plug hole 105, thereby forming the first conductive plug 106a in the conductive plug hole 105. When grinding the first conductive metal layer 106 on the dielectric layer 103, particles including nano-silica and nano-alumina are used as the grinding slurry, and hydrogen peroxide is used as the oxidant. Through chemical reaction and mechanical action, most of the first conductive metal layer 106 is removed, leaving a thickness of 40-50 nm for the remaining first conductive metal layer 106. Next, the polishing pressure is increased to remove the first conductive metal layer 106 on the dielectric layer 103. Due to the etching selectivity ratio between the first conductive metal layer 106 and the dielectric layer 103, a certain depression is formed above the first conductive metal layer 106 in the conductive plug hole 105. Then, the polishing slurry is changed to give the first conductive metal layer 106 and the dielectric layer 103 a greater etching selectivity ratio, for example, exceeding 10:1. A relatively soft polishing pad is selected, so that the first conductive metal layer 106 in the conductive plug hole 105 is etched more and the dielectric layer 103 is etched less, thus forming a depression region 107 in the dielectric layer 103. Figure 6 As can be seen, after the first conductive metal layer 106 in the conductive plug hole 105 is etched, a first conductive plug 106a is formed. The top surface of the first conductive plug 106a is lower than the top surface of the dielectric layer 103. In the horizontal direction, the width of the first conductive plug 106a is smaller than the width of the recessed area 107. That is, in the vertical direction, the projection area of the recessed area 107 can cover the projection area of the first conductive plug 106a.
[0076] like Figure 7 As shown, after forming the first conductive plug 106a, a second conductive metal is deposited on the dielectric layer 103 to form a second conductive metal layer 108. The material of the second conductive metal layer 108 is different from that of the first conductive plug 106a, and the second conductive plug 108 also covers the recessed area 107, thereby electrically connecting it to the first conductive plug 106a. In this embodiment, the second conductive metal layer 108 includes a second conductive metal, such as copper, gold, silver, or other metals. In this embodiment, the second conductive metal layer 108 is formed, for example, by electroplating or sputtering.
[0077] like Figure 8As shown, after the second conductive metal layer 108 is formed, a grinding process is then performed on the second conductive metal layer 108 to remove the second conductive metal layer 108 above the dielectric layer 103, leaving the second conductive metal layer 108 in the recessed region 107, thus forming a second conductive plug 108a in the recessed region 107. The top surface of the second conductive plug 108a is flush with the top surface of the dielectric layer 103. The second conductive plug 108a is located above the first conductive plug 106a and can cover the top surface of the first conductive plug 106a. At the same time, since the projected area of the recessed region 107 is large, the projected area of the second conductive plug 108a is larger than the projected area of the first conductive plug 106a, that is, the second conductive plug 108a can cover the first conductive plug 106a, so that the first conductive plug 106a does not come into contact with the outside world, that is, the second conductive plug 108a can prevent the first conductive plug 106a from reacting with the outside world. Meanwhile, the reactivity of the second conductive metal of the second conductive plug 108a is less than that of the first conductive metal of the first conductive plug 106a, meaning the second conductive metal is an inert metal relative to the first conductive metal. Therefore, the second conductive plug 108a will not react with the external environment. In this embodiment, the first conductive plug 106a is located in the conductive plug hole 105, and the second conductive plug 108a can also be understood as being in the conductive plug hole 105. That is, the first conductive plug 106a and the second conductive plug 108a are located in the same conductive plug hole 105, and the first conductive plug 106a and the second conductive plug 108a form a conductive plug.
[0078] like Figure 8 As shown, this embodiment uses a chemical mechanical polishing (CMP) process to remove most of the second conductive metal layer 108, thereby forming the second conductive plug 108a. To prevent depressions from forming on the second conductive plug 108a, this embodiment employs a multi-stage polishing process. For example, in the first CMP process, a polishing slurry with a first flow rate is provided to remove most of the second conductive metal layer 108. Then, a second CMP process is performed, with a polishing slurry with a second flow rate. The first flow rate is less than the second flow rate, resulting in a lower CMP rate in the second CMP process than in the first CMP process. This prevents depressions from forming in the second conductive plug 108a, ensuring that the second conductive plug 108a can cover the top surface of the first conductive plug 106a, thus preventing the first conductive plug 106a from contacting the outside environment.
[0079] like Figure 8As shown in this embodiment, in the vertical direction, the height of the first conductive plug 106a is greater than the height of the second conductive plug 108a. Since the spacing between adjacent first conductive plugs 106a is small, further increasing the height of the second conductive plug 108a would also increase its horizontal width, leading to the connection of adjacent second conductive plugs 108a, which in turn leads to the connection of adjacent first conductive plugs 106a, and consequently, a short circuit between adjacent device structures 104. Therefore, in this embodiment, the height of the first conductive plug 106a is greater than the height of the second conductive plug 108a. Simultaneously, the conductivity of the first conductive plug 106a is less than that of the second conductive plug 108a, meaning the second conductive plug 108a has better conductivity, thereby improving the overall conductivity of the conductive plugs.
[0080] like Figure 8 As shown, in this embodiment, the top surface of the first conductive plug 106a is concave, meaning the top surface of the first conductive plug 106a is concave downwards. The bottom surface of the second conductive plug 108a matches the top surface of the first conductive plug 106a, thereby increasing the contact area between the second conductive plug 108a and the first conductive plug 106a, thus reducing their contact resistance and further improving device performance. In this embodiment, while grinding the second metal conductive layer 106, a concave region is formed above the first conductive plug 106a by controlling the grinding process. The process is relatively simple and also reduces the impact on the first conductive plug 106a.
[0081] like Figure 9As shown, in step S3, after forming the second conductive plug 108a, a through-silicon via (TSV) 109 is formed in the substrate 101. The TSV 109 is located on one side of the first conductive plug 106a. The depth of the TSV 109 is greater than the sum of the heights of the first conductive plug 106a and the second conductive plug 108a. In this embodiment, a hard mask layer can be formed on the dielectric layer 103 first, and then a patterned photoresist can be formed on the hard mask layer. The hard mask layer can be a silicon nitride layer, silicon oxynitride, or the like. An opening can be formed in the photoresist layer (not shown) to expose the hard mask layer using exposure, baking, development, and / or other known lithography processes. Then, using the patterned photoresist as a mask, the exposed hard mask layer is etched by wet etching or dry etching to form an opening. Subsequently, using a hard mask layer and a patterned photoresist as a mask, the exposed substrate 101 is etched to form a through-silicon via (TSV) 109. After forming the TSV 109, the hard mask layer and photoresist layer are removed. The TSV 109 penetrates at least a portion of the substrate 102. The TSV 109 can be etched using any suitable etching method, such as plasma etching, chemical wet etching, laser drilling, and / or other known processes. In one embodiment, the etching includes etching the substrate 101 using a deep reactive ion etching (DRIE) process. The etching of the TSV 109 can extend from the front side of the substrate 101 down to a depth of tens to hundreds of micrometers without penetrating the back side of the substrate 101. The TSV 109 can have a vertical sidewall profile or a tapered sidewall profile.
[0082] like Figure 10 As shown, after forming the through-silicon via 109, an insulating layer 110 is formed on the aforementioned structure. This insulating layer 110 conformably covers the bottom and sidewalls of the through-silicon via 109 to prevent any conductive material from entering the active region of the circuitry in the substrate 101. The material of the insulating layer 110 can be silicon oxide, tetraethoxysilane (TEOS) silicon oxide, silicon nitride, or a combination thereof, and it can be formed by thermal oxidation, atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). For example, a tetraethoxysilane (TEOS) silicon oxide layer can be formed using tetraethoxysilane (TEOS) and ozone as precursors via low pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. In this embodiment, the insulating layer 110 also covers the front side of the dielectric layer 103 and the top surface of the second conductive plug 108a.
[0083] like Figure 11As shown, after forming the insulating layer 110, a third conductive metal is filled into the through-silicon via 109, thereby forming a third conductive metal layer 111. The third conductive metal layer 111 fills the through-silicon via 109 and also covers the insulating layer 110. This third conductive metal layer 111 can be a low-resistance conductive material, such as copper or a copper-based alloy. For example, the copper filling process may include the deposition of a metal seed layer and a copper electroplating process. The metal seed layer can be formed using physical vapor deposition or chemical vapor deposition. Subsequently, the substrate 101 is placed in an electroplating apparatus, such as an electrochemical electroplating apparatus, and a copper layer is electroplated on the substrate 101 to fill the through-silicon via 109. In this embodiment, the reactivity of the third conductive metal is greater than or equal to the reactivity of the second conductive metal, meaning the second conductive metal is an inert metal relative to the third conductive metal, i.e., the second conductive metal will not react with the metal ions of the third conductive metal. In this embodiment, the third conductive metal can be copper, and the second conductive metal can be copper, gold, or silver, etc.
[0084] like Figure 12As shown, after the third conductive metal layer 111 is formed, a chemical mechanical polishing process is used to remove the third conductive metal layer 111 located on the insulating layer 110 and outside the through-silicon via 109. Simultaneously, the insulating layer 110 located on the dielectric layer 103 and outside the through-silicon via 109 can also be removed, thus retaining the insulating layer 110 and the third conductive metal layer 111 within the through-silicon via 109. This results in the insulating layer 110 and the third conductive metal layer 111 forming a through-silicon via structure 112. In this embodiment, the third conductive metal is copper, and the insulating layer 110 is silicon nitride. During the polishing of the third conductive metal layer 111, multiple polishing processes can be used, employing a polishing slurry with a copper and silicon nitride etching ratio close to 1:1. This preserves the third conductive metal layer 111 and the insulating layer 110 within the through-silicon via 109 and prevents the formation of a recessed area on the second conductive plug 108. During the polishing process of the third conductive metal layer 111, the third conductive metal (copper) in the third conductive metal layer 111 reacts with the polishing slurry, thereby forming copper ions in the polishing slurry. Meanwhile, since the second conductive plug 108a is made of an inert metal, meaning the reactivity of the second conductive metal in the second conductive plug 108a is less than or equal to the reactivity of the third conductive metal, the second conductive plug 108a can be made of, for example, copper, gold, silver, or other metal materials. When the second conductive plug 108a is made of copper, the reactivity of the second conductive metal is equal to the reactivity of the third conductive metal. In this case, the second conductive metal will not react with the metal ions of the third conductive metal, thus preventing the formation of the third conductive metal on the dielectric layer 103. When the second conductive metal is made of gold, the reactivity of the second conductive metal is less than that of the third conductive metal. In this case, the second conductive metal will not react with the metal ions of the third conductive metal, thus preventing the formation of the third conductive metal on the dielectric layer 103. In this embodiment, since the first conductive plug 106a is made of tungsten metal, its reactivity is greater than that of the third conductive metal. When the first conductive plug 106a comes into contact with the polishing slurry, the tungsten metal reacts with the copper ions in the slurry, reducing the copper ions to copper metal, which could potentially lead to a short circuit. However, in this embodiment, the first conductive plug 106a and the polishing slurry are isolated by the second conductive plug 108a, which is made of an inert metal. This prevents the first conductive plug 106a from reacting with copper ions, and the second conductive plug 108a also does not react with copper ions, thus avoiding the reduction of copper ions to copper metal. This ensures that short circuits between the conductive plugs do not occur and also prevents copper contamination.
[0085] like Figure 12As shown in the embodiments of this disclosure, a semiconductor structure 100 is provided. The semiconductor structure 100 may include a substrate 101, which may include a substrate 102 and a dielectric layer 103, with the dielectric layer 103 located on the substrate 102. A device structure 104 is located on the substrate 101, and a conductive plug 113 is located above the device structure 104, electrically connected to the device structure 104. The conductive plug 113 includes a first conductive plug 106a and a second conductive plug 108a. The first conductive plug 106a is electrically connected to the device structure 104, and the second conductive plug 108a is located on the first conductive plug 106a, covering the top surface of the first conductive plug 106a. The top surface of the second conductive plug 108a is flush with the top surface of the dielectric layer 103. A through-silicon via (TSV) structure 112 is located on one side of the conductive plug 113. The TSV structure 112 extends from the dielectric layer 103 into the substrate 102 and has a depth greater than that of the first conductive plug 106a. The TSV structure 112 includes an insulating layer 110 and a third conductive metal layer 111. The insulating layer 110 can be lined within the TSV, and the third conductive metal layer 111 can fill the TSV.
[0086] like Figures 12-13As shown, in this embodiment of the present disclosure, the first conductive plug 106a is located between the second conductive plug 108a and the device structure 104. The height of the first conductive plug 106a is greater than the height of the second conductive plug 108a. The height of the first conductive plug 106a can be 1.5-3 μm, for example, 1.8 μm, 2.0 μm, 2.3 μm, 2.5 μm, or 2.8 μm. The height of the second conductive plug 108a is much smaller than the height of the first conductive plug 106a, and the height of the second conductive plug 108a can be 10-30 nm, for example, 15 nm, 20 nm, or 25 nm. The height of the through-silicon via (TSV) structure 112 is greater than the height of the first conductive plug 106a and greater than the sum of the heights of the first conductive plug 106a and the second conductive plug 108a. The height of the TSV structure 112 is between 20-80 μm, for example, 30 μm, 40 μm, 50 μm, 60 μm, or 70 μm. In this embodiment, the ratio of the height of the first conductive plug 106a to the height of the second conductive plug 108a is greater than the ratio of the height of the through-silicon via structure 112 to the height of the first conductive plug 106a. That is, the height of the first conductive plug 106a is much greater than the height of the second conductive plug 108a. This is because, in the horizontal direction, the width d1 of the first conductive plug 106a is 90-110nm, the width d2 of the second conductive plug 108a is 160-180nm, the width d3 of two adjacent first conductive plugs 106a is 300-500nm, and the width of two adjacent second conductive plugs 108a is even smaller. When the height of the second conductive plug 108a increases, the width of the second conductive plug 108a also increases. This may lead to the risk of two adjacent second conductive plugs 108a contacting each other, which could result in a short circuit. Therefore, in this embodiment, the height of the second conductive plug 108a is much smaller than the height of the first conductive plug 106a, so that the ratio of the height of the first conductive plug 106a to the height of the second conductive plug 108a is relatively large.
[0087] like Figure 12As shown, in this embodiment, the first conductive plug 106a can be made of a first conductive metal, the second conductive plug 108a can be made of a second conductive metal, and the through-silicon via (TSV) structure 112 can be made of a third conductive metal (third conductive metal layer 111). The first conductive metal can be different from the second conductive metal, and vice versa; of course, the second conductive metal can also be the same as the third conductive metal. In this embodiment, the reactivity of the third conductive metal can be greater than or equal to the reactivity of the second conductive metal. The reactivity of the first conductive metal can be greater than the reactivity of the third conductive metal. The reactivity of the first conductive metal can also be greater than the reactivity of the second conductive metal. In this embodiment, the first conductive metal can be tungsten, nickel, or other metals; the second conductive metal can be copper, gold, silver, or other metals; and the third conductive metal can be copper. During the formation of the TSV structure 112, the third conductive metal layer reacts with the polishing slurry to form copper ions, which then enter the polishing slurry. Since the second conductive plug 108a is an inert metal compared to the third conductive metal layer 111, it will not reduce the copper ions to copper metal. Simultaneously, the second conductive plug 108a completely covers the first conductive plug 106a, preventing the first conductive plug 106a from contacting the external polishing fluid, thus preventing the reduction of copper ions to copper metal, and consequently preventing the formation of copper metal on the dielectric layer 103. This also prevents short circuits between adjacent conductive plugs 113 and avoids copper contamination.
[0088] like Figure 5 , Figure 14 As shown, in some embodiments, after the first conductive metal layer 106 is formed, a reverse etching process can be used to etch away the first conductive metal layer 106 on the dielectric layer 103. Simultaneously, a portion of the first conductive metal layer 106 in the conductive plug hole 105 will also be etched away, thereby forming a first conductive plug 106a in the conductive plug hole 105. At this time, the top surface of the first conductive plug 106a is lower than the top surface of the dielectric layer 103, and the height of the first conductive plug 106a is also less than the depth of the conductive plug hole 105. Of course, through the etching process, the relative integrity of the dielectric layer 103 can be ensured, and no recessed areas will be formed on the dielectric layer 103.
[0089] like Figures 15-16As shown, after the first conductive plug 106a is formed, a second conductive metal layer 108 is formed on the dielectric layer 103. The second conductive metal layer 108 also fills the area above the first conductive plug 106a. Then, the second conductive metal layer 108 above the dielectric layer 103 is ground away by a chemical mechanical polishing process, leaving the second conductive metal layer 108 in the conductive plug hole 105, thus forming the second conductive plug 108a. At this time, the second conductive plug 108a is located above the first conductive plug 106a and can cover the top surface of the first conductive plug 106a. Since the first conductive plug 106a and the second conductive plug 108a are both located in the conductive plug hole 105, and the dielectric layer 103 is not etched, the projection area of the second conductive plug 108a can coincide with the projection area of the first conductive plug 106a, thereby ensuring that the first conductive plug 106a will not come into contact with the external polishing fluid.
[0090] like Figure 17 As shown, in some embodiments, after forming the first conductive plug 106a and before forming the second conductive plug 108a, a barrier layer 114 may be formed in the conductive plug hole. The barrier layer 114 may be deposited conformally on the sidewall of the conductive plug hole 105 and is also located on the top surface of the first conductive plug 106a. The barrier layer 114 can serve as a diffusion barrier layer to prevent metal diffusion. The material of the barrier layer 114 may be a refractory metal, a refractory metal nitride, a refractory metal silicide, or a combination thereof. The barrier layer 114 may include: refractory materials, TiN, TaN, Ta, Ti, TiSN, W, WN, Cr, Nb, Co, Ni, Pt, Ru, Pd, Au, CoP, CoWP, NiP, NiWP, a combination thereof, or other materials that can inhibit copper diffusion into the dielectric layer 103. It may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or electroplating. In one embodiment, the barrier layer 114 may include a TaN layer and a Ta layer, or the barrier layer 114 may be a TiN layer, or the barrier layer 22 may be a Ti layer.
[0091] It should be noted that the barrier layer 114 may also be formed on the sidewall of the conductive plug hole 106 before the first conductive metal layer 106 is formed in the conductive plug hole 105. During the fabrication of the through-silicon via structure 112, the barrier layer 114 may also be formed compliantly on the insulating layer 110 after the insulating layer 110 is formed, and the barrier layer 114 serves as an adhesive layer between the third conductive metal layer 111 and the dielectric layer 103.
[0092] like Figure 18 As shown in the embodiments of this disclosure, a semiconductor structure 100 is also proposed. Figure 18 Semiconductor structure 100 and Figure 12 The semiconductor structures in these 100 are basically the same, the difference being that... Figure 18 The width of the second conductive plug 108a is equal to the width of the first conductive plug 106a, thereby ensuring that adjacent conductive plugs 113 always maintain a large distance, thus preventing short circuits between adjacent conductive plugs 113. Figure 18 In this configuration, the height of the first conductive plug 106a is greater than the height of the second conductive plug 108. The conductivity of the second conductive plug 108a can be greater than that of the first conductive plug 106, thereby increasing the conductivity of the conductive plug 113. The materials of the first conductive plug 106a, the second conductive plug 108a, and the third conductive metal layer 111 can be referred to the above description.
[0093] In some embodiments, the semiconductor structure 100 described above can be applied in a packaged device. This packaged device can be applied to an electronic device. The electronic device may include one or more of the following: for example, a smartphone, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a home appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).
[0094] In summary, this disclosure provides a semiconductor structure and its manufacturing method. First, a conductive plug hole is formed in a substrate. Then, a first conductive plug and a second conductive plug are sequentially formed within the conductive plug hole, thus forming a conductive plug. The second conductive plug is located on top of the first conductive plug and completely covers its top surface. Next, a through-silicon via (TSV) structure is formed on one side of the conductive plug. Since the first conductive plug includes a first conductive metal, the second conductive plug includes a second conductive metal, and the TSV structure includes a third conductive metal, and the reactivity of the second conductive metal is less than or equal to that of the third conductive metal, during the formation of the TSV structure, the third conductive metal reacts with the polishing slurry to form metal ions. Simultaneously, the second conductive plug prevents the first conductive plug from contacting the polishing slurry, thereby preventing the first conductive metal from reacting with the metal ions. Meanwhile, since the reactivity of the second conductive metal is less than or equal to that of the third conductive metal, the second conductive metal will not react with the metal ions even if it comes into contact with the polishing slurry. In other words, the metal ions in the polishing slurry will not be reduced to the third conductive metal. This can prevent the formation of the third conductive metal on the conductive plug, thereby preventing short circuits between adjacent conductive plugs and also preventing metal contamination.
[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A conductive plug hole is formed in the substrate; A first conductive plug and a second conductive plug are sequentially formed in the conductive plug hole. The second conductive plug is located on the first conductive plug and covers the top surface of the first conductive plug. The first conductive plug includes a first conductive metal, and the second conductive plug includes a second conductive metal. A through-silicon via (TSV) structure is formed in the substrate, the TSV structure being located on one side of the first conductive plug, and the TSV structure comprising a third conductive metal; The reactivity of the second conductive metal is less than or equal to that of the third conductive metal.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps for forming the first conductive plug include: The first conductive metal is deposited into the conductive plug hole to form a first conductive metal layer, the first conductive metal layer covering the top surface of the substrate; The first conductive metal layer located on the substrate is ground to form the first conductive plug.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, During the grinding process of the first conductive metal layer located on the substrate, a recessed area is formed on the top of the first conductive plug so that the top surface of the first conductive plug is lower than the top surface of the substrate.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The steps for forming the second conductive plug include: The second conductive metal is deposited into the recessed area to form a second conductive metal layer, the second conductive metal layer covering the top surface of the substrate, wherein the reactivity of the first conductive metal is greater than that of the second conductive metal. The second conductive metal layer located on the substrate is ground to form the second conductive plug, the top surface of the second conductive plug being flush with the top surface of the substrate.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps for forming the first conductive plug include: The first conductive metal is deposited into the conductive plug hole to form a first conductive metal layer; The first conductive metal layer is etched to form the first conductive plug, the height of which is less than the depth of the conductive plug hole.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The steps for forming the second conductive plug include: The second conductive metal is formed in the conductive plug hole, and the second conductive metal covers the top surface of the substrate; The second conductive metal located on the substrate is ground to form the second conductive plug, the top surface of the second conductive plug being flush with the top surface of the substrate.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the vertical direction, the height of the second conductive plug is less than the height of the first conductive plug, and the conductivity of the first conductive plug is less than the conductivity of the second conductive plug.
8. The method for manufacturing a semiconductor structure according to any one of claims 1-7, characterized in that, After forming the first conductive plug, the method further includes forming a barrier layer on the first conductive plug, the barrier layer being located between the first conductive plug and the second conductive plug.
9. The method for manufacturing a semiconductor structure according to any one of claims 1-7, characterized in that, The steps for forming the through-silicon via structure include: Through-silicon vias are formed in the substrate; An insulating layer is formed inside the through-silicon via; The third conductive metal is deposited in the through-silicon via to form a third conductive metal layer, which covers the top surface of the substrate; The third conductive metal layer located on the substrate is polished to form the through-silicon via structure.
10. A semiconductor structure, characterized in that, include: Base; A conductive plug is located in the substrate. The conductive plug includes a first conductive plug and a second conductive plug located on the first conductive plug. The second conductive plug covers the first conductive plug. The first conductive plug includes a first conductive metal, and the second conductive plug includes a second conductive metal. A through-silicon via (TSV) structure is located in the substrate, on one side of the conductive plug, and the TSV structure includes a third conductive metal. The reactivity of the second conductive metal is less than or equal to that of the third conductive metal.
11. The semiconductor structure according to claim 10, characterized in that, In the vertical direction, the height of the first conductive plug is greater than the height of the second conductive plug.
12. The semiconductor structure according to claim 10, characterized in that, It also includes a barrier layer located between the first conductive plug and the second conductive plug.
13. The semiconductor structure according to claim 10, characterized in that, The reactivity of the second conductive metal is less than that of the first conductive metal.
14. The semiconductor structure according to claim 10, characterized in that, The conductivity of the second conductive metal is greater than that of the first conductive metal.
15. The semiconductor structure according to any one of claims 10-14, characterized in that, The ratio of the height of the first conductive plug to the height of the second conductive plug is greater than the ratio of the height of the through-silicon via structure to the height of the first conductive plug.