Semiconductor structure and method of fabricating the same
By introducing an intermediate dielectric layer and conductive vias into the semiconductor structure, electrical connections between chips are achieved, solving the problems of large overall height and difficult heat dissipation, and improving the space utilization and performance of the semiconductor structure.
CN122138730APending Publication Date: 2026-06-02BEIJING XIAOMI MOBILE SOFTWARE CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING XIAOMI MOBILE SOFTWARE CO LTD
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
Existing semiconductor structures suffer from problems such as large overall height and difficulty in heat dissipation due to limitations in device stacking methods, which affect layout design and performance.
Method used
By employing an intermediate dielectric layer and a conductive structure, and by setting a first chip layer and multiple second chip layers on the substrate, electrical connections between chips are achieved using conductive vias, thereby reducing the overall stacking height and shortening the heat dissipation path.
Benefits of technology
This reduces the overall height of the semiconductor structure, improves space utilization and heat dissipation efficiency, and enhances layout design and performance.
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Smart Images
Figure CN122138730A_ABST
Abstract
This disclosure relates to a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a first chip layer, an intermediate dielectric layer, and multiple second chip layers. A conductive structure is disposed on the substrate. The first chip layer is disposed on the substrate and includes a first chip electrically connected to the substrate. The intermediate dielectric layer is disposed on the first chip layer and has a first conductive via. Multiple second chip layers are stacked on the intermediate dielectric layer, each second chip layer including multiple second chips, and each second chip having a second conductive via. By providing an intermediate dielectric layer and multiple second chips in each second chip layer, the overall stacking height of the semiconductor structure is reduced, the heat dissipation path of the chips is shortened, the layout design of the semiconductor structure is facilitated, and the performance of the semiconductor structure is improved.
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