Electronic component embedded substrate

Abstract

The present disclosure provides an electronic component embedded substrate including a glass layer; a through cavity penetrating an area between an upper surface and a lower surface of the glass layer; a blind member disposed at least partially within the through cavity; an electronic component disposed at least partially within the through cavity and attached to an upper surface of the blind member; and an insulating material covering at least a portion of each of the glass layer, the blind member, and the electronic component and filling at least a portion of the through cavity.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0175651, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to an embedded substrate for electronic components. Background Technology

[0003] To meet the demands of high-performance and miniaturization strategies in semiconductors, printed circuit boards (PCBs) require increasingly smaller and higher densities. For example, manufacturing high-end products such as server boards necessitates high layer counts and large bodies. However, as the number of wiring layers increases and the body size grows, the board may become prone to warping. To prevent this problem, the use of glass cores is being considered. Furthermore, blind cavities can be fabricated to embed electronic components within the glass core, and these components can be positioned within them. However, when forming blind cavities within a glass core, the bottom and wall surfaces may be uneven due to the effects of laser processing and etching. This can lead to issues with the alignment of electronic components, variations in the thickness of the insulating material above the components, and via connectivity. Summary of the Invention

[0004] One aspect of this disclosure is to provide an electronic component embedded substrate including a cavity for embedding electronic components in a glass layer, which can improve the alignment capability of the electronic components, improve the dimensional freedom of the electronic components, reduce the impact on the angle of the cavity wall surface or the uniformity of the cavity bottom surface (e.g., the uniformity may refer to flatness), and improve the thickness deviation of the insulating material located on the upper side of the electronic components and / or the reliability of vias.

[0005] One aspect of this disclosure is that a through cavity is formed in the glass layer, a separate blind member is disposed on the underside of the through cavity, and an electronic component is disposed on the blind member in the through cavity such that the electronic component is embedded in the through cavity. The blind member can be, for example, but not limited to, a glass block, a metal block, or a combination thereof.

[0006] According to one aspect of this disclosure, an embedded substrate for an electronic component includes: a glass layer; a through cavity penetrating a region between an upper surface and a lower surface of the glass layer; a blind member disposed at least partially within the through cavity; an electronic component disposed at least partially within the through cavity and attached to the upper surface of the blind member; and an insulating material covering at least a portion of each of the glass layer, the blind member, and the electronic component, and filling at least a portion of the through cavity.

[0007] According to one aspect of this disclosure, an embedded substrate for an electronic component includes: a glass layer; a through cavity penetrating a region between an upper surface and a lower surface of the glass layer; a glass block disposed at least partially in the lower side of the through cavity; an electronic component disposed at least partially in the upper side of the through cavity; and an insulating material covering at least a portion of each of the glass layer, the glass block, and the electronic component, and filling at least a portion of the through cavity. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 This is a schematic cross-sectional view illustrating an example of an embedded substrate for electronic components; Figure 3 It is along Figure 2 A schematic cross-sectional view of the line A-A' cut; Figure 4 This is a schematic cross-sectional view illustrating another example of an embedded substrate for electronic components; and Figure 5 This is a cross-sectional view schematically illustrating another example of an embedded substrate for electronic components. Detailed Implementation

[0009] In the following description, this disclosure will be made with reference to the accompanying drawings. For clarity, the shapes and dimensions of the elements in the drawings may be exaggerated or reduced.

[0010] Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0011] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0012] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these, and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0013] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, LAN, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, but may also include components compatible with or operating according to various other wireless standards or protocols and wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0014] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, and may also include passive components in the form of chip assemblies for various other purposes. Additionally, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc., but are not limited thereto. These other electronic components may also be audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Furthermore, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0016] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, server, etc. However, electronic device 1000 is not limited to these, but can be any other electronic device capable of processing data.

[0017] Figure 2 This is a schematic cross-sectional view illustrating an example of an embedded substrate for electronic components.

[0018] Figure 3 It is along Figure 2 A schematic cross-sectional view of the line A-A' cut.

[0019] Reference Figure 2 and Figure 3An example electronic component embedded substrate 100A may include: a glass layer 110; a through cavity h penetrating the region between the upper and lower surfaces of the glass layer 110; a blind member 180, at least partially disposed on the lower side within the through cavity h; an electronic component 191, at least partially disposed on the upper side within the through cavity h; and an insulating material 115 covering at least a portion of each of the glass layer 110, the blind member 180, and the electronic component 191 and filling at least a portion of the through cavity h. The electronic component 191 may be attached to the upper surface of the blind member 180. For example, the electronic component 191 may have a connection electrode P located on the upper surface, and the lower surface of the electronic component 191 may be attached to the upper surface of the blind member 180 via an adhesive layer 192. The side surfaces of each of the blind member 180, the electronic component 191, and the adhesive layer 192 may be spaced apart from the wall surface of the through cavity h. For example, the wall surface of the through cavity h may continuously surround the side surface of each of the blind member 180, electronic component 191, and adhesive layer 192, but is not limited thereto. The insulating material 115 may fill at least a portion of the space between the wall surface of the through cavity h and the side surface of each of the blind member 180, electronic component 191, and adhesive layer 192.

[0020] In this manner, in the example electronic component embedded substrate 100A, a through cavity h is formed in the glass layer 110 instead of a blind cavity, thus preventing problems that may occur during the blind cavity formation process. At this time, a separate blind member 180 can be disposed on the lower side within the through cavity h, thus achieving a structure similar to a blind cavity. For example, the blind member 180 can provide a bottom surface on the lower side within the through cavity h. Therefore, the disadvantages of the blind cavity structure can be overcome while retaining its advantages. For example, the alignment capability of the electronic component 191 can be improved, the dimensional freedom of the electronic component 191 can be improved, the influence on the angle of the wall surface or the consistency of the cavity bottom surface of the through cavity h can be reduced, the thickness deviation of the region of the insulating material 115 disposed on the upper side of the electronic component 191 can be improved, and the reliability of the third connection via 133 formed in the region of the insulating material 115 disposed on the upper side of the electronic component 191 can be improved.

[0021] Reference Figure 2 and Figure 3The example electronic component embedded substrate 100A may further include: a metal via 130 penetrating at least a portion between the upper and lower surfaces of the glass layer 110; a first wiring layer 121 disposed on the upper surface of the insulating material 115; a second wiring layer 122 disposed on the lower surface of the insulating material 115; a first connection via 131 penetrating at least a portion of the upper insulating material 115 (i.e., the portion of the insulating material 115 located on the upper side of the glass layer 110) and connecting at least a portion of the first wiring layer 121 to the metal via 130; a second connection via 132 penetrating at least a portion of the lower insulating material 115 (i.e., the portion of the insulating material 115 located on the lower side of the glass layer 110) and connecting at least a portion of the second wiring layer 122 to the metal via 130; and a third connection via 133 penetrating at least another portion of the upper insulating material 115 and connecting at least another portion of the first wiring layer 121 to the connection electrode P. The metal via 130 can fill at least a portion of the through-hole formed in the glass layer 110 to form, for example, a through-glass via (TGV). The upper and lower surfaces of the metal via 130 may have a step difference with the upper and lower surfaces of the glass layer 110, but are not limited thereto. The first connecting via 131 and the second connecting via 132 can be directly connected to the metal via 130, and for example, can directly contact the metal via 130 without separate pads or solder pads. Therefore, the overall thickness of the substrate can be reduced, and the manufacturing process can be simplified.

[0022] Reference Figure 2 and Figure 3 The example electronic component embedded substrate 100A may further include a frame 105 and a penetration portion H penetrating the region between the upper and lower surfaces of the frame 105. A glass layer 110 may be at least partially disposed within the penetration portion H. An insulating material 115 may also cover at least a portion of the frame 105 and may also fill at least a portion of the penetration portion H. If desired, at least a portion of the penetration portion H may also be filled with a separate filler. The frame 105 may comprise various materials with excellent rigidity. The frame 105 can be used as a fixture during the process, thus allowing the process to be performed at the panel level via the frame 105, and process warpage can be easily controlled. Additionally, the frame 105 may be retained in the final unit after cutting, and in this case, warpage control of the final unit may be more advantageous.

[0023] Reference Figure 2 The example electronic component embedded substrate 100A may further include: a plurality of first stacked insulating layers 141 disposed on the upper surface of the insulating material 115; a plurality of first stacked wiring layers 142 disposed on or within the plurality of first stacked insulating layers 141; and a plurality of first stacked via layers 143. respectivelyThe electronic component embedded substrate 100A according to the embodiment may further include: a first passivation layer 161 disposed on the plurality of first stacked insulating layers 141 and having a plurality of first openings, the plurality of first openings exposing at least a portion of the uppermost first stacked wiring layer 142; and a second passivation layer 162 disposed on the plurality of second stacked insulating layers 151 and having a plurality of second openings, the plurality of second openings exposing at least a portion of the lowermost second stacked wiring layer 152. For example, the electronic component embedded substrate 100A according to the example may include a glass layer 110 as a core layer and stacked layers formed on one or both sides of the core layer, and therefore can be easily used as a packaging substrate, an interposer substrate, etc. In addition, the electronic component embedded substrate 100A can be easily applied to other various types and / or various forms of printed circuit boards.

[0024] In the following description, the components of the example electronic component embedded substrate 100A will be described in more detail with reference to the accompanying drawings.

[0025] Frame 105 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in a resin. For example, the organic insulating material may include, but is not limited to, copper-clad laminates (CCLs) or bare CCLs, and may also include other organic or inorganic materials with excellent rigidity. The penetration portion H may penetrate the area between the upper and lower surfaces of frame 105. The penetration portion H may continuously surround, but is not limited to, the side surface of glass layer 110.

[0026] Glass layer 110 may include glass, which is an amorphous solid. The glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, this disclosure is not limited to this, and alternative glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc., may also be used. Furthermore, other additives may be included to form a glass with specific physical properties. These additives include at least one of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates (e.g., calcium carbonate (e.g., lime), sodium carbonate (e.g., soda ash)) and oxides of these elements and other elements. Furthermore, glass layer 110 may be distinguished from organic insulating materials (e.g., copper-clad laminates (CCL), prepregs (PPG), etc.) that include glass fibers (e.g., glass fabrics, such as glass cloth). Glass layer 110 may be in the form of, for example, a glass plate. A through cavity h may penetrate the region between the upper and lower surfaces of glass layer 110. The through cavity h can continuously surround the side surfaces of the electronic component 191, the adhesive layer 192, and the blind member 180.

[0027] Insulating material 115 may include organic insulating materials. Organic insulating materials may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in a resin. For example, organic insulating materials may include, but are not limited to, prepreg (PPG), Ajinomoto laminate (ABF), photosensitive dielectric (PID), etc. Insulating material 115 may include multiple layers, which may be integral without boundaries between them, or the boundaries between the multiple layers may be easily distinguishable. The multiple layers may include, but are not limited to, substantially the same insulating material, and may include different insulating materials.

[0028] Both the first wiring layer 121 and the second wiring layer 122 may comprise metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, both the first wiring layer 121 and the second wiring layer 122 may include a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed by an electrolytic plating process based on the seed layer as a plating layer. The first wiring layer 121 and the second wiring layer 122 may each perform various functions according to the design. For example, both the first wiring layer 121 and the second wiring layer 122 may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various shapes, such as lines, traces, planes, pads, solder pads, etc.

[0029] The metal via 130 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal via 130 may include a titanium and copper layer (e.g., sputtered titanium and sputtered copper layers) formed by a sputtering process as a seed layer, and may include an electrolytically plated copper layer formed based on the titanium and copper layers by an electrolytic plating process as a plating layer. If desired, a chemically plated copper layer formed by an electroless plating process may also be included as a seed layer. The metal via 130 may perform various functions according to the design. For example, the metal via 130 may include a through-hole for signal transmission, a through-hole for power transmission, a through-hole for grounding transmission, etc. The metal via 130 may be a filled via formed by filling a through-hole with metal. The metal via 130 may have a generally cylindrical shape, but this disclosure is not limited thereto; for example, the metal via 130 may also have a generally hourglass shape. The upper and lower surfaces of the metal via 130 may be recessed inward relative to the upper and lower surfaces of the glass layer 110, respectively. Therefore, the upper and lower surfaces of the metal via 130 may have a step difference with the upper and lower surfaces of the glass layer 110, but are not limited thereto. The upper and lower surfaces of the metal via 130 may be coplanar with the upper and lower surfaces of the glass layer 110, respectively. There may be multiple metal vias 130.

[0030] The first connection via 131, the second connection via 132, and the third connection via 133 may all comprise metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first connection via 131, the second connection via 132, and the third connection via 133 may all comprise a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed by an electrolytic plating process based on the chemically plated copper layer as a plating layer. The first connection via 131, the second connection via 132, and the third connection via 133 may each perform various functions according to the design. For example, the first connection via 131, the second connection via 132, and the third connection via 133 may all comprise connection vias for signal transmission, connection vias for power transmission, connection vias for grounding transmission, etc. The first connecting via 131, the second connecting via 132, and the third connecting via 133 may each include a filled via formed by filling at least a portion of the via with metal, or may include a conformal via formed by distributing metal along the wall surface of the via. The first connecting via 131, the second connecting via 132, and the third connecting via 133 may each have a generally tapered shape. The first connecting via 131 and the second connecting via 132 may be directly connected to the upper and lower surfaces of the metal via 130, respectively, and, for example, may be in direct contact with the upper and lower surfaces of the metal via 130, respectively. When multiple metal vias 130 exist, the first connecting via 131 and the second connecting via 132 may also be correspondingly multiple. When multiple connecting electrodes P exist, the third connecting via 133 may also be correspondingly multiple.

[0031] Each of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in a resin. For example, the organic insulating material may include, but is not limited to, prepreg (PPG), Ajinomoto laminate (ABF), photosensitive dielectric (PID), etc. The respective plurality of layers of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may be integral with each other without boundaries, or the boundaries between the plurality of layers may be easily distinguishable. Furthermore, the respective plurality of layers of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may include substantially the same insulating material, or may include different insulating materials. The plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may have the same number of layers, but this is not limited to this; the plurality of first stacked insulating layers 141 may have a relatively larger number of layers. If necessary, multiple second stacked insulating layers 151 can be omitted.

[0032] Multiple first stacked wiring layers 142 and multiple second stacked wiring layers 152 may each comprise a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, multiple first stacked wiring layers 142 and multiple second stacked wiring layers 152 may each comprise a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed by an electrolytic plating process based on the chemically plated copper layer as a plating layer. Multiple first stacked wiring layers 142 and multiple second stacked wiring layers 152 may each perform various functions according to the design. For example, multiple first stacked wiring layers 142 and multiple second stacked wiring layers 152 may each comprise signal patterns, power patterns, ground patterns, etc. These patterns may have various shapes, such as lines, traces, planes, pads, solder pads, etc. The plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may have the same number of layers, but this disclosure is not limited thereto. For example, the plurality of first stacked wiring layers 142 may have a relatively larger number of layers. The plurality of second stacked wiring layers 152 may also be omitted when the plurality of second stacked insulating layers 151 are omitted.

[0033] The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may each comprise a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may each include a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed by an electrolytic plating process based on the chemically plated copper layer as a plating layer. The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may each perform various functions according to the design. For example, the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may each include connection vias for signal transmission, connection vias for power transmission, connection vias for grounding transmission, etc. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include a filled via formed by filling at least a portion of a via with metal, or may include a conformal via formed by distributing metal along the wall surface of a via. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include a plurality of connecting vias. The connecting vias included in each of the plurality of first stacked via layers 143 and the connecting vias included in each of the plurality of second stacked via layers 153 may have a generally tapered shape in opposite directions. The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may have the same number of layers, but this disclosure is not limited thereto; for example, the plurality of first stacked via layers 143 may have a relatively larger number of layers. If the plurality of second stacked insulating layers 151 are omitted, then the plurality of second stacked via layers 153 may also be omitted.

[0034] Both the first passivation layer 161 and the second passivation layer 162 may comprise an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers and / or organic fillers in a resin. For example, the organic insulating material may be, but is not limited to, Ajinomoto film (ABF), photosensitive dielectric (PID), solder resist (SR), etc. Both the first passivation layer 161 and the second passivation layer 162 may comprise multiple layers. Both the first passivation layer 161 and the second passivation layer 162 may have multiple openings, and the pattern exposed through each opening may be, but is not limited to, solder mask defined (SMD) type and / or non-solder mask defined (NSMD) type.

[0035] A blind member 180 may be disposed in the through cavity h to provide a bottom surface of the through cavity h. The blind member 180 may have various shapes and sizes. The width of the blind member 180 in cross-section may be wider than the width of each of the electronic component 191 and the adhesive layer 192 in cross-section, and the area of ​​the blind member 180 in the plane may be larger than the area of ​​each of the electronic component 191 and the adhesive layer 192 in the plane. Here, cross-section may refer to a cut section along the thickness direction of the glass layer 110 or the stacking direction of the printed circuit board. The blind member 180 may be spaced apart from the wall surface of the through cavity h. The blind member 180 may comprise various materials, and for example, in this example, the blind member 180 may comprise the glass described above with respect to the glass layer 110. For example, in this example, the blind member 180 may be a glass block 181. The glass block 181 may comprise substantially the same material as the glass layer 110, for example, substantially the same glass. Since the glass layer 110 and the glass block 181 that provides the bottom surface for the through cavity h are made of substantially the same material, the difference in the coefficient of thermal expansion can be reduced, which is more conducive to warpage control, etc.

[0036] Electronic component 191 can be attached to the bottom surface of glass block 181 with its face facing upwards. For example, electronic component 191 may include a connection electrode P for electrical connection, and the connection electrode P may be disposed on the upper surface (e.g., the front surface) of electronic component 191. The connection electrode P may include a conductive material, such as a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The connection electrode P may include pads, and may also include bumps or pillars disposed on the pads. Multiple connection electrodes P may be present. The lower surface (e.g., the back surface) of electronic component 191 may be attached to the upper surface of glass block 181 via adhesive layer 192. In this case, a known adhesive film (such as die attach film (DAF)) may be used as adhesive layer 192. Electronic component 191 may be thicker than adhesive layer 192. This arrangement further enhances the aforementioned technical effects. Electronic component 191 may include various types of active and / or passive components. For example, electronic component 191 may include, but is not limited to, various types of integrated circuit dies or semiconductor chips.

[0037] Figure 4 This is a cross-sectional view schematically illustrating another example of an embedded substrate for electronic components.

[0038] Reference Figure 4Compared to the electronic component embedded substrate 100A according to the example above, the electronic component embedded substrate 100B according to another example may include a metal block 182 as a blind member 180. In this case, heat dissipation can be better. The metal block 182 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and specifically, may include copper (Cu). In addition, if desired, the electronic component embedded substrate 100B may also include a fourth connection via 134, which penetrates at least another portion of the underlying insulating material 115 and connects at least another portion of the second wiring layer 122 to the blind member 180 (e.g., the metal block 182). Therefore, heat can be more easily released to the lower part of the substrate. The connection of the second wiring layer 122 to at least another portion of the metal block 182 may include, but is not limited to, ground patterns and / or power patterns. The detailed description of the fourth connection via 134 can be applied in substantially the same way as the descriptions of the first connection via 131, the second connection via 132, and the third connection via 133 described above. Other descriptions can be substantially the same as those described regarding the electronic component embedded substrate 100A according to the above example.

[0039] Figure 5 This is a cross-sectional view schematically illustrating another example of an embedded substrate for electronic components.

[0040] Reference Figure 5Compared to the electronic component embedded substrate 100A according to the example above, in the electronic component embedded substrate 100C according to another example, the blind member 180 includes a glass block 183 and a metal block 184. In this case, both the technical effects achieved by the glass block 183 and the technical effects achieved by the metal block 184 can be obtained. The metal block 184 can be attached to the lower surface of the glass block 183, and for example, can be directly connected to and in contact with the lower surface of the glass block 183. The metal block 184 can be thinner than the glass block 183. The detailed descriptions of the glass block 183 and the metal block 184 can be applied substantially the same as the descriptions of the glass block 181 and the metal block 182 described above. Furthermore, if desired, the electronic component embedded substrate 100C may also include a fourth connection via 134, which penetrates at least another portion of the underlying insulating material 115 and connects at least another portion of the second wiring layer 122 to the blind member 180 (e.g., the metal block 184). The connection of the second wiring layer 122 to at least another portion of the metal block 184 may include, but is not limited to, grounding patterns and / or power patterns. The detailed description of the fourth connection via 134 can be applied in substantially the same manner as the descriptions above regarding the first connection via 131, the second connection via 132, and the third connection via 133. Other descriptions may be substantially the same as those described regarding the electronic component embedded substrate 100A according to the above example and the electronic component embedded substrate 100B according to another example.

[0041] As described above, as an effect of this disclosure, in an electronic component embedded substrate including a cavity for embedding electronic components in a glass layer, the alignment capability of the electronic components can be improved, the dimensional freedom of the electronic components can be improved, the impact on the angle of the cavity wall surface or the consistency of the cavity bottom surface can be reduced, and the thickness deviation of the insulating material located on the upper side of the electronic component and / or the reliability of the vias can be improved.

[0042] In this disclosure, the term "cover" can include not only complete coverage but also partial coverage, and not only indirect coverage but also direct coverage. Similarly, the term "fill" can include not only partial filling but also complete filling, and also substantial filling. For example, it can include situations where gaps or voids exist. Furthermore, the term "surround" can include not only complete enclosure but also partial enclosure, and also substantial enclosure. Finally, "exposed" can include not only complete exposure but also partial exposure, and "exposed" can mean that an element is exposed from the component that buries the element.

[0043] In this disclosure, "set in the through cavity or penetrating portion" can include not only the case where the object is completely set in the through cavity or penetrating portion, but also the case where the object partially extends upward or downward in the cross-section. For example, if the object is set in the through cavity or penetrating portion on a plane, then it can be judged in a broader sense.

[0044] In this disclosure, "substantially / approximately" can be defined to include process errors, positional deviations, measurement errors, etc., that occur during the manufacturing process. For example, "set at substantially the same height" can include not only cases where the materials are set at exactly the same height, but also cases where they are set at approximately the same height. Similarly, "having a substantially specific shape" can include not only cases where the materials have exactly that shape, but also cases where the materials have approximately that shape. Furthermore, "substantially the same insulating material" can mean not only cases where the insulating materials are exactly the same, but also cases where the insulating materials are of the same type. Accordingly, the composition of the insulating materials can be substantially the same, but their specific component ratios can be slightly different.

[0045] In this disclosure, the term "section" can mean the shape of a cross section when an object is cut vertically, or the shape of an object when viewed from a side view. The term "plane" can mean the shape when an object is cut horizontally, or the planar shape of an object when viewed from a top or bottom view.

[0046] In this disclosure, for convenience, the word "lower" in "lower part," "lower surface," etc., is used to indicate the downward direction of the cross-section based on the drawings, and the word "upper" in "upper part," "upper surface," etc., is used to indicate the opposite direction. However, these directions are defined for ease of description, and the scope of the claims is not particularly limited by the description of these directions; the concepts of "upper" and "lower" may change at any time.

[0047] In this disclosure, the term "connection" includes not only direct connections but also indirect connections such as those via adhesive layers. Furthermore, the term "electrical connection" encompasses both physical and non-physical connections. Additionally, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] In this disclosure, thickness, width, length, depth, linewidth, spacing, pitch, separation distance, surface roughness, etc., can be measured using scanning electron microscopy, optical microscopy, or similar methods based on cross-sections obtained by polishing or cutting an embedded substrate for electronic components. The cut cross-section can be vertical or horizontal, and each value can be measured based on the desired cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the value is not constant, it can be determined as the average of values ​​measured at five random points.

[0049] The expression "(a) example" as used in this disclosure does not imply the same embodiment and is provided to emphasize and describe different unique characteristics. However, the examples presented above do not preclude implementations in combination with features of other examples. For example, unless there is a description that contradicts or contradicts the content of another example, even if something described in a particular example is not described in another example, it may be understood as a description related to the other example.

[0050] The terminology used in this disclosure is for illustrative purposes only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. An embedded substrate for electronic components, comprising: Glass layer; A through cavity that penetrates the area between the upper and lower surfaces of the glass layer; A blind component is disposed at least partially within the through cavity; Electronic components are disposed at least partially within the through cavity and attached to the upper surface of the blind member; as well as An insulating material covers at least a portion of each of the glass layer, the blind member, and the electronic assembly, and fills at least a portion of the through cavity.

2. The embedded substrate for electronic components according to claim 1, wherein, The side surfaces of each of the blind member and the electronic assembly are spaced apart from the wall surface of the through cavity, and The insulating material fills at least a portion between the side surface of each of the blind member and the electronic assembly and the wall surface of the through cavity.

3. The embedded substrate for electronic components according to claim 1, wherein, The blind component includes a glass block.

4. The embedded substrate for electronic components according to claim 3, wherein, The glass block and the glass layer consist of the same glass.

5. The embedded substrate for electronic components according to claim 1, wherein, The blind component comprises a metal block.

6. The embedded substrate for electronic components according to claim 5, wherein, The metal block includes copper.

7. The embedded substrate for electronic components according to claim 1, wherein, The blind component includes a glass block and a metal block, the metal block being connected to the lower surface of the glass block and the metal block being thinner than the glass block.

8. The embedded substrate for electronic components according to claim 7, wherein, The glass block and the glass layer comprise the same glass, and The metal block includes copper.

9. The embedded substrate for electronic components according to claim 1, wherein, Connection electrodes are provided on the upper surface of the electronic component. The lower surface of the electronic component is attached to the upper surface of the blind member via an adhesive layer.

10. The embedded substrate for electronic components according to claim 9, wherein the embedded substrate for electronic components further comprises: A metal via, penetrating at least a portion between the upper and lower surfaces of the glass layer; A first wiring layer is disposed on the upper surface of the insulating material; A second wiring layer is disposed on the lower surface of the insulating material; A first connection via penetrates at least a portion of the insulating material located above the glass layer and connects at least a portion of the first wiring layer to the metal via; The second connection via penetrates at least a portion of the insulating material located below the glass layer and connects at least a portion of the second wiring layer to the metal via; as well as A third connection via penetrates at least another portion of the insulating material located above the glass layer and connects at least another portion of the first wiring layer to the connection electrode.

11. The embedded substrate for electronic components according to claim 10, wherein, The first and second connecting vias are directly connected to the metal vias, respectively.

12. The embedded substrate for electronic components according to claim 10, further comprising a fourth connection via penetrating at least another portion of the insulating material located below the glass layer, and connecting at least another portion of the second wiring layer to the blind member, and The blind component includes a metal block connected to the fourth connection via.

13. The embedded substrate for electronic components according to claim 10, wherein the embedded substrate for electronic components further comprises: frame; as well as The penetrating portion penetrates the area between the upper and lower surfaces of the frame. Wherein, the glass layer is at least partially disposed within the penetrating portion, and The insulating material also covers at least a portion of the frame and fills at least a portion of the penetrating portion.

14. The embedded substrate for electronic components according to claim 10, further comprising: Multiple first stacked insulating layers are disposed on the upper surface of the insulating material; Multiple first stacked wiring layers are respectively disposed on or within the multiple first stacked insulating layers; Multiple first stacked via layers are respectively disposed within the multiple first stacked insulating layers; Multiple second stacked insulating layers are disposed on the lower surface of the insulating material; Multiple second stacked wiring layers are respectively disposed on or within the multiple second stacked insulating layers; as well as Multiple second stacked via layers are respectively disposed within the multiple second stacked insulating layers.

15. The embedded substrate for electronic components according to claim 14, further comprising: A first passivation layer is disposed on the plurality of first stacked insulating layers and has a plurality of first openings, the plurality of first openings respectively exposing at least a portion of the uppermost first stacked wiring layer among the plurality of first stacked wiring layers; as well as A second passivation layer is disposed on the plurality of second stacked insulating layers and has a plurality of second openings, the plurality of second openings respectively exposing at least a portion of the lowermost second stacked wiring layer among the plurality of second stacked wiring layers.

16. An embedded substrate for electronic components, comprising: Glass layer; A through cavity that penetrates the area between the upper and lower surfaces of the glass layer; A glass block is disposed, at least partially, in the lower side of the through cavity; Electronic components are at least partially disposed in the upper side of the through cavity; as well as An insulating material covers at least a portion of each of the glass layer, the glass block, and the electronic components, and fills at least a portion of the through cavity.

17. The embedded substrate for electronic components according to claim 16, wherein, The glass block and the glass layer consist of the same glass.

18. The embedded substrate for electronic components according to claim 16, wherein, The upper surface of the electronic component is provided with connecting electrodes, and The lower surface of the electronic component is attached to the upper surface of the glass block via an adhesive layer.

19. The embedded substrate for electronic components according to claim 18, wherein, The side surfaces of each of the electronic components, the adhesive layer, and the glass block are spaced apart from the wall surface of the through cavity, and The insulating material fills at least a portion between the side surface of each of the electronic components, the adhesive layer, and the glass block and the wall surface of the through cavity.

20. The embedded substrate for electronic components according to claim 18, wherein, The width of the glass block in the cross-section is wider than the width of the electronic component in the cross-section.

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