Semiconductor structure and method of forming the same

Abstract

This invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first dielectric layer, a first metal layer, and a barrier layer. The first metal layer is disposed on the first dielectric layer. The barrier layer covers the upper surface and side surfaces of the first metal layer. The barrier layer includes a first via located above the first metal layer. Furthermore, the barrier layer includes an intermetallic compound.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a redistribution layer (RDL) in a semiconductor package structure and a method for forming the RDL. Background Technology

[0002] With the increasing demand for smaller devices with more features, package-on-package (PoP) technology is becoming increasingly popular. PoP technology vertically stacks two or more packages and minimizes the trace length between different components, such as the trace length between a controller and a memory device. This provides better electrical performance because shorter interconnects allow for faster signal propagation and reduce noise and crosstalk defects.

[0003] Redistribution layers (RDLs) play a crucial role in packaging technology. They enable fan-out of circuitry and allow lateral communication between chips attached to an interposer. Redistribution layers can redistribute I / O access to different parts of the chip and make it easier to add bumps to the chip.

[0004] While existing semiconductor packages are generally adequate, they are unsatisfactory in various aspects. For example, metal diffusion can occur between conductors in the redistribution layer, which can easily lead to short-circuit failures due to dendrite growth. Furthermore, the fabrication of the redistribution layer requires expensive additives and chemical mechanical polishing (CMP) processes, increasing both cost and complexity. Therefore, further improvements to the redistribution layer structure are needed to provide better reliability. Summary of the Invention

[0005] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, and a barrier layer. The first metal layer is disposed on the first dielectric layer. The barrier layer covers the upper surface and side surfaces of the first metal layer. The barrier layer includes a first via located above the first metal layer. Furthermore, the barrier layer includes an intermetallic compound.

[0006] According to some other embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, and a barrier layer. The first metal layer is disposed on the first dielectric layer. The barrier layer covers a side surface of the first metal layer. The barrier layer includes a via overlapping the first metal layer. Furthermore, the barrier layer includes titanium, palladium, gold, nickel, tin, or a combination thereof.

[0007] According to some other embodiments of the present invention, a method for forming a semiconductor structure is also provided. The method includes forming a first dielectric layer. The method includes forming a first metal layer on the first dielectric layer. The method includes forming an elemental layer covering the first metal layer. The method includes performing an annealing process to form a barrier layer covering the upper and side surfaces of the first metal layer. Furthermore, the barrier layer includes an intermetallic compound formed by the reaction of the first metal layer and the elemental layer. The method also includes forming a first via over the first metal layer.

[0008] The following embodiments are described in detail with reference to the accompanying drawings. Attached Figure Description

[0009] A more comprehensive understanding of the invention can be obtained by reading the following detailed description and examples, and by referring to the accompanying drawings, wherein: Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H These are cross-sectional views of exemplary semiconductor structures at different stages of the manufacturing process according to some embodiments of the present invention; Figure 2A , Figure 2B , Figure 2C These are cross-sectional views of exemplary semiconductor structures at different stages of the manufacturing process according to some embodiments of the present invention; Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 These are cross-sectional views of exemplary electronic devices at different stages of the manufacturing process according to some embodiments of the present invention. Detailed Implementation

[0010] The semiconductor structure and its formation method according to the present invention will be described in detail below. It should be understood that numerous specific details and embodiments are set forth in the following detailed description in order to provide a thorough understanding of the invention. The elements and configurations described in the following detailed description are for the purpose of clearly describing the invention. These embodiments are for illustrative purposes only, and the invention is not limited thereto. Furthermore, different embodiments may use the same and / or corresponding numbers to represent the same and / or corresponding elements in order to clearly describe the invention. However, the use of the same and / or corresponding numbers in different embodiments does not indicate any relationship between the different embodiments.

[0011] It should be understood that relative expressions may be used in the embodiments. For example, "lower," "bottom," "upper," or "top" are used to describe the position of one element relative to another. It should be understood that if the device is flipped, the "lower" element will become the "upper" element. The invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. The drawings are also considered part of the description of the invention. It should be understood that the drawings of the invention may not be drawn to scale. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the invention.

[0012] Furthermore, expressing "the first material layer is disposed on or located on the second material layer" may indicate that the first material layer and the second material layer are in direct contact, or that they are in indirect contact. In the case of indirect contact, one or more intermediate layers may exist between the first and second material layers. However, expressing "the first material layer is directly disposed on or located on the second material layer" implies that the first material layer and the second material layer are in direct contact, and there are no intermediate elements or layers between them.

[0013] Furthermore, it should be understood that ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify an element, do not in themselves imply that the element (or elements) has any prior ordinal number, nor do they indicate the order of one element with another, or the order in which the manufacturing process takes place. These ordinal numbers are used to clearly distinguish an element with a certain name from another element with the same name. The same terms may not be used in the claims and the specification. For example, the first element in the specification may refer to the second element in the claim.

[0014] In the following description, the terms “approximately,” “basically,” and “about” generally mean + / - 10% of the value, or generally + / - 5% of the value, or generally + / - 3% of the value, or generally + / - 2% of the value, or generally + / - 1% of the value, or generally + / - 0.5% of the value. The expression “between the first and second values” means that the range includes the first value, the second value, and other values ​​in between.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should be understood that, in each case, where a term is defined in a commonly used dictionary, it should be interpreted as having a meaning consistent with the relative skill and context of the invention, and should not be interpreted in an idealized or overly formal manner unless so defined.

[0016] According to embodiments of the present invention, a semiconductor structure is provided. This semiconductor structure can be a redistribution layer (RDL) structure. The semiconductor structure includes a barrier layer disposed on the side surface of a metal layer. The barrier layer can reduce metal diffusion between metal layers in the redistribution layer, thereby improving the reliability of the semiconductor structure. Furthermore, through specific configurations of the barrier layer and the dielectric layer, the manufacturing cost and complexity of the semiconductor structure can be reduced.

[0017] Please see Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H These are cross-sectional views of exemplary semiconductor structures 10 at different stages of the manufacturing process according to some embodiments of the present invention. According to some embodiments, additional operations may be provided before, during, and / or after the method of forming the semiconductor structure 10. According to some embodiments, some of the described operations may be replaced or deleted. According to some embodiments, the order of operations may be interchanged. Furthermore, for clarity, some elements of the semiconductor structure 10 may be omitted in the figures, and only some elements are schematically shown. According to some embodiments, additional features may be added to the semiconductor structure 10 described below. According to other embodiments, some features of the semiconductor structure 10 described below may be replaced or omitted.

[0018] like Figure 1A As shown, according to some embodiments, a substrate 102 is provided. The substrate 102 can be used as a carrier substrate. According to some embodiments, the substrate 102 may include a glass carrier substrate, a ceramic carrier substrate, a carrier strip, other suitable structures or combinations thereof, but is not limited thereto.

[0019] Furthermore, a first dielectric layer 104a can be formed on the substrate 102. This first dielectric layer 104a can be made of an organic polymer material. According to some embodiments, the material of the first dielectric layer 104a includes, but is not limited to, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer dielectric materials, or combinations thereof. According to some embodiments, the first dielectric layer 104a is formed by spin coating, chemical vapor deposition (CVD), other suitable processes, or combinations thereof. Chemical vapor deposition processes can include, for example, low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0020] Then, see Figure 1B According to some embodiments, a seed layer 106 can be formed on the first dielectric layer 104a. The seed layer 106 can have a composite structure, for example, comprising a first sublayer 106a and a second sublayer 106b formed on the first sublayer 106a. According to some embodiments, the first sublayer 106a and the second sublayer 106b are respectively a titanium (Ti) layer and a copper (Cu) layer. According to some embodiments, the material of the seed layer 106 may include tantalum (Ta), gold (Au), nickel (Ni), aluminum (Al), other suitable conductive materials, or combinations thereof, but is not limited thereto. According to some embodiments, the seed layer 106 is formed by physical vapor deposition (PVD), electroplating, electroless plating, other suitable processes, or combinations thereof. Physical vapor deposition processes may include, for example, sputtering, evaporation, or pulsed laser deposition.

[0021] Then, a photoresist layer PR can be formed on the seed layer 106. According to some embodiments, the photoresist layer PR is formed by a coating and curing process, a lamination process, other applicable processes, or a combination thereof. Figure 1B As shown, a portion of the photoresist layer PR can be removed to form a patterned photoresist layer PR. The patterned photoresist layer PR can define the outline of the subsequently formed first metal layer 108a. The photoresist layer PR can be a positive or negative photoresist material. According to some embodiments, the photoresist material is patterned by one or more photolithography and / or etching processes to form the patterned photoresist layer PR. According to some embodiments, the photolithography process can include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process can include dry etching or wet etching.

[0022] See Figure 1C A first metal layer 108a is formed on the first dielectric layer 104a and the seed layer 106. Specifically, a patterned photoresist layer PR can be used as a mask to form the first metal layer 108a. According to some embodiments, the material of the first metal layer 108a includes copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), cobalt (Co), tantalum (Ta), ruthenium (Ru), alloys of the above metals, other suitable conductive materials, or combinations thereof, but is not limited thereto. According to some embodiments, the material of the first metal layer 108a includes copper. According to some embodiments, the first metal layer 108a is formed by physical vapor deposition (PVD), electroplating, electroless plating, other applicable processes, or combinations thereof.

[0023] Then, see Figure 1D A portion of the photoresist layer PR and the seed layer 106 can be removed. Specifically, according to some embodiments, the portion of the seed layer 106 covered by the photoresist layer PR is removed together with the photoresist layer PR; while the portion of the seed layer 106 covered by the first metal layer 108a is retained. According to some embodiments, the photoresist layer PR is removed by a wet stripping process, a plasma ashing process, other applicable processes, or a combination thereof.

[0024] refer to Figure 1E An element layer 110e is formed to cover the first metal layer 108a. Specifically, the element layer 110e covers the side surface 108d and the top surface 108t of the first metal layer 108a. According to some embodiments, the element layer 110e is formed conformally on the side surface 108d and the top surface 108t of the first metal layer 108a. According to some embodiments, the element layer 110e is also formed on the side surface of the seed layer 106. According to some embodiments, the material of the element layer 110e includes tin (Sn). According to some embodiments, the element layer 110e is formed by an electroless plating process, other applicable processes, or a combination thereof. According to some embodiments, the thickness T110-1 of the element layer 110e is less than or equal to 0.1 micrometers (μm), for example, it can be 0.01 μm, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, but is not limited thereto. Specifically, the thickness T110-1 of the element layer 110e can be controlled to be less than or equal to 0.1 micrometers, so that the subsequent process of removing the remaining element layer 110e after annealing can be omitted. The process of forming the semiconductor structure can be simplified, and the cost can be reduced.

[0025] Then, refer to Figure 1F An annealing process AP is performed to form a barrier layer 110 covering the upper surface 108t and side surface 108d of the first metal layer 108a. According to some embodiments, the barrier layer 110 may also cover the side surface of the seed layer 106. According to some embodiments, the barrier layer 110 directly contacts the upper surface 108t and side surface 108d of the first metal layer 108a. The barrier layer 110 comprises an intermetallic compound 110C formed by the reaction of the first metal layer 108a and the element layer 110e. According to some embodiments, the barrier layer 110 is composed of the intermetallic compound 110C formed by the reaction of the first metal layer 108a and the element layer 110e. According to some embodiments, the intermetallic compound 110C comprises Cu. x Sn y The copper-tin compound, where x and y are positive integers. Specifically, according to some embodiments, the copper-tin compound includes Cu3Sn, Cu6Sn5, or combinations thereof. In particular, the barrier layer 110 can reduce metal diffusion between metal layers in a semiconductor structure (e.g., a redistribution layer) and can prevent the formation of Kirkendall voids, thereby improving the reliability of the semiconductor structure 10.

[0026] According to some embodiments, the thickness T110-2 of the barrier layer 110 is between 0.05 micrometers and 0.35 micrometers, for example, it can be 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, or 0.3 micrometers, but is not limited thereto. According to some embodiments, the thickness T110-2 of the barrier layer 110 is greater than the thickness T110-1 of the element layer 110e. For example, according to some embodiments, the ratio of the thickness T110-2 of the barrier layer 110 to the thickness T110-1 of the element layer 110e is approximately 3:1.

[0027] Furthermore, according to some embodiments, the annealing process AP is carried out at a temperature between 150°C and 200°C, such as 155°C, 160°C, 165°C, 170°C, 175°C, 180°C, 185°C, 190°C, or 195°C, but is not limited thereto. According to some embodiments, the duration of the annealing process AP is from 1 hour to 8 hours, such as 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours, 4 hours, 4.5 hours, 5 hours, 5.5 hours, 6 hours, 6.5 hours, 7 hours, or 7.5 hours, but is not limited thereto.

[0028] As described above, according to some embodiments, the entire elemental layer 110e reacts with the first metal layer 108a, and no elemental layer 110e remains after the annealing process AP is performed. In this case, the subsequent process of removing the remaining elemental layer 110e can be omitted. However, according to some other embodiments, the thickness T110-1 of the elemental layer 110e formed on the first metal layer 108a (e.g., Figure 1E The steps shown can be greater than 0.1 micrometers, and the method can further include the step of removing the remaining elemental layer 110e after the annealing process. For example, the remaining elemental layer 110e can be removed by a dry etching process or a wet etching process.

[0029] Next, refer to Figure 1G A first via 110V is formed over the first metal layer 108a. Specifically, according to some embodiments, a second dielectric layer 104b is formed on the first dielectric layer 104a to cover the first metal layer 108a, and then a portion of the barrier layer 110 is removed to form the first via 110V over the first metal layer 108a. According to some embodiments, the second dielectric layer 104b may be formed on the first dielectric layer 104a and cover the barrier layer 110, and a portion of the barrier layer 110 contacting the first metal layer 108a may be removed. Furthermore, as... Figure 1G As shown, a portion of the second dielectric layer 104b was also removed to form a second via 104V, and the second via 104V is connected to the first via 110V.

[0030] The second dielectric layer 104b can be made of an organic polymer material. According to some embodiments, the material of the second dielectric layer 104b includes, but is not limited to, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer dielectric materials, or combinations thereof. According to some embodiments, the second dielectric layer 104b is formed by spin coating, chemical vapor deposition (CVD), other applicable processes, or combinations thereof.

[0031] Furthermore, portions of the barrier layer 110 and the second dielectric layer 104b are removed by one or more photolithography and / or etching processes to form the first via 110V and the second via 104V. According to some embodiments, the first via 110V and the second via 104V can be formed in the same step. In particular, since the second dielectric layer 104b is photosensitive, the second via 104V can be formed without providing an additional photoresist mask during the photolithography process.

[0032] According to some embodiments, after forming the first via 110V and the second via 104V, the first portion S1 of the upper surface 108t of the first metal layer 108a overlapping with the first via 110V has a first roughness, and the lower surface 108m of the first metal layer 108a has a second roughness, and the first roughness is different from the second roughness. For example, according to some embodiments, the first roughness is greater than the second roughness. Furthermore, according to some embodiments, the second portion S2 of the upper surface 108t of the first metal layer 108a that does not overlap with the first via 110V has a third roughness, and the first roughness is different from the third roughness. For example, according to some embodiments, the first roughness is greater than the third roughness. Moreover, the aforementioned first portion S1 of the upper surface 108t of the first metal layer 108a refers to the portion of the upper surface 108t that overlaps with the bottom of the first via 110V, for example, in the normal direction of the substrate 102 (e.g., the Z direction in the figure). The second portion S2 of the upper surface 108t of the aforementioned first metal layer 108a refers to the portion of the upper surface 108t that does not overlap with the bottom of the first through hole 110V, for example, in the normal direction of the substrate 102 (e.g., the Z direction in the figure).

[0033] Then, refer to Figure 1HA second metal layer 108b is formed in the first via 110V and the second via 104V. The second metal layer 108b disposed in the first via 110V and the second via 104V can serve as a conductive via electrically connected to the first metal layer 108a. According to some embodiments, a portion of the second metal layer 108b is disposed on the upper surface of the second dielectric layer 104b, and another portion penetrates through the first via 110V and the second via 104V. According to some embodiments, before forming the second metal layer 108b, a seed layer 106 can be formed on the upper surface of the second dielectric layer 104b and extend into the first via 110V and the second via 104V. According to some embodiments, the material of the second metal layer 108b includes copper, titanium, aluminum, tungsten, silver, gold, tin, molybdenum, chromium, nickel, platinum, cobalt, tantalum, ruthenium, alloys of the above metals, other suitable conductive materials, or combinations thereof, but is not limited thereto. According to some embodiments, the material of the second metal layer 108b includes copper. According to some embodiments, the second metal layer 108b is formed by physical vapor deposition (PVD), electroplating, electroless plating, other applicable processes, or combinations thereof.

[0034] like Figure 1H As shown, the semiconductor structure 10 formed by the above method includes a first dielectric layer 104a, a first metal layer 108a, and a barrier layer 110. The first metal layer 108a is disposed on the first dielectric layer 104a. The barrier layer 110 covers the upper surface 108t and side surface 108d of the first metal layer 108a and includes a first via 110V located above the first metal layer 108a. Furthermore, the barrier layer 110 includes an intermetallic compound. According to some embodiments, the intermetallic compound includes a compound having the chemical formula Cu. x Sn y The copper-tin compound, wherein x and y are positive integers. Specifically, according to some embodiments, the copper-tin compound includes Cu3Sn, Cu6Sn5, ... , Or a combination thereof. According to some embodiments, the thickness T110-2 of the barrier layer 110 is between 0.05 micrometers and 0.35 micrometers, for example, it may be 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers or 0.3 micrometers, but is not limited thereto.

[0035] According to some embodiments, the semiconductor structure 10 further includes a second dielectric layer 104b disposed on the first dielectric layer 104a. The second dielectric layer 104b includes a second via 104V connecting the first via 110V. According to some embodiments, the semiconductor structure 10 further includes a second metal layer 108b disposed in the first via 110V and the second via 104V. The second metal layer 108b is electrically connected to the first metal layer 108a through the first via 110V and the second via 104V. According to some embodiments, the semiconductor structure 10 further includes a seed layer 106 disposed between the lower surface 108m of the first dielectric layer 104a and the first metal layer 108a. According to some embodiments, the semiconductor structure 10 further includes a seed layer 106 disposed between the second metal layer 108b and the second dielectric layer 104b.

[0036] According to some embodiments, the first portion S1 of the upper surface 108t of the first metal layer 108a overlapping with the first through hole 110V has a first roughness, and the lower surface 108m of the first metal layer 108a has a second roughness, and the first roughness is different from the second roughness. For example, according to some embodiments, the first roughness is greater than the second roughness. Furthermore, according to some embodiments, the second portion S2 of the upper surface 108t of the first metal layer 108a that does not overlap with the first through hole 110V has a third roughness, and the first roughness is different from the third roughness. For example, according to some embodiments, the first roughness is greater than the third roughness.

[0037] According to some embodiments, the first metal layer 108a and the second metal layer 108b serve as wiring traces for the redistribution layer. Furthermore, according to some embodiments, the width W108a of the first metal layer 108a is less than or equal to 5 micrometers, for example, it can be 4.5 micrometers, 4 micrometers, 3.5 micrometers, 3 micrometers, 2.5 micrometers, 2 micrometers, 1.5 micrometers, or 1 micrometer, but is not limited thereto. According to some embodiments, the gap between adjacent first metal layers 108a is less than or equal to 5 micrometers, for example, it can be 4.5 micrometers, 4 micrometers, 3.5 micrometers, 3 micrometers, 2.5 micrometers, 2 micrometers, 1.5 micrometers, or 1 micrometer, but is not limited thereto.

[0038] Next, please refer to Figures 2A to 2C These figures are cross-sectional views of exemplary semiconductor structures 20 at different stages of a manufacturing process according to some other embodiments of the present invention. It should be understood that components or elements that are identical or similar in the context are designated by the same or similar reference numerals. The materials, manufacturing methods, and functions of these components or elements are the same or similar to those described above, and therefore will not be repeated in the following description.

[0039] Specifically, Figure 2A The steps shown can be continued. Figure 1DThe steps are shown. That is, the method of forming semiconductor structure 20 may include the following steps: providing a substrate 102; forming a first dielectric layer 104a on the substrate 102; forming a seed layer 106 on the first dielectric layer 104a; forming a photoresist layer PR on the seed layer 106; forming a first metal layer 108a on the first dielectric layer 104a; and removing a portion of the photoresist layer PR and the seed layer 106.

[0040] Then, as Figure 2A As shown, in this embodiment, a barrier layer 110 is formed to cover the upper surface 108t and side surface 108d of the first metal layer 108a. The barrier layer 110 can be formed conformally on the side surface 108d and the upper surface 108t of the first metal layer 108a. According to some embodiments, the barrier layer 110 can also be formed on the side surface of the seed layer 106 and the upper surface of the first dielectric layer 104a. In this embodiment, the material of the barrier layer 110 includes titanium (Ti), palladium (Pd), gold (Au), nickel (Ni), tin (Sn), or combinations thereof. In one embodiment, the material of the barrier layer 110 includes titanium. The barrier layer 110 can be formed by physical vapor deposition (PVD), electroplating, electroless plating, other applicable processes, or combinations thereof.

[0041] Then, see Figure 2B The portion of the barrier layer 110 disposed on the upper surface 108t of the first metal layer 108a and the first dielectric layer 104a is removed. The upper surface 108t of the first metal layer 108a can be exposed. In this embodiment, the thickness T110-2 of the barrier layer 110 is between 0.05 micrometers and 0.35 micrometers, for example, it can be 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers or 0.3 micrometers, but is not limited thereto. Furthermore, a dry etching process or a wet etching process can be used to remove the portion of the barrier layer 110 disposed on the upper surface 108t of the first metal layer 108a and the first dielectric layer 104a.

[0042] Next, see Figure 2C A second via 104V is formed above the first metal layer 108a. Specifically, a second dielectric layer 104b can be formed on the first dielectric layer 104a to cover the first metal layer 108a, and then a portion of the second dielectric layer 104b can be removed to form the second via 104V above the first metal layer 108a. In particular, since the second dielectric layer 104b is photosensitive, no additional photoresist mask is required to form the second via 104V during photolithography.

[0043] In this embodiment, after forming the second via 104V, the first portion S1 of the upper surface 108t of the first metal layer 108a overlapping with the second via 104V can have a first roughness, and the lower surface 108m of the first metal layer 108a can have a second roughness. Furthermore, the first roughness can be different from the second roughness. For example, the first roughness can be greater than the second roughness. Additionally, the second portion S2 of the upper surface 108t of the first metal layer 108a that does not overlap with the second via 104V can have a third roughness, and the first roughness can be different from the third roughness. For example, the first roughness can be greater than the third roughness. Furthermore, the aforementioned first portion S1 of the upper surface 108t of the first metal layer 108a refers to the portion of the upper surface 108t that overlaps with the bottom of the second via 104V, for example, in the normal direction of the substrate 102 (e.g., the Z direction in the figure). The second portion S2 of the upper surface 108t of the aforementioned first metal layer 108a refers to the portion of the upper surface 108t that does not overlap with the bottom of the second through hole 104V, for example, in the normal direction of the substrate 102 (e.g., the Z direction in the figure).

[0044] like Figure 2C As shown, a second metal layer 108b is then formed in the second via 104V. The second metal layer 108b disposed in the second via 104V can serve as a conductive via electrically connected to the first metal layer 108a. A portion of the second metal layer 108b can be disposed on the upper surface of the second dielectric layer 104b, and another portion can penetrate the second via 104V. Before forming the second metal layer 108b, a seed layer 106 can be formed on the upper surface of the second dielectric layer 104b and extend into the second via 104V.

[0045] The semiconductor structure 20 formed by the above method includes a first dielectric layer 104a, a first metal layer 108a, and a barrier layer 110. The first metal layer 108a is disposed on the first dielectric layer 104a. The barrier layer 110 covers the side surface 108d of the first metal layer 108a and includes a second via 104V located above the first metal layer 108a. Furthermore, the material of the barrier layer 110 includes titanium (Ti), palladium (Pd), gold (Au), nickel (Ni), tin (Sn), or combinations thereof. According to some embodiments, the thickness T110-2 of the barrier layer 110 is between 0.05 micrometers and 0.35 micrometers, for example, it can be 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, or 0.3 micrometers, but is not limited thereto.

[0046] According to some embodiments, the semiconductor structure 20 further includes a second dielectric layer 104b disposed on the first dielectric layer 104a. The second dielectric layer 104b includes a second via 104V. According to some embodiments, the semiconductor structure 20 further includes a second metal layer 108b disposed in the second via 104V. The second metal layer 108b is electrically connected to the first metal layer 108a through the second via 104V. According to some embodiments, the semiconductor structure 20 further includes a seed layer 106 disposed between the lower surface 108m of the first dielectric layer 104a and the first metal layer 108a. According to some embodiments, the semiconductor structure 20 further includes a seed layer 106 disposed between the second metal layer 108b and the second dielectric layer 104b.

[0047] The first metal layer 108a and the second metal layer 108b can serve as wiring traces for the redistribution layer. Furthermore, according to some embodiments, the width W108a of the first metal layer 108a is less than or equal to 5 micrometers, for example, it can be 4.5 micrometers, 4 micrometers, 3.5 micrometers, 3 micrometers, 2.5 micrometers, 2 micrometers, 1.5 micrometers, or 1 micrometer, but is not limited thereto. According to some embodiments, the gap between adjacent first metal layers 108a is less than or equal to 5 micrometers, for example, it can be 4.5 micrometers, 4 micrometers, 3.5 micrometers, 3 micrometers, 2.5 micrometers, 2 micrometers, 1.5 micrometers, or 1 micrometer, but is not limited thereto.

[0048] According to embodiments of the present invention, the provided method for forming a semiconductor structure can be applied to, for example, wafer-level packaging (WLP) or panel-level packaging (PLP) processes, and can use chip-first or post-chip / RDL-first processes. Furthermore, the semiconductor structure mentioned in this invention can be applied to electronic devices, which may include package-on-package (POP), system-on-chip (SoC), system-in-package (SiP), chip-on-wafer-on-substrate (CoWoS) packaging, system-on-integrated-chip (SoIC), antenna-in-package (AiP), co-packaged optics (CPO), microelectromechanical systems (MEMS), or combinations thereof, but the invention is not limited thereto.

[0049] Figures 3 to 8 These are cross-sectional views of an exemplary electronic device 1 at different stages of the manufacturing process according to some embodiments of the present invention. It should be understood that, for clarity of illustration, some components of the electronic device 1 may be omitted from the figures, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 1 described below.

[0050] Specifically, the electronic device 1 can be formed based on the aforementioned semiconductor structure as a redistribution layer. For example, the electronic device 1 can be applied to a chip-on-wafer-on-substrate (CoWoS) package structure.

[0051] like Figure 3 As shown, a substrate 102 is provided, and a redistribution layer CR is formed on the substrate 102. According to some embodiments, the redistribution layer CR has a structure based on the semiconductor structure 10 described above, but is not limited thereto. The redistribution layer CR may also have a structure based on the semiconductor structure 20 described above. The redistribution layer CR may include a dielectric layer 104 and a plurality of metal layers 108 formed in the dielectric layer 104. The redistribution layer CR includes a barrier layer 110 covering the upper surface 108t and side surfaces 108d of the metal layers 108. The redistribution layer CR may also include a seed layer 106 disposed between the lower surface of the metal layer 108 and the dielectric layer 104. According to some embodiments, a portion of the metal layer 108 may serve as a conductive pad (e.g., under-bump metallization, UBM) for electrical connection to a chip.

[0052] See Figure 4 Multiple electronic units 200 can be provided on the redistribution layer CR. According to some embodiments, the electronic unit 200 may include, but is not limited to, known-good die (KGD), integrated circuit chip (IC), surface mount device (SMD), dummy chip, diode, or other suitable electronic components. Specifically, according to some embodiments, the electronic unit 200 may include a system on a chip (SoC), dynamic random access memory, high-bandwidth memory (HBM), photonic integrated circuit, application-specific integrated circuit, or other logic integrated circuit. According to other embodiments, the electronic unit 200 is of different types. For clarity, Figure 4Different electronic units 200 are designated as electronic units 200-1, 200-2, and 200-3. For example, according to some embodiments, electronic unit 200-1 is a high-bandwidth memory, electronic unit 200-2 is a system-on-a-chip, and electronic unit 200-3 is a dummy chip, but the invention is not limited thereto.

[0053] Furthermore, the electronic unit 200 can be electrically connected to the redistribution layer CR via a plurality of first connecting elements 202. According to some embodiments, the electronic unit 200 includes a plurality of conductive elements 204, which can serve as contact pads, and the conductive elements 204 can be electrically connected to the first connecting elements 202. According to some embodiments, the first connecting elements 202 are disposed between the conductive elements 204 of the electronic unit 200 and the metal layer 108 of the redistribution layer CR. According to some embodiments, the material of the first connecting elements 202 may include tin, silver, lead-free tin, copper, gallium, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the first connecting elements 202 can be bonded to the redistribution layer CR via reflow bonding, fusion bonding, hybrid bonding, metal-to-metal bonding, other applicable processes, or combinations thereof. The electronic unit 200 can therefore be bonded to the redistribution layer CR.

[0054] Reference Figure 5 The first insulating layer 206 can be formed to surround the first connecting element 202 and the conductive element 204, and can be used to fill the gap between the electronic unit 200 and the redistribution layer CR to provide structural support. The first insulating layer 206 can also be disposed on the side surface of the electronic unit 200. According to some embodiments, the first insulating layer 206 can be an encapsulation material or a bottom filler to reduce the impact of water and oxygen in the external environment on the first connecting element 202 and / or the conductive element 204. According to some embodiments, the first insulating layer 206 can include, but is not limited to, molding compounds, epoxy resins, other suitable encapsulation materials, or combinations thereof. According to some embodiments, the first insulating layer 206 can be formed by compression molding, transfer molding, other applicable processes, or combinations thereof. According to some embodiments, the first insulating layer 206 can be molded in a liquid or semi-liquid state and then cured.

[0055] Then, refer to Figure 6A second insulating layer 208 can be formed to surround the first insulating layer 206 and the electronic unit 200. According to some embodiments, the second insulating layer 208 and the first insulating layer 206 can be made of the same or similar materials. The substrate 102 can then be removed, and a plurality of second connecting elements 302 can be formed on the redistribution layer CR. According to some embodiments, the second connecting elements 302 and the first connecting elements 202 are disposed on opposite sides of the redistribution layer CR. According to some embodiments, the second connecting elements 302 can be electrically connected to the metal layer 108 of the redistribution layer CR. According to some embodiments, the material and formation method of the second connecting elements 302 are the same as or similar to those of the first connecting elements 202, and therefore will not be repeated here.

[0056] Next, refer to Figure 7 A second substrate 402 is provided, and the above-described structure can be disposed on the second substrate 402. Specifically, the second connecting element 302 can be disposed between the redistribution layer CR and the second substrate 402. In other words, the redistribution layer CR can serve as an interposer layer. According to some embodiments, the second substrate 402 may also include one or more conductive layers 404. According to some embodiments, the second connecting element 302 can be electrically connected to the conductive layers 404 of the second substrate 402. According to some embodiments, the second substrate 402 may include a redistribution layer, a glass via substrate, a printed circuit board, other suitable substrates, or combinations thereof.

[0057] like Figure 7 As shown, a third insulating layer 304 can be formed to surround the first insulating layer 206, the second insulating layer 208, the redistribution layer CR, and the second connecting element 302. The third insulating layer 304 can be used to fill the gaps between the second connecting elements 302 to provide structural support. According to some embodiments, the third insulating layer 304 and the first insulating layer 206 can be made of the same or similar materials.

[0058] Then, refer to Figure 8 The support element 408 may be formed on the second substrate 402. The support element 408 may have an annular shape in a top view. According to some embodiments, the support element 408 may include a frame, spacers, a sealant, or a combination thereof. The material of the support element 408 may include an insulating material, a conductive material, or other suitable material.

[0059] In addition, such as Figure 8As shown, a plurality of third connection elements 406 may be formed on the second substrate 402. According to some embodiments, the third connection elements 406 and the second connection elements 302 are disposed on opposite sides of the second substrate 402. The third connection elements 406 may be electrically connected to the conductive layer 404 of the second substrate 402. According to some embodiments, the third connection element 406 may include microbumps, controlled-collapse chip connection (C4) bumps, conductive pillars, solder paste, ball grid array (BGA) balls, frame boards, other suitable connection components, or combinations thereof. According to some embodiments, the material of the third connection element 406 may be made of metal, including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, alloys of the above metals, other suitable conductive materials, or combinations thereof, but is not limited thereto.

[0060] In summary, according to embodiments of the present invention, the provided semiconductor structure can be a redistribution layer structure. The semiconductor structure includes a barrier layer disposed on the side surface and / or top surface of the metal layer. The barrier layer can reduce metal diffusion occurring between metal layers in the redistribution layer, thereby improving the reliability of the semiconductor structure. Furthermore, through specific configurations of the barrier layer and the dielectric layer, the manufacturing cost and complexity of the semiconductor structure can also be reduced.

[0061] While the invention has been described by way of example and preferred embodiments, it should be understood that the invention is not limited to the embodiments described. Rather, it is intended to cover various modifications and similar arrangements (as would be understood by those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure, comprising: First dielectric layer; A first metal layer disposed on the first dielectric layer; as well as A barrier layer covering the upper and side surfaces of the first metal layer, and including a first through-hole located above the first metal layer. The barrier layer includes an intermetallic compound.

2. The semiconductor structure of claim 1, further comprising a second dielectric layer disposed on the first dielectric layer, wherein, The second dielectric layer includes a second via that connects to the first via.

3. The semiconductor structure of claim 2, further comprising a second metal layer disposed in the first via and the second via.

4. The semiconductor structure as described in claim 1, wherein, This intermetallic compound includes compounds with the chemical formula Cu. x Sn y A copper-tin compound, where x and y are positive integers.

5. The semiconductor structure as described in claim 4, wherein, The copper-tin compound includes Cu3Sn, Cu6Sn5, or a combination thereof.

6. The semiconductor structure as claimed in claim 1, wherein, The thickness of the barrier layer is between 0.05 micrometers and 0.35 micrometers.

7. The semiconductor structure as claimed in claim 1, wherein, The first portion of the upper surface of the first metal layer that overlaps with the first through hole has a first roughness, and the lower surface of the first metal layer has a second roughness, wherein the first roughness is different from the second roughness.

8. The semiconductor structure as claimed in claim 7, wherein, The first roughness is greater than the second roughness.

9. The semiconductor structure as claimed in claim 7, wherein, The second portion of the upper surface of the first metal layer that does not overlap with the first through hole has a third roughness, and the first roughness is different from the third roughness.

10. A semiconductor structure comprising: First dielectric layer; A first metal layer disposed on the first dielectric layer; as well as A barrier layer covering the side surface of the first metal layer, and including through-holes overlapping the first metal layer. The barrier layer includes titanium, palladium, gold, nickel, tin, or a combination thereof.

11. The semiconductor structure of claim 10, further comprising: A second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer includes the via; and A second metal layer is disposed in the through hole and electrically connected to the first metal layer.

12. The semiconductor structure of claim 10, further comprising a seed layer disposed between the lower surfaces of the first dielectric layer and the first metal layer.

13. The semiconductor structure of claim 10, wherein, The width of the first metal layer is less than or equal to 5 micrometers.

14. A method for forming a semiconductor structure, comprising: Form the first dielectric layer; A first metal layer is formed on the first dielectric layer; Forming an elemental layer covering the first metal layer; An annealing process is performed to form a barrier layer covering the upper and side surfaces of the first metal layer, wherein the barrier layer is an intermetallic compound formed by the reaction of the first metal layer and the element layer; and A first through-hole is formed above the first metal layer.

15. The method for forming a semiconductor structure as described in claim 14, wherein, The thickness of this elemental layer is less than or equal to 0.1 micrometers.

16. The method of forming a semiconductor structure as described in claim 14, wherein, The elemental layer has a thickness greater than 0.1 micrometers, and the method further includes removing the elemental layer remaining after the annealing process.

17. The method of forming a semiconductor structure as described in claim 14, wherein, The steps for forming the first through hole include: A second dielectric layer is formed on the first dielectric layer and covers the first metal layer; and A portion of the barrier layer is removed to form the first through-hole over the first metal layer.

18. The method of forming a semiconductor structure as described in claim 17, further comprising: A portion of the second dielectric layer is removed to form a second via, wherein the second via is connected to the first via; and A second metal layer is formed in the first through hole and the second through hole.

19. The method of forming a semiconductor structure as claimed in claim 14, wherein the elemental layer comprises tin.

20. The method of forming a semiconductor structure as claimed in claim 14, wherein the annealing process is performed at a temperature between 150°C and 200°C.

21. The method for forming a semiconductor structure as described in claim 14, wherein the duration of the annealing process is from 1 hour to 8 hours.

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