Power supply calibration for voltage controlled oscillators

Abstract

The clock generation circuit includes a voltage-controlled oscillator (VCO) comprising a first transistor pair series-coupled between a power rail and ground, a replica transistor pair series-coupled between a reference node and ground, and a current source having an output coupled to the reference node. The current source is coupled to a control signal that determines the amplitude of the current flowing through the replica transistor pair. A voltage regulator has an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. Each transistor in the replica transistor pair is cascaded on the integrated circuit with its corresponding transistor in the first transistor pair and is of the same type as its corresponding transistor in the first transistor pair.

Description

Cross-references to related applications

[0001] This patent application claims priority to pending non-U.S. provisional application No. 18 / 512,617, filed November 17, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates generally to clock generation circuits, and more specifically, to clock generation circuits capable of automatically compensating for process, voltage, or temperature deviations. Background Technology

[0003] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0004] High-speed serial buses offer advantages over parallel communication links when reduced power consumption and a smaller footprint are required, for example, in integrated circuit (IC) devices. In a serial interface, a serializer converts data from parallel words into a serial bit stream, and a deserializer converts the data back into parallel words at the receiver. For example, high-speed bus interfaces can be implemented using peripheral component interconnect high-speed (PCIe) buses, universal serial bus (USB), or serial advanced technology accessory (SATA).

[0005] IC devices may include serializers / deserializers (SERDES) that transmit and receive data over a communication link. In high-speed applications, the timing of SERDES operation can be controlled by a high-speed clock signal. The performance, accuracy, or reliability of SERDES can depend on the frequency of the clock signal, and deviations or other variations in the phase relationship of the clock signal can cause errors in the received or transmitted data. Therefore, there is a continuous need for new technologies to provide reliable, low-power clock generation and calibration circuitry for components used to receive clock signals over high-speed serial links. Summary of the Invention

[0006] Certain aspects of this disclosure relate to integrated circuit (IC) devices that include a bus interface. The bus interface may include clock generation circuitry that automatically adapts to deviations in process, voltage, or temperature affecting transistors in a voltage-controlled oscillator (VCO).

[0007] In various aspects of this disclosure, the clock generation circuit has a VCO (Voltage Control Unit) comprising: a first transistor pair coupled in series between a power rail and ground; a replica transistor pair coupled in series between a reference node and ground; a current source having an output coupled to the reference node and further coupled to a control signal that determines the amplitude of the current flowing through the replica transistor pair; and a voltage regulator having an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. The replica transistor pair is juxtaposed with the first transistor pair on an integrated circuit. Each transistor in the replica transistor pair is of the same type as the corresponding transistor in the first transistor pair.

[0008] In various aspects of this disclosure, a method for generating a clock signal includes: configuring the amplitude of a current supplied by a current source to a pair of replicated transistors through a reference node; and supplying power to the power rails of a VCO using a voltage regulator coupled to the reference node. The voltage regulator can be configured to maintain the power rails at a voltage level defined by the voltage level of the reference node. The VCO includes a first pair of transistors series coupled between the power rails and ground. The replicated transistor pair is series coupled between the reference node and ground and is juxtaposed with the first transistor pair on an integrated circuit. Each transistor in the replicated transistor pair may be of the same type as the corresponding transistor in the first transistor pair.

[0009] In various aspects of this disclosure, the apparatus includes: means for supplying current to a pair of replica transistors; means for configuring the magnitude of the current supplied to the pair of replica transistors; and means for supplying power to a power rail of a VCO. The means for supplying current to the pair of replica transistors includes a current source coupled to the pair of replica transistors at a reference node. The means for supplying power to the power rail of the VCO includes a voltage regulator having an input coupled to the reference node. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. The VCO includes a first pair of transistors series coupled between the power rail and ground. The replica transistor pair includes transistors series coupled between the reference node and ground. The replica transistor pair may be paralleled with the first transistor pair on an integrated circuit. Each transistor in the replica transistor pair is of the same type as the corresponding transistor in the first transistor pair.

[0010] In some respects, the VCO also includes a second pair of transistors series coupled between the power rail and ground. The first pair of transistors may be cross-coupled with the second pair of transistors.

[0011] In some aspects, the first transistor pair includes: an N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and a P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to a power rail and a drain coupled to the first common node. The replicated transistor pair may include: an NMOS transistor having a source coupled to ground and a gate and drain coupled to a second common node; and a PMOS transistor having a source coupled to a reference node and a gate and drain coupled to the second common node.

[0012] In some aspects, the clock generation circuitry includes a comparator having a first input coupled to a voltage reference signal and a second input coupled to a reference node; and a calibration circuit having an input coupled to the output of the comparator and providing a control signal to a current source. The current source may include a current-to-analog converter (IDAC), and the control signal may encode a multi-bit digital value. The calibration circuitry may be configured to determine a process corner characterizing the replicated transistor pair, and to select the maximum and minimum values ​​of the multi-bit digital value based on the process corner. The calibration circuitry provides or configures the voltage reference signal.

[0013] In one respect, changes in manufacturing processes can affect both the replicated transistor pair and the first transistor pair to the same extent.

[0014] In one respect, replicating transistor pairs can track the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair that can be attributed to manufacturing process deviations. Attached Figure Description

[0015] Figure 1 Examples of on-chip systems according to certain aspects of this disclosure are illustrated.

[0016] Figure 2 An example of a device employing interconnect chips is shown.

[0017] Figure 3 An example of a device in which small chips are vertically stacked on a substrate is shown.

[0018] Figure 4 An example of a system employing a multi-channel data communication link is shown.

[0019] Figure 5An example of a high-frequency clock generation circuit that uses a regulator to control the voltage supplied to the power of a voltage-controlled oscillator is shown.

[0020] Figure 6 A first example of a high-frequency clock generation circuit configured according to certain aspects of this disclosure is illustrated.

[0021] Figure 7 A second example of a high-frequency clock generation circuit configured according to certain aspects of this disclosure is illustrated.

[0022] Figure 8 This is a flowchart of a method for generating clock signals according to certain aspects of this disclosure. Detailed Implementation

[0023] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0024] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0025] Data communication links used by system-on-a-chip (SoC) and other integrated circuit (IC) devices to connect processors to modems and other peripherals may operate according to industry or proprietary standards or protocols associated with certain functions or types of devices. According to certain aspects of this disclosure, serial data links may be used to interconnect electronic devices that are sub-components of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similarly functional devices.

[0026] Certain aspects of this disclosure apply to input / output (I / O) circuitry that provides an interface between core circuitry and memory devices. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances as LPDDR. x ,in x This describes the technology generations of LPDDR SDRAM. Later generations of LPDDR SDRAM, designed to operate at higher frequencies, can use lower voltage levels in the core of a SoC or memory device to mitigate the power increase associated with higher operating frequencies.

[0027] The process technologies used to manufacture semiconductor devices, including IC devices, are constantly being improved. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of the circuitry in an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the manufacture of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0028] This document illustrates certain examples of circuits implemented using P-type metal-oxide-semiconductor (PMOS) transistors, N-type metal-oxide-semiconductor (NMOS) transistors, or some combination of NMOS and PMOS transistors. These circuits are provided by way of example only, and it is expected that the concepts disclosed herein can be implemented in circuits using various combinations of NMOS and PMOS transistors.

[0029] Figure 1An example of device 100 is illustrated, in which certain components and interconnects are implemented in a System-on-a-Chip (SoC). The SoC may include or be coupled to a memory interface / bus 126 that may be adapted according to certain aspects of this disclosure. Device 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. Processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible with off-chip signal propagation. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), and allows for more coordinated cooperation between the cores.

[0030] Device 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion and / or wireless data transmission, and for performing other specialized operations, such as decoding high-definition video, video processing, etc. System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on computing devices. System components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0031] The device 100 may also include a serial bus controller 112 (such as a Universal Serial Bus (USB) controller), one or more memory controllers 114, and a centralized resource manager (CRM) 116. The device 100 may also include input / output modules (not illustrated) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0032] Processors 102, 104, 106, and 108 can be interconnected via interconnect / bus module 122 to serial bus controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components. This interconnect / bus module may include reconfigurable logic gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0033] Interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., data transfer in burst mode, block transfer mode, etc.) to set duration, number of operations, number of bytes, etc. In some cases, interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. Memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from memory 124 via memory interface / bus 126.

[0034] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic units, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. In some aspects, the memory 124 may be part of the device 100.

[0035] Figure 2 An example of device 200 is illustrated, in which certain components are implemented using multiple chiplets, which are interconnected using one or more data communication buses. In one example, device 200 may be enclosed within a wearable device, a portable or wearable processing and / or communication device (each of which is referred to herein as a portable communication device or PCD), a sensor, instrument, electrical appliance, and other such devices including one or more ICs. These devices may include mobile phones, tablet computers, handheld computers, portable digital assistants (PDAs), portable game consoles, and other portable electronic devices, such as the illustrated smartwatch 210. A PCD typically contains an integrated circuit or SoC, which includes many components or subsystems designed to work together to deliver functionality to a user. Various SoC subsystems may communicate with each other via one or more on-chip data buses or similar data communication interconnects. A PCD may have multiple SoCs communicating with each other via similar inter-chip interconnects. ICs are typically packaged in an IC package (which may be referred to as a “semiconductor package” or “chip package”). An IC package typically includes a package substrate and one or more IC chips or other electronic modules mounted to the package substrate to provide electrical connectivity to the IC chips. For example, an IC chip within an IC package can be configured as a System-on-a-Chip (SoC). The IC chip is electrically coupled to other IC chips and / or to other components within the IC package via metal wires electrically coupled to the package substrate. The IC chip can also be electrically coupled to other circuitry outside the IC package via electrical connections of external metal interconnects (e.g., solder bumps) of the IC package.

[0036] Chipset technology can be used to address some of the performance, power, and size design requirements of complex SoCs used in certain mobile or wearable devices. Figure 2 The block diagram illustrates certain aspects of a device 200 constructed using chiplets. Device 200 can be configured by selecting combinations of chiplets that implement certain subsystems or different functional elements. In the illustrated example, device 200 includes a main chiplet set 202 enabling device 200 to perform core processing, security, and communication functions. Main chiplet set 202 includes a processor, memory, and one or more modems. The illustrated device 200 also includes a dedicated chiplet set 204, which includes an application processor, display driver, camera interface, and audio controller. In remote sensing devices or electrical appliances, audio-visual components may be omitted and replaced, for example, with an analog-to-digital controller.

[0037] Device 200 may include various processing engines, such as a central processing unit (CPU) with multiple cores, a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), a wireless transceiver unit (also known as a modem), peripherals, a display, and an imaging interface. Each of these subsystems and other functional elements may be implemented as a separate chiplet or as a combination of chiplets. The chiplets included in device 200 may be proprietary or available from various sources. A System-on-a-Chip (SoC) may be constructed from chiplets manufactured at different process nodes and / or operating at different voltages.

[0038] Figure 3 An example of SoC 300 is illustrated, wherein specific chiplets 304, 306, and 308 are vertically stacked on substrate 310. Some chiplets may be included in a stack deployed across the surface of substrate 310, while others may be individually mounted on the surface of the substrate. Solder balls 302 may be used to mount the chiplets on the surface of the substrate, providing electrical and / or thermal coupling between the substrate and the mounted chiplets. Interconnect structures may be formed that enable the chiplets 304, 306, and 308 in the chiplet stack to communicate with each other, with other chiplets mounted on substrate 310, and with input / output structures that connect device 200 to other circuitry, displays, imaging sensors, and other peripherals of the device.

[0039] The use of chiplets can reduce the area size of substrate 310 and increase 3D packaging density. Chipslets can provide complex features and high performance within a smaller form factor, operating at lower power specifications. Furthermore, each chiplet can define multiple power domains, operate at different frequencies, and different chiplets can independently manage power / frequency modes. In some instances, two or more chiplets can operate in mutually exclusive power states. Additionally, in addition to application-defined operating modes, the operating conditions of the SoC also depend on the type, number, and arrangement of the chiplets included on the substrate. It is necessary to consider the power usage of all chiplets in the SoC to ensure compliance with the power budget assigned to the application or device.

[0040] Conventional chiplet-based implementations face limitations, including complex or difficult interconnect routing, localized hotspots caused by wiring congestion due to interconnect architecture, and challenges to signal timing specifications. In some examples, localized hotspots may be caused by wiring congestion, increased feature complexity, and circuit clustering. In some examples, the increased number of isolation clamps required due to logic placement, the number of voltage domains, and reduced planar layout may compromise signal timing specifications. Long wire crossings between chiplets can also lead to wiring congestion.

[0041] Each chiplet within a SoC can perform a specific function or function type, and the configuration of the chiplets can introduce further complexity and challenges for designers. For example, a chiplet may include RF front-end circuitry that generates high-frequency signals up to 5 GHz or higher, and may also include interfaces used by low-frequency power management circuitry. Designers can import previously defined circuit blocks to implement some of the internal functions within the SoC. These circuit blocks may be referred to as macros. Imported circuit blocks for a given process technology can be described, characterized, or defined by a set of masks, hardware description languages, specifications, and test data. Commercially available or proprietary circuit blocks may be referred to as hard macros. Hard macros are tested and validated against a set of design and operational specifications. Hard macros and other circuit blocks typically define multiple power domains.

[0042] Figure 4 An example of a system employing a multi-channel data communication link 480 to couple a modem 400 to a wireless transceiver 440 is illustrated. The data communication link 480 includes data channels 482 and 486 and a clock channel 484, which provide the transmission medium through which signals propagate between the devices. In the illustrated example, the modem 400 transmits data in a first signal to the wireless transceiver 440 via the first data channel 482 and receives data in a second signal transmitted via the second data channel 486. Data signals are transmitted via data channels 482 and 486 according to timing information provided by a bus clock signal 430 transmitted via the clock channel 484.

[0043] Modem 400 may include serializer 402, which is configured to... n Bit-parallel data elements, bytes, or words are converted into a serial data stream for transmission via the first data channel 482 in a transmit data signal 422. The transmit data signal 422 may be pre-adjusted by a pre-equalization circuit (such as the illustrated digital feedforward equalizer (FFE 404)) to combat or compensate for signal distortion attributable to inter-symbol interference (ISI), reflections, and other effects that may limit the bandwidth of the first data channel 482. The pre-adjusted transmit data signal 424 output from the FFE 404 is provided to a driver circuit 406 configured to drive the first data channel 482.

[0044] Modem 400 may include serializer 402, which is configured to... n Bit-parallel data elements, bytes, or words are converted into a serial data stream for transmission in a serialized data signal 422. The serialized data signal 422 may be pre-adjusted by a pre-equalization circuit (such as the illustrated digital feedforward equalizer (FFE 404)) to combat or compensate for signal distortion attributable to inter-symbol interference (ISI), reflections, and other effects that may limit the bandwidth in the first data channel 482. The pre-adjusted data signal 424 output from FFE 404 is provided to a driver circuit 406 configured to generate a differential transmit data signal 426 and transmit it through the first data channel 482. For the purposes of this disclosure, the differential signal comprises two complementary signals phase-shifted relative to each other by 180°.

[0045] Wireless transceiver 440 can be configured to process data signal 460 received via first data channel 482. Data signal 460 can be provided to differential receiver 442, which may include or cooperate with equalization circuitry. In one example, continuous-time linear equalization (CTLE) can be used to compensate for some losses experienced in the first data channel 482. The first data channel 482 can be characterized in some respects as a low-pass filter. In the illustrated example, differential receiver 442 outputs an equalized data signal 462 sampled by limiter 444. Limiter 444 can be implemented using a D flip-flop, etc., and can be configured to capture the signaling state of equalized data signal 462 under the control of an edge in a sampling clock signal 472 generated by clock and data recovery (CDR) circuitry 448. The output of limiter 444 can be provided to deserializer 446, which clocks according to one or more clock signals provided by CDR circuitry 448. CDR circuit 448 can be configured to delay or phase-shift transceiver clock signal 470 to ensure that the edges in sampling clock signal 472 are timed to optimize sampling reliability.

[0046] In the illustrated wireless transceiver 440, the transceiver clock signal 470 is derived from the received bus clock signal 474 from the clock channel 484. A differential receiver 452 coupled to the clock channel 484 can be configured to equalize the received bus clock signal 474, and a duty cycle correction circuit 450 can be used to adjust the duty cycle of the transceiver clock signal 470. The transceiver clock signal 470 is provided to a serializer 454, which is configured to... n Bit-parallel data elements, bytes, or words are converted into a serial data stream for transmission in a serialized data signal 464. The serialized data signal 464 may be pre-adjusted by a pre-equalization circuit (such as the illustrated FFE 456) to counteract or compensate for signal distortion attributable to ISI, reflections, and other effects that may limit the bandwidth in the second data channel 486. The pre-adjusted data signal 466 output from the FFE 456 is provided to a driver circuit 458 configured to generate a differential transmit data signal 468 and transmit this differential transmit data signal through the second data channel 486.

[0047] The illustrated modem 400 can be configured to process a data signal 432 received via a second data channel 486. The data signal 432 can be provided to a differential receiver 420, which may include or cooperate with an equalization circuit. In one example, a CTLE can be used to compensate for some losses experienced in the second data channel 486. The second data channel 486 can be characterized in some respects as a low-pass filter. In the illustrated example, the differential receiver 420 outputs an equalized data signal 428 sampled by a limiter 418. The limiter 418 can be implemented using a D flip-flop, etc., and can be configured to capture the signaling state of the equalized data signal 428 under the control of the edges of the sampling clock signal 434 generated by the CDR circuit 414. The output of the limiter 418 can be provided to a deserializer 416, which clocks according to one or more clock signals provided by the CDR circuit 414. The CDR circuit 414 can be configured to delay or phase-shift the transmitter clock signal to ensure that the edges of the sampling clock signal 434 are timed to optimize sampling reliability.

[0048] The clock generation circuit, including the illustrated PLL 408, can generate multiple clock signals 436a, 436b, and 436c for use by the modem 400. One or more of the clock signals 436a, 436b, and 436c can be a divided version of the basic clock signal generated by the PLL 408. One or more of the clock signals 436a, 436b, and 436c can be phase-shifted relative to the basic clock signal. In one example, the serializer 402 can use the timing provided by the first clock signal 436a to generate a serialized data signal 422. In another example, the bus clock signal 430 transmitted via clock channel 484 can be derived from the second clock signal 436b. In some cases, the duty cycle correction circuit 410 can be used to adjust the duty cycle of the second clock signal 436b and provide input to the driver circuit 412 configured to drive the clock channel 484. In another example, the CDR circuit 448 can generate a sampling clock signal 434 from the third clock signal 436c.

[0049] Communication specifications for high-speed clock signals used in some next-generation chiplets require low jitter and reduced power consumption. In many implementations, voltage-controlled oscillators (VCOs) are used to generate stable, adjustable high-frequency clock signals. The required jitter tolerance can be met by using a VCO that includes a resonant circuit in the feedback loop. In many implementations, the resonant circuit includes an inductor and a capacitor and may be referred to as an energy storage circuit. The term "LC VCO" can be used to refer to a VCO with a resonant circuit that has an inductor (L) and a capacitor (C). Voltage regulators can be used to reduce jitter in the generated high-frequency clock signal by ensuring that the VCO is powered at a stable voltage.

[0050] Figure 5 An example of a clock generation circuit 500 is illustrated, which uses a regulator 502 to control the voltage supplying power to a VCO 504. In the illustrated example, the VCO 504 is powered via a power rail 512, which can be provided for separate use by the VCO 504 and associated circuitry. The power rail 512 has a predefined nominal voltage level measured relative to circuit ground 522. The regulator 502 tracks and adjusts the voltage of the power rail 512 based on a comparison of its output voltage with a reference voltage 510. The reference voltage 510 may be defined by another power rail or voltage reference circuitry. The bias circuit block 530 in the VCO 504 is controlled by a bias input signal 516.

[0051] In the illustrated example, VCO 504 includes an LC resonant circuit 506 that can be configured to generate a desired resonant frequency. The LC resonant circuit 506 has an inductor 524 (L) coupled in parallel with a variable capacitor 526 (C). In one example, the variable capacitor 526 includes multiple switched capacitors that can be coupled in parallel when a corresponding switch is closed. The switches are responsive to a multi-bit control signal 528 that configures the capacitance value provided by the variable capacitor 526, thereby controlling the oscillation frequency of VCO 504 and the frequency of the output clock signal 520.

[0052] When variations in manufacturing process, voltage, or temperature (PVT) affect the operation of transistors and other components in an IC device, configuring regulator 502 to conform the output voltage to a fixed reference voltage 510 can result in suboptimal performance of VCO 504. For example, process variations attributable to the device manufacturing process can affect components of VCO 504, leading to differences in transistor impedance and / or switching speed. These differences affect the resonant frequency and cause different instances of VCO 504 to produce output clock signals 520 with different frequencies under the same voltage and temperature conditions, including at process corners that indicate external constraints on certain process parameters. Process corners can be defined by manufacturing tolerances and can be used to calculate the range of performance levels for all possible combinations of process variations.

[0053] According to certain aspects of this disclosure, a VCO receives power from a low-dropout (LDO) voltage regulator that automatically adjusts its output to accommodate process variations affecting the components of the VCO. The LDO voltage regulator optimizes performance across all process corners. For the purposes of this disclosure, the term "LDO voltage regulator" may refer to a voltage regulator that can generate an output from a power supply at a configured direct current (DC) voltage, which provides input to the voltage regulator at a voltage level close to the output voltage.

[0054] Figure 6 A first example of a high-frequency clock generation circuit 600 configured according to certain aspects of this disclosure is illustrated. The clock generation circuit 600 generates an output that is a function of a process corner associated with one or more devices in a VCO 604. When switch 606 is on and a second switch 608 is off, the output 626 of the regulating circuit 602 is coupled to the power rail 618 of the VCO 604 via switch 606. When the second switch 608 is on and switch 606 is off, the power rail 618 of the VCO 604 is coupled to ground. The regulating circuit 602 includes a voltage regulator 612, which may be a low-dropout (LDO) voltage regulator. The voltage regulator 612 locks the output 626 of the regulating circuit 602 to a reference voltage level defined using a current source 614 and a replica cross-coupled transistor pair 616.

[0055] The current source 614 can be controlled by a control signal (I Control 622) is implemented using a current digital-to-analog converter (IDAC) configuration. In one example, I Control 622 is a multi-bit signal encoded from a multi-bit codeword. The current source 614 outputs a signal with characteristics determined by I... Control The current of the amplitude defined in 622 (I) Ref 640). The output of current source 614 is coupled to the replicated cross-coupled transistor pair 616 via reference node 624. The reference voltage level corresponds to the voltage at reference node 624, which in turn corresponds to the voltage drop across the replicated cross-coupled transistor pair 616.

[0056] In the illustrated example, the replicated cross-coupled transistor pair 616 is a copy of the two cross-coupled transistor pairs 630a and 630b in VCO 604. The replicated cross-coupled transistor pair 616 includes two transistors 620a and 620b connected in series between reference node 624 and ground. The cross-coupled transistor pair 630a includes two transistors 632a and 632b connected in series between the power rail 618 of VCO 604 and ground. The cross-coupled transistor pair 630b includes two transistors 634a and 634b connected in series between the power rail 618 of VCO 604 and ground. For the purposes of this description, when each transistor 620a or 620b is manufactured using the same process as its corresponding transistor 632a or 632b and / or 634a or 634b, and when transistors 620a and 620b are coupled together in the same configuration as transistors 632a and 632b or 634a and 634b, transistors 620a and 620b can be considered as replicas of the cross-coupled transistor pair 630a or 630b in VCO 604. In some specific embodiments, transistors 620a and 620b are constructed on an IC device that is physically close to transistors 632a, 632b or 634a and 634b of at least one cross-coupled transistor pair 630a or 630b in VCO 604. When transistors 620a and 620b are constructed on an IC device that is physically close to transistors 632a, 632b and / or 634a and 634b, or when transistors 620a and 620b are expected to be subjected to variations in the manufacturing process, voltage, and / or temperature (PVT) of transistors 632a, 632b and / or 634a and 634b, transistors 620a and 620b in the replicated cross-coupled transistor pair 616 can be considered to be juxtaposed with transistors 632a, 632b and / or 634a and 634b.

[0057] In the illustrated example, PMOS transistor 620a and NMOS transistor 620b are coupled in series. The gates of transistors 620a and 620b are coupled to their respective drains, and transistors 620a and 620b are turned on. The source of PMOS transistor 620a receives input current from current source 614, and the source of NMOS transistor 620b is coupled to ground. The drains of transistors 620a and 620b are coupled together. The magnitude of the current flowing through transistors 620a and 620b is nominally equal to I. Ref The amplitude is 640. The output terminal 626 of the voltage regulator 612 tracks a reference voltage level corresponding to the voltage at the source of the PMOS transistor 620a.

[0058] The combination and structure of transistors 632a and 632b can be repeated multiple times within VCO 604. k The illustrated VCO 604 includes a first cross-coupled transistor pair 630a, which includes a PMOS transistor 632a coupled in series with an NMOS transistor 632b, such that the drains of transistors 632a and 632b are coupled together. The source of the PMOS transistor 632a is coupled to a power rail 618 and receives input current from a regulation circuit 602, and the source of the NMOS transistor 632b is coupled to ground. The illustrated VCO 604 also includes a second cross-coupled transistor pair 630b, which includes a PMOS transistor 634a coupled in series with an NMOS transistor 634b, such that the drains of transistors 634a and 634b are coupled together. The source of the PMOS transistor 634a is coupled to a power rail 618 and receives input current from a regulation circuit 602, and the source of the NMOS transistor 634b is coupled to ground.

[0059] I Ref The amplitude of 640 can be used to reliably configure the voltage level of power rail 618. It can be expected that the voltage applied to each cross-coupled transistor pair 630a, 630b will be nominally equal to I. Ref A current of 640 flows through each of the cross-coupled transistor pairs 630a and 630b. The VCO 604 includes... k In a typical case of a cross-coupled transistor pair, the current (I) flowing out of the voltage regulator 612 Out 642) can be estimated as The other circuitry in VCO 604 draws current from power rail 618 and can change I... Out The magnitude is 642, but it is not expected to affect I. Ref The relationship between the voltage levels of 640 and power rail 618.

[0060] The replicated cross-coupled transistor pair 616 can track the process corner characterizing an instance of VCO 604. By tracking the process corner of VCO 604, the replicated cross-coupled transistor pair 616 can optimize the power rail voltage level and operating point of VCO 604. It is expected that the voltages across each cross-coupled transistor pair 630a, 630b will be the same as those across the replicated cross-coupled transistor pair 616, even in the presence of PVT deviations. It is expected that PVT deviations, including manufacturing process variations, will affect the cross-coupled transistor pairs 630a, 630b and the replicated cross-coupled transistor pair 616 of VCO 604 to the same extent. Therefore, the replicated transistor pair 616 can track the process corner associated with VCO 604 by adapting to or compensating for variations in the performance or operation of transistor pairs 630a, 630b that are attributable to manufacturing process variations. In one example, for a given I... Ref 640, the voltage across the cross-coupled transistor pair 616 can be expected to be equal to the voltage level of the power rail 618 supplied to the transistor pairs 630a and 630b of VCO 604, regardless of the process corner.

[0061] Using a replicated cross-coupled transistor pair 616 to control the voltage level of the power rail 618 in the VCO 604 can be considered an open-loop system. The voltage on the power rail 618 is determined by the current generated by the current source 614, which can be configured during a calibration process that can account for process variations. Certain aspects of this disclosure relate to providing a calibration system that can limit variations in the voltage level of the power rail 618 in the VCO 604 by imposing certain constraints on the configuration of the current source 614.

[0062] Figure 7 A second example of a high-frequency clock generation circuit 700 configured according to certain aspects of this disclosure is illustrated. The clock generation circuit 700 generates an output that is a function of a process corner associated with one or more devices in a VCO 704. The output 726 of a regulation circuit 702 is coupled to a power rail 718 of the VCO 704. The regulation circuit 702 includes a voltage regulator 712, which may be an LDO voltage regulator. The voltage regulator 712 locks the output 726 of the regulation circuit 702 to a reference voltage level defined using a current source 714 and a replica cross-coupled transistor pair 716.

[0063] The current source 714 can be controlled by a control signal (I Control 744) IDAC configuration is used to implement this. In one example, I Control 744 is a multi-bit signal encoded using a multi-bit codeword. The current source 714 output has a function derived from I... Control The current of the amplitude defined by 744 (I) Ref740). The output of current source 714 is coupled to the replicated cross-coupled transistor pair 716 via reference node 724. The reference voltage level corresponds to the voltage at reference node 724, which in turn corresponds to the voltage drop across the replicated cross-coupled transistor pair 716.

[0064] In the illustrated example, the replicated cross-coupled transistor pair 716 is a replica of the two cross-coupled transistor pairs 730a and 730b in VCO 704. The replicated cross-coupled transistor pair 716 includes two transistors 720a and 720b connected in series between reference node 724 and ground. The cross-coupled transistor pair 730a includes two transistors 732a and 732b connected in series between the power rail 718 of VCO 704 and ground. The cross-coupled transistor pair 730b includes two transistors 734a and 734b connected in series between the power rail 718 of VCO 704 and ground. For the purposes of this description, when each transistor 720a or 720b is manufactured using the same process as its corresponding transistor 732a or 732b and / or 734a or 734b, and when transistors 720a and 720b are coupled together in the same configuration as transistors 732a and 732b or 734a and 734b, transistors 720a and 720b can be considered as replicas of the cross-coupled transistor pair 730a or 730b in VCO 704. In some specific embodiments, transistors 720a and 720b are constructed on an IC device that is physically close to transistors 732a, 732b or 734a and 734b of at least one cross-coupled transistor pair 730a or 730b in VCO 704. When transistors 720a and 720b are constructed on an IC device that is physically close to transistors 732a, 732b and / or 734a and 734b, or when transistors 720a and 720b are expected to be subjected to variations in the manufacturing process, voltage, and / or temperature (PVT) of transistors 732a, 732b and / or 734a and 734b, transistors 720a and 720b in the replicated cross-coupled transistor pair 716 can be considered to be juxtaposed with transistors 732a, 732b and / or 734a and 734b.

[0065] In the illustrated example, PMOS transistor 720a and NMOS transistor 720b are coupled in series. The gates of transistors 720a and 720b are coupled to their respective drains, and transistors 720a and 720b are turned on. The source of PMOS transistor 720a receives input current from current source 714, and the source of NMOS transistor 720b is coupled to ground. The drains of transistors 720a and 720b are coupled together. The magnitude of the current flowing through transistors 720a and 720b is nominally equal to I. RefThe amplitude is 740. The output terminal 726 of the voltage regulator 712 tracks a reference voltage level corresponding to the voltage at the source of the PMOS transistor 720a.

[0066] The combination and structure of transistors 732a and 732b can be repeated multiple times within VCO 704. k The illustrated VCO 704 includes a first cross-coupled transistor pair 730a, which includes a PMOS transistor 732a coupled in series with an NMOS transistor 732b, such that the drains of transistors 732a and 732b are coupled together. The source of the PMOS transistor 732a is coupled to a power rail 718 and receives input current from a regulation circuit 702, and the source of the NMOS transistor 732b is coupled to ground. The illustrated VCO 704 also includes a second cross-coupled transistor pair 730b, which includes a PMOS transistor 734a coupled in series with an NMOS transistor 734b, such that the drains of transistors 734a and 734b are coupled together. The source of the PMOS transistor 734a is coupled to a power rail 718 and receives input current from a regulation circuit 702, and the source of the NMOS transistor 734b is coupled to ground.

[0067] I Ref The amplitude of 740 can be used to reliably configure the voltage level of power rail 718. It can be expected that the voltage applied to each cross-coupled transistor pair 730a, 730b will be nominally equal to I. Ref A current of 740 flows through each of the cross-coupled transistor pairs 730a and 730b. The VCO 704 includes... k In a typical case of a cross-coupled transistor pair, the current (I) flowing out of the voltage regulator 712 Out 742) can be estimated as The other circuitry in the VCO 704 draws current from the power rail 718 and can change I... Out The amplitude is 742, but it is not expected to affect I. Ref The relationship between the voltage levels of 740 and power rail 718.

[0068] The replicated cross-coupled transistor pair 716 can track the process corner characterizing an instance of VCO 704. By tracking the process corner of VCO 704, the replicated cross-coupled transistor pair 716 can optimize the power rail voltage level and operating point of VCO 704. It is expected that the voltages across each cross-coupled transistor pair 730a, 730b will be the same as those across the replicated cross-coupled transistor pair 716, even in the presence of PVT deviations. It is expected that PVT deviations, including manufacturing process variations, will affect transistor pairs 730a, 730b and the replicated cross-coupled transistor pair 716 of VCO 704 to the same extent. Therefore, the replicated transistor pair 716 can track the process corner associated with VCO 704 by adapting to or compensating for variations in the performance or operation of transistor pairs 730a, 730b that are attributable to manufacturing process variations. In one example, for a given I... Ref 740, the voltage across the cross-coupled transistor pair 716 can be expected to be equal to the voltage level of the power rail 718 supplied to the transistor pairs 730a and 730b of VCO 704, regardless of the process corner.

[0069] The calibration system used with the clock generation circuit 700 includes a calibration circuit 722 that configures and controls the current source 714 in the regulation circuit 702. A comparator 708 generates a feedback signal 728 representing the voltage difference between the voltage level of the reference node 724 and the voltage reference 706. The feedback signal 728 is provided to a digital calibration engine 710, which can be configured to generate a current source 714 in the clock generation circuit. Control The codeword provided in 744 to the current source 714. In some specific implementations, the digital calibration engine 710 also configures, calibrates, and / or controls the circuitry providing the voltage reference 706. In one example, the digital calibration engine 710 can be configured to impose a limit on the range of voltage levels of the reference node 724.

[0070] Using a duplicated cross-coupled transistor for process tracking of 616 or 716 can cause the power rail 718 in VCO 704 to have a voltage level that deviates from the specified nominal voltage level by a proportion exceeding the tolerances defined for VCO 704. These deviations can occur when unpredictable, unexpected, or uncommon process deviations occur, which have unpredictable effects on the cross-coupled transistor pairs 730a and 730b of VCO 704 and cause the voltage levels across reference node 724 and cross-coupled transistor pairs 730a and 730b to be unsuitable for circuit operation. In one example, a power rail 718 with an excessively high voltage level may exceed the voltage tolerances of transistors 732a, 732b, 734a, and 734b. In another example, when the power rail 718 has an excessively low voltage level, transistors 732a, 732b, 734a, and 734b may fail to switch states at a predefined operating frequency. In another example, when the power rail 718 has a voltage level exceeding a specified maximum voltage or a voltage below a specified minimum voltage, the switching speed of transistors 732a, 732b, 734a, and 734b can be sufficiently altered to generate a clock signal with an acceptable or undesirable frequency, where the specified maximum or minimum voltage may exceed the voltage tolerance of VCO 704.

[0071] The digital calibration engine 710 can be configured using calibration information accumulated for different IC devices and / or calibration information generated during previous calibrations of one or more clock generation circuits 700. In some implementations, the digital calibration engine 710 can access calibration information from an external source. In some implementations, the digital calibration engine 710 is configured during system integration, configuration, and / or initialization processes. The calibration information may include calibration information obtained for multiple process corners.

[0072] In some specific implementations, the digital calibration engine 710 can be configured to define limitations for operating the current source 714. These limitations may correspond to I... Ref The maximum or minimum current level is 740. In one example, the limit is determined by I... Control The maximum and minimum values ​​of the multi-bit codeword provided to the current source 714 in the 744 are represented. This allows for the representation of I... Control The maximum and minimum values ​​of the multi-bit codeword provided in 744 are indexed to process corner data. In some examples, the calibration engine can determine the process corner of the clock generation circuit 700 based on information obtained from one or more calibration processes. For example, the measured voltage of reference node 724 can be determined by using comparator 708 and compared with the value for I. ControlThe process corner is identified by the difference between different values ​​of voltage reference 706 at 744. The current process corner is identified by the difference between the voltage level configured for voltage reference 706 detected by comparator 708 and the corresponding measurement of the voltage at reference node 724 obtained for one or more codewords. The identified process corner can be used to select I. Control The upper and lower boundaries of the multi-bit codewords provided in 744.

[0073] Clock generation circuit 600 or 700 can automatically adjust the output of voltage regulator 612 or 712 according to the process corner in VCO 604 or 704. A duplicate cross-coupled transistor pair 616 or 716 can be used to identify the process corner in VCO 604 or 704. Controlling the output of voltage regulator 612 or 712 in this way optimizes the power delivered to VCO 604 or 704, regardless of the process or process corner. VCO 604 and 704 can be used without bias circuit block 530 included in VCO 504. Figure 5 This operates under the condition of the associated bias input signal 516 as illustrated. Relative to... Figure 5 The removal of bias circuit block 530 from VCO 504, as illustrated, can reduce the power consumption of VCOs 604 and 704. Compared to... Figure 5 The removal of bias circuit block 530 in the illustrated VCO 504 also reduces phase noise in VCOs 604 and 704. This improved phase noise performance enables VCOs 604 and 704 to support [significantly different phase noise levels]. Figure 5 The VCO 504 illustrated operates at a higher frequency. In one example, the power consumption of VCOs 604 and 704 is reduced by more than 30%, and the phase noise is reduced by more than 6dB. The simplification and optimization of VCOs 604 and 704 can reduce the jitter of the output clock signals 650 and 750 generated by VCOs 604 and 704.

[0074] Each of VCOs 604 and 704 includes LC resonant circuits 636 and 736, which can be configured to generate a desired resonant frequency. LC resonant circuits 636 and 736 can correspond to... Figure 5 The LC resonant circuit 506 illustrated herein can similarly respond to the corresponding multi-bit control signals 638, 738, which can control the oscillation frequency of VCO 604, 704 and the frequency of the output clock signals 650, 750 by configuring variable capacitors in the LC resonant circuits 636, 736.

[0075] In one aspect of this disclosure, the use of current sources 614, 714 and replicated cross-coupled transistor pairs 616, 716 as a tracking mechanism enables the supply voltage provided on the power rails 618, 718 of VCOs 604, 704 to have an optimal voltage for operating VCOs 604, 704. In one example, VCOs 604, 704 require and receive higher voltage power for process corners characterized by transistors slower than nominal transistors. In another example, VCOs 604, 704 receive lower voltage power for process corners characterized by transistors faster than nominal transistors.

[0076] Figure 8 This is a flowchart 800 of a method for generating a clock signal according to certain aspects of this disclosure. In some examples, the method includes supplying power to the power rail of the VCO using an LDO voltage regulator. In some cases, the method may be implemented or involve the use of one or more processors or controllers.

[0077] At block 802 of the illustrated method, the magnitude of the current supplied by the current source to the replica transistor pair can be configured. The replica transistor pair can be coupled to the current source via a reference node. At block 804 of the illustrated method, a voltage regulator having an input coupled to the reference node can be used to supply power to the power rail of the VCO. The voltage regulator can be configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. The VCO may include a first transistor pair coupled in series between the power rail and ground. The replica transistor pair can be coupled in series between the reference node and ground. The replica transistor pair can be paralleled on the IC with the first transistor pair. Each transistor in the replica transistor pair can be of the same type as the corresponding transistor in the first transistor pair.

[0078] In some implementations, the VCO also includes a second pair of transistors series coupled between the power rail and ground. The first pair of transistors may be cross-coupled with the second pair of transistors. In one example of cross-coupling, the gate of each transistor in the first pair is coupled to the drain of two transistors in the second pair, and the gate of each transistor in the second pair is coupled to the drain of two transistors in the first pair.

[0079] In some implementations, the first transistor pair includes an NMOS transistor and a PMOS transistor. In one example, the NMOS transistor has a source coupled to ground and a drain coupled to a first common node, and the PMOS transistor has a source coupled to a power rail and a drain coupled to the first common node. In this example, the replicated transistor pair also includes an NMOS transistor and a PMOS transistor. The NMOS transistor has a source coupled to ground and a gate and drain coupled to a second common node, and the PMOS transistor has a source coupled to a reference node and a gate and drain coupled to the second common node. In another example, the PMOS transistor in the first transistor pair has a source coupled to ground and a drain coupled to the first common node, and the NMOS transistor in the first transistor pair has a source coupled to a power rail and a drain coupled to the first common node, while the NMOS transistor in the replicated transistor pair has a source coupled to ground and a gate and drain coupled to the second common node, and the PMOS transistor in the replicated transistor pair has a source coupled to a reference node and a gate and drain coupled to the second common node.

[0080] In some implementations, a voltage reference signal can be compared with the voltage level of a reference node. In some cases, the amplitude of the current supplied by a current source can be configured using the comparison result of the voltage reference signal and the voltage level of the reference node. In some cases, the amplitude of the current supplied by a current source can be calibrated using the comparison result of the voltage reference signal and the voltage level of the reference node. The current source can be implemented using an IDAC responsive to a multi-bit digital code. The maximum and minimum code values ​​for the multi-bit digital code can be selected based on the process angle characterizing the replica transistor pair. The process angle can be determined during the calibration process, which compares the voltage level of the reference node with the voltage reference signal when the voltage reference signal changes and / or when the value of the multi-bit digital code voltage changes. In some implementations, the voltage reference signal is configured based on the determined process angle.

[0081] Manufacturing process variations can affect both the replicated transistor pair and the first transistor pair to the same extent. The replicated transistor pair can track the manufacturing process angle associated with the VCO by compensating for changes in the performance or operation of the first transistor pair attributable to manufacturing process deviations.

[0082] Figure 8The methods illustrated herein can be implemented in an IC device. In one example, the IC device includes a System-on-a-Chip (SoC). In another example, the IC device includes one of a plurality of semiconductor dies mounted on a substrate. In some cases, the IC device can be implemented as a chiplet. The IC device may include a bus interface. The bus interface may include clock generation circuitry including a VCO, a pair of replicated transistors, a current source, and a voltage regulator. The VCO may include a first pair of transistors, wherein the transistors are coupled in series between a power rail and ground. The transistors in the replicated transistor pair may be coupled in series between a reference node and ground. The replicated transistor pair may be juxtaposed on the IC device with the first pair of transistors. Each transistor in the replicated transistor pair may be manufactured as the same type as the corresponding transistor in the first pair of transistors. A replicated transistor pair may be considered to be juxtaposed on the IC device with the first pair of transistors when both pairs of transistors are located in a sufficiently small area of ​​the IC such that it is expected that the transistors in both pairs of transistors will be affected by any deviations in the manufacturing process in substantially the same manner.

[0083] The current source has an output coupled to the reference node. The current source may also be coupled to a control signal that determines the magnitude of the current flowing through the replica transistor pair and / or through the reference node. In some examples, the voltage regulator is an LDO voltage regulator. The voltage regulator is coupled to the reference node and has an output coupled to the power rail. The voltage regulator can be configured to maintain the power rail at a voltage level defined by the voltage level of the reference node.

[0084] In some implementations, the VCO also includes a second pair of transistors series coupled between the power rail and ground. The first pair of transistors may be cross-coupled with the second pair of transistors. In one example of cross-coupling, the gate of each transistor in the first pair is coupled to the drain of two transistors in the second pair, and the gate of each transistor in the second pair is coupled to the drain of two transistors in the first pair.

[0085] In some implementations, the first transistor pair includes an NMOS transistor and a PMOS transistor. In one example, the NMOS transistor has a source coupled to ground and a drain coupled to a first common node, and the PMOS transistor has a source coupled to a power rail and a drain coupled to the first common node. In this example, the replicated transistor pair also includes an NMOS transistor and a PMOS transistor. The NMOS transistor has a source coupled to ground and a gate and drain coupled to a second common node, and the PMOS transistor has a source coupled to a reference node and a gate and drain coupled to the second common node. In another example, the PMOS transistor in the first transistor pair has a source coupled to ground and a drain coupled to the first common node, and the NMOS transistor in the first transistor pair has a source coupled to a power rail and a drain coupled to the first common node, while the NMOS transistor in the replicated transistor pair has a source coupled to ground and a gate and drain coupled to the second common node, and the PMOS transistor in the replicated transistor pair has a source coupled to a reference node and a gate and drain coupled to the second common node.

[0086] The clock generation circuit may also include a comparator and a calibration circuit. The comparator may have a first input coupled to a voltage reference signal and a second input coupled to a reference node. The calibration circuit may have an input coupled to the output of the comparator and provide a control signal to a current source. The current source may be included in the IDAC, and the control signal may encode a multi-bit digital value controlling the output of the IDAC. The calibration circuit may be configured to determine a process corner characterizing the replicated transistor pair, and to select the maximum and minimum values ​​of the multi-bit digital value based on the process corner. The calibration circuit may provide or configure the voltage reference signal.

[0087] Typically, manufacturing process variations affect both the replicated transistor pair and the first transistor pair to the same extent. The replicated transistor pair can track the manufacturing process angle associated with the VCO by compensating for changes in the performance or operation of the first transistor pair attributable to manufacturing process variations.

[0088] Some specific implementation examples are described in the following numbered clauses: 1. A clock generation circuit comprising: a voltage-controlled oscillator (VCO) including a first transistor pair series coupled between a power rail and ground; a replica transistor pair series coupled between a reference node and ground, and disposed on an integrated circuit alongside the first transistor pair, each transistor in the replica transistor pair having the same type as a corresponding transistor in the first transistor pair; a current source having an output coupled to the reference node, the current source also being coupled to a control signal determining the amplitude of a current flowing through the replica transistor pair; and a voltage regulator having an input coupled to the reference node and an output coupled to the power rail, the voltage regulator being configured to maintain the power rail at a voltage level defined by a voltage level of the reference node. 2. The clock generation circuit according to Clause 1, wherein the VCO further comprises: a second transistor pair, the second transistor pair being coupled in series between the power rail and ground, wherein the first transistor pair is cross-coupled with the second transistor pair. 3. The clock generation circuit according to Clause 1 or Clause 2, wherein the first transistor pair comprises: an N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and a P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node. 4. A clock generation circuit according to any one of clauses 1 to 3, wherein the replica transistor pair comprises: an NMOS transistor having a source coupled to ground and a gate and drain coupled to a second common node; and a PMOS transistor having a source coupled to the reference node and a gate and drain coupled to the second common node. 5. The clock generation circuit according to Clause 1, further comprising: a comparator having a first input coupled to a voltage reference signal and a second input coupled to the reference node; and a calibration circuit having an input coupled to the output of the comparator and providing the control signal to the current source. 6. The clock generation circuit according to Clause 5, wherein the current source includes a current digital-to-analog converter (IDAC), and the control signal encodes a multi-bit digital value. 7. The clock generation circuit according to Clause 6, wherein the calibration circuit is configured to: determine a process angle characterizing the replicated transistor pair; and select a maximum and minimum value of the multi-bit digital value based on the process angle. 8. A clock generation circuit according to any one of clauses 5 to 7, wherein the calibration circuit provides or configures the voltage reference signal. 9. The clock generation circuit according to any one of clauses 1 to 8, wherein variations in manufacturing process affect the replicated transistor pair and the first transistor pair to the same extent. 10. A clock generation circuit according to any one of clauses 1 to 9, wherein the replicated transistor pair tracks the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair attributable to manufacturing process deviations. 11. A method for generating a clock signal, the method comprising: configuring the amplitude of a current supplied by a current source to a pair of replicated transistors through a reference node; and supplying power to a power rail of a voltage-controlled oscillator (VCO) using a voltage regulator having an input coupled to the reference node, the voltage regulator being configured to maintain the power rail at a voltage level defined by a voltage level of the reference node, wherein the VCO includes a first pair of transistors series coupled between the power rail and ground, wherein the replicated pair of transistors is series coupled between the reference node and ground and is co-located on an integrated circuit with the first pair of transistors, and wherein each transistor in the replicated pair of transistors has the same type as a corresponding transistor in the first pair of transistors. 12. The method according to Clause 11, wherein the VCO further comprises a second pair of transistors coupled in series between the power rail and ground, and wherein the first pair of transistors is cross-coupled with the second pair of transistors. 13. The method according to Clause 11 or Clause 12, wherein the first transistor pair comprises: an N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and a P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node. 14. The method according to any one of claims 11 to 13, wherein the replicated transistor pair comprises: an NMOS transistor having a source coupled to ground and a gate and a drain coupled to a second common node; and a PMOS transistor having a source coupled to the reference node and a gate and a drain coupled to the second common node. 15. The method according to any one of Clauses 11 to 14, the method further comprising: comparing a voltage reference signal with a voltage level of the reference node; and using the result of comparing the voltage reference signal with the voltage level of the reference node to configure the amplitude of the current provided by the current source. 16. The method according to any one of Clauses 11 to 15, the method further comprising: comparing a voltage reference signal with a voltage level of the reference node; and using the result of comparing the voltage reference signal with the voltage level of the reference node to calibrate the amplitude of the current provided by the current source. 17. The method according to Clause 16, wherein the current source includes a current digital-to-analog converter (IDAC) responsive to a multi-digit code. 18. The method according to Clause 17, the method further comprising: determining a process angle characterizing the replicated transistor pair; and selecting a maximum and minimum value of the multi-bit code based on the process angle. 19. The method according to Clause 18, the method further comprising: configuring the voltage reference signal based on the process angle. 20. The method according to any one of clauses 11 to 19, wherein variations in the manufacturing process affect the replicated transistor pair and the first transistor pair to the same extent. 21. The method according to any one of clauses 11 to 20, wherein the replicated transistor pair tracks the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair attributable to manufacturing process deviations. 22. An apparatus comprising: means for supplying current to a pair of replica transistors, the means including a current source coupled to the pair of replica transistors at a reference node; means for configuring the amplitude of the current supplied to the pair of replica transistors; and means for supplying power to a power rail of a voltage-controlled oscillator (VCO), the means including a voltage regulator having an input coupled to the reference node, the voltage regulator being configured to maintain the power rail at a voltage level defined by a voltage level of the reference node, wherein the VCO includes a first pair of transistors series coupled between the power rail and ground, wherein the replica transistor pair includes a transistor series coupled between the reference node and ground, wherein the replica transistor pair is juxtaposed with the first pair of transistors on an integrated circuit, and wherein each transistor in the replica transistor pair has the same type as a corresponding transistor in the first pair of transistors. 23. The apparatus according to Clause 22, wherein the VCO further comprises a second pair of transistors coupled in series between the power rail and ground, and wherein the first pair of transistors is cross-coupled with the second pair of transistors. 24. The apparatus according to Clause 22 or Clause 23, wherein the first transistor pair comprises: an N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and a P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node. 25. The apparatus according to any one of claims 22 to 24, wherein the replicating transistor pair comprises: an NMOS transistor having a source coupled to ground and a gate and a drain coupled to a second common node; and a PMOS transistor having a source coupled to the reference node and a gate and a drain coupled to the second common node. 26. The apparatus according to any one of clauses 22 to 25, wherein the component for configuring the amplitude of the current is configured to: calibrate the current source by comparing a voltage reference signal with the voltage level of the reference node using a comparator; and configure the amplitude of the current based on the result of comparing the voltage reference signal with the voltage level of the reference node. 27. The apparatus according to Clause 26, wherein the current source includes a current digital-to-analog converter (IDAC) that responds to a multi-digital value. 28. The apparatus according to Clause 27, wherein the component for configuring the amplitude of the current is further configured to: determine a process angle characterizing the replicated transistor pair; and select a maximum and a minimum value of the multi-digit value based on the process angle. 29. The apparatus according to any one of clauses 26 to 28, wherein the component for calibrating the current source is further configured to: calibrate or configure the voltage reference signal. 30. The apparatus according to any one of clauses 22 to 29, wherein variations in the manufacturing process affect the replicated transistor pair and the first transistor pair to the same extent. 31. The apparatus according to any one of clauses 22 to 30, wherein the replicated transistor pair tracks the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair attributable to manufacturing process deviations.

[0089] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0090] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language of the claims, wherein an element referred to in the singular is not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. No claim element should be construed as a component plus a function unless the element is explicitly stated using the phrase “component for…”.

Claims

1. A clock generation circuit, the clock generation circuit comprising: A voltage-controlled oscillator (VCO) comprising a first pair of transistors coupled in series between a power rail and ground; A pair of replicated transistors is coupled in series between a reference node and ground and is placed on an integrated circuit alongside the first pair of transistors, wherein each transistor in the replicated pair is of the same type as the corresponding transistor in the first pair of transistors. A current source having an output coupled to the reference node; and A voltage regulator having an input coupled to the reference node and an output coupled to the power rail, the voltage regulator being configured to maintain the power rail at a voltage level defined by the voltage level of the reference node.

2. The clock generation circuit according to claim 1, wherein the VCO further comprises: A second transistor pair, which is coupled in series between the power rail and ground, wherein the first transistor pair is cross-coupled with the second transistor pair.

3. The clock generation circuit according to claim 1, wherein the first transistor pair comprises: An N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and A P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node.

4. The clock generation circuit of claim 1, wherein the replicated transistor pair comprises: An NMOS transistor having a source coupled to ground and a gate and drain coupled at a second common node; and A PMOS transistor having a source coupled to the reference node and a gate and drain coupled to the second common node.

5. The clock generation circuit according to claim 1, further comprising: A comparator having a first input coupled to a voltage reference signal and a second input coupled to the reference node; and A calibration circuit having an input coupled to the output of the comparator and configured to control the current source.

6. The clock generation circuit of claim 5, wherein the current source includes a current digital-to-analog converter (IDAC) and is coupled to a control signal that encodes a multi-bit digital value determining the amplitude of the current flowing through the replica transistor pair.

7. The clock generation circuit of claim 6, wherein the calibration circuit is configured to: Determine the process angle characterizing the replicated transistor pair; and The maximum and minimum values ​​of the multi-digit number are selected based on the process angle.

8. The clock generation circuit of claim 5, wherein the calibration circuit provides or configures the voltage reference signal.

9. The clock generation circuit of claim 1, wherein manufacturing process variations affect the replicated transistor pair and the first transistor pair to the same extent.

10. The clock generation circuit of claim 1, wherein the replicated transistor pair tracks the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair attributable to manufacturing process deviations.

11. A method for generating a clock signal, the method comprising: Configure the amplitude of the current supplied to the replicated transistor pair by the current source through the reference node; as well as Power is supplied to the power rail of the voltage-controlled oscillator (VCO) using a voltage regulator having an input coupled to the reference node, the voltage regulator being configured to maintain the power rail at the voltage level defined by the voltage level of the reference node. The VCO includes a first pair of transistors series coupled between the power rail and ground. The replicated transistor pair is coupled in series between the reference node and ground, and is placed alongside the first transistor pair on the integrated circuit. Each transistor in the replicated transistor pair is of the same type as the corresponding transistor in the first transistor pair.

12. The method of claim 11, wherein the VCO further comprises a second pair of transistors, the second pair of transistors being coupled in series between the power rail and ground, and wherein the first pair of transistors is cross-coupled with the second pair of transistors.

13. The method of claim 11, wherein the first transistor pair comprises: An N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and A P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node.

14. The method of claim 11, wherein the replicated transistor pair comprises: An NMOS transistor having a source coupled to ground and a gate and drain coupled at a second common node; and A PMOS transistor having a source coupled to the reference node and a gate and drain coupled to the second common node.

15. The method of claim 11, further comprising: The voltage reference signal is compared with the voltage level of the reference node; as well as The amplitude of the current supplied by the current source is configured using the result of comparing the voltage reference signal with the voltage level of the reference node.

16. The method of claim 11, further comprising: The voltage reference signal is compared with the voltage level of the reference node; as well as The amplitude of the current supplied by the current source is calibrated using the result of comparing the voltage reference signal with the voltage level of the reference node.

17. The method of claim 16, wherein the current source comprises a current digital-to-analog converter (IDAC) responsive to a multi-bit digital code.

18. The method of claim 17, further comprising: Determine the process corner that characterizes the replicated transistor pair; as well as The maximum and minimum values ​​of the multi-digit code are selected based on the process angle.

19. The method according to claim 18, further comprising: The voltage reference signal is configured based on the process angle.

20. The method of claim 11, wherein the manufacturing process variation affects the replicated transistor pair and the first transistor pair to the same extent.

21. An apparatus comprising: Components for supplying current to the replicated transistor pair, the components including a current source coupled to the replicated transistor pair at a reference node; Components for configuring the amplitude of the current supplied to the pair of replica transistors; and Components for supplying power to the power rail of a voltage-controlled oscillator (VCO), the components including a voltage regulator having an input coupled to the reference node, the voltage regulator being configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. The VCO includes a first pair of transistors series coupled between the power rail and ground. The replicated transistor pair includes a transistor series coupled between the reference node and ground, and the replicated transistor pair is disposed on the integrated circuit alongside the first transistor pair. Each transistor in the replicated transistor pair is of the same type as the corresponding transistor in the first transistor pair.

22. The apparatus of claim 21, wherein the VCO further comprises a second pair of transistors, the second pair of transistors being coupled in series between the power rail and ground, and wherein the first pair of transistors is cross-coupled with the second pair of transistors.

23. The apparatus of claim 21, wherein the first transistor pair comprises: An N-type metal-oxide-semiconductor (NMOS) transistor having a source coupled to ground and a drain coupled to a first common node; and A P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the power rail and a drain coupled to the first common node.

24. The apparatus of claim 21, wherein the replicated transistor pair comprises: An NMOS transistor having a source coupled to ground and a gate and drain coupled at a second common node; as well as A PMOS transistor having a source coupled to the reference node and a gate and drain coupled to the second common node.

25. The apparatus of claim 21, wherein the component for configuring the amplitude of the current is configured to: The current source is calibrated by comparing the voltage reference signal with the voltage level of the reference node using a comparator; and The magnitude of the current is configured based on the result of comparing the voltage reference signal with the voltage level of the reference node.

26. The apparatus of claim 25, wherein the current source comprises a current digital-to-analog converter (IDAC) that responds to a multi-digital value.

27. The apparatus of claim 26, wherein the component for configuring the amplitude of the current is further configured to: Determine the process angle characterizing the replicated transistor pair; and The maximum and minimum values ​​of the multi-digit number are selected based on the process angle.

28. The apparatus of claim 25, wherein the component for configuring the amplitude of the current is further configured to calibrate or configure the voltage reference signal.

29. The apparatus of claim 21, wherein variations in the manufacturing process affect the replicated transistor pair and the first transistor pair to the same extent.

30. The apparatus of claim 21, wherein the replicated transistor pair tracks the manufacturing process angle associated with the VCO by compensating for variations in the performance or operation of the first transistor pair attributable to manufacturing process deviations.

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