Display panel and display device

Abstract

A display panel and a display device are disclosed. The display panel includes: a substrate, a plurality of pixel driving circuit groups, a plurality of first power lines, an electrode layer, and a pixel defining layer. The plurality of pixel driving circuit groups are arrayed along a first direction and a second direction, the first direction and the second direction intersecting. Each pixel driving circuit group includes two adjacent pixel driving circuits along the first direction, and the orthographic projections of the two pixel driving circuits in the same pixel driving circuit group onto the substrate are at least partially mirror-symmetrical. The orthographic projections of the first power lines onto the substrate extend along the second direction, and the first power lines and pixel driving circuits are correspondingly arranged. The first power lines are used to provide power signals to their corresponding pixel driving circuits. Each first power line includes a first extension segment. In the same pixel driving circuit group, the first extension segments of the two first power lines corresponding to two pixel driving circuits are connected, and the two connected first extension segments form a conductive block (61). A missing portion is formed on the conductive block (61). Electrodes... The layer includes multiple electrode portions, each electrode portion including a body portion, the body portion being used to form the first electrode of the light-emitting unit; a pixel defining layer is located on the side of the electrode layer away from the substrate, multiple pixel openings are formed on the pixel defining layer, the pixel openings and the body portions are correspondingly disposed, the orthographic projection of the body portion on the substrate and the orthographic projection of its corresponding pixel opening on the substrate coincide; the multiple body portions include a first body portion and a second body portion, the orthographic projection of the first body portion on the substrate and the orthographic projection of the conductive layer where the first power line is located on the substrate partially overlap and partially do not overlap; the orthographic projection of the second body portion on the substrate and the orthographic projection of the conductive block on the substrate partially overlap, and the orthographic projection of the second body portion on the substrate and the orthographic projection of the missing portion on the substrate partially overlap.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. BACKGROUND

[0002] In the related art, the anodes of the red light emitting unit and the blue light emitting unit and the anode of the green light emitting unit have different flatness, thereby causing the display panel to have color cast problem.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel comprises:

[0006] a substrate substrate;

[0007] a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction, the first direction and the second direction intersect, the pixel driving circuit group comprises two pixel driving circuits adjacent in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged in orthographic projection on the substrate substrate;

[0008] a plurality of first power lines, the orthographic projection of the first power lines on the substrate substrate extends along the second direction, the first power lines and the pixel driving circuits are correspondingly arranged, and the first power lines are configured to provide power signals to the pixel driving circuits corresponding thereto;

[0009] the first power lines comprise first extension segments, in the same pixel driving circuit group, the first extension segments in two first power lines corresponding to two pixel driving circuits are connected, the connected two first extension segments form a conductive block, and the conductive block has a missing part;

[0010] an electrode layer comprising a plurality of electrode parts, the electrode part comprises a body part, and the body part is configured to form a first electrode of a light emitting unit;

[0011] a pixel definition layer located on a side of the electrode layer away from the substrate substrate, the pixel definition layer has a plurality of pixel openings formed thereon, the pixel openings and the body parts are correspondingly arranged, and the orthographic projection of the body part on the substrate substrate and the orthographic projection of the pixel opening corresponding thereto on the substrate substrate are coincident;

[0012] The plurality of body portions include a first body portion and a second body portion, wherein the orthographic projection of the first body portion on the substrate and the orthographic projection of the conductive layer containing the first power line on the substrate partially overlap and partially do not overlap;

[0013] The orthographic projection of the second body portion on the substrate and the orthographic projection of the conductive block on the substrate overlap, and the orthographic projection of the second body portion on the substrate and the orthographic projection of the missing portion on the substrate overlap.

[0014] In one exemplary embodiment of this disclosure, the missing portion includes a first notch and a second notch, the first notch and the second notch being located on both sides of the conductive block in the first direction;

[0015] The two ends of the orthographic projection of the second body portion on the substrate in the second direction at least partially overlap with the orthographic projections of the first notch and the second notch on the substrate.

[0016] In an exemplary embodiment of this disclosure, the second body portion is composed of a first sub-body portion and a second sub-body portion. The dividing line between the orthographic projection of the first sub-body portion on the substrate and the orthographic projection of the second sub-body portion on the substrate extends straight along the first direction. The size of the orthographic projection of the first sub-body portion on the substrate in the second direction is equal to the size of the orthographic projection of the second sub-body portion on the substrate in the second direction.

[0017] Wherein, the overlapping area of ​​the orthographic projection of the first sub-body portion on the substrate and the orthographic projection of the first notch on the substrate is smaller than the overlapping area of ​​the orthographic projection of the second sub-body portion on the substrate and the orthographic projection of the second notch on the substrate.

[0018] In an exemplary embodiment of this disclosure, the second body portion is composed of a first sub-body portion and a second sub-body portion. The dividing line between the orthographic projection of the first sub-body portion on the substrate and the orthographic projection of the second sub-body portion on the substrate extends straight along the first direction. The size of the orthographic projection of the first sub-body portion on the substrate in the second direction is equal to the size of the orthographic projection of the second sub-body portion on the substrate in the second direction.

[0019] The overlapping area of ​​the orthographic projection of the first sub-body portion on the substrate and the orthographic projection of the conductive block on the substrate is greater than the overlapping area of ​​the orthographic projection of the second sub-body portion on the substrate and the orthographic projection of the conductive block on the substrate.

[0020] In one example embodiment of the present disclosure, the conductive block includes a first conductive block, a second conductive block, and a third conductive block, the second conductive block being connected between the first conductive block and the third conductive block;

[0021] In one example embodiment of the present disclosure, the first conductive block has a first direction and a second direction perpendicular to the first direction, the first conductive block has a first body portion and a second body portion, the first body portion and the second body portion are connected to each other, the first body portion has a first direction and a second direction perpendicular to the first direction, the first direction of the first body portion is parallel to the first direction of the conductive block, the second direction of the first body portion is parallel to the second direction of the conductive block, the first body portion has a first side edge and a second side edge, the first side edge includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0022] In one example embodiment of the present disclosure, the first conductive block has a first direction and a second direction perpendicular to the first direction, the first conductive block has a first body portion and a second body portion, the first body portion and the second body portion are connected to each other, the first body portion has a first direction and a second direction perpendicular to the first direction, the first direction of the first body portion is parallel to the first direction of the conductive block, the second direction of the first body portion is parallel to the second direction of the conductive block, the first body portion has a first side edge and a second side edge, the first side edge includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0023] In one example embodiment of the present disclosure, the first conductive block has a first direction and a second direction perpendicular to the first direction, the first conductive block has a first body portion and a second body portion, the first body portion and the second body portion are connected to each other, the first body portion has a first direction and a second direction perpendicular to the first direction, the first direction of the first body portion is parallel to the first direction of the conductive block, the second direction of the first body portion is parallel to the second direction of the conductive block, the first body portion has a first side edge and a second side edge, the first side edge includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0024] In one example embodiment of the present disclosure, the first conductive block has a first direction and a second direction perpendicular to the first direction, the first conductive block has a first body portion and a second body portion, the first body portion and the second body portion are connected to each other, the first body portion has a first direction and a second direction perpendicular to the first direction, the first direction of the first body portion is parallel to the first direction of the conductive block, the second direction of the first body portion is parallel to the second direction of the conductive block, the first body portion has a first side edge and a second side edge, the first side edge includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0025] In one example embodiment of the present disclosure, the first conductive block has a first direction and a second direction perpendicular to the first direction, the first conductive block has a first body portion and a second body portion, the first body portion and the second body portion are connected to each other, the first body portion has a first direction and a second direction perpendicular to the first direction, the first direction of the first body portion is parallel to the first direction of the conductive block, the second direction of the first body portion is parallel to the second direction of the conductive block, the first body portion has a first side edge and a second side edge, the first side edge includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0026] In one example embodiment of the present disclosure, the second conductive block includes a first extension line and a second extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0027] In one example embodiment of the present disclosure, the second conductive block includes a first side edge, the first side edge includes a first extension line, a second extension line, and a third extension line, the second extension line is connected between the first extension line and the third extension line, the third conductive block is connected to the second extension line.

[0028] A projection of the second body portion on the substrate substrate covers a projection of the first extension line on the substrate substrate, and a projection of the second body portion on the substrate substrate and a projection of the third extension line on the substrate substrate do not overlap.

[0029] In one example embodiment of the present disclosure, the missing portion includes a first gap and a second gap, the first gap and the second gap are located on both sides of the conductive block in the first direction;

[0030] A projection of the second body portion on the substrate substrate at least partially overlaps a projection of the first gap on the substrate substrate and a projection of the second gap on the substrate substrate at both ends in the first direction.

[0031] In one example embodiment of the present disclosure, the missing portion includes a third gap, the third gap is located on one side of the conductive block in the second direction, and a projection of the third gap on the substrate substrate extends along the second direction;

[0032] A projection of the third gap on the substrate substrate and a projection of the second body portion on the substrate substrate at least partially overlap, and a projection of the second body portion on the substrate substrate at least partially overlaps a projection of the conductive block on the substrate substrate at both ends in the first direction.

[0033] In one example embodiment of the present disclosure, the missing portion further includes a fourth gap, a projection of the fourth gap on the substrate substrate is located on one side of a projection of the third gap on the substrate substrate in the second direction, and a projection of the third gap on the substrate substrate is located between a projection of the fourth gap on the substrate substrate and a part of the conductive block on the substrate substrate;

[0034] A size of a projection of the fourth gap on the substrate substrate in the first direction is greater than a size of a projection of the third gap on the substrate substrate in the first direction;

[0035] The second body portion is composed of a first sub-body portion and a second sub-body portion, a separation line between a projection of the first sub-body portion on the substrate substrate and a projection of the second sub-body portion on the substrate substrate extends linearly along the first direction, and a size of the projection of the first sub-body portion on the substrate substrate in the second direction is equal to a size of the projection of the second sub-body portion on the substrate substrate in the second direction;

[0036] A projection of the second sub-body portion on the substrate and a projection of the fourth gap on the substrate at least partially overlap, and a projection of the first sub-body portion on the substrate and a projection of the fourth gap on the substrate do not overlap.

[0037] In an example embodiment of the present disclosure, the missing portion includes at least one strip-shaped opening, and a projection of the at least one strip-shaped opening on the substrate extends along the second direction and is spaced along the first direction.

[0038] A projection of the strip-shaped opening on the substrate and a projection of the second body portion on the substrate at least partially overlap.

[0039] In an example embodiment of the present disclosure, part of the first body portions are used to form first electrodes of red light emitting units, part of the first body portions are used to form first electrodes of blue light emitting units, and the second body portion is used to form a first electrode of a green light emitting unit.

[0040] An overlapping area of a projection of the first body portion for forming a first electrode of a blue light emitting unit on the substrate and a projection of the conductive layer where the first power line is located on the substrate is S1.

[0041] An overlapping area of a projection of the first body portion for forming a first electrode of a red light emitting unit on the substrate and a projection of the conductive layer where the first power line is located on the substrate is S2.

[0042] An overlapping area of a projection of the second body portion on the substrate and a projection of the conductive layer where the first power line is located on the substrate is S3.

[0043] |S3-S1| / S1 is 38%-58%, and / or |S3-S2| / S2 is 10%-30%.

[0044] In an example embodiment of the present disclosure, part of the first body portions are used to form first electrodes of red light emitting units, part of the first body portions are used to form first electrodes of blue light emitting units, and the second body portion is used to form a first electrode of a green light emitting unit.

[0045] In an example embodiment of the present disclosure, the conductive layer where the first power line is located further includes:

[0046] A data line, a projection of which on the substrate extends along the second direction.

[0047] a second fan-out line, a projection of which on the substrate substrate extends along the second direction;

[0048] The first power line further comprises a second extension section connected between two adjacent first extension sections.

[0049] The projection of one or more of the data line, the second fan-out line, and the second extension section on the substrate substrate and the projection of the first body portion on the substrate substrate overlap.

[0050] According to an aspect of the present disclosure, there is provided a display device comprising the display panel described above.

[0051] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is readily apparent to one of ordinary skill in the art that the accompanying drawings are merely exemplary of embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure.

[0053] FIG. 1 is a partial structure layout of a display panel in the related art;

[0054] FIG. 2 is a structure layout of a third source-drain layer in FIG. 1;

[0055] FIG. 3 is a partial cross-sectional view of the display panel shown in FIG. 1 along the dotted line AA;

[0056] FIG. 4 is a partial cross-sectional view of the display panel shown in FIG. 1 along the dotted line BB;

[0057] FIG. 5 is a structure layout of an exemplary embodiment of a display panel according to the present disclosure;

[0058] FIG. 6 is a partial structure layout of the display panel shown in FIG. 5;

[0059] FIG. 7 is a structure layout of a conductive layer in which a first power line is located in the display panel shown in FIG. 6;

[0060] FIG. 8 is a structure layout of an electrode layer in the display panel shown in FIG. 6;

[0061] FIG. 9 is a structure layout of a local area CC in the display panel shown in FIG. 6;

[0062] FIG. 10 is a structure layout of a first power line in the local area CC in the display panel shown in FIG. 6;

[0063] FIG. 11 is a structural layout of another exemplary embodiment of the display panel of the present disclosure;

[0064] FIG. 12 is a structural layout of the conductive layer in which the first power supply line is located in the display panel shown in FIG. 11;

[0065] FIG. 13 is a structural layout of the local area EE in the display panel shown in FIG. 11;

[0066] FIG. 15 is a structural layout of another exemplary embodiment of the display panel of the present disclosure;

[0067] FIG. 16 is a structural layout of the conductive layer in which the first power supply line is located in the display panel shown in FIG. 15;

[0068] FIG. 17 is a structural layout of the local area FF in the display panel shown in FIG. 15;

[0069] FIG. 18 is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure;

[0070] FIG. 19 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG. 18;

[0071] FIG. 20 is a structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0072] FIG. 21 is a structural layout of the shielding layer in FIG. 20;

[0073] FIG. 22 is a structural layout of the first active layer in FIG. 20;

[0074] FIG. 23 is a structural layout of the first gate layer in FIG. 20;

[0075] FIG. 24 is a structural layout of the second gate layer in FIG. 20;

[0076] FIG. 25 is a structural layout of the second active layer in FIG. 20;

[0077] FIG. 26 is a structural layout of the third gate layer in FIG. 20;

[0078] FIG. 27 is a structural layout of the first source-drain layer in FIG. 20;

[0079] FIG. 28 is a structural layout of the second source-drain layer in FIG. 20;

[0080] FIG. 29 is a structural layout of the third source-drain layer in FIG. 20;

[0081] FIG. 30 is a structural layout of the electrode layer in FIG. 20;

[0082] FIG. 31 is a structural layout of the shielding layer, the first active layer in FIG. 20;

[0083] Fig. 32 is a structure layout of the shielding layer, the first active layer, and the first gate layer in Fig. 20;

[0084] Fig. 33 is a structure layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Fig. 20;

[0085] Fig. 34 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Fig. 20;

[0086] Fig. 35 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Fig. 20;

[0087] Fig. 36 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in Fig. 20;

[0088] Fig. 37 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in Fig. 20;

[0089] Fig. 38 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, the second source-drain layer, and the third source-drain layer in Fig. 20;

[0090] Fig. 39 is a partial cross-sectional view of the display panel shown in Fig. 20 taken along the line HH;

[0091] Fig. 40 is a partial structure layout of the display panel shown in Fig. 11;

[0092] Fig. 41 is a partial structure layout of the display panel shown in Fig. 15. DETAILED DESCRIPTION

[0093] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views and the detailed description.

[0094] The terms "one", "a", "said" are used to indicate that there is one or more of the elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusion of elements / components / etc. in the resulting product or process "including" and "having" do not exclude that there are additional elements / components / etc. in addition to those listed.

[0095] As shown in FIG. 1 and FIG. 2, FIG. 1 is a partial structure layout of a display panel in the related art, and FIG. 2 is a structure layout of a third source-drain layer in FIG. 1. The display panel can include a substrate, a third source-drain layer, and an electrode layer located on a side of the third source-drain layer away from the substrate. The third source-drain layer can include a first power line VDD, a data line Da, and a second fan-out line FIPV. The electrode layer includes a plurality of electrode portions, including a plurality of first electrode portions, a second electrode portion G, and a plurality of first electrode portions including a first electrode portion R and a first electrode portion B. The display panel can further include a pixel definition layer located on a side of the electrode layer away from the substrate, and the pixel definition layer can have a plurality of pixel openings formed thereon. The pixel openings and the body portions are arranged correspondingly, and the orthographic projection of the body portions on the substrate and the orthographic projection of the pixel openings corresponding thereto on the substrate coincide. The body portions are used to form first electrodes of light-emitting units, and the pixel openings can be used to form light-emitting layers of the light-emitting units. For example, the second electrode portion G includes a second body portion G1, the first electrode portion R includes a first body portion R1, and the first electrode portion B includes a first body portion B1. The first body portion R1 can be used to form a first electrode of a red light-emitting unit, the first body portion B1 can be used to form a first electrode of a blue light-emitting unit, and the second body portion G1 can be used to form a first electrode of a green light-emitting unit.

[0096] As shown in FIG. 1 and FIG. 2, the first power line VDD includes a first extension VDD1 and a second extension VDD2. The first extensions VDD1 in adjacent two first power lines VDD are connected, and the connected two first extensions VDD1 form a conductive block 61. As shown in FIG. 1 and FIG. 2, the orthographic projection of the second body portion G1 on the substrate is located within the orthographic projection of the conductive block 61 on the substrate, and the orthographic projection of the first body portion R1 on the substrate overlaps with the orthographic projection of the data line Da on the substrate, the orthographic projection of the second fan-out line FIPV on the substrate, and the orthographic projection of the second extension VDD2 on the substrate.

[0097] As shown in FIG. 3, which is a partial cross-sectional view of the display panel shown in FIG. 1 along the dashed line AA. The display panel further includes a light-emitting layer EL and a cathode layer Ch. The light-emitting layer EL is located on a side of the electrode layer away from the substrate, and the cathode layer Ch is located on a side of the light-emitting layer EL away from the substrate. The light-emitting layer EL can emit light under the voltage of the body portion and the cathode layer Ch. As shown in FIG. 3, due to the partial structure of the first body portion B1 being raised by the structures such as the first power line VDD, the data line Da, and the second fan-out line FIPV in the third source-drain layer, the first body portion B1 will be in an up-and-down state in the first direction X. Similarly, the first body portion R1 will also be in an up-and-down state in the first direction X.

[0098] As shown in FIG. 4, it is a sectional view of the display panel shown in FIG. 1 along the dotted line BB. Since the orthographic projection of the second body portion G1 on the substrate substrate is located within the orthographic projection of the conductive block 61 on the substrate substrate. The second body portion G1 is relatively flat in the first direction X.

[0099] As shown in FIGS. 3 and 4, since the first body portion R1 and the first body portion B1 have relatively large undulations in the first direction X, the second body portion G1 is relatively flat in the first direction X. The different light-emitting angles (shown by arrows in FIGS. 3 and 4) of the red light-emitting unit / blue light-emitting unit and the green light-emitting unit in the first direction cause color ratio differences, thereby causing the display panel to have color differences, which are more obvious at a large viewing angle in the first direction.

[0100] Based on this, the present example embodiment provides a display panel, as shown in FIGS. 5-10, FIG. 5 is a structural layout of an example embodiment of the display panel of the present disclosure, FIG. 6 is a partial structural layout of the display panel shown in FIG. 5, wherein FIG. 6 only shows the body part in the electrode layer, FIG. 7 is a structural layout of the conductive layer where the first power supply line is located in the display panel shown in FIG. 6, FIG. 8 is a structural layout of the electrode layer in the display panel shown in FIG. 6, FIG. 9 is a structural layout of the local area CC in the display panel shown in FIG. 6, and FIG. 10 is a structural layout of the first power supply line in the local area CC in the display panel shown in FIG. 6. The display panel comprises a substrate, a plurality of pixel driving circuit groups Pz, a plurality of first power supply lines, an electrode layer, and a pixel definition layer. The plurality of pixel driving circuit groups Pz are arrayed along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X can be the row direction, and the second direction Y can be the column direction. The pixel driving circuit group Pz comprises two pixel driving circuits Pix adjacent in the first direction X, and the orthographic projection of the two pixel driving circuits Pix in the same pixel driving circuit group PZ on the substrate is at least partially mirror-symmetrically arranged; the orthographic projection of the first power supply line VDD on the substrate extends along the second direction Y, the first power supply line VDD and the pixel driving circuit Pix are correspondingly arranged, and the first power supply line VDD is used to provide a power supply signal to the pixel driving circuit Pix corresponding thereto; the first power supply line VDD comprises a first extension segment VDD1, and in the same pixel driving circuit group Pz, the first extension segments VDD1 of the two first power supply lines VDD corresponding to the two pixel driving circuits Pix are connected, the connected two first extension segments VDD1 form a conductive block 61, and the conductive block 61 has a missing part MP; the electrode layer comprises a plurality of electrode parts, the electrode part comprises a body part, and the body part is used to form a first electrode of a light-emitting unit; the pixel definition layer is located on the side of the electrode layer away from the substrate, the pixel definition layer has a plurality of pixel openings formed thereon, the pixel openings and the body parts are correspondingly arranged, the orthographic projection of the body part on the substrate and the orthographic projection of the pixel opening corresponding thereto on the substrate coincide; the plurality of body parts comprise a first body part and a second body part, the orthographic projection of the first body part on the substrate and the orthographic projection of the conductive layer where the first power supply line is located on the substrate partially overlap and partially do not overlap; the orthographic projection of the second body part on the substrate and the orthographic projection of the conductive block on the substrate partially overlap, and the orthographic projection of the second body part on the substrate and the orthographic projection of the missing part on the substrate partially overlap. For example, the plurality of electrode parts comprise a first electrode part R, a first electrode part B, and a second electrode part G, the first electrode part R comprises a first body part R1, the first electrode part B comprises a first body part B1, and the second electrode part G comprises a second body part G1.The orthographic projection of the first electrode portion R and the first electrode portion B on the substrate substrate partially overlaps and partially does not overlap with the orthographic projection of the first power line on the conductive layer on the substrate substrate; the orthographic projection of the second body portion G1 on the substrate substrate partially overlaps with the orthographic projection of the conductive block 61 on the substrate substrate, and the orthographic projection of the second body portion G1 on the substrate substrate partially overlaps with the orthographic projection of the missing portion MP on the substrate substrate.

[0101] The present exemplary embodiment forms the missing portion MP on the conductive block 61, so that the second body portion G1 can also form a structure that rises and falls up and down. This arrangement can make the second body portion G1 have the same or similar light-emitting effects on different angles of the first direction corresponding to the light-emitting units and the first body portion corresponding to the light-emitting units, so that this arrangement can improve the color deviation problem of the display panel.

[0102] It should be noted that the orthographic projection of the missing portion on the substrate substrate at least includes a region in the orthographic projection of the electrode portion on the substrate substrate that does not overlap with the orthographic projection of the first power line on the film layer on the substrate substrate.

[0103] As shown in FIGS. 5-10, the missing portion MP includes a first notch MP1 and a second notch MP2, and the first notch MP1 and the second notch MP2 are located on both sides of the conductive block in the first direction X; the orthographic projection of the second body portion G1 on the substrate substrate at least partially overlaps with the orthographic projection of the first notch MP1 on the substrate substrate and the orthographic projection of the second notch MP2 on the substrate substrate at both ends in the first direction X. This arrangement can make the second body portion G1 have a floating up and down in the first direction X, so that the color deviation problem of the display panel can be improved.

[0104] In the present exemplary embodiment, under the cushioning effect of other conductive layers, the first body portion R1 and the first body portion B1 will have a high-low tilt problem in the second direction Y, and the high-low direction is perpendicular to the substrate substrate. For example, in the present exemplary embodiment, the upper part of the first body portion R1 and the first body portion B1 is higher (farther from the substrate substrate), and the lower part is lower (closer to the substrate substrate), so that there is a tilt problem of high up and low down, which can also cause the color deviation problem of the display panel.

[0105] As shown in FIGS. 5-10, the orthographic projection of the second body portion G1 on the substrate substrate at both ends in the second direction Y can at least partially overlap with the orthographic projection of the first notch MP1 on the substrate substrate and the orthographic projection of the second notch MP2 on the substrate substrate. This arrangement can adjust the tilt state of the second body portion G1 in the second direction Y by adjusting the overlapping area of the orthographic projection of the second body portion G1 on the substrate substrate at both ends in the second direction Y and the missing portion, so that the first body portion and the second body portion have the same or similar tilt state, and thus the color deviation problem of the display panel can be improved.

[0106] As shown in FIGS. 5-10, the second body part G1 is composed of the first sub-body part G11 and the second sub-body part G12, a separation line DD between the orthogonal projection of the first sub-body part G11 on the substrate and the orthogonal projection of the second sub-body part G12 on the substrate extends linearly in the first direction, the size of the orthogonal projection of the first sub-body part G11 on the substrate in the second direction Y is equal to the size of the orthogonal projection of the second sub-body part G12 on the substrate in the second direction Y; wherein the overlapping area of the orthogonal projection of the first sub-body part G11 on the substrate and the orthogonal projection of the first notch MP1 on the substrate is less than the overlapping area of the orthogonal projection of the second sub-body part G12 on the substrate and the orthogonal projection of the second notch MP2 on the substrate. This setting can make the second body part G1 form an upper-high and lower-low inclined state, thereby improving the color deviation of the display panel.

[0107] It should be understood that in other exemplary embodiments, when the first body part is in an upper-low and lower-high inclined state, the overlapping area of the orthogonal projection of the first sub-body part G11 on the substrate and the orthogonal projection of the first notch MP1 on the substrate can be greater than the overlapping area of the orthogonal projection of the second sub-body part G12 on the substrate and the orthogonal projection of the second notch MP2 on the substrate, which can adjust the first body part to an upper-low and lower-high inclined state.

[0108] In the present exemplary embodiment, as shown in FIGS. 5-10, the overlapping area of the orthogonal projection of the first sub-body part G11 on the substrate and the orthogonal projection of the conductive block 61 on the substrate can be greater than the overlapping area of the orthogonal projection of the second sub-body part G12 on the substrate and the orthogonal projection of the conductive block 61 on the substrate.

[0109] In the example embodiment, as shown in FIGS. 5-10, the conductive block includes a first conductive block 611, a second conductive block 612, and a third conductive block 613, the second conductive block 612 being connected between the first conductive block 611 and the third conductive block 613; wherein, in the direction in which the orthographic projection of the first conductive block 611 on the substrate substrate faces the orthographic projection of the second conductive block 612 on the substrate substrate, the size of the orthographic projection of the first conductive block 611 on the substrate substrate in the first direction gradually decreases; the size of the orthographic projection of the third conductive block 613 on the substrate substrate in the first direction X is smaller than the size of the orthographic projection of the second conductive block 612 on the substrate substrate in the first direction X; wherein, the orthographic projection of the first sub-body portion G11 on the substrate substrate and the orthographic projection of the second conductive block 612 on the substrate substrate at least partially overlap, the orthographic projection of the second sub-body portion G12 on the substrate substrate and the orthographic projection of the second conductive block 612 on the substrate substrate at least partially overlap; the orthographic projection of the first sub-body portion G11 on the substrate substrate and the orthographic projection of the first conductive block 611 on the substrate substrate at least partially overlap, the orthographic projection of the second sub-body portion G12 on the substrate substrate and the orthographic projection of the third conductive block 613 on the substrate substrate at least partially overlap. This arrangement can achieve that the overlapping area of the orthographic projection of the first sub-body portion G11 on the substrate substrate and the orthographic projection of the first gap MP1 on the substrate substrate is smaller than the overlapping area of the orthographic projection of the second sub-body portion G12 on the substrate substrate and the orthographic projection of the second gap MP2 on the substrate substrate.

[0110] In the example embodiment, as shown in FIGS. 5-10, the second conductive block 612 includes an equal-width extension segment 6124, the equal-width extension segment 6124 being connected to the first conductive block 611, and the orthographic projection of the equal-width extension segment 6124 on the substrate substrate has equal sizes in the first direction X of any segment in the second direction.

[0111] In the example embodiment, as shown in FIGS. 5-10, the second conductive block 612 includes a first side edge 612C, the first side edge 612C includes a first extension segment 6121, a second extension segment 6122, and a third extension segment 6123, the second extension segment 6122 is connected between the first extension segment 6121 and the third extension segment 6123, and the third conductive block 613 is connected to the second extension segment 6122; a normal projection of the second body portion G1 on the substrate substrate covers a normal projection of the first extension segment 6121 on the substrate substrate, and a normal projection of the second body portion G1 on the substrate substrate and a normal projection of the third extension segment 6123 on the substrate substrate do not overlap. A gap MP21 can be formed between the first extension segment 6121 and the third conductive block 613, the gap MP21 forms part of the second gap MP2, and the gap MP21 can increase an overlapping area of a normal projection of the second sub-body portion G12 on the substrate substrate and a normal projection of the second gap MP2 on the substrate substrate, so as to realize that an overlapping area of a normal projection of the first sub-body portion G11 on the substrate substrate and a normal projection of the first gap MP1 on the substrate substrate is less than an overlapping area of a normal projection of the second sub-body portion G12 on the substrate substrate and a normal projection of the second gap MP2 on the substrate substrate.

[0112] In the example embodiment, as shown in FIGS. 5-10, the first body portion R1 is used to form a first electrode of a red light emitting unit, the first body portion B1 is used to form a first electrode of a blue light emitting unit, and the second body portion G1 is used to form a first electrode of a green light emitting unit. An overlapping area of a normal projection of the first body portion B1 on the substrate substrate and a normal projection of the conductive layer where the first power line is located on the substrate substrate is S1; an overlapping area of a normal projection of the first body portion R1 on the substrate substrate and a normal projection of the conductive layer where the first power line is located on the substrate substrate is S2; and an overlapping area of a normal projection of the second body portion G1 on the substrate substrate and a normal projection of the conductive layer where the first power line is located on the substrate substrate is S3; wherein |S3-S1| / S1 is 38%-58%, and / or |S3-S2| / S2 is 10%-30%. For example, |S3-S1| / S1 can be equal to 38%, 40%, 42%, 44%, 46%, 48%, 50%, 52%, 54%, 56%, 58%, etc. |S3-S2| / S2 can be equal to 10%, 12%, 14%, 16%, 18%, 20%, 22%, 24%, 26%, 28%, 30%, etc.

[0113] In the example embodiment, as shown in FIGS. 5-10, an area of a normal projection of the first body portion B1 on the substrate substrate is S4, an area of a normal projection of the first body portion R1 on the substrate substrate is S5, and an area of a normal projection of the second body portion G1 on the substrate substrate is S6. Wherein S1 / S4 is less than 50%, S2 / S5 is less than 50%, and S3 / S6 is greater than 50%.

[0114] In the example embodiment, as shown in FIGS. 11-14, FIG. 11 is a structural layout of another example embodiment of the display panel of the present disclosure, wherein FIG. 11 only shows the body part in the electrode layer, and the electrode part in the display panel shown in FIG. 11 can also include the extension part around the body part, FIG. 12 is a structural layout of the conductive layer where the first power supply line is located in the display panel shown in FIG. 11, FIG. 13 is a structural layout of the local area EE in the display panel shown in FIG. 11, and FIG. 14 is a structural layout of the first power supply line in the local area EE in the display panel shown in FIG. 11.

[0115] In the example embodiment, as shown in FIGS. 11-14, the missing part MP can include a third gap MP3, the third gap MP3 is located on one side of the conductive block 61 in the second direction, and the orthographic projection of the third gap MP3 on the substrate substrate extends along the second direction Y; the orthographic projection of the third gap MP3 on the substrate substrate and the orthographic projection of the second body part G1 on the substrate substrate at least partially overlap, and the orthographic projection of the second body part G1 on the substrate substrate at least partially overlaps the orthographic projection of the conductive block 61 on the substrate substrate at both ends in the first direction X. This arrangement can also make the second body part G1 undulate up and down in the first direction X, thereby improving the color difference problem of the display panel.

[0116] In the example embodiment, as shown in FIGS. 11-14, the missing part MP further includes a fourth gap MP4, the orthographic projection of the fourth gap MP4 on the substrate substrate is located on one side of the orthographic projection of the third gap MP3 on the substrate substrate in the second direction Y, and the orthographic projection of the third gap MP3 on the substrate substrate is located between the orthographic projection of the fourth gap MP4 on the substrate substrate and the orthographic projection of part of the conductive block 61 on the substrate substrate; the size of the orthographic projection of the fourth gap MP4 on the substrate substrate in the first direction X is greater than the size of the orthographic projection of the third gap MP3 on the substrate substrate in the first direction; the orthographic projection of the second sub-body part G12 on the substrate substrate and the orthographic projection of the fourth gap MP4 on the substrate substrate at least partially overlap, and the orthographic projection of the first sub-body part G11 on the substrate substrate and the orthographic projection of the fourth gap MP4 on the substrate substrate do not overlap. This arrangement can achieve that the overlapping area of the orthographic projection of the first sub-body part G11 on the substrate substrate and the orthographic projection of the first gap MP1 on the substrate substrate is less than the overlapping area of the orthographic projection of the second sub-body part G12 on the substrate substrate and the orthographic projection of the second gap MP2 on the substrate substrate, thereby realizing the structure of high on the second body part G1 and low, and further improving the color deviation of the display panel.

[0117] In the example embodiment, as shown in FIGS. 15-17, FIG. 15 is a structural layout of another example embodiment of the display panel of the present disclosure, wherein FIG. 15 only shows the body portions in the electrode layer, and the electrode portions in the display panel shown in FIG. 15 can also include the extension portions around the body portions, FIG. 16 is a structural layout of the conductive layer where the first power lines are located in the display panel shown in FIG. 15, and FIG. 17 is a structural layout of the local area FF in the display panel shown in FIG. 15.

[0118] In the example embodiment, as shown in FIGS. 15-17, the missing portion MP includes at least one strip-shaped opening MPT, a projection of the strip-shaped opening MPT on the substrate substrate extends along the second direction Y and is spaced apart along the first direction X; and a projection of the strip-shaped opening MPT on the substrate substrate and a projection of the second body portion G1 on the substrate substrate at least partially overlap. This arrangement can also make the second body portion G1 undulate up and down in the first direction X, thereby improving the color difference problem of the display panel.

[0119] In the example embodiment, as shown in FIGS. 15-17, the missing portion MP includes three strip-shaped openings MPT, and it should be understood that in other example embodiments, the missing portion MP can also include other numbers of strip-shaped openings MPT.

[0120] In the example embodiment, as shown in FIGS. 11-17, the first body portion R1 is used to form the first electrode of the red light-emitting unit, the first body portion B1 is used to form the first electrode of the blue light-emitting unit, and the second body portion G1 is used to form the first electrode of the green light-emitting unit. The overlapping area of the projection of the first body portion B1 on the substrate substrate and the projection of the conductive layer where the first power lines are located on the substrate substrate is S1; the overlapping area of the projection of the first body portion R1 on the substrate substrate and the projection of the conductive layer where the first power lines are located on the substrate substrate is S2; the overlapping area of the projection of the second body portion G1 on the substrate substrate and the projection of the conductive layer where the first power lines are located on the substrate substrate is S3; wherein |S3-S1| / S1 is 50%-70%, and / or |S3-S2| / S2 is 25%-45%. For example, |S3-S1| / S1 can be equal to 50%, 52%, 54%, 56%, 58%, 60%, 62%, 64%, 66%, 68%, 70%, etc. |S3-S2| / S2 can be equal to 25%, 27%, 29%, 31%, 33%, 35%, 37%, 39%, 41%, 43%, 45%, etc.

[0121] In the example embodiment, as shown in FIGS. 5-17, the conductive layer where the first power line is located further includes a data line Da and a second fan-out line FIPV, and the first power line VDD further includes a second extension VDD2 connected between two adjacent first extensions VDD1. The orthogonal projection of the data line Da, the second fan-out line FIPV, and the second extension VDD2 on the substrate substrate overlaps with the orthogonal projection of the first body portion R1 / B1 on the substrate substrate.

[0122] It should be understood that in other example embodiments, the orthogonal projection of part of the data line Da, the second fan-out line FIPV, and the second extension VDD2 on the substrate substrate overlaps with the orthogonal projection of the first body portion R1 / B1 on the substrate substrate.

[0123] The example embodiment first provides a pixel driving circuit, as shown in FIGS. 18 and 19. FIG. 18 is a structural schematic diagram of an example embodiment of the pixel driving circuit of the present disclosure, and FIG. 19 is a timing diagram of part of the nodes in an example embodiment of the pixel driving circuit shown in FIG. 18.

[0124] The pixel driving circuit can comprise a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to a second gate driving signal terminal GT2. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fifth transistor T5 is connected to an enable signal terminal EM. The gate electrode of the driving transistor T3 is connected to a node N. The first electrode of the second transistor T2 is connected to the node N, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate electrode of the second transistor T2 is connected to a first gate driving signal terminal GT1. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate electrode of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and the gate electrode of the seventh transistor T7 is connected to a second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to a first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate electrode of the first transistor T1 is connected to a first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to a third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate electrode of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be used to drive a light emitting unit L. The first electrode of the light emitting unit L can be connected to the second electrode of the sixth transistor T6, the second electrode of the light emitting unit L can be connected to a second power supply terminal VSS, the first electrode of the light emitting unit L can be an anode of the light emitting unit L, and the second electrode of the light emitting unit L can be a cathode of the light emitting unit L. The second transistor T2 can be an N-type transistor, for example, the second transistor T2 can be an N-type metal oxide transistor. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low temperature poly-silicon transistors. The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0125] As shown in FIG. 19, wherein GT1 represents the timing of the first gate drive signal end GT1, GT2 represents the timing of the second gate drive signal end GT2, Re2 represents the timing of the second reset signal end Re2, Re1 represents the timing of the first reset signal end Re1, and EM represents the timing of the enable signal end EM. One driving cycle of the pixel driving circuit can include a first reset stage t1, a second reset stage t2, a data writing stage t3, a third reset stage t5, and a light emitting stage t6.

[0126] In the first reset stage t1, the second reset signal end Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal end Vinit2 inputs a second initial signal to the first electrode of the light emitting unit L, and the third initial signal end Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3, so as to improve the hysteresis problem of the driving transistor T3. In the second reset stage t2, the first gate drive signal end GT1 outputs a high level, the first reset signal end Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal end Vinit1 inputs a first initial signal to the node N through the first transistor T1 and the second transistor T2. In the data writing stage t3, the second gate drive signal end GT2 outputs a low level signal, the first gate drive signal end GT1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal end Da writes a compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, wherein Vdata is the voltage of the data signal on the data signal end, and Vth is the threshold voltage of the driving transistor T3. In the third reset stage t5, the second reset signal end RE2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal end Vinit2 inputs a second initial signal to the first electrode of the light emitting unit L, and the third initial signal end Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the light emitting stage t6, the enable signal end EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0127] Wherein I is the output current of the driving transistor, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the above pixel driving circuit is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2The pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current.

[0128] The display panel shown in FIG. 5 can include a substrate, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, a third source-drain layer, and an electrode layer which are sequentially stacked. An insulating layer can be provided between adjacent layers. As shown in FIGS. 20-38, FIG. 20 is a structure layout of an exemplary embodiment of the display panel of the present disclosure, FIG. 21 is a structure layout of the shielding layer in FIG. 20, FIG. 22 is a structure layout of the first active layer in FIG. 20, FIG. 23 is a structure layout of the first gate layer in FIG. 20, FIG. 24 is a structure layout of the second gate layer in FIG. 20, FIG. 25 is a structure layout of the second active layer in FIG. 20, FIG. 26 is a structure layout of the third gate layer in FIG. 20, FIG. 27 is a structure layout of the first source-drain layer in FIG. 20, FIG. 28 is a structure layout of the second source-drain layer in FIG. 20, FIG. 29 is a structure layout of the third source-drain layer in FIG. 20, FIG. 30 is a structure layout of the electrode layer in FIG. 20, FIG. 31 is a structure layout of the shielding layer and the first active layer in FIG. 20, FIG. 32 is a structure layout of the shielding layer, the first active layer, and the first gate layer in FIG. 20, FIG. 33 is a structure layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 20, FIG. 34 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 20, FIG. 35 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 20, FIG. 36 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in FIG. 20, FIG. 37 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG. 20, and FIG. 38 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, the second source-drain layer, and the third source-drain layer in FIG. 20.

[0129] The equivalent circuit diagram of the pixel driving circuit in the display panel can be as shown in FIG. 18. As shown in FIG. 38, the orthographic projections of two pixel driving circuits Pix in the same pixel driving circuit group PZ on the substrate are at least partially arranged in mirror symmetry along the symmetry axis GG. The orthographic projections of the channel regions of the same type of transistors in the two pixel driving circuits which are at least partially mirror symmetric in structure are arranged in mirror symmetry on the substrate, for example, the orthographic projections of the channel regions of the first transistors in the two pixel driving circuits are arranged in mirror symmetry along the symmetry axis GG on the substrate.

[0130] As shown in FIGS. 20, 21, 31, the shielding layer includes a plurality of first shielding portions 81 arranged along the first direction X and the second direction Y, and the first shielding portions 81 are connected to each other.

[0131] As shown in FIGS. 20, 22, 31, 32, the first active layer can include a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and an eighteenth active portion 718. The first active portion 71 is used to form a channel region of the first transistor T1; the third active portion 73 can be used to form a channel region of the driving transistor T3; the fourth active portion 74 can be used to form a channel region of the fourth transistor T4; the fifth active portion 75 can be used to form a channel region of the fifth transistor T5; the sixth active portion 76 can be used to form a channel region of the sixth transistor T6; the seventh active portion 77 can be used to form a channel region of the seventh transistor T7; the eighth active portion 78 can be used to form a channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the twelfth active portion 712 are connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fifth active portion 75 and the third active portion 73; the thirteenth active portion 713 is connected to a side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer can be formed of a polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0132] As shown in FIGS. 20, 23, 32, the first gate layer can include: the first conductive part 11, the second gate line GT2, the enable signal line EM, the first reset signal line Re1, the second reset signal line Re2. The second gate line GT2 can be used to provide the second gate driving signal end in FIG. 18; the enable signal line EM can be used to provide the enable signal end in FIG. 18; the first reset signal line Re1 can be used to provide the first reset signal end in FIG. 18; the second reset signal line Re2 can be used to provide the second reset signal end in FIG. 18. The orthogonal projection of the second gate line GT2 on the substrate substrate, the orthogonal projection of the enable signal line EM on the substrate substrate, the orthogonal projection of the first reset signal line Re1 on the substrate substrate, the orthogonal projection of the second reset signal line Re2 on the substrate substrate can extend along the first direction X. The orthogonal projection of the second gate line GT2 on the substrate substrate covers the orthogonal projection of the fourth active part 74 on the substrate substrate, and part of the structure of the second gate line GT2 is used to form the gate of the fourth transistor. The orthogonal projection of the enable signal line EM on the substrate substrate covers the orthogonal projection of the fifth active part 75 on the substrate substrate, the orthogonal projection of the sixth active part 76 on the substrate substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, the sixth transistor T6 respectively. The orthogonal projection of the first reset signal line Re1 on the substrate substrate can cover the orthogonal projection of the first active part 71 on the substrate substrate, and part of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthogonal projection of the second reset signal line Re2 on the substrate substrate can cover the orthogonal projection of the seventh active part 77 on the substrate substrate, the orthogonal projection of the eighth active part 78 on the substrate substrate, and part of the structure of the first reset signal line Re1 can be used to form the gate of the seventh transistor T7, the eighth transistor T8 respectively. The orthogonal projection of the first conductive part 11 on the substrate substrate covers the orthogonal projection of the third active part 73 on the substrate substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first gate layer can form the channel region of the transistor, and the region of the first active layer not covered by the first gate layer forms a conductor structure.

[0133] As shown in FIGS. 20, 24, and 33, the second gate layer can include a first initial signal line Vinit1, a third gate line 2GT1, and a second conductive portion 22. The orthogonal projection of the first initial signal line Vinit1 on the substrate substrate and the orthogonal projection of the third gate line 2GT1 on the substrate substrate extend along the first direction X. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG. 18, and the third gate line 2GT1 can be used to provide the first gate driving signal terminal in FIG. 18. The orthogonal projection of the second conductive portion 22 on the substrate substrate can at least partially overlap the orthogonal projection of the first conductive portion 11 on the substrate substrate. The second conductive portion 22 can be used to form the second electrode of the capacitor C. The second gate layer can further include a second connecting portion 23. The second conductive portion 22 in each of the two adjacent pixel driving circuit groups in the first direction X is connected by the second connecting portion 23.

[0134] As shown in FIGS. 20, 25, and 34, the second active layer can include an active portion 9. The active portion 9 can include a second active portion 92, a nineteenth active portion 919, and a twentieth active portion 920 connected to both ends of the second active portion 92. The second active portion 92 can be used to form the channel region of the second transistor T2. The second active layer can be formed of indium gallium zinc oxide. Accordingly, the second transistor T2 can be an N-type metal oxide thin film transistor. The orthogonal projection of the third gate line 2GT1 on the substrate substrate can cover the orthogonal projection of the second active portion 92 on the substrate substrate. Part of the structure of the third gate line 2GT1 can be used to form the bottom gate of the second transistor T2.

[0135] As shown in FIGS. 20, 26, and 35, the third gate layer can include a first gate line 3GT1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthogonal projection of the first gate line 3GT1 on the substrate substrate, the orthogonal projection of the second initial signal line Vinit2 on the substrate substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate substrate can all extend along the first direction X. The first gate line 3GT1 can be used to provide the first gate driving signal terminal in FIG. 18. The orthogonal projection of the first gate line 3GT1 on the substrate substrate can cover the orthogonal projection of the second active portion 92 on the substrate substrate. Part of the structure of the first gate line 3GT1 can be used to form the top gate of the second transistor T2. Meanwhile, the first gate line 3GT1 can be connected to the third gate line 2GT1 through a via in the display panel frame region. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 18, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG. 18. In addition, the third gate layer can be used as a mask to perform a conductorization process on the second active layer. That is, the region of the second active layer covered by the third gate layer can form the channel region of the transistor, and the region of the second active layer not covered by the third gate layer can form a conductor structure.

[0136] As shown in FIGS. 20, 27, 36, the first source-drain layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, and a ninth bridge portion 49. The first bridge portion 41 is connected to the twelfth active portion 712 and the third initial signal line Vinit3 by a via, to connect the first electrode of the eighth transistor T8 and the third initial signal end. The second bridge portion 42 is connected to the ninth active portion 79, the seventeenth active portion 717, and the twentieth active portion 920 by a via, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 by a via, to connect the first electrode of the first transistor T1 and the first initial signal end. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 by a via, to connect the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridge portion 45 is connected to the thirteenth active portion 713 by a via, to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 by a via, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the second connection portion 23 and the fifteenth active portion 715 by a via, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5, wherein the same seventh bridge portion 47 is shared by two adjacent pixel driving circuit groups in the first direction X. The eighth bridge portion 48 is connected to the sixteenth active portion 716 by a via, to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the seventeenth active portion 917 and the first conductive portion 11 by a via, to connect the gate electrode of the driving transistor T3 and the first electrode of the second transistor T2, wherein an opening 221 can be formed on the second conductive portion 22, and the via between the ninth bridge portion 49 and the first conductive portion 11 is disposed in the opening 221.

[0137] As shown in FIGS. 20, 28, 37, the second source-drain layer can include the first connecting part 51, the tenth bridge part 510, the eleventh bridge part 511, and the first fan-out line FIPH. The orthogonal projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can be a row direction fan-out line for connecting data lines in the FIP (Fanout In Pixel). The tenth bridge part 510 can be connected to the fifth bridge part 45 through a via to connect the first electrode of the fourth transistor. In the same pixel driving circuit group, the first connecting part 51 is connected between two adjacent ninth bridge parts 59 in the first direction X. The eleventh bridge part 511 can be connected to the eighth bridge part 48 through a via to connect the second electrode of the sixth transistor T6.

[0138] As shown in FIGS. 20, 29, 38, the third source-drain layer can include the data line Da, the first power line VDD, the second fan-out line FIPV, and the twelfth bridge part 6120. The orthogonal projection of the data line Da, the first power line VDD, and the second fan-out line FIPV on the substrate can extend along the second direction Y. The data line Da is used to provide the data signal end in FIG. 18, and the first power line VDD is used to provide the first power end in FIG. 18. The data line Da can be connected to the tenth bridge part 510 through a via to connect the data signal end and the first electrode of the fourth transistor. The first power line VDD is used to provide the first power end in FIG. 18, and the first power line VDD can be a plurality of lines. One first power line VDD can be provided for each column of pixel driving circuits, and the first power line VDD can be connected to the first connecting part 51 through a via to provide a power signal to the pixel driving circuit corresponding thereto.

[0139] As shown in FIGS. 20, 29, 38, the first conductive block further includes a fourth conductive block 615 connected to one end of the third conductive block 613 away from the second conductive block 612. The orthogonal projection of the fourth conductive block 615 on the substrate and the orthogonal projection of the second active part 92 on the substrate at least partially overlap. The fourth conductive block 615 can be used to shade the second active part 92 to reduce the influence of light on the characteristics of the second transistor.

[0140] The second fan-out line FIPV can be a column direction fan-out line connecting data lines in a fan-out in pixel (FIP) region. Outside the FIP region, the second fan-out line FIPV and the first fan-out line FIPH can form a mesh structure which can connect a stable voltage terminal to reduce voltage difference of the terminal at different positions of the display panel. For example, the mesh structure can connect a common electrode layer in the display panel, which can be located on a side of the light emitting cell away from the substrate, and the common electrode layer is used to form a second electrode of the light emitting cell. The twelfth bridge 6120 can be connected to the eleventh bridge 511 through a via, and the twelfth bridge 6120 can also be connected to a first electrode of the light emitting cell.

[0141] As shown in FIGS. 20 and 30, the structure of the electrode layer is the same as the display panel shown in FIG. 5.

[0142] As shown in FIG. 39, it is a partial cross-sectional view of the display panel shown in FIG. 20 along the dashed line HH. The display panel can further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, a second planarization layer 109, a third planarization layer 110. Among them, the substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planarization layer 108, the second source-drain layer, the second planarization layer 109, the third source-drain layer, the third planarization layer 110, the electrode layer, and the pixel definition layer PDL are sequentially stacked. Among them, the pixel definition layer PDL is formed with a pixel opening H. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108, the second planarization layer 109, and the third planarization layer 110 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), and the like. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer, the second source-drain layer, and the third source-drain layer can include metal materials, such as one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer. The sheet resistance of any one of the first source-drain layer, the second source-drain layer, and the third source-drain layer can be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0143] As shown in FIGS. 40 and 41, FIG. 40 is a partial structure layout of the display panel shown in FIG. 11, and FIG. 41 is a partial structure layout of the display panel shown in FIG. 15. The structures of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in the display panels shown in FIGS. 40 and 41 can be the same as those of the display panel shown in FIG. 20.

[0144] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel can also be other structures, for example, the pixel driving circuit can be a 7T1C, 9T1C, or the like structure, and the display panel can also only include two source-drain layers, and accordingly, the first power supply line is located at the second source-drain layer.

[0145] It should be noted that, as shown in FIGS. 20-41, the black squares drawn on the side of the first source-drain layer away from the substrate substrate represent vias of the first source-drain layer connecting other levels facing the substrate substrate side; the black rectangles drawn on the side of the second source-drain layer away from the substrate substrate represent vias of the second source-drain layer connecting other levels facing the substrate substrate side, the black squares with chamfers drawn on the side of the third source-drain layer away from the substrate substrate represent vias of the third source-drain layer connecting other levels facing the substrate substrate side; the black circles drawn on the side of the electrode layer away from the substrate substrate represent vias of the electrode layer connecting other levels facing the substrate substrate side, and the vias at different positions can penetrate different insulating layers.

[0146] In addition, it should be noted that the proportions of the drawings in the present disclosure can be used as a reference in actual processes, but are not limited thereto, for example: the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only structural schematic diagrams. In addition, the adjectives first, second, and the like are only used to limit different structural names, and do not have the meaning of a specific order, and the same structure layer can be formed by the same patterning process. In the present exemplary embodiment, the orthogonal projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as that the orthogonal projection of the structure on the substrate substrate extends linearly or bends in the direction.

[0147] The present exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, a tablet computer, a television, or the like.

[0148] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the description herein, with the disclosure now being generally described. The present application intends to cover any variations, uses, or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the technical field of the present disclosure that are not disclosed by the present disclosure. The specification and examples are only considered as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0149] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

[0150] It should be understood that the present disclosure is not limited to the precise structures as herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of pixel driving circuit groups, a plurality of the pixel driving circuit groups are arrayed along a first direction and a second direction, the first direction and the second direction intersect, the pixel driving circuit group comprises two pixel driving circuits adjacent in the first direction, the orthographic projection of the two pixel driving circuits in the same pixel driving circuit group on the substrate substrate is at least partially mirror-symmetrically arranged; a plurality of first power lines, the orthographic projection of the first power line on the substrate substrate extends along the second direction, the first power line and the pixel driving circuit correspondingly arranged, the first power line is used for providing power signal to the pixel driving circuit corresponding thereto; the first power line comprises a first extension section, in the same pixel driving circuit group, the first extension section of two first power lines corresponding to two pixel driving circuits is connected, the connected two first extension sections form a conductive block, and a missing part is formed on the conductive block; an electrode layer comprising a plurality of electrode parts, the electrode part comprising a body part, the body part is used for forming a first electrode of a light-emitting unit; a pixel defining layer located on the side of the electrode layer away from the substrate substrate, a plurality of pixel openings are formed on the pixel defining layer, the pixel opening and the body part are correspondingly arranged, the orthographic projection of the body part on the substrate substrate and the orthographic projection of the pixel opening corresponding thereto on the substrate substrate coincide; a plurality of the body part includes a first body part and a second body part, the orthographic projection of the first body part on the substrate substrate and the orthographic projection of the first power line on the conductive layer on the substrate substrate partially overlap and partially do not overlap; the orthographic projection of the second body part on the substrate substrate and the orthographic projection of the conductive block on the substrate substrate partially overlap, and the orthographic projection of the second body part on the substrate substrate and the orthographic projection of the missing part on the substrate substrate partially overlap.

2. The display panel of claim 1, wherein, The missing part comprises a first notch and a second notch, the first notch and the second notch are located on both sides of the conductive block in the first direction; the orthographic projection of the second body part on the substrate substrate in the second direction The ends of the orthographic projection of the second body part on the substrate substrate in the second direction respectively and the orthographic projection of the first notch on the substrate substrate, the orthographic projection of the second notch on the substrate substrate at least partially overlap.

3. The display panel of claim 2, wherein, The second body part is composed of a first sub-body part and a second sub-body part, the separation line between the orthographic projection of the first sub-body part on the substrate substrate and the orthographic projection of the second sub-body part on the substrate substrate extends linearly along the first direction, the size of the orthographic projection of the first sub-body part on the substrate substrate in the second direction is equal to the size of the orthographic projection of the second sub-body part on the substrate substrate in the second direction; wherein, the overlapping area of the orthographic projection of the first sub-body part on the substrate substrate and the orthographic projection of the first notch on the substrate substrate is less than the overlapping area of the orthographic projection of the second sub-body part on the substrate substrate and the orthographic projection of the second notch on the substrate substrate.

4. The display panel according to any one of claims 1-3, wherein, The second body part is composed of a first sub-body part and a second sub-body part, a separation line between a projection of the first sub-body part on the substrate and a projection of the second sub-body part on the substrate extends linearly along the first direction, and a size of the projection of the first sub-body part on the substrate in the second direction is equal to a size of the projection of the second sub-body part on the substrate in the second direction; An overlapping area of the projection of the first sub-body part on the substrate and a projection of the conductive block on the substrate is greater than an overlapping area of the projection of the second sub-body part on the substrate and the projection of the conductive block on the substrate.

5. The display panel of claim 4, wherein, The conductive block includes a first conductive block, a second conductive block and a third conductive block, the second conductive block is connected between the first conductive block and the third conductive block; In a direction in which the projection of the first conductive block on the substrate faces the projection of the second conductive block on the substrate, a size of the projection of the first conductive block on the substrate in the first direction gradually decreases; A size of the projection of the third conductive block on the substrate in the first direction is less than a size of the projection of the second conductive block on the substrate in the first direction; The second body part is composed of a first sub-body part and a second sub-body part, a separation line between a projection of the first sub-body part on the substrate and a projection of the second sub-body part on the substrate extends linearly along the first direction, and a size of the projection of the first sub-body part on the substrate in the second direction is equal to a size of the projection of the second sub-body part on the substrate in the second direction; The projection of the first sub-body part on the substrate and the projection of the second conductive block on the substrate at least partially overlap, and the projection of the second sub-body part on the substrate and the projection of the second conductive block on the substrate at least partially overlap; The projection of the first sub-body part on the substrate and the projection of the first conductive block on the substrate at least partially overlap, and the projection of the second sub-body part on the substrate and the projection of the third conductive block on the substrate at least partially overlap.

6. The display panel of claim 5, wherein, The second conductive block includes an equal-width extension segment, the equal-width extension segment is connected to the first conductive block, and a size of any segment of the projection of the equal-width extension segment on the substrate in the second direction in the first direction is equal.

7. The display panel of claim 5, wherein, The second conductive block includes a first side edge, the first side edge includes a first extension line, a second extension line and a third extension line, the second extension line is connected between the first extension line and the third extension line, and the third conductive block is connected to the second extension line. A projection of the second body portion on the substrate substrate covers a projection of the first extension line on the substrate substrate, and a projection of the second body portion on the substrate substrate and a projection of the third extension line on the substrate substrate do not overlap.

8. The display panel according to any one of claims 1-7, wherein, The missing portion includes a first gap and a second gap, the first gap and the second gap are located on both sides of the conductive block in the first direction; The projection of the second body portion on the substrate substrate at least partially overlaps the projection of the first gap on the substrate substrate and the projection of the second gap on the substrate substrate at both ends in the first direction.

9. The display panel of claim 1, wherein, The missing portion includes a third gap, the third gap is located on one side of the conductive block in the second direction, and the projection of the third gap on the substrate substrate extends along the second direction; The projection of the third gap on the substrate substrate and the projection of the second body portion on the substrate substrate at least partially overlap, and the projection of the second body portion on the substrate substrate at least partially overlaps the projection of the conductive block on the substrate substrate at both ends in the first direction.

10. The display panel of claim 9, wherein, The missing portion further includes a fourth gap, the projection of the fourth gap on the substrate substrate is located on one side of the projection of the third gap on the substrate substrate in the second direction, and the projection of the third gap on the substrate substrate is located between the projection of the fourth gap on the substrate substrate and the projection of the conductive block on the substrate substrate; The size of the projection of the fourth gap on the substrate substrate in the first direction is greater than the size of the projection of the third gap on the substrate substrate in the first direction; The second body portion is composed of a first sub-body portion and a second sub-body portion, a separation line between the projection of the first sub-body portion on the substrate substrate and the projection of the second sub-body portion on the substrate substrate extends linearly along the first direction, and the size of the projection of the first sub-body portion on the substrate substrate in the second direction is equal to the size of the projection of the second sub-body portion on the substrate substrate in the second direction; The projection of the second sub-body portion on the substrate substrate and the projection of the fourth gap on the substrate substrate at least partially overlap, and the projection of the first sub-body portion on the substrate substrate and the projection of the fourth gap on the substrate substrate do not overlap.

11. The display panel of claim 1, wherein, The missing portion includes at least one strip-shaped opening, at least one projection of the strip-shaped opening on the substrate substrate extends along the second direction and is spaced apart along the first direction; The projection of the strip-shaped opening on the substrate substrate and the projection of the second body portion on the substrate substrate at least partially overlap.

12. The display panel of any of claims 2-8, wherein, Part of the first body portion in the plurality of first body portions is used to form a first electrode of a red light emitting unit, part of the first body portion in the plurality of first body portions is used to form a first electrode of a blue light emitting unit, and the second body portion is used to form a first electrode of a green light emitting unit; An overlapping area of a normal projection of the first body part for forming the first electrode of the blue light emitting unit on the substrate and a normal projection of the conductive layer where the first power line is located on the substrate is S1; An overlapping area of a normal projection of the first body part for forming the first electrode of the red light emitting unit on the substrate and a normal projection of the conductive layer where the first power line is located on the substrate is S2; An overlapping area of a normal projection of the second body part on the substrate and a normal projection of the conductive layer where the first power line is located on the substrate is S3; Wherein, |S3-S1| / S1 is 38%-58%, and or, |S3-S2| / S2 is 10%-30%.

13. The display panel according to any one of claims 1-11, wherein, Part of the first body parts in the plurality of first body parts are used for forming the first electrode of the red light emitting unit, part of the first body parts in the plurality of first body parts are used for forming the first electrode of the blue light emitting unit, and the second body part is used for forming the first electrode of the green light emitting unit.

14. The display panel according to any one of claims 1-11, wherein, The conductive layer where the first power line is located further comprises: A data line, a normal projection of which on the substrate extends along the second direction; A second fan-out line, a normal projection of which on the substrate extends along the second direction; The first power line further comprises a second extension section, which is connected between two adjacent first extension sections; Wherein, one or more of the normal projection of the data line, the second fan-out line, and the second extension section on the substrate and the normal projection of the first body part on the substrate overlap.

15. A display device, wherein, The display device comprises the display panel of any one of claims 1-14.

Images