Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a substrate, a plurality of sub-pixels (Pxij) and a plurality of first signal lines (L11) disposed on one side of the substrate, at least part of the sub-pixels (Pxij) comprising a pixel driving circuit, the pixel driving circuits of at least part of the sub-pixels (Pxij) forming a plurality of rows, the first signal lines (L11) corresponding to at least part of the pixel driving circuits in at least one row of the pixel driving circuits, the plurality of first signal lines (L11) extending along a first direction (X) and arranged along a second direction (Y), the first direction (X) intersecting the second direction (Y); the first signal lines (L11) and the corresponding pixel driving circuits are electrically connected in a direct connection manner.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising a substrate, a plurality of sub-pixels and a plurality of first signal lines disposed on one side of the substrate, at least part of the sub-pixels comprising a pixel driving circuit, the pixel driving circuits of the at least part of the sub-pixels forming a plurality of rows, the first signal lines corresponding to at least part of the pixel driving circuits in at least one row of the pixel driving circuits, the plurality of first signal lines extending along a first direction and being arranged along a second direction, the first direction intersecting the second direction.

[0006] The first signal line and the corresponding pixel driving circuit are electrically connected in a direct connection manner.

[0007] In an exemplary embodiment, the display substrate further comprises a plurality of first signal auxiliary lines corresponding to at least part of the first signal lines, the first signal auxiliary lines being located on the side away from the substrate of the corresponding first signal lines, and the first signal auxiliary lines and the corresponding first signal lines being electrically connected through a via hole.

[0008] In an exemplary embodiment, in a direction perpendicular to the plane on which the substrate is located, the pixel driving circuit comprises at least one transistor, the transistor comprising an active layer disposed on one side of the substrate, a control electrode located on the side away from the substrate of the active layer, a source electrode and a drain electrode located on the side away from the substrate of the control electrode.

[0009] The first signal line is arranged in the same layer as the active layer or the control electrode.

[0010] In an exemplary embodiment, the plurality of first signal lines comprises a plurality of initial signal lines and a plurality of scan control lines, the initial signal lines are arranged in the same layer as the active layer, and the scan control lines are arranged in the same layer as the control electrode.

[0011] The initial signal line is electrically connected to the active layer of at least one transistor in the corresponding pixel driving circuit, and the scan control line is at least partially overlapped with the orthographic projection of the active layer of at least one transistor in the corresponding pixel driving circuit on the substrate.

[0012] In an exemplary embodiment, the plurality of transistors comprises a third transistor as a driving transistor, a first transistor as a reset transistor, and a seventh transistor as a reset transistor, the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the plurality of initial signal lines comprises a first initial signal line and a second initial signal line.

[0013] The first initial signal line is electrically connected to the active layer of the first transistor, and the second initial signal line is electrically connected to the active layer of the seventh transistor.

[0014] In an exemplary embodiment, the first initial signal line and the active layer of the first transistor in the corresponding pixel driving circuit are integrally formed, and the second initial signal line and the active layer of the seventh transistor in the corresponding pixel driving circuit are integrally formed.

[0015] In an exemplary embodiment, the display substrate further comprises a first initial signal auxiliary line and a second initial signal auxiliary line, the plurality of first initial signal auxiliary lines correspond one-to-one to the plurality of first initial signal lines, and the plurality of second initial signal auxiliary lines correspond one-to-one to the plurality of second initial signal lines; the pixel driving circuit further comprises a capacitor, a first plate of the capacitor is arranged in the same layer as the control electrode, and a second plate of the capacitor is located between the control electrode and the source electrode and the drain electrode in a direction perpendicular to the plane on which the substrate lies.

[0016] The first initial signal auxiliary line and the second initial signal auxiliary line are arranged in the same layer as the source electrode and the drain electrode, or the first initial signal auxiliary line and the second initial signal auxiliary line are arranged in the same layer as the second plate of the capacitor; the first initial signal auxiliary line is electrically connected to the corresponding first initial signal line, and the second initial signal auxiliary line is electrically connected to the corresponding second initial signal line.

[0017] In an example embodiment, in the same pixel driving circuit, in the second direction, the first transistor and the seventh transistor are located on both sides of the capacitor and the third transistor, the first initial signal line and the first initial signal auxiliary line are located on the same side of the capacitor and the third transistor, and the second initial signal line and the seventh transistor are located on the same side of the capacitor and the third transistor.

[0018] In an example embodiment, in the same row of pixel driving circuits, the first initial signal auxiliary line and the corresponding first initial signal line at least partially overlap in the orthographic projection on the substrate, and the second initial signal auxiliary line and the corresponding second initial signal line at least partially overlap in the orthographic projection on the substrate; the first initial signal auxiliary line and the corresponding first initial signal line are electrically connected through a via, and the second initial signal auxiliary line and the corresponding second initial signal line are electrically connected through a via.

[0019] In an example embodiment, in the same pixel driving circuit, the orthographic projection of the third transistor on the substrate at least partially overlaps the orthographic projection of the capacitor on the substrate, and the first plate of the capacitor serves as the control electrode of the third transistor.

[0020] In an example embodiment, the plurality of scan control lines includes a first reset control line and a second reset control line.

[0021] The region where the first reset control line overlaps with the active layer of the first transistor serves as the control electrode of the first transistor, and the region where the second reset control line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor.

[0022] In the same pixel driving circuit, in the second direction, the first transistor and the seventh transistor are located on both sides of the third transistor, the first initial signal line is located on the side of the first reset control line away from the third transistor, and the second initial signal line is located on the side of the second reset control line away from the third transistor.

[0023] In an example embodiment, the display substrate further includes a plurality of first reset control auxiliary lines and a plurality of second reset control auxiliary lines, the plurality of first reset control auxiliary lines and the plurality of second reset control auxiliary lines are disposed in the same layer as the source and the drain; the plurality of first reset control auxiliary lines correspond one-to-one to the plurality of first reset control lines, and the plurality of second reset control auxiliary lines correspond one-to-one to the plurality of second reset control lines.

[0024] In the same row of pixel driving circuits, the first reset control auxiliary line and the first reset control line are at least partially overlapped in the orthographic projection on the substrate, and the second reset control auxiliary line and the second reset control line are at least partially overlapped in the orthographic projection on the substrate; the first reset control auxiliary line and the corresponding first reset control line are electrically connected through a via, and the second reset control auxiliary line and the corresponding second reset control line are electrically connected through a via.

[0025] In an example embodiment, the plurality of transistors further comprises a second transistor as a compensation transistor, a fourth transistor as a data writing transistor, the plurality of scan control lines comprises a scan signal line, an area where the scan signal line overlaps with an active layer of the second transistor as a control electrode of the second transistor, and an area where the scan signal line overlaps with an active layer of the fourth transistor as a control electrode of the fourth transistor.

[0026] In the same pixel driving circuit, in the second direction, the second transistor and the fourth transistor are located between the first transistor and the third transistor, and the scan signal line is located on one side of the first reset control line close to the third transistor.

[0027] In an example embodiment, the display substrate further comprises a plurality of scan signal auxiliary lines, the plurality of scan signal auxiliary lines are arranged in the same layer as the source electrode and the drain electrode, a main part of the plurality of scan signal auxiliary lines extends along the first direction and is arranged along the second direction; the plurality of scan signal auxiliary lines correspond to the plurality of scan signal lines one by one.

[0028] In the same row of pixel driving circuits, the scan signal auxiliary line is electrically connected to the corresponding scan signal line.

[0029] In an example embodiment, a plurality of scan signal connection structures are arranged on the scan signal auxiliary line, in the same row of pixel driving circuits, the plurality of scan signal connection structures are arranged at intervals along the first direction, in the second direction, the plurality of scan signal connection structures are located on one side of the main part of the scan signal auxiliary line close to the third transistor, and the main part of the scan signal auxiliary line is located between the scan signal line and the first reset control auxiliary line.

[0030] In the same row of pixel driving circuits, the plurality of scan signal connection structures on the scan signal auxiliary line are electrically connected to the corresponding scan signal line through a via.

[0031] In an exemplary embodiment, the plurality of transistors further comprises a fifth transistor and a sixth transistor as light emitting control transistors, the plurality of scan control lines further comprises a light emitting control line, a region where the light emitting control line overlaps with an active layer of the fifth transistor as a control electrode of the fifth transistor, and a region where the light emitting control line overlaps with an active layer of the sixth transistor as a control electrode of the sixth transistor.

[0032] In the same pixel driving circuit, in the second direction, the fifth transistor and the sixth transistor are located between the third transistor and the seventh transistor, and the light emitting control line is located between the third transistor and the second reset control line.

[0033] In an exemplary embodiment, a plurality of sub-pixels located in the same row form a plurality of pixel units, and at least two sub-pixels are included in the same pixel unit, and pixel driving circuits of the at least two sub-pixels are arranged in sequence along the first direction.

[0034] In the same row of pixel driving circuits, the first reset control auxiliary line and the first reset control line are electrically connected through a plurality of first connection vias, and the number of first connection vias in the same pixel unit does not exceed the number of sub-pixels in the pixel unit; and the second reset control auxiliary line and the second reset control line are electrically connected through a plurality of second connection vias, and the number of second connection vias in the same pixel unit does not exceed the number of sub-pixels in the pixel unit.

[0035] In an exemplary embodiment, in the same row of pixel driving circuits, one first connection via and one second connection via are arranged in n pixel units, and n is a positive integer greater than or equal to 1.

[0036] In a second aspect, the embodiments of the present disclosure further provide a display device, comprising the display substrate of any of the above-mentioned embodiments.

[0037] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0039] FIG. 1 is a structural schematic diagram of a display device;

[0040] FIG. 2 is a planar structural schematic diagram of a display substrate;

[0041] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0042] FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0043] FIG. 5a is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0044] FIG. 5b is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG. 5c is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG. 5d is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0047] FIG. 6a is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG. 6b is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0049] FIG. 7 is a schematic diagram of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0050] FIG. 8a is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0051] FIG. 8b is a schematic diagram of a first conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0052] FIG. 9a is a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0053] FIG. 9b is a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0054] FIG. 10 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0055] FIG. 11a is a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0056] FIG. 11b is a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0057] FIG. 12 is a schematic diagram of a display substrate after forming a first planar layer pattern according to an exemplary embodiment of the present disclosure;

[0058] FIG. 13a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0059] FIG. 13b shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0060] FIG. 13c shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0061] FIG. 13d shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0062] FIG. 14 shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0063] FIG. 15a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0064] FIG. 15b shows a schematic diagram of an anode conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG. 16a shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0066] FIG. 16b shows a schematic diagram of a pixel definition layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0067] FIG. 17a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0068] FIG. 17b shows a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0069] FIG. 18 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0070] FIG. 19a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0071] FIG. 19b shows a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0072] FIG. 20a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0073] FIG. 20b is a schematic view of the third conductive layer in the display substrate according to an example embodiment of the present disclosure;

[0074] FIG. 21 is a schematic view of the display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0075] FIG. 22 is a schematic view of the display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0076] FIG. 23 is a schematic view of the display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0077] FIG. 24a is a schematic view of the display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0078] FIG. 24b is a schematic view of the third conductive layer in the display substrate according to an example embodiment of the present disclosure;

[0079] FIG. 25 is a schematic view of a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] Embodiments of the present disclosure will be described in detail below with reference to the drawings. Although the embodiments can be implemented in various forms, one skilled in the art can easily understand that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, detailed description of some known functions and known components will be omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0081] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the thickness and interval of each film layer, the width and interval of each signal line, can be adjusted according to the actual situation. The drawings described in the present disclosure are only schematic views of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0082] The ordinal numbers "first", "second", "third", and the like in the specification are set to avoid confusion of the components, and are not intended to be limiting in terms of quantity.

[0083] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship of the components are used to describe the positional relationship of the components with reference to the drawings only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of each component described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0084] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0085] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0086] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other. In the embodiments of the present disclosure, the gate electrode can be referred to as the control electrode.

[0087] In this specification, "electrically connected" includes the case where the components are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the connected components. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0088] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, an angle of 85° or more and 95° or less is also included.

[0089] In this specification, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be sometimes changed into "conductive film". Similarly, "insulating film" can be sometimes changed into "insulating layer".

[0090] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like are not strictly so, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, an arc edge, and deformation, and the like.

[0091] In this specification, "about" in the embodiment of the present disclosure means not strictly limited to a limit, and allows a value within a range of process and measurement error.

[0092] FIG. 1 is a structural schematic of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit connected to the circuit unit, the circuit unit can include a pixel driving circuit, the pixel driving circuit being connected to the scan signal line, the data signal line, and the light emitting signal line, respectively. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3,..., and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. o can be a natural number.

[0093] FIG. 2 is a schematic diagram of a planar structure of a display substrate. In an example embodiment, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P can include a first sub-pixel P1 emitting light rays of a first color, a second sub-pixel P2 emitting light rays of a second color, and a third sub-pixel P3 emitting light rays of a third color, the three sub-pixels can each include a circuit unit and a light emitting unit, the circuit unit can include a pixel driving circuit, the pixel driving circuit is connected with a scan signal line, a data signal line, and a light emitting signal line respectively, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, output a corresponding current to the light emitting unit, and the light emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0094] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light rays, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light rays, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light rays. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular shape.

[0095] In another example embodiment, the pixel unit P can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, diamond, or square shape, which is not limited in the present disclosure.

[0096] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate. In some possible implementations, the display substrate can include other film layers, such as a spacer, which is not limited in the present disclosure.

[0097] In an example embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 (may be referred to as a circuit structure layer) of each sub-pixel can include a plurality of circuit units, which can include a pixel driving circuit composed of a plurality of transistors and a storage capacitor, and only one driving transistor and one storage capacitor are taken as an example for illustration in FIG. 3. The light-emitting structure layer 103 of each sub-pixel can include a plurality of light-emitting units, which can include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, the anode is connected to the drain electrode of the driving transistor through a via, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0098] In an example embodiment, the organic light-emitting layer can include an emission layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an example embodiment, the hole injection layer, the electron injection layer, the hole transport layer, the electron transport layer, the hole blocking layer, and the electron blocking layer of all light-emitting units can be common layers connected together, the emission layers of adjacent light-emitting units can have a small amount of overlap, or can be isolated.

[0099] FIG. 4 is an equivalent circuit schematic diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 4, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is connected to 9 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, light-emitting signal line E, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS).

[0100] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0101] In the example embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, i.e., the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0102] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit1, and the second electrode of the first transistor is connected to the second node N2. When the turn-on level scan signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

[0103] The control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the turn-on level scan signal is applied to the scan signal line Gate, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0104] The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0105] The control electrode of the fourth transistor T4 is connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is connected with the data signal line D, and the second electrode of the fourth transistor T4 is connected with the first node N1. The fourth transistor T4 can be referred to as a switch transistor, a scan transistor, etc., and when an on-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0106] The control electrode of the fifth transistor T5 is connected with the emission signal line E, the first electrode of the fifth transistor T5 is connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected with the first node N1. The control electrode of the sixth transistor T6 is connected with the emission signal line E, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the first electrode of the light emitting device EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When an on-level emission signal is applied to the emission signal line E, the fifth transistor T5 and the sixth transistor T6 make the light emitting device EL emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0107] The control electrode of the seventh transistor T7 is connected with the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected with the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting device EL. When an on-level scan signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits an initial voltage to the first electrode of the light emitting device EL to initialize the amount of charge accumulated in the first electrode of the light emitting device EL or release the amount of charge accumulated in the first electrode of the light emitting device EL.

[0108] In an exemplary embodiment, the light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0109] In an exemplary embodiment, the second electrode of the light emitting device EL is connected with the second power supply line VSS, and the signal of the second power supply line VSS is a continuously provided low-level signal. The signal of the first power supply line VDD is a continuously provided high-level signal.

[0110] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0111] In an example embodiment, the first transistor T1 to the seventh transistor T7 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0112] In an example embodiment, taking the 7 transistors in the pixel driving circuit in FIG. 4 as P-type transistors OLED as an example, the working process of the pixel driving circuit can include:

[0113] The first stage A1 is called a reset stage, the signal of the first reset control line Reset1 is a low level signal, and the signals of the scanning signal line Gate and the light emitting signal line E are high level signals. The signal of the first reset control line Reset1 is a low level signal, so that the first transistor T1 is turned on, and the signal of the initial signal line INIT is provided to the second node N2, so as to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the scanning signal line Gate, the second reset control line Reset2 and the light emitting signal line E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are disconnected, and the OLED does not emit light in this stage.

[0114] In the second stage A2, called data writing stage or threshold compensation stage, the signals of the scan signal line Gate and the second reset control line Reset2 are low level signals, the signals of the first reset control line Resetl and the emitting signal line E are high level signals, and the data signal line D outputs data voltage. In this stage, the second end of the storage capacitor C is low level, so the third transistor T3 is turned on. The signals of the scan signal line Gate and the second reset control line Reset2 are low level signals, so the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage outputted by the data signal line D is provided to the second node N2 through the first node Nl, the turned-on third transistor T3 and the third node N3, and the difference between the data voltage outputted by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, so that the voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage outputted by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode of the OLED is emptied, the initialization is completed, and it is ensured that the OLED does not emit light. The signal of the first reset control line Resetl is high level signal, so the first transistor Tl is turned off. The signal of the emitting signal line E is high level signal, so the fifth transistor T5 and the sixth transistor T6 are turned off.

[0115] In the third stage A3, called emitting stage, the signal of the emitting signal line E is low level signal, and the signals of the scan signal line Gate, the second reset control line Reset2 and the first reset control line Resetl are high level signals. The signal of the emitting signal line E is low level signal, so the fifth transistor T5 and the sixth transistor T6 are turned on, the power voltage outputted by the first power supply line VDD is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the OLED is driven to emit light.

[0116] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the third transistor T3. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd) 2

[0117] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power voltage output by the first power supply line VDD.

[0118] The product film layer stack in the OLED display substrate is complex, process control is difficult, process fluctuation of each batch of products is large, and via hole loss or blind via hole (that is, a defect of via hole failure) often occurs. The signal cannot be written in the via hole loss position (that is, the signal cannot be transmitted in the via hole loss position), so that via hole failure (the failure categories caused by blind via holes of different positions and different signals are different, such as bright and dark spots) occurs. Especially for large-size products, the product size is large, the number of chips is low, and the cost loss caused by via hole failure is large (for example, the blind via hole failure rate of a certain large-size product is about 0.5-1%). There is a technical problem of high product preparation cost and low efficiency caused by via hole failure.

[0119] The display substrate provided by the example embodiments of the present disclosure can include a substrate, a plurality of sub-pixels Pxij arranged on one side of the substrate, and a plurality of first signal lines L11. At least part of the sub-pixels Pxij includes a pixel driving circuit, and the pixel driving circuits of the at least part of the sub-pixels Pxij form a plurality of rows. The first signal lines L11 correspond to at least part of the pixel driving circuits in at least one row of the pixel driving circuits. The plurality of first signal lines L11 extend along a first direction X and are arranged along a second direction Y. The first direction X intersects the second direction Y.

[0120] The first signal lines L11 are electrically connected to the corresponding pixel driving circuits in a direct connection manner.

[0121] The display substrate provided by the example embodiments of the present disclosure can include a substrate, a plurality of sub-pixels Pxij arranged on one side of the substrate, and a plurality of first signal lines L11. At least part of the sub-pixels Pxij includes a pixel driving circuit, and the pixel driving circuits of the at least part of the sub-pixels Pxij form a plurality of rows. The first signal lines L11 correspond to at least part of the pixel driving circuits in at least one row of the pixel driving circuits. The plurality of first signal lines L11 extend along a first direction X and are arranged along a second direction Y. The first direction X intersects the second direction Y.

[0122] As shown in FIGS. 5a-5d, the display substrate can include a substrate, a plurality of sub-pixels Pxij arranged on one side of the substrate, and a plurality of first signal lines L11. At least part of the sub-pixels Pxij includes a pixel driving circuit, and the pixel driving circuits of the at least part of the sub-pixels Pxij form a plurality of rows. The first signal lines L11 correspond to at least part of the pixel driving circuits in at least one row of the pixel driving circuits. The plurality of first signal lines L11 extend along a first direction X and are arranged along a second direction Y. The first direction X intersects the second direction Y.

[0123] The first signal lines L11 are electrically connected to the corresponding pixel driving circuits in a direct connection manner.

[0124] In an exemplary embodiment, the display substrate can further include a plurality of first signal auxiliary lines L12 corresponding to at least part of the first signal lines L11, the first signal auxiliary lines L12 being located on a side of the corresponding first signal lines L11 away from the substrate, and the first signal auxiliary lines L12 being electrically connected to the corresponding first signal lines L11 by vias. By electrically connecting the first signal auxiliary lines L12 to the corresponding first signal lines L11 by vias (i.e., multi-layer parallel connection), the voltage drop of the first signal lines L11 can be reduced, and the display uniformity can be improved.

[0125] In an exemplary embodiment, in a direction perpendicular to the plane on which the substrate lies, the pixel driving circuit can include at least one transistor, the transistor can include an active layer disposed on one side of the substrate, a control electrode located on a side of the active layer away from the substrate, a source electrode and a drain electrode located on a side of the control electrode away from the substrate.

[0126] The first signal lines L11 can be disposed in the same layer as the active layer or the control electrode.

[0127] In an exemplary embodiment, the plurality of first signal lines L11 can include a plurality of initial signal lines and a plurality of scan control lines, the initial signal lines can be disposed in the same layer as the active layer, and the scan control lines can be disposed in the same layer as the control electrode.

[0128] The initial signal lines are electrically connected (e.g., can be directly connected) to the active layer of at least one transistor in the corresponding pixel driving circuit, and the scan control lines at least partially overlap the orthographic projection of the active layer of at least one transistor in the corresponding pixel driving circuit on the substrate.

[0129] In an exemplary embodiment, the plurality of transistors can include a third transistor T3 as a driving transistor, a first transistor T1 as a reset transistor, and a seventh transistor T7 as a reset transistor, the second electrode of the first transistor T1 being electrically connected to the control electrode of the third transistor T3; the plurality of initial signal lines can include a first initial signal line Vinit1 and a second initial signal line Vinit2.

[0130] The first initial signal line Vinit1 can be electrically connected to the active layer of the first transistor T1, and the second initial signal line Vinit2 can be electrically connected to the active layer of the seventh transistor T7.

[0131] In the example embodiment, the first initial signal line Vinit1 can be integrally formed with the active layer of the first transistor T1 in the corresponding pixel driving circuit, and the second initial signal line Vinit2 can be integrally formed with the active layer of the seventh transistor T7 in the corresponding pixel driving circuit, that is, the first initial signal line Vinit1 and the second initial signal line Vinit2 do not need to be electrically connected to the active layer of the corresponding transistor through a via, which can avoid the technical problem that the initial signal cannot be written due to poor via, thereby improving product yield and reducing preparation cost.

[0132] In the example embodiment, as shown in FIGS. 5b and 5c, the display substrate can further include a plurality of first initial signal auxiliary lines Vinit11 (L12) and a plurality of second initial signal auxiliary lines Vinit21 (L12), the plurality of first initial signal auxiliary lines Vinit11 correspond to the plurality of first initial signal lines Vinit1 one by one, and the plurality of second initial signal auxiliary lines Vinit21 can correspond to the plurality of second initial signal lines Vinit2 one by one; the pixel driving circuit can further include a capacitor C, a first plate 23 of the capacitor C can be disposed in the same layer as the control electrode, and in a direction perpendicular to the plane in which the substrate is located, a second plate 31 of the capacitor C can be located between the control electrode and the source electrode and the drain electrode.

[0133] The first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 can be disposed in the same layer as the source electrode and the drain electrode, or the first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 are disposed in the same layer as the second plate 31 of the capacitor C, the first initial signal auxiliary line Vinit11 can be electrically connected to the corresponding first initial signal line Vinit1 (i.e., double-layer parallel connection), and the second initial signal auxiliary line Vinit21 can be electrically connected to the corresponding second initial signal line Vinit2 (i.e., double-layer parallel connection), which can reduce the voltage drop of the first initial signal line Vinit1 and the second initial signal line Vinit2, and improve display uniformity.

[0134] In the example embodiment, as shown in FIGS. 5b and 5c, in the same pixel driving circuit, in the second direction Y, the first transistor T1 and the seventh transistor T7 can be located on both sides of the capacitor C and the third transistor T3, the first initial signal line Vinit1 and the first initial signal auxiliary line Vinit11 are located on the same side of the capacitor C and the third transistor T3 as the first transistor T1, and the second initial signal line Vinit2 and the second initial signal auxiliary line Vinit21 are located on the same side of the capacitor C and the third transistor T3 as the seventh transistor T7.

[0135] In the exemplary embodiments, in the same row pixel driving circuit, the first initial signal auxiliary line Vinit11 and the corresponding first initial signal line Vinit1 at least partially overlap in the orthographic projection on the substrate, and the second initial signal auxiliary line Vinit21 and the corresponding second initial signal line Vinit2 at least partially overlap in the orthographic projection on the substrate; the first initial signal auxiliary line Vinit11 and the corresponding first initial signal line Vinit1 are electrically connected through the via hole, and the second initial signal auxiliary line Vinit21 and the corresponding second initial signal line Vinit2 are electrically connected through the via hole.

[0136] In the exemplary embodiments, as shown in FIGS. 5b-5c, in the same pixel driving circuit, the orthographic projection of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the capacitor C on the substrate, and the first plate 23 of the capacitor C can serve as the control electrode of the third transistor T3.

[0137] In the exemplary embodiments, as shown in FIGS. 5a-5d, the plurality of scan control lines can include a first reset control line 21 and a second reset control line 25.

[0138] The region where the first reset control line 21 overlaps with the active layer of the first transistor T1 can serve as the control electrode of the first transistor T1, and the region where the second reset control line 25 overlaps with the active layer of the seventh transistor T7 can serve as the control electrode of the seventh transistor T7.

[0139] In the same pixel driving circuit, in the second direction Y, the first transistor T1 and the seventh transistor T7 can be located on both sides of the third transistor T3, the first initial signal line Vinit1 can be located on the side of the first reset control line 21 away from the third transistor T3, and the second initial signal line Vinit2 can be located on the side of the second reset control line 25 away from the third transistor T3.

[0140] In the exemplary embodiments, the region where the first reset control line 21 overlaps with the active layer of the first transistor T1 directly serves as the control electrode of the first transistor T1, and the region where the second reset control line 25 overlaps with the active layer of the seventh transistor T7 directly serves as the control electrode of the seventh transistor T7. The first reset control line 21 does not need to be electrically connected to the control electrode of the first transistor T1 through the via hole, and the second reset control line 25 needs to be electrically connected to the control electrode of the seventh transistor T7 through the via hole. This can avoid the situation that the signal of the first reset control line 21 cannot be written into the first transistor T1 due to poor via hole, and the situation that the signal of the second reset control line 25 cannot be written into the seventh transistor T7 due to poor via hole, thereby reducing the risk of poor via hole, improving product yield, and reducing preparation cost.

[0141] In an exemplary embodiment, as shown in FIGS. 5a-5d, the display substrate can further include a plurality of first reset control auxiliary lines 46 and a plurality of second reset control auxiliary lines 48, which are arranged in the same layer as the source and the drain; the plurality of first reset control auxiliary lines 46 correspond to the plurality of first reset control lines 21 one by one, and the plurality of second reset control auxiliary lines 48 correspond to the plurality of second reset control lines 25 one by one.

[0142] In the same row of pixel driving circuits, the orthographic projection of the first reset control auxiliary line 46 and the corresponding first reset control line 21 on the substrate at least partially overlaps, and the orthographic projection of the second reset control auxiliary line 48 and the corresponding second reset control line 25 on the substrate at least partially overlaps; the first reset control auxiliary line 46 and the corresponding first reset control line 21 are electrically connected through a via, and the second reset control auxiliary line 48 and the corresponding second reset control line 25 are electrically connected through a via.

[0143] In an exemplary embodiment, the first reset control auxiliary line 46 and the corresponding first reset control line 21 are electrically connected through a via (i.e., double-layer parallel connection), and the second reset control auxiliary line 48 and the corresponding second reset control line 25 are electrically connected through a via (i.e., double-layer parallel connection), which can reduce the voltage drop of the first reset control line 21 and the second reset control line 25 and improve display uniformity.

[0144] In an exemplary embodiment, as shown in FIGS. 5a-5d, the plurality of transistors can further include a second transistor T2 as a compensation transistor and a fourth transistor T4 as a data writing transistor, and the plurality of scan control lines can include a scan signal line 22, the region where the scan signal line 22 overlaps with the active layer of the second transistor T2 can be used as the control electrode of the second transistor T2, and the region where the scan signal line 22 overlaps with the active layer of the fourth transistor T4 can be used as the control electrode of the fourth transistor T4.

[0145] In the same pixel driving circuit, in the second direction Y, the second transistor T2 and the fourth transistor T4 can be located between the first transistor T1 and the third transistor T3, and the scan signal line 22 is located on the side of the first reset control line 21 close to the third transistor T3.

[0146] In the example embodiment, the region where the scan signal line 22 overlaps with the active layer of the second transistor T2 can serve as the control electrode of the second transistor T2, and the region where the scan signal line 22 overlaps with the active layer of the fourth transistor T4 can serve as the control electrode of the fourth transistor T4. The scan signal line 22 does not need to be electrically connected to the control electrodes of the second transistor T2 and the fourth transistor T4 through a via, which can avoid the situation that the signal of the scan signal line 22 cannot be written into the second transistor T2 and the fourth transistor T4 due to poor via, thereby reducing the risk of poor via, improving product yield, and reducing production cost.

[0147] In the example embodiment, as shown in FIGS. 5a-5d, the display substrate can further include a plurality of scan signal auxiliary lines 47, which are arranged in the same layer as the source and the drain. The main part of the plurality of scan signal auxiliary lines 47 can extend along the first direction X and be arranged along the second direction Y. The plurality of scan signal auxiliary lines 47 can correspond to the plurality of scan signal lines 22 one-to-one.

[0148] In the same row of pixel driving circuits, the scan signal auxiliary line 47 can be electrically connected to the corresponding scan signal line 22.

[0149] In the example embodiment, the scan signal auxiliary line 47 can be electrically connected to the corresponding scan signal line 22 (i.e., double-layer parallel connection), which can reduce the voltage drop of the scan signal line 22 and improve display uniformity.

[0150] In the example embodiment, the scan signal auxiliary line 47 can be provided with a plurality of scan signal connection structures 471. In the same row of pixel driving circuits, the plurality of scan signal connection structures can be arranged at intervals along the first direction X. In the second direction Y, the plurality of scan signal connection structures 471 can be located on the side of the main part of the scan signal auxiliary line 47 close to the third transistor T3, and the main part of the scan signal auxiliary line 47 is located between the scan signal line 22 and the first reset control auxiliary line 46.

[0151] In the same row of pixel driving circuits, the scan signal connection structure 471 on the scan signal auxiliary line 47 can be electrically connected to the corresponding scan signal line 22 through a via.

[0152] In the example embodiment, as shown in FIGS. 5a-5d, the plurality of transistors can further include a fifth transistor T5 and a sixth transistor T6 as light-emitting control transistors, and the plurality of scan control lines can further include a light-emitting control line 24. The region where the light-emitting control line 24 overlaps with the active layer of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, and the region where the light-emitting control line 24 overlaps with the active layer of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6.

[0153] In the same pixel driving circuit, in the second direction Y, the fifth transistor T5 and the sixth transistor T6 can be located between the third transistor T3 and the seventh transistor T7, and the light-emitting control line 24 can be located between the third transistor T3 and the second reset control line 25.

[0154] In the exemplary embodiments, the region where the light-emitting control line 24 overlaps with the active layer of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, the region where the light-emitting control line 24 overlaps with the active layer of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6, and the light-emitting control line 24 does not need to be electrically connected to the control electrodes of the fifth transistor T5 and the sixth transistor T6 through a via, which can avoid the risk of the signal of the light-emitting control line 24 failing to be written into the fifth transistor T5 and the sixth transistor T6 due to a poor via, thereby reducing the risk of a poor via, improving product yield, and reducing production costs.

[0155] In the exemplary embodiments, as shown in FIGS. 5a-5d, a plurality of sub-pixels Pxij located in the same row can form a plurality of pixel units P; at least two sub-pixels Pxij can be included in the same pixel unit P, and the pixel driving circuits of the at least two sub-pixels Pxij are arranged in sequence along the first direction X.

[0156] In the same row of pixel driving circuits, the first reset control auxiliary line 46 and the first reset control line 21 can be electrically connected through a plurality of first connection vias VM1, and the number of first connection vias VM1 in the same pixel unit P is not more than the number of sub-pixels Pxij in the pixel unit P; the second reset control auxiliary line 48 and the second reset control line 25 can be electrically connected through a plurality of second connection vias VM2, and the number of second connection vias VM2 in the same pixel unit P is not more than the number of sub-pixels Pxij in the pixel unit P.

[0157] In the exemplary embodiments, as shown in FIG. 5d, in the same row of pixel driving circuits, one first connection via VM1 and one second connection via VM2 can be provided in n pixel units P, where n is a positive integer greater than or equal to 1, for example, in the same row of pixel driving circuits, one first connection via VM1 and one second connection via VM2 can be provided in the same pixel unit P.

[0158] In the exemplary embodiments, one pixel unit P can include three sub-pixels Pxij, and one first connection via VM1 and one second connection via VM2 can be provided in the pixel unit P containing the three sub-pixels Pxij, instead of providing three first connection vias VM1 and three second connection vias VM2, which can reduce the number of vias and the via density, increase the line width and line spacing of the signal line, and improve product yield.

[0159] In the exemplary embodiments, in the structure shown in FIG. 5d, one pixel unit P can be provided with one first connection via VM1 and one second connection via VM2, but is not limited thereto. For example, in the same row of pixel driving circuits, n pixel units P can be provided with one first connection via VM1 and one second connection via VM2, where n can be a positive integer greater than or equal to 1. For example, two pixel units P can be provided with one first connection via VM1 and one second connection via VM2, or three pixel units P can be provided with one first connection via VM1 and one second connection via VM2. In a row of pixel driving circuits, n pixel units P can be provided with one first connection via VM1 and one second connection via VM2, which can greatly reduce the number of vias and the via density, increase the line width and line spacing of the signal line, and improve the product yield.

[0160] In the exemplary embodiments, as shown in FIG. 6a, it is a schematic diagram of a display substrate structure. In the structure shown in FIG. 6a, the control electrode T2g of the second transistor T2 and the control electrode T4g of the fourth transistor T4 exist independently, that is, in a row of pixel driving circuits, the control electrodes T2g of the second transistors T2 and the control electrodes T4g of the fourth transistors T4 in a plurality of sub-pixels Pxij are independent of each other, and the control electrodes T2g of the second transistors T2 and the control electrodes T4g of the fourth transistors T4 in adjacent two sub-pixels Pxij are not connected to each other. The scanning signal line 22 needs to be electrically connected to the control electrodes T2g of the second transistors T2 and the control electrodes T4g of the fourth transistors T4 through vias. If the via for electrically connecting the scanning signal line 22 to the control electrodes T2g of the second transistors T2 and the control electrodes T4g of the fourth transistors T4 in one sub-pixel Pxij is missing (the via is defective), the signal of the scanning signal line 22 cannot be written into the corresponding second transistor T2 and fourth transistor T4, resulting in an increase in product defect rate and an increase in manufacturing cost. In the embodiments of the present disclosure, as shown in FIGS. 5a to 5d, the area where the scanning signal line 22 overlaps with the active layer of the second transistor T2 can be used as the control electrode of the second transistor T2, and the area where the scanning signal line 22 overlaps with the active layer of the fourth transistor T4 can be used as the control electrode of the fourth transistor T4. The scanning signal line 22 does not need to be electrically connected to the control electrodes of the second transistor T2 and the fourth transistor T4 through vias, which can avoid the signal of the scanning signal line 22 from being unable to be written into the second transistor T2 and the fourth transistor T4 due to the via defect, thereby reducing the risk of via defect, improving the product yield, and reducing the manufacturing cost.

[0161] In the structure shown in FIG. 6a, in an exemplary embodiment, the first initial signal line Vinit1 needs to be electrically connected to the active layer of the first transistor T1 through a via hole. In the case where the via hole connected to the first initial signal line Vinit1 in one of the sub-pixels Pxij is missing, the signal of the first initial signal line Vinit1 cannot be written into the corresponding first transistor T1, resulting in an increase in product failure rate and manufacturing cost. Similarly, the second initial signal line Vinit2 in FIG. 6a needs to be electrically connected to the active layer of the seventh transistor T7 through a via hole. In the case where the via hole connected to the second initial signal line Vinit2 in one of the sub-pixels Pxij is missing, the signal of the second initial signal line Vinit2 cannot be written into the corresponding seventh transistor T7, resulting in an increase in product failure rate and manufacturing cost. In the embodiments of the present disclosure, as shown in FIGS. 5a to 5d, the first initial signal line Vinit1 is integrally formed with the active layers of the plurality of first transistors T1 in a row of pixel driving circuits (the first initial signal line Vinit1 is pulled along the first direction X), and the second initial signal line Vinit2 is integrally formed with the active layers of the plurality of seventh transistors T7 in a row of pixel driving circuits (the second initial signal line Vinit2 is pulled along the first direction X), which can avoid the technical problem that the initial signal cannot be written due to the poor via hole, thereby improving the product yield and reducing the preparation cost.

[0162] In an exemplary embodiment, the above-mentioned implementation scheme can be applied to the 7T1C pixel driving circuit as shown in FIG. 4, but is not limited thereto, for example, can be applied to the 8T1C pixel driving circuit as shown in FIG. 6b. The difference between FIG. 6b and FIG. 4 is that an eighth transistor T8 is added, the control electrode of the eighth transistor T8 is electrically connected to the second reset control line Reset2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line Vinit3, and the second electrode of the eighth transistor T8 can be electrically connected to the first electrode of the third transistor T3.

[0163] In an exemplary embodiment, in the pixel driving circuit shown in FIG. 4, the above-mentioned first signal line can include an initial signal line and a scan control line, wherein the initial signal line can include a first initial signal line Vinit1 and a second initial signal line Vinit2, and the scan control line can include a first reset control line 21 (i.e. Reset1 in FIG. 4), a second reset control line 25 (i.e. Reset2 in FIG. 4), a scan signal line 22 (i.e. Gate in FIG. 4), and a light-emitting control line 24 (i.e. light-emitting signal line E in FIG. 4).

[0164] In the pixel driving circuit shown in FIG. 6b, in an exemplary embodiment, the first signal line can include an initial signal line and a scan control line, wherein the initial signal line can include a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3, and the scan control line can include a first reset control line 21 (i.e., Reset1 in FIG. 6b), a second reset control line 25 (i.e., Reset2 in FIG. 6b), a scan signal line 22 (i.e., Gate in FIG. 6b), and a light-emitting control line 24 (i.e., light-emitting signal line E in FIG. 6b).

[0165] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, etc. for organic materials. The deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can use any one or more of spraying, spin coating, and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a material made on a substrate (or a substrate substrate) by deposition, coating, or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0166] In an exemplary embodiment, taking three sub-pixels (3 pixel driving circuits in 1 sub-pixel row and 3 sub-pixel columns) in the display area (AA) as an example, the preparation process of one display substrate can include the following operations:

[0167] (101) A substrate is prepared on a glass carrier. In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an example embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing into a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0168] (102) A semiconductor layer pattern is formed. In an example embodiment, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film by a patterning process, forming a first insulating layer covering the barrier layer pattern, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 7, which is a plan view of three sub-pixel semiconductor layers.

[0169] In an example embodiment, the semiconductor layer pattern of at least part of the sub-pixels can include the active layer 11 of the first transistor T1 to the active layer 17 of the seventh transistor T7, the first initial signal line Vinit1, and the second initial signal line Vinit2, which are an integrated structure connected to each other in the same pixel driving circuit.

[0170] In the exemplary embodiment, in the first direction X, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on the same side of the active layer 13 of the third transistor T3, and the active layer 12 of the second transistor T2 and the active layer 16 of the sixth transistor T6 are located on the other side of the active layer 13 of the third transistor T3; in the second direction Y, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on both sides of the active layer 13 of the third transistor T3, and the active layer 15 of the fifth transistor T5, the active layer 16 of the sixth transistor T6, and the active layer 17 of the seventh transistor T7 are located on the same side of the active layer 13 of the third transistor T3, the active layer 14 of the fourth transistor T4, the active layer 12 of the second transistor T2, and the active layer 11 of the first transistor T1 are located on the same side of the active layer 13 of the third transistor T3, the active layer 17 of the seventh transistor T7 is located on the side of the active layer 16 of the sixth transistor T6 away from the active layer 12 of the second transistor T2, the active layer 11 of the first transistor T1 is located on the side of the active layer 12 of the second transistor T2 away from the active layer 16 of the sixth transistor T6, the first initial signal line Vinit1 is located on the side of the active layer 11 of the first transistor T1 away from the active layer 12 of the second transistor T2, and the second initial signal line Vinit2 is located on the side of the active layer 17 of the seventh transistor T7 away from the active layer 16 of the sixth transistor T6.

[0171] In the exemplary embodiment, taking the sub-pixel in the Mth row and the Nth column as an example: in the first direction X, the active layer 14 of the fourth transistor T4 and the active layer 15 of the fifth transistor T5 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixels in the N-1th column, and the active layer 12 of the second transistor T2 and the active layer 16 of the sixth transistor T6 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixels in the N+1th column; in the second direction Y, the active layer 11 of the first transistor T1, the active layer 12 of the second transistor T2, and the active layer 14 of the fourth transistor T4 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixels in the M+1th row, the active layer 15 of the fifth transistor T5, the active layer 16 of the sixth transistor T6, and the active layer 17 of the seventh transistor T7 are located on the side of the active layer 13 of the third transistor T3 away from the sub-pixels in the M-1th row, the active layer 17 of the seventh transistor T7 is located on the side of the active layer 16 of the sixth transistor T6 away from the active layer 13 of the third transistor T3, the active layer 11 of the first transistor T1 is located on the side of the active layer 12 of the second transistor T2 away from the active layer 13 of the third transistor T3, the first initial signal line Vinit1 is located on the side of the active layer 11 of the first transistor T1 away from the active layer 12 of the second transistor T2, and the second initial signal line Vinit2 is located on the side of the active layer 17 of the seventh transistor T7 away from the active layer 16 of the sixth transistor T6.

[0172] In the example embodiment, the first initial signal line Vinit1 and the second initial signal line Vinit2 are in the shape of a bar or a broken line extending in the first direction X, the active layer 11 of the first transistor T1 can be in the shape of an "I" or a "T", the active layer 12 of the second transistor T2, the active layer 15 of the fifth transistor T5, and the active layer 17 of the seventh transistor T7 can be in the shape of an "L", the active layer 13 of the third transistor T3 can be in the shape of a bar, and the active layer 14 of the fourth transistor T4 and the active layer 16 of the sixth transistor T6 can be in the shape of an "I".

[0173] In the example embodiment, the active layer of at least part of the transistors can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region 13-1 of the active layer 13 of the third transistor T3 can serve as the second region 14-2 of the active layer 14 of the fourth transistor T4 and the second region 15-2 of the active layer 15 of the fifth transistor T5, the second region 13-2 of the active layer 13 of the third transistor T3 can serve as the second region 12-2 of the active layer 12 of the second transistor T2 and the first region 16-1 of the active layer 16 of the sixth transistor T6, the second region 16-2 of the active layer 16 of the sixth transistor T6 can serve as the second region 17-2 of the active layer 17 of the seventh transistor T7, the second region 11-2 of the active layer 11 of the first transistor T1 can serve as the first region 12-1 of the active layer 12 of the second transistor T2, and the first region 11-1 of the active layer 11 of the first transistor T1, the first region 14-1 of the active layer 14 of the fourth transistor T4, the first region 15-1 of the active layer 15 of the fifth transistor T5, and the first region 17-1 of the active layer 17 of the seventh transistor T7 can be separately provided. The first region 11-1 of the active layer 11 of the first transistor T1 can be connected to the first initial signal line Vinit1, the first region 17-1 of the active layer 17 of the seventh transistor T7 can be connected to the second initial signal line Vinit2, the first initial signal line Vinit1 can be connected to the first region 11-1 of the active layer 11 of the first transistor T1 in a row of pixel driving circuits, and the second initial signal line Vinit2 can be connected to the first region 17-1 of the active layer 17 of the seventh transistor T7 in a row of pixel driving circuits.

[0174] In the example embodiment, the shapes of the active layers of the plurality of sub-pixels can be consistent (may be substantially consistent).

[0175] In the example embodiment, the semiconductor layer can adopt polycrystalline silicon (p-Si), i.e., the first transistor T1 to the seventh transistor T7 can be LTPS thin film transistors. In the example embodiment, the patterning of the semiconductor thin film through the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment, and forming a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a semiconductor layer pattern.

[0176] (103) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film through a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 8a and 8b, FIG. 8b being a plan view of the first conductive layer in FIG. 8a. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0177] In the example embodiment, the first conductive layer pattern can at least include: a first reset control line 21, a scan signal line 22, a first plate of a capacitor 23, a light-emitting control line 24, and a second reset control line 25. The main body portions of the first reset control line 21, the scan signal line 22, the light-emitting control line 24, and the second reset control line 25 can extend along the first direction X, and in the same sub-pixel, the first reset control line 21, the scan signal line 22, the first plate of the capacitor 23, the light-emitting control line 24, and the second reset control line 25 can be arranged at intervals along the second direction Y.

[0178] In the example embodiment, in the second direction Y, the scan signal line 22 and the light-emitting control line 24 are located on the two sides of the first plate of the capacitor 23, and the scan signal line 22 is located on the side of the scan signal line 22 away from the first plate of the capacitor 23. For example, in the second direction Y, the first reset control line 21, the scan signal line 22, the first plate of the capacitor 23, the light-emitting control line 24, and the second reset control line 25 are arranged in sequence.

[0179] Taking the Mth row and Nth column sub-pixel as an example, in the second direction Y, the light-emitting control line 24 can be located on the side of the first plate of the capacitor 23 of the sub-pixel close to the M+1th row sub-pixel; the scan signal line 22 can be located on the side of the light-emitting control line 24 away from the first plate of the capacitor 23, the first reset control line 21 can be located on the side of the scan signal line 22 close to the M-1th row sub-pixel, and the second reset control line 25 can be located on the side of the light-emitting control line 24 close to the M+1th row sub-pixel.

[0180] In the exemplary embodiment, in the second direction Y, the first plate 23 can be located between the light-emitting control line 24 and the scan signal line 22, the first plate 23 can be rectangular, the corners of the rectangular shape can be provided with chamfers, and the orthographic projection of the first plate 23 on the substrate overlaps the orthographic projection of the active layer of the third transistor T3 on the substrate. In the exemplary embodiment, the first plate 23 can simultaneously serve as one plate of the storage capacitor and the control electrode of the third transistor T3.

[0181] In the exemplary embodiment, the area where the first reset control line 21 (which can serve as the first reset control line Reset1 in FIG. 4) overlaps the active layer of the first transistor T1 can serve as the control electrode of the first transistor T1; the area where the scan signal line 22 (which can serve as the second reset control line Reset2 in FIG. 4) overlaps the active layer of the second transistor T2 can serve as the control electrode of the second transistor T2, the area where the scan signal line 22 overlaps the active layer of the fourth transistor T4 can serve as the control electrode of the fourth transistor T4; the area where the light-emitting control line 24 (which can serve as the light-emitting signal line E in FIG. 4) overlaps the active layer of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, the area where the light-emitting control line 24 overlaps the active layer of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6; and the area where the second reset control line 25 (which can serve as the second reset control line Reset2 in FIG. 4) overlaps the seventh transistor T7 can serve as the control electrode of the seventh transistor T7.

[0182] In the exemplary embodiment, the first reset control line 21 can be provided with a plurality of first protruding structures 211, the plurality of first protruding structures 211 are arranged at intervals along the first direction X, the first protruding structure 211 is arranged on the side of the first reset control line 21 close to the scan signal line 22, the shape of the first protruding structure 211 can be L-shaped, and the first protruding structure 211 and the main body part of the first reset control line 21 form a U-shaped structure rotated 90° clockwise. The area where the first protruding structure 211 and the main body part of the first reset control line 21 overlap the active layer of the first transistor T1 serves as the double-gate structure of the first transistor T1 (i.e., the first transistor T1 includes two control electrodes).

[0183] In the exemplary embodiment, the scan signal line 22 can be provided with a plurality of second protruding structures 221, the plurality of second protruding structures 221 are arranged at intervals along the first direction X, the second protruding structure 221 is arranged on the side of the scan signal line 22 close to the first plate 23 of the capacitor, and the shape of the second protruding structure 221 is substantially a strip extending along the second direction Y or a broken line type. The area where the second protruding structure 221 and the main body part of the scan signal line 22 overlap the active layer of the second transistor T2 serves as the double-gate of the second transistor T2 (i.e., the second transistor T2 includes two control electrodes).

[0184] In the example embodiment, the main body part of the first reset control line 21, the scan signal line 22, the light emitting control line 24, and the second reset control line 25 can be designed with equal width or non-equal width, which can facilitate the layout of the pixel structure and reduce the parasitic capacitance between the signal lines.

[0185] In the example embodiment, after forming the first conductive layer pattern, the semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, i.e., the first region and the second region of the active layer 11 of the first transistor T1 to the active layer 17 of the seventh transistor T7 are conductorized.

[0186] (104) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned patterns are formed, patterning the second conductive film by a patterning process, forming a third insulating layer covering the first conductive layer, and forming a second conductive layer pattern on the third insulating layer, as shown in FIGS. 9a and 9b. FIG. 9a is a plan view of three sub-pixels, and FIG. 9b is a plan view of the second conductive layer in FIG. 9a. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0187] In the example embodiment, the second conductive layer pattern at least includes: a second plate 31 of a capacitor. The second plate 31 of the capacitor serves as the other plate of the capacitor.

[0188] In the example embodiment, the outline of the second plate 31 can be rectangular, the corners of the rectangle can be chamfered, at least one edge of the rectangle can be a broken line, and the second plate 31 has an overlapping region with the first plate 23 in the orthographic projection on the substrate. The first plate 23 and the second plate 31 constitute a storage capacitor of the pixel driving circuit. The second plate 32 is provided with an opening 311, which can be located in the middle of the second plate 31. The opening 311 can be rectangular, so that the second plate 31 forms a ring structure. The opening 311 exposes the third insulating layer covering the first plate 23, and the orthographic projection of the first plate 23 on the substrate contains the orthographic projection of the opening 311 on the substrate. In the example embodiment, the opening 311 is configured to accommodate a ninth via hole formed subsequently, the ninth via hole is located in the opening 311 and exposes the first plate 23, so that the second electrode of the first transistor T1 formed subsequently is connected to the first plate 23.

[0189] In the example embodiment, the second plate 31 is provided with a connecting structure 312. In the first direction, the connecting structure 312 is arranged on at least one side of the second plate 31. In the same sub-pixel row, two adjacent second plates 31 are connected to each other through the connecting structure 312, so that the plurality of second plates 31 in the same sub-pixel row have substantially the same potential. The second plate of the storage capacitor of the adjacent sub-pixels has the same potential, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0190] In the example embodiment, the shape of the second conductive layer in the plurality of sub-pixel rows can be the same, and the shape of the second conductive layer in the plurality of sub-pixel columns can be the same.

[0191] (105) Forming a fourth insulating layer pattern. In the example embodiment, forming the fourth insulating layer pattern can include: depositing a fourth insulating film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating film by using a patterning process to form a fourth insulating layer covering the second conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 10, which is a planar structure diagram of three sub-pixels.

[0192] In the example embodiment, the plurality of vias in at least part of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0193] In the example embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the active layer 11 of the first transistor T1 (also the first initial signal line Vinit1) on the substrate (for example, the orthographic projection of the first via V1 on the substrate can be located within the range of the orthographic projection of the first region 11-1 of the active layer 11 of the first transistor T1 on the substrate, and also within the range of the orthographic projection of the first initial signal line Vinit1 on the substrate). The fourth insulating layer, the third insulating layer, and the second insulating layer in the first via V1 are etched away, exposing the surface of the active layer 11 of the first transistor T1 (for example, exposing the surface of the first region 11-1 of the active layer 11 of the first transistor T1, and also exposing the surface of the first initial signal line Vinit1). The first via V1 is configured to allow the first electrode of the first transistor T1 formed subsequently to be electrically connected to the active layer 11 of the first transistor T1 (also the first initial signal line Vinit1) through the via.

[0194] In an example embodiment, the second via V2 is configured such that a second electrode of the first transistor T1 is electrically connected to the second electrode of the first transistor T1 through the via, and a first electrode of the second transistor T2 is electrically connected to the first electrode of the second transistor T2 through the via.

[0195] In an example embodiment, the third via V3 is configured such that a first electrode of the fourth transistor T4 is electrically connected to the active layer 14 of the fourth transistor T4 through the via.

[0196] In an example embodiment, the fourth via V4 is configured such that a first electrode of the fifth transistor T5 is electrically connected to the active layer 15 of the fifth transistor T5 through the via.

[0197] In an example embodiment, the fifth via V5 is configured such that a second electrode of the sixth transistor T6 is electrically connected to the active layer 16 of the sixth transistor T6 through the via, and a second electrode of the seventh transistor T7 is electrically connected to the active layer 17 of the seventh transistor T7 through the via.

[0198] In the exemplary embodiment, the sixth via V6 is located within the footprint of the active layer 17 of the seventh transistor T7 on the substrate, and the fourth, third and second insulating layers within the sixth via V6 are etched away to expose the surface of the first region 17-1 of the active layer 17 of the seventh transistor T7. The sixth via V6 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to connect to the active layer 17 of the seventh transistor T7 through the via.

[0199] In the exemplary embodiment, the seventh via V7 is located within the footprint of the first reset control line 21 on the substrate, and the fourth and third insulating layers within the seventh via V7 are etched away to expose the surface of the first reset control line 21. The seventh via V7 is configured to allow the subsequently formed first reset control auxiliary line to electrically connect to the first reset control line 21 through the via.

[0200] In the exemplary embodiment, the eighth via V8 is located within the footprint of the scan signal line 22 on the substrate, and the fourth and third insulating layers within the eighth via V8 are etched away to expose the surface of the scan signal line 22. The eighth via V8 is configured to allow the subsequently formed scan signal auxiliary line to electrically connect to the scan signal line 22 through the via.

[0201] In the exemplary embodiment, the ninth via V9 is located within the footprint of the opening 311 on the substrate, and the fourth and third insulating layers within the ninth via V9 are etched away to expose the surface of the first electrode plate 23. The ninth via V9 is configured to allow the second electrode of the first transistor T1 (also the first electrode of the second transistor T2) to connect to the first electrode plate 23 through the via.

[0202] In the exemplary embodiment, the tenth via V10 is located within the footprint of the second reset control line 24 on the substrate, and the fourth and third insulating layers within the tenth via V10 are etched away to expose the surface of the second reset control line 24. The tenth via V10 is configured to allow the subsequently formed second reset control auxiliary line to electrically connect to the second reset control line 24 through the via.

[0203] In the example embodiment, the eleventh via V11 is located within the range of the orthographic projection of the second plate 31 on the substrate, and the fourth insulating layer within the eleventh via V11 is etched to expose the surface of the second plate 31. The eleventh via V11 is configured to allow the first power connection line formed subsequently to pass through the via and be electrically connected to the second plate 31. In the example embodiment, the eleventh via V11 as the power via can include a plurality of eleventh vias V11, which can be arranged in sequence along the second direction Y or the first direction X to increase the connection reliability of the first power connection line to the second plate 31.

[0204] (106) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, and patterning the third conductive thin film by using a patterning process to form a third conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 11a and 11b, FIG. 11a is a planar structural diagram of three columns of sub-pixels (i.e., three sub-pixels) in the Nth column to the N+2th column in a row of sub-pixels, and FIG. 11b is a planar schematic diagram of the third conductive layer in FIG. 11a. In the example embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0205] In the example embodiment, the third conductive layer pattern at least includes: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44 (which can serve as an anode switching electrode), a fifth connection electrode 45, a first reset control auxiliary line 46, a scan signal auxiliary line 47, a first power connection line VDDL, and a second reset control auxiliary line 48. The main body portions of the first reset control auxiliary line 46, the scan signal auxiliary line 47, the first power connection line VDDL, and the second reset control auxiliary line 48 can extend along the first direction X, and in the same row of sub-pixels, the first reset control auxiliary line 46, the scan signal auxiliary line 47, the first power connection line VDDL, and the second reset control auxiliary line 48 can be arranged in sequence along the second direction Y.

[0206] In the example embodiment, in the same row of sub-pixels, along the second direction Y, the first connection electrode 41 can be located on the side of the first reset control auxiliary line 46 away from the scan signal auxiliary line 47, the second connection electrode 42 can be located between the first reset control auxiliary line 46 and the scan signal auxiliary line 47, the third connection electrode 43 can be located between the scan signal auxiliary line 47 and the first power connection line VDDL, the fourth connection electrode 44 can be located between the first power connection line VDDL and the second reset control auxiliary line 48, and the fifth connection electrode 45 can be located on the side of the second reset control auxiliary line 48 away from the first power connection line VDDL.

[0207] In the example embodiment, the first reset control auxiliary line 46 can be arranged to be electrically connected to the first reset control line 21 in a row of sub-pixels through a plurality of seventh vias V7, so that the first reset control signal can be provided to the plurality of first transistors T1 in a row of sub-pixels, the first reset control signal can be provided to the first transistor T1 through the first reset control auxiliary line 46 and the first reset control line 21, the first reset control auxiliary line 46 and the first reset control line 21 form a double-layer structure (i.e., the first reset control auxiliary line 46 and the first reset control line 21 are connected in parallel), which can reduce the voltage drop and improve the consistency of the first reset control signal in a row of sub-pixels.

[0208] In the example embodiment, a plurality of scan signal connection structures 471 can be arranged on the scan signal auxiliary line 47, in the second direction Y, the scan signal connection structure 471 can be arranged on the side of the scan signal auxiliary line 47 close to the first power connection line VDDL, the shape of the scan signal connection structure 471 can be approximately a polyline or a strip shape extending in the second direction Y, the scan signal connection structure 471 can be arranged to be electrically connected to the scan signal line 22 in a row of sub-pixels through an eighth via V8, so that the scan signal auxiliary line 47 can provide the scan signal to the plurality of first transistors T1 in a row of sub-pixels, the scan signal can be provided to the fourth transistor T4 through the scan signal auxiliary line 47 and the scan signal line 22, the scan signal auxiliary line 47 and the scan signal line 22 form a double-layer structure (i.e., the scan signal auxiliary line 47 and the first reset control line 21 are connected in parallel), which can reduce the voltage drop and improve the consistency of the reset control signal in a row of sub-pixels.

[0209] In the example embodiment, a plurality of power connection electrodes 49 can be arranged on the first power connection line VDDL, in the second direction Y, the plurality of power connection electrodes 49 can be arranged on the side of the first power connection line VDDL away from the scan signal auxiliary line 47, the shape of the power connection electrode 49 can be approximately a polyline or a strip shape extending in the second direction Y, the power connection electrode 49 can be arranged to be electrically connected to the active layer 15 of the plurality of fifth transistors T5 in a row of sub-pixels through a plurality of fourth vias V4, and electrically connected to the plurality of second plates 31 in a row of sub-pixels through a plurality of eleventh vias V11, so that the first power connection line VDDL can provide the first power signal to the plurality of fifth transistors T5 and the plurality of second plates 31 in a row of sub-pixels, so that the second plate 31 and the first electrode of the fifth transistor T1 have substantially the same potential.

[0210] In the example embodiment, the second reset control auxiliary line 48 can be configured to be electrically connected with the second reset control line 24 in a row of sub-pixels through a plurality of tenth vias V10, so that the second reset control signal can be provided to the plurality of seventh transistors T7 in a row of sub-pixels, the second reset control signal can be provided to the seventh transistor T7 through the second reset control auxiliary line 48 and the second reset control line 24, the second reset control auxiliary line 48 and the second reset control line 24 form a double-layer structure (i.e., the second reset control auxiliary line 48 and the second reset control line 24 are connected in parallel), which can reduce the voltage drop and improve the consistency of the second reset control signal in a row of sub-pixels.

[0211] In the example embodiment, the first connection electrode 41 can have a shape of a broken line or a strip shape extending along the first direction X, or a block structure, and the first connection electrode 41 can be connected with the active layer 11 of the first transistor T1 (also the first initial signal line Vinit1) through the first via V1. In the example embodiment, the first connection electrode 41 can serve as the first electrode of the first transistor T1. In the same row of sub-pixels, the plurality of first connection electrodes 41 can be located on the side of the first reset control auxiliary line 46 away from the scan signal auxiliary line 47 in the second direction Y.

[0212] In the example embodiment, the second connection electrode 42 can have a shape of a block structure or a rectangular structure, and the second connection electrode 42 can be connected with the first region 14-1 of the active layer 14 of the fourth transistor T4 through the third via V3. In the example embodiment, the second connection electrode 42 can serve as the first electrode of the fourth transistor T4. In the same row of sub-pixels, the plurality of second connection electrodes 42 can be located between the first reset control auxiliary line 46 and the scan signal auxiliary line 47 in the second direction Y.

[0213] In the example embodiment, the third connection electrode 43 can have a shape of a broken line or a strip shape extending along the second direction Y, one end of the third connection electrode 43 is connected with the first region 12-1 of the active layer 12 of the second transistor T2 (also the second region 11-2 of the active layer 11 of the first transistor T1) through the second via V2, and the other end is connected with the first plate 23 of the capacitor through the ninth via V9, so that the first plate 23, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential. In the example embodiment, the third connection electrode 43 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2. In the same row of sub-pixels, the plurality of third connection electrodes 43 can be located between the first power connection line VDDL and the scan signal auxiliary line 47 in the second direction Y, and the plurality of third connection electrodes 43 and the plurality of scan signal connection structures 471 can be alternately arranged along the first direction X.

[0214] In the exemplary embodiment, the fourth connection electrode 44 can have a shape of a broken line or a strip shape extending along the second direction Y, and the fourth connection electrode 44 can be connected to the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7) through the fifth via V5. In the exemplary embodiment, the fourth connection electrode 44 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In the exemplary embodiment, in the same row of sub-pixels, the fourth connection electrode 44 can be located between the main body portion of the first power connection line VDDL and the second reset control auxiliary line 48 in the second direction Y, and a plurality of fourth connection electrodes 44 and a plurality of power connection electrodes 49 can be arranged alternately along the first direction X.

[0215] In the exemplary embodiment, the fifth connection electrode 45 can have a shape of a broken line or a strip shape extending along the first direction X, or a block structure, and the fifth connection electrode 45 can be connected to the active layer 17 of the seventh transistor T7 (also the second initial signal line Vinit2) through the sixth via V6. In the exemplary embodiment, the fifth connection electrode 45 can serve as the first electrode of the seventh transistor T7. In the same row of sub-pixels, a plurality of fifth connection electrodes 45 can be located on the side of the second reset control auxiliary line 48 away from the first power connection line VDDL in the second direction Y.

[0216] (107) Forming a fifth insulating layer and a first planar layer pattern. In the exemplary embodiment, forming the fifth insulating layer and the first planar layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the fifth insulating thin film and the first planar thin film by using a patterning process, to form a fifth insulating layer covering the third conductive layer and a first planar layer disposed on the fifth insulating layer, and the fifth insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 12, which is a planar structure diagram of three sub-pixels.

[0217] In the exemplary embodiment, the plurality of vias in at least part of the sub-pixels at least include: a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, and a sixteenth via V16.

[0218] In the exemplary embodiment, the twelfth via V12 is located within the range of the orthogonal projection of the first connection electrode 41 on the substrate, the fifth insulating layer and the first planar layer within the twelfth via V12 are etched away, and the surface of the first connection electrode 41 is exposed. The twelfth via V12 is configured to allow a first initial signal connection line formed subsequently to pass through the via and connect with the first connection electrode 41, so that the first initial signal connection line is connected with the first initial signal line Vinit1 due to the connection between the first connection electrode 41 and the first initial signal line Vinit1.

[0219] In the exemplary embodiment, the thirteenth via V13 is located within the range of the orthogonal projection of the fifth connection electrode 45 on the substrate, the fifth insulating layer and the first planar layer within the thirteenth via V13 are etched away, and the surface of the fifth connection electrode 45 is exposed. The thirteenth via V13 is configured to allow a second initial signal connection line formed subsequently to pass through the via and connect with the fifth connection electrode 45, so that the second initial signal connection line is connected with the second initial signal line Vinit2 due to the connection between the fifth connection electrode 45 and the second initial signal line Vinit2.

[0220] In the exemplary embodiment, the fourteenth via V14 is located within the range of the orthogonal projection of the second connection electrode 42 on the substrate, the fifth insulating layer and the first planar layer within the fourteenth via V14 are etched away, and the surface of the second connection electrode 42 is exposed. The fourteenth via V14 is configured to allow a data signal line formed subsequently to pass through the via and connect with the second connection electrode 42.

[0221] In the exemplary embodiment, the fifteenth via V15 is located within the range of the orthogonal projection of the first power connection line VDDL (e.g., the power connection electrode 49 on the first power connection VDDL) on the substrate, the fifth insulating layer and the first planar layer within the fifteenth via V15 are etched away, and the surface of the power connection line VDDL is exposed. The fifteenth via V15 is configured to allow a first power line formed subsequently to pass through the via and connect with the first power connection line VDDL.

[0222] In the exemplary embodiment, the sixteenth via V16 is located within the range of the orthogonal projection of the fourth connection electrode 44 on the substrate, the fifth insulating layer and the first planar layer within the sixteenth via V16 are etched away, and the surface of the fourth connection electrode 44 is exposed. The sixteenth via V16 is configured to allow an anode connection electrode formed subsequently to pass through the via and connect with the fourth connection electrode 44.

[0223] (108) A fourth conductive layer pattern is formed. In an exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film using a patterning process, forming the fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 13a-13d, FIG. 13a is a planar structure diagram of three sub-pixels (i.e., three sub-pixels) in the Nth column to the N+2th column in a row of sub-pixels, FIG. 13c is a planar structure diagram of six sub-pixels (i.e., six sub-pixels) in the Nth column to the N+2th column in a row of sub-pixels, FIG. 13b is a planar schematic diagram of the fourth conductive layer in FIG. 13a, and FIG. 13d is a planar schematic diagram of the fourth conductive layer in FIG. 13c. The fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0224] In an exemplary embodiment, the fourth conductive layer at least includes: a first power supply line VDD, a data signal line D, a first initial signal connection line 51, and an anode connection electrode 52. In an exemplary embodiment, the anode connection electrode 52 is an anode connection electrode of a light emitting element. In an exemplary embodiment, in the first direction X, the first power supply line VDD, the data signal line D, and the first initial signal connection line 51 are disposed at intervals. In the first direction X, the size of the main body portion of the first power supply line VDD is greater than the size of the main body portion of the other signal lines.

[0225] In an exemplary embodiment, the data signal line D can be a polyline or a bar shape with the main body portion extending along the second direction Y, and the data signal line D is connected to the first connection electrode 41 through the fourteenth via V14. Since the first connection electrode 41 is connected to the first region 14-1 of the active layer 14 of the fourth transistor T4 through the via, the connection of the data signal line D to the first electrode of the fourth transistor T4 is achieved, and the data signal is written into the fourth transistor T4.

[0226] In an exemplary embodiment, the first power supply line VDD can be a polyline with the main body portion extending along the second direction Y, and the first power supply line VDD can be connected to the first power supply connection line VDDL through the fifteenth via V15. Since the first power supply connection line VDD is connected to the second plate 31 through the via, the connection of the first power supply line VDD to the second plate 31 is achieved, and the power supply signal is written into the second plate 31. Since the first power supply connection line VDDL is connected to the first region 15-1 of the active layer 15 of the fifth transistor T5 through the via, the connection of the first power supply line VDD to the first electrode of the fifth transistor T5 is achieved, and the power supply signal is written into the fifth transistor T5.

[0227] In the example embodiment, the first initial signal connection line 51 can be a zigzag or strip structure extending along the second direction Y for the main body part, and the first initial signal connection line 51 can be connected with the first connection electrode 41 through the twelfth via V12, so that the first initial signal connection line 51 can be connected with the first initial signal line Vinit1 due to the connection of the first connection electrode 41 with the first initial signal line Vinit1. Since the first initial signal connection line 51 can be electrically connected with the plurality of first initial signal lines Vinit1 arranged along the second direction Y, the initial signals provided by the plurality of first initial signal lines Vinit1 can be substantially the same, and the initial signals obtained by the first transistors T1 in the plurality of rows of sub-pixels can be substantially consistent due to the connection of the first initial signal lines Vinit1 with the first regions 11-1 of the first transistors T1, which is conducive to improving the display uniformity of the display substrate.

[0228] In the example embodiment, the anode connection electrode 52 can be connected with the fourth connection electrode 44 through the sixteenth via V16. Since the fourth connection electrode 44 is connected with the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7) through the via, the connection of the anode connection electrode 52 with the second poles of the sixth transistor T6 and the seventh transistor T7 is achieved.

[0229] In the example embodiment, as shown in FIGS. 13a and 13b, the first initial signal connection line 51 can also be connected with the fifth connection electrode 45 through the thirteenth via V13, so that the first initial signal connection line 51 can be connected with the second initial signal line Vinit2. Since the first initial signal connection line 51 can be electrically connected with the plurality of second initial signal lines Vinit2 arranged along the second direction Y, the initial signals provided by the plurality of second initial signal lines Vinit2 can be substantially the same, and the initial signals obtained by the seventh transistors T7 in the plurality of rows of sub-pixels can be substantially consistent due to the connection of the second initial signal lines Vinit2 with the first regions 17-1 of the seventh transistors T7, which is conducive to improving the display uniformity of the display substrate. In the structure shown in FIGS. 13a and 13b, the initial signals provided by the second initial signal lines Vinit2 can be the same as the initial signals provided by the first initial signal lines Vinit1.

[0230] In the example embodiment, as shown in FIGS. 13c and 13d, the fourth conductive layer can further include a second initial signal connection line 52, which can be in a broken line shape extending along the second direction Y, and the second initial signal connection line 52 can be connected with the fifth connection electrode 45 through a thirteenth via V13, so that the second initial signal connection line 52 can be connected with the second initial signal line Vinit2. Since the second initial signal connection line 53 can be electrically connected with the plurality of second initial signal lines Vinit2 arranged along the second direction Y, the initial signals provided by the plurality of second initial signal lines Vinit2 can be substantially the same, and since the second initial signal line Vinit2 is connected with the first region 17-1 of the seventh transistor T7, the initial signals obtained by the seventh transistor T7 in the plurality of rows of sub-pixels can be substantially the same, which is conducive to improving the display uniformity of the display substrate. In the structure shown in FIGS. 13c and 13d, the first initial signal connection line 51 is connected with the first initial signal line Vinit1 and is not connected with the second initial signal line Vinit2; the second initial signal connection line 53 is connected with the second initial signal line Vinit2 and is not connected with the first initial signal line Vinit1, and the initial signal provided by the first initial signal line Vinit1 can be the same as or different from the initial signal provided by the second initial signal line Vinit2.

[0231] (109) forming a second planar layer pattern. In the example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, coating a second planar film, patterning the second planar film by using a patterning process, and forming a second planar layer covering the fourth conductive layer pattern, the second planar layer being provided with a plurality of vias, as shown in FIG. 14, which is a planar structure diagram of three sub-pixels.

[0232] In the example embodiment, the plurality of vias in at least part of the sub-pixels at least include a seventeenth via V17.

[0233] In the example embodiment, the seventeenth via V17 is within the range of the normal projection of the anode connection electrode 52 on the substrate, the second planar layer in the seventeenth via V17 is etched away, and the surface of the anode connection electrode 52 is exposed. The seventeenth via V17 is configured to allow the anode formed subsequently to be connected with the anode connection electrode 52 through the via.

[0234] At this point, the circuit structure layer (i.e., the driving circuit layer) can be prepared. In an example embodiment, after the circuit structure layer (or referred to as the driving circuit layer) is prepared, the light-emitting structure layer is prepared on the circuit structure layer, and the preparation process of the light-emitting structure layer can include the following operations: forming an anode pattern (i.e., an anode conductive layer), the anode being connected with the anode connecting electrode through an anode via hole (which can be the seventeenth via hole V17); forming a pixel definition layer, the pixel definition layer being provided with a pixel opening 70, the pixel opening 70 exposing the anode; forming an organic light-emitting layer by using an evaporation or inkjet printing process, the organic light-emitting layer being connected with the anode through the pixel opening 70, and forming a cathode on the organic light-emitting layer; forming an encapsulation layer, the encapsulation layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer. The steps of forming the anode conductive layer and the pixel definition layer are as follows:

[0235] (110) Forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film by using a patterning process to form the anode conductive layer arranged on the second planar layer, as shown in FIGS. 15a and 15b, FIG. 15a is a planar structure diagram of three sub-pixels, and FIG. 15b is a planar structure diagram of the anode conductive layer in FIG. 15a.

[0236] In an example embodiment, the anode conductive layer at least includes: the anodes 60 of the plurality of light-emitting elements.

[0237] In an example embodiment, the anode 60 can be substantially rectangular in structure, and the anode 60 is connected with the anode connecting electrode 52 through the seventeenth via hole V17. Since the anode connecting electrode 52 is connected with the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7) through the via hole, the anode 60 can be connected with the second region 16-2 of the active layer 16 of the sixth transistor T6 (also the second region 17-2 of the active layer 17 of the seventh transistor T7), so that the pixel driving circuit drives the light-emitting device to emit light.

[0238] In an example embodiment, the plurality of anodes 60 can include: a first anode 61, a second anode 62 and a third anode 63. The region where the first anode 61 is located can form a red light-emitting unit emitting red light, the region where the second anode 62 is located can form a blue light-emitting unit emitting blue light, and the region where the third anode 63 is located can form a green light-emitting unit emitting green light.

[0239] In the example embodiment, the first anode 61, the second anode 62 and the third anode 63 can be connected with the anode connecting electrode 52 in the corresponding sub-pixel through the seventeenth via hole V17. Since the anode connecting electrode 52 in the sub-pixel is electrically connected with the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via hole, the first anode 61, the second anode 62 and the third anode 63 can be connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connecting electrode 52, so as to realize the driving of the light-emitting device by the pixel driving circuit.

[0240] In the example embodiment, the anode 60 can include a main body part 601 and a connecting part 602. The main body part 601 can be in a rectangular structure. The anode connecting part 602 is connected with the anode main body part 601 at one end and is electrically connected with the anode connecting electrode 52 through the seventeenth via hole V17 at the other end.

[0241] (111) Forming a pixel definition layer pattern. In the example embodiment, forming the pixel definition layer pattern can include: depositing a pixel definition layer thin film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition layer by using a patterning process, and forming the pixel definition layer pattern arranged on the anode conductive layer, as shown in FIGS. 16a and 16b. FIG. 16a is a schematic diagram of the planar structure of three sub-pixels, and FIG. 16b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 16a.

[0242] In the example embodiment, the pixel definition layer pattern can include a plurality of pixel openings 70, and the pixel openings 70 expose the anode 60. In the example embodiment, the orthographic projection of the pixel openings 70 on the substrate is within the range of the orthographic projection of the anode 60 on the substrate. In the example embodiment, the pixel openings 70 can include a pixel opening 71 of the first sub-pixel, a pixel opening 72 of the second sub-pixel and a pixel opening 73 of the third sub-pixel. The orthographic projection of the pixel opening 71 of the first sub-pixel on the substrate overlaps with the orthographic projection of the first anode 61 on the substrate. The orthographic projection of the pixel opening 72 of the second sub-pixel on the substrate overlaps with the orthographic projection of the second anode 62 on the substrate. The orthographic projection of the pixel opening 73 of the third sub-pixel on the substrate overlaps with the orthographic projection of the third anode 63 on the substrate.

[0243] The structure and the preparation process thereof shown in the foregoing embodiments of the present disclosure are merely exemplary, and in the example embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate of the present disclosure can be applied to other display devices having a pixel driving circuit, such as quantum dot display, and the present disclosure is not limited thereto.

[0244] In the example embodiment, taking three sub-pixels (one sub-pixel pixel driving circuit row, three sub-pixels pixel driving circuit column) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (111) as described above, and the difference from the steps (101) to (111) is as follows:

[0245] The second conductive layer formed in the step (104) can be as shown in FIGS. 17a and 17b. FIG. 17a is a planar structure diagram of three sub-pixels after the second conductive layer is formed, and FIG. 17b is a planar diagram of the second conductive layer in FIG. 17a. The difference between the second conductive layer pattern shown in FIG. 17b and the second conductive layer pattern shown in FIG. 9b is that, in the fourth conductive layer pattern shown in FIG. 17, a first initial signal auxiliary line Vinit11 and a second initial signal auxiliary line Vinit21 are newly added. In the same row of pixel driving circuits, in the second direction Y, the first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 are located on both sides of the second plate 31 of the capacitor. The first initial signal auxiliary line Vinit11 of the Mth row is located on the side of the second plate 31 of the capacitor close to the (M-1)th row of sub-pixels. The second initial signal auxiliary line Vinit21 of the Mth row is located on the side of the second plate 31 of the capacitor close to the (M+1)th row of sub-pixels. The shape of the first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 can be a strip shape or a polyline shape extending along the first direction X. In the example embodiment, the orthographic projection of the first initial signal auxiliary line Vinit11 on the substrate at least partially overlaps the orthographic projection of the first initial signal line Vinit1 on the substrate; and the orthographic projection of the second initial signal auxiliary line Vinit21 on the substrate at least partially overlaps the orthographic projection of the second initial signal line Vinit2 on the substrate.

[0246] The fourth insulating layer formed in the step (105) can be as shown in FIG. 18. The fourth insulating layer pattern shown in FIG. 18 is different from the fourth insulating layer pattern shown in FIG. 10 in that: in the fourth insulating layer pattern shown in FIG. 18, an eighteenth via hole V18 and a nineteenth via hole V19 are newly added. The orthogonal projection of the eighteenth via hole V18 on the substrate is located within the range of the orthogonal projection of the first initial signal auxiliary line Vinit11 on the substrate. The fourth insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away, exposing the surface of the first initial signal auxiliary line Vinit11. The eighteenth via hole V18 is configured to enable the first electrode of the first transistor T1 to be formed later to be electrically connected to the first initial signal auxiliary line Vinit11 through the via hole. The orthogonal projection of the nineteenth via hole V19 on the substrate is located within the range of the orthogonal projection of the second initial signal auxiliary line Vinit21 on the substrate. The fourth insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away, exposing the surface of the second initial signal auxiliary line Vinit21. The nineteenth via hole V19 is configured to enable the first electrode of the seventh transistor T7 to be formed later to be electrically connected to the second initial signal auxiliary line Vinit21 through the via hole.

[0247] The third conductive layer formed in the step (106) can be as shown in FIGS. 19a and 19b. FIG. 19a is a planar structural view of the three sub-pixels after the third conductive layer is formed. FIG. 19b is a planar schematic view of the third conductive layer in FIG. 19a. The third conductive layer pattern shown in FIG. 19b is different from the third conductive layer pattern shown in FIG. 11b in that: in the third conductive layer pattern shown in FIG. 19b, the first connection electrode 41 can also be electrically connected to the first initial signal auxiliary line Vinit11 through the eighteenth via hole V18. Since the first connection electrode 41 is electrically connected to the first initial signal line Vinit1, the first initial signal auxiliary line Vinit11 is electrically connected to the first initial signal line Vinit1. The fifth connection electrode 45 can also be electrically connected to the second initial signal auxiliary line Vinit21 through the nineteenth via hole V19. Since the fifth connection electrode 45 is electrically connected to the second initial signal line Vinit2, the second initial signal auxiliary line Vinit21 is electrically connected to the second initial signal line Vinit2.

[0248] In an exemplary embodiment, taking 3 sub-pixels (1 pixel driving circuit row of sub-pixels, 3 pixel driving circuit columns of sub-pixels) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (111) as described above, wherein the difference from the steps (101) to (111) is as follows:

[0249] The third conductive layer formed in the step (106) can be as shown in FIGS. 20a and 20b. FIG. 20a is a plan view of three sub-pixels after the third conductive layer is formed, and FIG. 20b is a plan view of the third conductive layer in FIG. 20a. The difference between the third conductive layer pattern shown in FIG. 20b and the third conductive layer pattern shown in FIG. 11b is that, in the third conductive layer pattern shown in FIG. 20b, the first connection electrode 41 and the fifth connection electrode 45 are not provided, and a first initial signal auxiliary line Vinit11 and a second initial signal auxiliary line Vinit21 are newly added. In the same row of pixel driving circuits, in the second direction Y, the first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 are located on both sides of the second plate 31 of the capacitor, the first initial signal auxiliary line Vinit11 of the Mth row is located on the side of the second plate 31 of the capacitor close to the (M-1)th row of sub-pixels, the second initial signal auxiliary line Vinit21 of the Mth row is located on the side of the second plate 31 of the capacitor close to the (M+1)th row of sub-pixels, and the shapes of the first initial signal auxiliary line Vinit11 and the second initial signal auxiliary line Vinit21 can be strip-shaped or zigzag-shaped extending along the first direction X. In an exemplary embodiment, the orthogonal projection of the first initial signal auxiliary line Vinit11 on the substrate at least partially overlaps the orthogonal projection of the first initial signal line Vinit1 on the substrate; the orthogonal projection of the second initial signal auxiliary line Vinit21 on the substrate at least partially overlaps the orthogonal projection of the second initial signal line Vinit2 on the substrate; the first initial signal auxiliary line Vinit11 is arranged to be electrically connected to the first initial signal line Vinit1 through the first via V1, and the second initial signal auxiliary line Vinit21 is arranged to be electrically connected to the second initial signal line Vinit2 through the sixth via V6.

[0250] The fifth insulating layer and the first planarization layer pattern formed by the above step (107) can be as shown in FIG. 21 (pixel driving circuit of the Nth column to the N+2th column sub-pixel) and FIG. 22 (pixel driving circuit of the N+3th column to the N+5th column sub-pixel). The difference between the fourth insulating layer pattern shown in FIG. 21 and FIG. 22 and the fourth insulating layer pattern shown in FIG. 12 is that, in the fourth insulating layer pattern shown in FIG. 21 and FIG. 22, the twelfth via hole V12 is located within the range of the orthogonal projection of the first initial signal auxiliary line Vinit11 on the substrate, the fifth insulating layer and the first planarization layer in the twelfth via hole V12 are etched away, exposing the surface of the first initial signal auxiliary line Vinit11, and the twelfth via hole V12 is configured to allow the first initial signal connection line 51 formed subsequently to connect with the first initial signal auxiliary line Vinit11 through the via hole, so that the first initial signal connection line is connected with the first initial signal line Vinit1 due to the connection between the first initial signal auxiliary line Vinit11 and the first initial signal line Vinit1; the thirteenth via hole V13 is located within the range of the orthogonal projection of the second initial signal auxiliary line Vinit21 on the substrate, the fifth insulating layer and the first planarization layer in the thirteenth via hole V13 are etched away, exposing the surface of the second initial signal auxiliary line Vinit21, and the thirteenth via hole V13 is configured to allow the second initial signal connection line formed subsequently to connect with the second initial signal auxiliary line Vinit21 through the via hole, so that the second initial signal connection line is connected with the second initial signal line Vinit2 due to the connection between the second initial signal auxiliary line Vinit21 and the second initial signal line Vinit2.

[0251] In the exemplary embodiment, taking 3 sub-pixels (1 row of pixel driving circuits of sub-pixels, 3 columns of pixel driving circuits of sub-pixels) in the display area (AA) as an example, another preparation process of the display substrate can include the above steps (101) to (111), and the difference from the above steps (101) to (111) is as follows.

[0252] The fourth insulating layer formed by the above step (105) can be as shown in FIG. 23. The difference between the fourth insulating layer pattern shown in FIG. 23 and the fourth insulating layer pattern shown in FIG. 10 is that, in the fourth insulating layer pattern shown in FIG. 23, one seventh via hole V7 and one tenth via hole V10 are arranged in one pixel unit, the number of via holes is reduced, the via hole density is reduced, the line width and the line spacing of the conductive layer signal line are increased, and the product yield of the display substrate is improved.

[0253] The third conductive layer formed in step 106 can be as shown in FIGS. 24a and 24b. FIG. 40a is a plan view of three sub-pixels after the third conductive layer is formed, and FIG. 24b is a plan view of the third conductive layer in FIG. 24a. The difference between the third conductive layer pattern shown in FIG. 24b and the third conductive layer pattern shown in FIG. 11b is that, in FIG. 24b, in a row of pixel driving circuits, the first reset control auxiliary line 46 can be configured to be electrically connected to the first reset control line 21 in a row of sub-pixels through a seventh via V7 in a plurality of pixel units, and the second reset control auxiliary line 48 can be configured to be electrically connected to the second reset control line 24 in the row of sub-pixels through a tenth via V10 in the plurality of pixel units. In the same row of sub-pixels, the plurality of pixel units are arranged along the first direction X, and each pixel unit can include three sub-pixels. The first reset control auxiliary line 46 and the first reset control line 21 are electrically connected through one seventh via V7 in one pixel unit, and the second reset control auxiliary line 48 and the second reset control line 24 are electrically connected through one tenth via V10. The number of vias is reduced, the via density is reduced, the line width and the line spacing of the conductive layer signal line are increased, and the product yield of the display substrate is improved.

[0254] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or a vehicle-mounted display.

[0255] The display substrate and the display device provided by the embodiments of the present disclosure have the first signal line and the corresponding pixel driving circuit electrically connected in a direct connection manner, the occurrence of via defects is reduced, and the technical problems of high manufacturing cost and low efficiency caused by via defects are overcome to some extent.

[0256] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0257] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0258] Although the embodiments disclosed in the embodiments of the present disclosure are as described above, the content is only the implementation adopted to facilitate the understanding of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Any person skilled in the art to which the embodiments of the present disclosure belong can make any modification and change in the implementation form and details without departing from the spirit and scope of the embodiments of the present disclosure. The patent protection scope of the embodiments of the present disclosure shall be subject to the scope defined by the attached claims.

Claims

A display substrate, comprising a substrate and a plurality of sub-pixels, a plurality of first signal lines, at least part of the sub-pixels comprising a pixel driving circuit, the pixel driving circuits of the at least part of the sub-pixels forming a plurality of rows, the first signal lines corresponding to at least part of the pixel driving circuits in at least one row, the plurality of first signal lines extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; The first signal line and the corresponding pixel driving circuit are electrically connected in a direct connection manner. The display substrate according to claim 1, further comprising a plurality of first signal auxiliary lines corresponding to at least part of the first signal lines, the first signal auxiliary lines being located on a side of the corresponding first signal lines away from the substrate, and the first signal auxiliary lines and the corresponding first signal lines being electrically connected through a via hole. The display substrate according to claim 1, wherein In a direction perpendicular to a plane in which the substrate is located, the pixel driving circuit comprises at least one transistor, the transistor comprising an active layer located on a side of the substrate, a control electrode located on a side of the active layer away from the substrate, a source electrode and a drain electrode located on a side of the control electrode away from the substrate; The first signal line and the active layer or the control electrode are provided in the same layer. The display substrate according to claim 3, wherein The plurality of first signal lines comprise a plurality of initial signal lines and a plurality of scan control lines, the initial signal lines being provided in the same layer as the active layer, and the scan control lines being provided in the same layer as the control electrode; The initial signal line and the active layer of at least one transistor in the corresponding pixel driving circuit are electrically connected, and a normal projection of the scan control line and the active layer of at least one transistor in the corresponding pixel driving circuit on the substrate at least partially overlaps. The display substrate according to claim 4, wherein The plurality of transistors comprise a third transistor as a driving transistor, a first transistor as a reset transistor, and a seventh transistor as a reset transistor, a second electrode of the first transistor and a control electrode of the third transistor being electrically connected; the plurality of initial signal lines comprise a first initial signal line and a second initial signal line; The first initial signal line and the active layer of the first transistor are electrically connected, and the second initial signal line and the active layer of the seventh transistor are electrically connected. The display substrate according to claim 5, wherein The first initial signal line and the active layer of the first transistor in the corresponding pixel driving circuit are formed in an integral structure, and the second initial signal line and the active layer of the seventh transistor in the corresponding pixel driving circuit are formed in an integral structure. The display substrate according to claim 5, further comprising a plurality of first initial signal auxiliary lines and a plurality of second initial signal auxiliary lines, the plurality of first initial signal auxiliary lines corresponding to the plurality of first initial signal lines one by one, and the plurality of second initial signal auxiliary lines corresponding to the plurality of second initial signal lines one by one; the pixel driving circuit further comprises a capacitor, a first plate of the capacitor being provided in the same layer as the control electrode, and in a direction perpendicular to a plane in which the substrate is located, a second plate of the capacitor being located between the control electrode and the source electrode and the drain electrode. The first initial signal auxiliary line and the second initial signal auxiliary line are arranged in the same layer as the source electrode and the drain electrode, or the first initial signal auxiliary line and the second initial signal auxiliary line are arranged in the same layer as the second plate of the capacitor; the first initial signal auxiliary line is electrically connected with the corresponding first initial signal line, and the second initial signal auxiliary line is electrically connected with the corresponding second initial signal line. The display substrate according to claim 7, wherein In the same pixel driving circuit, in the second direction, the first transistor and the seventh transistor are located on both sides of the capacitor and the third transistor, the first initial signal line and the first initial signal auxiliary line are located on the same side of the capacitor and the third transistor, and the second initial signal line and the second initial signal auxiliary line are located on the same side of the capacitor and the third transistor. The display substrate according to claim 7 or 8, wherein In the same row of pixel driving circuits, the orthographic projection of the first initial signal auxiliary line and the corresponding first initial signal line on the substrate at least partially overlaps, and the orthographic projection of the second initial signal auxiliary line and the corresponding second initial signal line on the substrate at least partially overlaps. The first initial signal auxiliary line and the corresponding first initial signal line are electrically connected through a via, and the second initial signal auxiliary line and the corresponding second initial signal line are electrically connected through a via. The display substrate according to claim 7 or 8, wherein In the same pixel driving circuit, the orthographic projection of the third transistor on the substrate at least partially overlaps the orthographic projection of the capacitor on the substrate, and the first plate of the capacitor serves as the control electrode of the third transistor. The display substrate according to claim 5, wherein The plurality of scan control lines includes a first reset control line and a second reset control line. The region where the first reset control line overlaps with the active layer of the first transistor serves as the control electrode of the first transistor, and the region where the second reset control line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor. In the same pixel driving circuit, in the second direction, the first transistor and the seventh transistor are located on both sides of the third transistor, the first initial signal line is located on the side of the first reset control line away from the third transistor, and the second initial signal line is located on the side of the second reset control line away from the third transistor. The display substrate according to claim 11 further comprises a plurality of first reset control auxiliary lines and a plurality of second reset control auxiliary lines, the plurality of first reset control auxiliary lines and the plurality of second reset control auxiliary lines are arranged in the same layer as the source electrode and the drain electrode; the plurality of first reset control auxiliary lines correspond one-to-one to the plurality of first reset control lines, and the plurality of second reset control auxiliary lines correspond one-to-one to the plurality of second reset control lines; In the same row of pixel driving circuits, the orthographic projection of the first reset control auxiliary line and the corresponding first reset control line on the substrate at least partially overlaps, and the orthographic projection of the second reset control auxiliary line and the corresponding second reset control line on the substrate at least partially overlaps. ​ The first reset control auxiliary line is electrically connected with the corresponding first reset control line through a via hole, and the second reset control auxiliary line is electrically connected with the corresponding second reset control line through a via hole. The display substrate according to claim 12, wherein The plurality of transistors further comprises a second transistor as a compensation transistor and a fourth transistor as a data writing transistor, the plurality of scan control lines comprises a scan signal line, an area where the scan signal line overlaps with an active layer of the second transistor as a control electrode of the second transistor, and an area where the scan signal line overlaps with an active layer of the fourth transistor as a control electrode of the fourth transistor; In the same pixel driving circuit, in the second direction, the second transistor and the fourth transistor are located between the first transistor and the third transistor, and the scan signal line is located on one side of the first reset control line close to the third transistor. The display substrate according to claim 13 further comprises a plurality of scan signal auxiliary lines, the plurality of scan signal auxiliary lines are arranged in the same layer as the source and the drain, main body parts of the plurality of scan signal auxiliary lines extend along the first direction and are arranged along the second direction; the plurality of scan signal auxiliary lines correspond to the plurality of scan signal lines one by one. In the same row of pixel driving circuits, the scan signal auxiliary line is electrically connected with the corresponding scan signal line. The display substrate according to claim 14, wherein The scan signal auxiliary line is provided with a plurality of scan signal connection structures, in the same row of pixel driving circuits, the plurality of scan signal connection structures are arranged at intervals along the first direction, and in the second direction, the plurality of scan signal connection structures are located on one side of the main body part of the scan signal auxiliary line close to the third transistor, and the main body part of the scan signal auxiliary line is located between the scan signal line and the first reset control auxiliary line. In the same row of pixel driving circuits, the plurality of scan signal connection structures on the scan signal auxiliary line are electrically connected with the corresponding scan signal line through a via hole. The plurality of transistors further comprises a fifth transistor and a sixth transistor as light emitting control transistors, and the plurality of scan control lines further comprises a light emitting control line, an area where the light emitting control line overlaps with an active layer of the fifth transistor as a control electrode of the fifth transistor, and an area where the light emitting control line overlaps with an active layer of the sixth transistor as a control electrode of the sixth transistor; The display substrate according to claim 12, wherein In the same pixel driving circuit, in the second direction, the fifth transistor and the sixth transistor are located between the third transistor and the seventh transistor, and the light emitting control line is located between the third transistor and the second reset control line. A plurality of sub-pixels located in the same row form a plurality of pixel units; in the same pixel unit, at least two sub-pixels are arranged in sequence along the first direction; The display substrate according to any one of claims 12 to 16, wherein ​ In the same row pixel driving circuit, the first reset control auxiliary line and the first reset control line are electrically connected through a plurality of first connection vias, and the number of the first connection vias in the same pixel unit is not more than the number of sub-pixels in the pixel unit; the second reset control auxiliary line and the second reset control line are electrically connected through a plurality of second connection vias, and the number of the second connection vias in the same pixel unit is not more than the number of sub-pixels in the pixel unit. The display substrate according to claim 17, wherein In the same row pixel driving circuit, one first connection via and one second connection via are arranged in n pixel units, and n is a positive integer greater than or equal to 1. A display device comprises the display substrate as claimed in any one of claims 1 to 18.

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