A method for preparing a transparent microelectrode array chip
By using ITO thin-film electrodes and photoresist mask etching processes in MEA chips, the problems of poor light transmittance and metal residue were solved, enabling simultaneous detection of electrophysiological recording and optical imaging, and improving the detection accuracy and stability of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WESTLAKE INSTITUTE FOR OPTOELECTRONICS
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-05
Smart Images
Figure CN122144654A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of microelectrode fabrication technology, and more particularly to a method for fabricating a transparent microelectrode array chip. Background Technology
[0002] Microelectrode arrays (MEAs) are key biomedical engineering devices for detecting and stimulating electrophysiological signals at the cellular or tissue level. Through a multi-channel microelectrode array on the chip, extracellular action potentials or field potentials at multiple sites can be recorded simultaneously, thereby revealing the electrical activity patterns, functional connections, and signal transduction pathways of cellular networks. They enable high-throughput, long-term, and real-time monitoring and intervention of bioelectrical activity in a non-invasive manner, making them an important tool for biomedical research.
[0003] In the prior art, such as the multi-site detection area microelectrode array and its preparation method proposed in patent CN106645346B, most MEA chips use quartz, polymers and other materials as substrates, and metals such as Ti and Au as electrode materials. These chips have poor light transmittance and can only obtain a single electrical signal, making it difficult to achieve optical observation and unable to complete the simultaneous detection of electrophysiological recording and optical imaging.
[0004] Therefore, there is an urgent need for an optimized method for fabricating transparent MEA chips that can ensure high light transmittance of the chip and high precision of the electrodes, enabling spatiotemporal synchronization of electrophysiological recording and morphological imaging, while also avoiding interference from metal residues on the detection signal and improving the chip's detection accuracy and stability. Summary of the Invention
[0005] In view of this, the purpose of one or more embodiments of this specification is to propose a solution to the technical problems of poor light transmittance of existing MEA chips, which prevents simultaneous photoelectric detection, and the metal residue caused by metal hard mask etching, which affects electrical signals. The solution is to optimize the fabrication process of ITO thin film electrodes and obtain a transparent MEA chip with high light transmittance, high electrical performance, and high detection accuracy, so as to realize non-destructive, high-precision spatiotemporal synchronous observation of electrophysiological signal detection and optical imaging.
[0006] To achieve the above objectives, one or more embodiments of this specification provide a method for fabricating a transparent microelectrode array chip, comprising the following steps: S1. Pre-treat the glass substrate to improve the surface cleanliness of the substrate and the adsorption of the electrode film; S2. An ITO thin film is deposited on the surface of a pretreated glass substrate using magnetron sputtering to serve as a transparent electrode; S3. Spin-coat photoresist onto the surface of the ITO thin film and perform patterning. Then, use a dry etching process to etch the ITO thin film to form a preset electrode structure. After etching, remove the photoresist and clean and dry the film. S4. PECVD process is used to deposit the substrate surface. Insulating layer, for The insulating layer is patterned and etched using a dry etching process to create electrode windows. After completion, the photoresist is removed and the material is cleaned and dried. In typical applications, after completing step S4, the wafer can be sliced to obtain an independent transparent microelectrode array chip. For thin-bottom chips that require bonding and packaging, the following step is also included: S5. The outer electrodes of the thin-bottom chip are patterned, and an Au layer is deposited on the surface of the outer electrodes as a transition bonding layer using an electron beam evaporation process. After removing the excess plating layer, the chip is bonded and packaged with the PCB board.
[0007] The pretreatment described in S1 includes alternating ultrasonic cleaning, gradient baking, oxygen plasma surface roughening, and silanization modification.
[0008] The patterning process described in S3 includes a photolithography process of spin coating an adhesion layer, spin coating a photoresist, exposure, development, and hard film treatment.
[0009] The dry etching process described in S3 is performed using an inductively coupled plasma etching machine, and the etching gas is Ar gas.
[0010] The patterning of the SiNx insulating layer in S4 uses the same photolithography process as the ITO thin film patterning in S3.
[0011] The dry etching process described in S4 is performed using an inductively coupled plasma etching machine, and the etching gas is a mixture of CF4, CHF3, and Ar.
[0012] The patterning of the external electrode described in S5 is accomplished using photolithography.
[0013] Before depositing the Au layer in S5, a layer of metallic Cr is first vapor-deposited as an adhesion layer between the Au layer and the ITO electrode.
[0014] In S5, acetone solution is used to dissolve the excess Au layer outside the external electrode area, thus completing the coating stripping.
[0015] In S5, UV-curable adhesive is used to attach the thin-bottom chip with the deposited Au transition layer to the PCB board, and the wire bonding packaging of the chip and the PCB board is completed by a wire bonding machine.
[0016] As can be seen from the above, the beneficial effects of the transparent microelectrode array chip fabrication method provided by one or more embodiments of this specification are as follows: Achieving synchronous photoelectric detection: Using ITO as a transparent electrode and glass as a transparent substrate, the fabricated chip has excellent light transmittance, breaking through the technical barriers between electrophysiological recording and optical imaging. It realizes non-destructive, high-precision synchronous observation of bioelectrical signal detection and morphological imaging in time and space, promoting the development of biomedical research towards multimodal directions.
[0017] To avoid interference from metal residues: The entire etching process uses photoresist masks instead of traditional metal hard masks, which completely solves the problem of metal residues affecting electrophysiological detection signals and greatly improves the detection accuracy and stability of the chip. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 MEA chip layout diagram; Figure 2 This is a fabrication process diagram for a transparent microelectrode array chip. Figure 3 The image shows the patterned ITO electrode. Figure 4 This is a diagram of the MEA chip after ITO etching. Figure 5 for Image of the MEA chip after coating; Figure 6 for Microscopic images of the patterned surface; Figure 7 for Image of the MEA chip after etching; Figure 8 This is a diagram of the MEA chip after it has been sliced. Figure 9 Image of a thin-base MEA chip with gold-plated external electrodes; Figure 10 This is a diagram of a thin-bottom MEA chip after bonding and packaging. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments.
[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in one or more embodiments of this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in one or more embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0022] Example: like Figure 1-10 As shown, this embodiment of the invention provides a method for fabricating a transparent microelectrode array (MEA) chip. This embodiment uses a commercial glass substrate or cover glass as the core substrate, accommodating both transparent MEA chip fabrication for conventional applications and thin-bottom MEA chip fabrication requiring wire bonding and packaging. The overall process is as follows: Figure 2 As shown, for ordinary glass substrates, the following steps are performed sequentially: substrate pretreatment, ITO transparent electrode magnetron sputtering deposition, ITO electrode patterning and dry etching. In conventional applications, the insulating layer is deposited by PECVD and then windowed. In such cases, the chip can be obtained by wafer slicing. However, for thin-bottom MEA chips with a 170μm thick cover glass as the substrate, due to their fragility, they cannot be used independently and must be packaged and bonded to a PCB board. However, directly connecting the ITO electrode to the PCB by wire bonding is prone to detachment. Therefore, on the basis of the above, it is necessary to additionally complete the external electrode patterning, Au transition bonding layer deposition, and Au external electrode after peeling. The packaging is completed by Au-Au wire bonding technology, and finally, a thin-bottom MEA chip that can be used in practice is obtained.
[0023] S1, Pretreatment of the glass substrate: This step involves multi-dimensional pretreatment of commercially purchased glass substrates. The operations sequentially include alternating ultrasonic cleaning, gradient baking, oxygen plasma surface roughening, and silanization modification. The core objective is to thoroughly remove impurities such as oil, dust, and residual moisture from the substrate surface, improving surface cleanliness. Simultaneously, roughening and modification treatments increase the surface roughness and optimize the surface physicochemical properties, significantly enhancing the substrate's ability to withstand subsequent ITO electrode film deposition. The adsorption properties and bonding strength of the insulating layer prevent problems such as film peeling and coating cracking in subsequent processes, ensuring the stability and yield of chip fabrication. The specific operation is as follows: Alternating ultrasonic cleaning: The glass substrate is placed in acetone and IPA solution alternately for ultrasonic treatment, with each ultrasonic treatment lasting 15 minutes. The strong degreasing ability of acetone and the dissolving properties of IPA are used to remove organic oil and sticky impurities from the substrate surface. After completion, the substrate is transferred to anhydrous ethanol and 60°C deionized water (DIW) and ultrasonically treated alternately for 15 minutes to further remove inorganic impurities and residual solvent. At the same time, 60°C deionized water can improve cleaning efficiency and reduce impurity adsorption. Gradient baking: The ultrasonically cleaned glass substrate is placed on a hot plate for gradient baking. The baking temperature is increased sequentially to 40℃, 70℃, 90℃ and 105℃, and the baking time for each temperature segment is 120s. Gradient baking instead of direct high temperature baking can avoid cracking of the substrate due to thermal stress caused by sudden temperature rise. At the same time, it gradually removes the adsorbed moisture and residual cleaning solution on the substrate surface, so as to achieve thorough drying of the substrate surface. Oxygen plasma surface roughening: The dried substrate is placed in an oxygen plasma etching machine for surface roughening treatment. Oxygen plasma can perform micro- and nano-scale etching on the substrate surface, increasing the surface roughness. At the same time, the strong oxidizing properties of the plasma can introduce active groups such as hydroxyl groups on the substrate surface, providing reaction sites for subsequent silanization modification. Silanization modification: The roughened substrate was quickly placed into an evaporation dish containing 2 ml of γ-mercaptopropyltrimethoxysilane stock solution. The evaporation dish was sealed and evacuated to a vacuum. Then, the evaporation dish was placed in an oven and baked at a constant temperature of 60°C for 60 min. The vacuum environment allows the silane reagent to fully contact the substrate surface. 60°C is the optimal temperature for the silanization reaction, which can promote the covalent bonding between the silane reagent and the active groups on the substrate surface, forming a uniform silane-modified film. This further optimizes the surface properties of the substrate, significantly improves the adsorption capacity for subsequent inorganic films, and ensures the bonding stability between the electrode film and the insulating layer.
[0024] S2, Magnetron sputtering deposition of ITO transparent electrodes: Indium tin oxide (ITO) thin films are deposited on the surface of a pre-treated glass substrate using magnetron sputtering. These films serve as the core transparent electrodes for the chip. Magnetron sputtering offers advantages such as good coating uniformity, high film density, and strong adhesion to the substrate, making it suitable for the micro-nano fabrication requirements of microelectrode array chips. Simultaneously, ITO material possesses excellent conductivity, high light transmittance, and good mechanical properties, meeting both the electrical requirements for electrophysiological signal detection and the light transmittance requirements for optical imaging, breaking through the technical barrier of poor light transmittance of traditional metal electrodes. This step uses dedicated magnetron sputtering equipment with RF power controlled at 200W. Through precise control of process parameters, the deposited ITO film has a thickness of 200nm and a sheet resistance of 20Ω / □. These parameters achieve an optimal balance between transmittance and conductivity, ensuring both the clarity of optical imaging and efficient transmission and detection of electrophysiological signals without signal attenuation or distortion, meeting the core electrode requirements for simultaneous photoelectric detection.
[0025] S3, Patterning and Dry Etching of the ITO Thin Film: This step involves precise patterning of the ITO thin film using photolithography, followed by inductively coupled plasma (ICP) dry etching to etch the ITO thin film according to the preset pattern, forming an electrode structure that meets the design requirements of the microelectrode array. After etching, post-processing such as resist removal, cleaning, and drying is performed. The specific operation is divided into two parts: patterning photolithography and dry etching and post-processing. Each step is precise and the parameters are controllable to ensure the accuracy and consistency of the electrode structure, as detailed below: 3.1 Patterning photolithography of ITO thin films: Patterning is a core step in micro / nano fabrication, directly determining the precision of the electrode structure. This step involves five sequential operations: spin-coating of the adhesion layer, spin-coating of the photoresist, exposure, development, and hardening. Precise control of process parameters at each step ensures clear photolithographic patterns, neat edges, and perfect matching with the pre-defined electrode structure. Specific operations are as follows: Spin-coating adhesion layer: A special AR300-80new adhesion layer is spin-coated onto the surface of the ITO film at 4000 rpm for 60 seconds. After spin-coating, the film is placed on a 100℃ hot plate for 120 seconds. The adhesion layer can effectively improve the adhesion between the photoresist and the ITO film, avoid problems such as photoresist peeling and edge lifting during exposure and development, and ensure photolithography accuracy. Spin-coating photoresist: Spin-coat AZ1518 photoresist on the surface of the adhesion layer at 1500 rpm for 60 seconds. After spin-coating, bake on a hot plate at 100℃ for 90 seconds to form a photoresist film layer with uniform thickness and no pinholes. AZ1518 photoresist has advantages such as high resolution and good development performance, and is suitable for the preparation of fine patterns of microelectrode arrays. Exposure: The substrate with photoresist spin-coated was placed in a Karl Suss MA6 contact exposure machine, and exposure was performed using the soft-contact mode. The exposure light source was g-line, and the exposure dose was controlled at 200 mJ / cm². 2 The soft-contact mode reduces direct contact between the photoresist and the mask, avoiding mask contamination and photoresist scratches. At the same time, precise exposure dosage ensures the clarity and edge accuracy of the lithographic pattern. Development: Place the exposed substrate in the developer AZ300mif and develop it at a constant temperature of 22℃ for 60s. The developer can precisely dissolve the photoresist in the exposed area and retain the photoresist in the unexposed area, forming a photoresist mask pattern consistent with the preset electrode structure. Hardening: The developed substrate is placed on a hot plate at 115℃ and baked for 120 seconds to perform photoresist hardening treatment. High-temperature baking improves the cross-linking degree and etching resistance of the photoresist, enhances the adhesion between the photoresist mask and the ITO film, avoids photoresist swelling and peeling during subsequent dry etching, and prevents the etching solution from corroding the ITO film in non-etched areas.
[0026] 3.2 Dry Etching and Post-processing of ITO Thin Films: Inductively Coupled Plasma (ICP) dry etching replaces traditional wet etching. Dry etching offers advantages such as high etching precision, good anisotropy, and perpendicular etching contours, enabling precise etching of micro / nano-scale fine electrode structures, perfectly meeting the processing requirements of microelectrode array chips. Specific operations are as follows: Dry etching: The patterned substrate is placed in a SamcoRIE-230iP inductively coupled plasma etching machine. Pure Ar gas is used as the etching gas and as an inert gas. The ITO thin film is physically etched by plasma bombardment. There is no chemical reaction during the etching process, which avoids corrosion of the substrate and photoresist. After etching, an ITO microelectrode array structure that is completely consistent with the preset pattern is formed on the substrate surface. Resin removal and post-processing: The etched MEA substrate is placed in an N-methylpyrrolidone (NMP) solution and immersed at a constant temperature of 60°C for 30-90 minutes. The NMP solution can efficiently dissolve the photoresist mask on the surface without damaging the ITO electrode and the glass substrate. After the resist removal is completed, the substrate is rinsed with deionized water (DIW) for 1 minute to remove the residual NMP solution and resist residue on the surface. Finally, the substrate is dried to obtain the etched ITO electrode structure. The dried substrate surface is clean, the electrode outline is clear, and there are no residual impurities or film peeling problems.
[0027] S4, The insulating layer deposition and electrode windowing are performed using plasma-enhanced chemical vapor deposition (PECVD) on the substrate surface. The insulating layer is then processed using photolithography and dry etching. Patterned etching of the insulating layer creates electrode windows, exposing the detection electrodes and ensuring effective acquisition of electrophysiological signals. The insulating layer provides insulation protection for electrodes in non-detection areas, preventing signal crosstalk, short circuits, and other problems, thus ensuring the chip's detection accuracy. Specific operations include... The chip post-processing consists of three parts: insulating layer deposition, insulating layer patterning and dry etching, and standard chip post-processing, as detailed below: 4.1 PECVD deposition The insulating layer was deposited on the substrate surface using a Samco PD-220NL (TEOS dual-frequency) dedicated PECVD equipment, with a mixed gas of SiH4, N2O, and NH3 as the reaction gas source. The insulating layer, PECVD process can achieve thin film deposition at lower temperatures, avoiding damage to the prepared ITO electrode caused by high temperatures, while the deposited layer... Thin films possess advantages such as uniform thickness, high density, excellent insulation properties, and strong adhesion to ITO films, making them ideal insulating layer materials for microelectrode array chips.
[0028] The process parameters for this step are controlled as follows: RF power 50W, deposition temperature 350℃, and deposition time 900s. The product deposited using the above process... The film thickness is 300-500nm. This thickness of insulating layer can reduce the impact on optical imaging while ensuring insulation performance, and at the same time avoid cracking and peeling problems caused by excessive film thickness.
[0029] 4.2, Patterning and dry etching of the insulating layer The patterning and etching of the insulating layer is crucial for achieving electrode windowing. This step employs the same photolithography process and dry etching equipment as the ITO thin film in S3, adjusting only the etching gas and some process parameters to ensure precise windowing position and clean edges, preventing electrode detection failure due to windowing deviation. Specific procedures are as follows: Patterning: Utilizing a photolithography process identical to S3.1, the process involves sequentially spin-coating an adhesion layer, spin-coating photoresist, exposure, development, and hardening. The window pattern of the electrode is developed on the surface of the insulating layer to ensure that the window pattern is precisely matched with the central detection electrode, without any offset or misalignment. Dry etching: The patterned substrate is placed in the same SamcoRIE-230iP inductively coupled plasma etching machine as S3.2. The etching gas is a mixture of CF4, CHF3, and Ar, with a mixing ratio of CF4:CHF3:Ar = 1:1:1~1:2:3 and a total gas flow rate of 80~120 sccm. Among them, CF4 and CHF3 are reactive gases and can react with... A chemical reaction occurs, generating volatile substances. Ar gas is used as the physical etching gas. Plasma bombardment promotes the removal of reaction products. The combination of physical and chemical etching achieves the desired etching effect. Highly efficient and precise etching of the insulating layer; etching process parameters are controlled as follows: cavity pressure 0.5~1.2Pa, ICP power 200W-300W, RF power 100W-200W, etching time 5~10min, precisely etching away the windowed area. An insulating layer completely exposes the underlying ITO central detection electrode, ensuring direct acquisition of electrophysiological signals. Post-processing: After etching, following the same method as in S3.2, the substrate was placed in an NMP solution to remove the resist, then rinsed with deionized water and dried to obtain a MEA substrate with completed electrode windows. The surface of this substrate... The insulating layer effectively protects the non-detection area, and the central detection electrode is unobstructed and undamaged, providing the basic conditions for signal acquisition.
[0030] 4.3 Post-processing of chips in conventional application scenarios: For most conventional MEA chip application scenarios, no subsequent bonding and packaging is required. After completing the above electrode windowing, the wafer is sliced using a dedicated slicing device to obtain an independent transparent microelectrode array chip.
[0031] The slicing process uses laser cutting technology to ensure that the chip edges are neat and free of chipping, avoiding electrode breakage and insulation layer damage caused by slicing damage. The sliced independent chips can be directly used for electrophysiological signal detection and optical imaging of cells and tissues. It is easy to operate, highly adaptable, and meets the needs of routine biomedical engineering research.
[0032] S5, External Electrode Processing and PCB Bonding and Packaging of Thin-Bottom MEA Chips: For thin-bottom MEA chips fabricated with a 170μm thick cover glass substrate, due to the thinness and low mechanical strength of the cover glass, these chips cannot be used independently and need to be wire-bonded onto a PCB board to improve mechanical strength and practicality. Simultaneously, the physicochemical properties of ITO electrodes prevent direct wire bonding to the PCB board. Therefore, based on S4, a special treatment is required for the external electrodes, depositing an Au layer as a transition bonding layer to achieve effective bonding between the chip and the PCB board. The specific operations include four parts: external electrode patterning photolithography, electron beam evaporation deposition of the Au transition bonding layer, removal of excess plating, and chip-PCB board bonding and packaging, as detailed below: 5.1 Patterning of the External Electrode: The external electrode is patterned using photolithography. The core process is consistent with the patterning of the ITO electrode in S3. Only the photoresist type and some exposure and development parameters are specifically adjusted according to the process requirements of the external electrode to ensure accurate patterning and suitability for subsequent Au transition layer deposition and bonding. Specifically, AZ5214e photoresist is used instead of AZ1518; spin-coating parameters are 4000 rpm for 60 seconds, followed by baking at 100℃ for 60 seconds; the exposure light source is an i-line, and the exposure dose is adjusted to 120 mJ / cm². 2 The development time is controlled at 30-45 seconds. The remaining processes, such as spin coating of the adhesion layer and selection of the developer, are exactly the same as in S3 to ensure the accuracy and consistency of the external electrode pattern. After patterning, a layer of photoresist is applied to the remaining areas except for the external electrode.
[0033] 5.2 Electron beam evaporation deposition of Au transition bonding layer: An Au layer is deposited on the surface of the external electrode as a transition bonding layer using electron beam evaporation. Electron beam evaporation offers advantages such as controllable deposition rate, high coating purity, and good film uniformity. The deposited Au layer exhibits excellent conductivity and bonding performance, enabling efficient and stable connection between the ITO external electrode and the PCB board leads. Simultaneously, to enhance the adhesion between the Au layer and the ITO external electrode and prevent Au layer detachment during bonding and use, a Cr metal layer is first deposited as an adhesion layer. Specific procedures are as follows: Equipment and Vacuum Preparation: Using the ULVAC EI-5Z dedicated electron beam evaporation equipment, the patterned thin-layer MEA substrate is placed into the equipment chamber, and the chamber is evacuated to a vacuum level of 10. -7 Torr, a high-vacuum environment, can prevent the film from being oxidized during the deposition process, ensuring the purity and conductivity of the coating; Adhesion layer evaporation: First, a metal Cr layer is evaporated as an adhesion layer. The thickness of the Cr layer is controlled to be 5~10nm and the evaporation rate is 0.5~2Å / s. The thin and uniform Cr layer can achieve a firm bond between the Au layer and the ITO electrode without affecting the conductivity. Au transition layer deposition: After the Cr layer is deposited, the Au layer is deposited as a transition bonding layer. The evaporation rate of the Au layer is controlled at 0.2~1 Å / s. By precisely controlling the evaporation rate, the Au layer is ensured to have uniform thickness, high density, and good bonding performance.
[0034] 5.3 Excess Plating Stripping: The thin-bottom MEA chip with completed plating is placed in an acetone solution. The photoresist outside the external electrode area dissolves in the acetone, causing the deposited transition bonding layer to be stripped away along with it. After stripping, a thin-bottom MEA chip with only the external electrode area covered by the Au transition layer is obtained. This chip can be directly bonded and packaged onto a PCB board. It is important to note that using an inverted chip during the stripping process can prevent metal residue from adhering to the chip when it is removed from the solution.
[0035] 5.4. Chip bonding and packaging to the PCB board: This step is the final molding step for the thin-bottom MEA chip. Through physical bonding and wire bonding, a strong connection and circuit connection are achieved between the chip and the PCB board, improving the chip's mechanical strength and usability. Specific operations are as follows: Chip bonding: A thin-layer MEA chip with a deposited Au transition layer is bonded to a predetermined position on the PCB board using UV-curing adhesive. UV light is then used to irradiate the chip for 60 seconds to allow the adhesive to fully cure. UV-curing adhesive offers advantages such as high bonding strength, fast curing speed, good light transmittance, and no volatile impurities. It achieves a firm bond between the chip and the PCB board without affecting the chip's optical imaging or electrical signal transmission. Wire bonding: Using a dedicated wire bonding machine, the Au transition layer on the surface of the chip's external electrode is precisely bonded to the lead electrode on the PCB board, achieving electrical connection between the ITO electrode and the PCB board, ensuring efficient conduction and output of electrophysiological signals; Finished product molding: After bonding is completed, a complete and packaged thin-bottom MEA chip is obtained. This chip has high light transmittance, excellent conductivity and good mechanical strength. It can be directly applied to various high-precision bioelectrophysiological signal detection and optical imaging research, and is suitable for precision experimental scenarios where conventional chips cannot be used.
[0036] The transparent microelectrode array chip prepared by the above process in this invention uses glass as a transparent substrate and ITO as transparent electrodes. As an insulating layer, the entire process employs a photomask etching process, eliminating the use of traditional metal hard masks. This fundamentally solves the technical problem of metal residue affecting electrical signal detection in existing processes, optimizes the fabrication process of ITO thin film electrodes, and improves the detection accuracy and stability of the chip.
[0037] Meanwhile, the chip's fully transparent structure enables perfect synchronization of electrophysiological recording and morphological imaging in time and space, breaking the technical barrier that traditional MEA chips cannot synchronize electrophysiological detection and optical imaging. This advances research in fields such as neuroscience from traditional single-modal recording to a new paradigm of multimodal, mutually corroborative, and controllable recording, truly realizing in-situ testing of biological signals.
[0038] The preparation method of this invention is controllable, simple in steps, and has a high yield. The prepared chip has good conductivity, high light transmittance, excellent insulation and mechanical stability, and can be widely used in many biomedical engineering fields such as neuroscience research, cardiac electrophysiological detection, organ-on-a-chip development, and tissue engineering. It has extremely high practical application value and market prospects.
[0039] Comparative experiments to verify: To verify the process advantages and chip performance of the preparation method of the present invention, two sets of comparative experiments were designed. The experiments were conducted under the same laboratory environment and equipment operating conditions, with only the core variables changed. The remaining process parameters were consistent with the embodiments of the present invention, as follows: Comparative experiment: Performance comparison of etching ITO electrodes with photoresist mask and metal hard mask.
[0040] Experimental objective: To verify the advantages of the photoresist mask etching method of this invention for etching ITO electrodes compared to the existing technology of etching ITO electrodes with a metal Cr hard mask, in terms of metal residue and electrical signal detection stability.
[0041] The experimental procedure is as follows: Experimental group: The photoresist mask etching process of the present invention is used, namely, the photoresist mask dry etching of ITO electrodes in step cj, to prepare a transparent MEA chip; Control group: The metal hard mask etching process of the existing patent CN115763246A was used to deposit a 5nm Cr layer on the surface of the ITO thin film as a hard mask. After patterning, the ITO electrode was dry etched. The rest of the process was the same as the experimental group to prepare the MEA chip.
[0042] Testing indicators: 1. Metal residue content: The residual Cr content in the electrode areas of the two sets of chips was detected by inductively coupled plasma mass spectrometry (ICP-MS); 2. Electrical signal stability: The impedance values of the two sets of chip electrodes in physiological saline (at a frequency of 1 kHz) were detected using an electrochemical workstation, and the signal-to-noise ratio (SNR) of the electrophysiological signals of in vitro nerve cells was recorded.
[0043] The experimental results and analysis are as follows: ; Experimental results show that the control group, which uses a Cr hard mask, has significant Cr metal residue in the electrode area after etching. The residual metal ions interfere with the transmission of electrophysiological signals, resulting in a significant decrease in the signal-to-noise ratio and greater fluctuations in electrode impedance. In contrast, the present invention uses photoresist mask etching, without introducing any additional metal materials throughout the process. There is no metal residue in the electrode area, the electrical signal-to-noise ratio is improved by about 60%, and the electrode impedance is more stable. This effectively solves the technical problem of metal residue affecting the detection results in the prior art.
[0044] Comparative Experiment 2: Performance Comparison of ITO Transparent Electrode and Traditional Au Metal Electrode MEA Chip Experimental objective: This study verifies the advantages of the ITO transparent electrode MEA chip prepared by this invention over the traditional Au metal electrode MEA chip in terms of light transmittance and photoelectric synchronous detection.
[0045] Experimental plan: Experimental group: ITO transparent electrode MEA chip (glass substrate + ITO transparent electrode) was prepared using the preparation method of the present invention. Reference group: Using the same substrate pretreatment, patterning, and etching process as this invention, the electrode material is replaced with traditional Au metal, and a 200nm Au layer is deposited by magnetron sputtering as the electrode to prepare an Au metal electrode MEA chip.
[0046] Testing indicators: Transmittance: The average transmittance of the two sets of chips in the 400-800nm visible light band was measured using a UV-Vis spectrophotometer; Photoelectric synchronous observation effect: Rat hippocampal neurons were seeded on the surface of two sets of chips. Cell morphology optical imaging was performed using a fluorescence microscope, and cell electrophysiological signals were recorded simultaneously using an MEA acquisition system to observe whether photoelectric synchronous observation could be achieved in the same field of view and at the same time.
[0047] Experimental Results and Analysis: Transmittance: The average transmittance of the experimental group chip in the visible light band was 89±2%, while the average transmittance of the control group Au metal electrode chip was only 3±1%, which was almost completely opaque. Photoelectric synchronous observation: The experimental group can clearly observe cell morphology and fluorescently labeled neural synapses under a fluorescence microscope, and simultaneously record clear cell action potential signals, realizing photoelectric synchronous non-destructive observation; the control group, because the electrodes are completely opaque, cannot observe cell morphology on the chip surface through an optical microscope, and can only collect electrophysiological signals.
[0048] Experimental results show that the ITO transparent electrode MEA chip prepared in this invention has both high light transmittance and good electrical signal detection performance, breaking through the technical barrier that traditional metal electrode chips cannot synchronize electrophysiological recording and optical imaging, and realizing in-situ synchronous detection of "electro-optic" dual modes. In contrast, traditional Au metal electrode chips can only realize single electrical signal detection, which cannot meet the photoelectric synchronous observation requirements of modern biomedical research.
[0049] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this specification as described above, which are not provided in detail for the sake of brevity.
[0050] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.
[0051] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.
Claims
1. A method for fabricating a transparent microelectrode array chip, characterized in that, Includes the following steps: S1. Pre-treat the glass substrate to improve the surface cleanliness of the substrate and the adsorption of the electrode film; S2. An ITO thin film is deposited on the surface of a pretreated glass substrate using magnetron sputtering to serve as a transparent electrode; S3. Spin-coat photoresist onto the surface of the ITO thin film and perform patterning. Then, use a dry etching process to etch the ITO thin film to form a preset electrode structure. After etching, remove the photoresist and clean and dry the film. S4. PECVD process is used to deposit the substrate surface. Insulating layer, for The insulating layer is patterned and etched using a dry etching process to create windows. After completion, the photoresist is removed and the layer is cleaned and dried. In typical application scenarios, after completing step S4, the wafer can be sliced to obtain an independent transparent microelectrode array chip. For thin-bottom chips that require bonding and packaging, the following step is also included: S5. Patterning the outer electrodes of the thin-bottom chip, depositing an Au layer on the surface of the outer electrodes as a transition bonding layer using electron beam evaporation, and bonding and packaging the chip to the PCB board after removing the excess plating layer.
2. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, The pretreatment described in S1 includes alternating ultrasonic cleaning, gradient baking, oxygen plasma surface roughening, and silanization modification.
3. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, The patterning process described in S3 includes a photolithography process of spin coating an adhesion layer, spin coating a photoresist, exposure, development, and hard film treatment.
4. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, The dry etching process described in S3 is performed using an inductively coupled plasma etching machine, and the etching gas is Ar gas.
5. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, S4 The patterning of the insulating layer uses the same photolithography process as the ITO thin film patterning in S3.
6. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, The dry etching process described in S4 is performed using an inductively coupled plasma etching machine, and the etching gas is a mixture of CF4, CHF3, and Ar.
7. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, The patterning of the external electrode described in S5 is accomplished using photolithography.
8. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, Before depositing the Au layer in S5, a layer of metallic Cr is first vapor-deposited as an adhesion layer between the Au layer and the ITO electrode.
9. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, In S5, acetone solution is used to dissolve the excess Au layer outside the external electrode area, thus completing the coating stripping.
10. The method for fabricating a transparent microelectrode array chip according to claim 1, characterized in that, In S5, UV-curable adhesive is used to attach the thin-bottom chip with the deposited Au transition layer to the PCB board, and the wire bonding packaging of the chip and the PCB board is completed by a wire bonding machine.