A low dropout linear voltage regulator with high power supply rejection ratio

Abstract

The application discloses a low-dropout linear voltage stabilizing circuit with high power supply rejection ratio, comprising a feedforward ripple circuit, an error amplifier, a summing circuit, a driving circuit, a power tube and a feedback network, a negative feedback loop is formed through the error amplifier and the power tube and the feedback network, so that the output voltage VOUT is proportional to the reference voltage of the in-phase input end of the error amplifier, and the ripple on the power supply is processed through the feedforward ripple circuit, and then injected into the gate end of the power tube through the summing circuit, so that the power supply rejection ratio of the low-dropout linear voltage stabilizing circuit is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to the design of a low dropout linear regulator circuit with high power supply rejection ratio. Background Technology

[0002] Low-dropout linear regulators (LDOs) are power management integrated circuits (PMICs) whose advantage lies in providing low-noise output. This characteristic makes them widely used in cutting-edge fields such as 5G communications, artificial intelligence, and medical electronics, improving circuit accuracy and anti-interference capabilities. To meet the higher noise suppression requirements of modern mixed-signal systems, it is necessary to further improve the power supply rejection ratio (PSRR) of LDOs.

[0003] Currently, there are generally two approaches to improve the PSRR of an LDO: (1) Using an NMOS power transistor: Since power supply noise is superimposed on the drain of the NMOS power transistor, it has little impact on the gate-source voltage of the power transistor, thus avoiding the power supply noise from affecting the output of the LDO, i.e., the LDO has a high PSRR. However, due to the shielding effect of the NMOS power transistor on power supply noise, it is difficult to further improve the PSRR of the LDO through ripple injection. (2) Using a PMOS power transistor to improve the PSRR through feedforward ripple injection. By replicating the ripple of the power supply, i.e., the source of the PMOS power transistor, and injecting it into the gate of the PMOS power transistor, the gate-source voltage of the power transistor remains unchanged, thus avoiding the power supply noise from affecting the output of the LDO, making the LDO have a high PSRR. However, due to the poor shielding effect of the PMOS power transistor on power supply noise, the PSRR of the LDO is more dependent on the implementation effect of feedforward ripple injection. Summary of the Invention

[0004] The purpose of this invention is to address the problem that existing technologies for improving the power supply rejection ratio (PSRR) of LDOs are insufficient to further improve the PRR through ripple injection due to the shielding effect of NMOS power transistors on power supply noise. This invention proposes a low-dropout linear regulator circuit with high PRR, which uses an NMOS output power transistor and employs feedforward ripple elimination technology to achieve the required high PRR.

[0005] The technical solution of the present invention is as follows: a low dropout linear regulator circuit with high power supply rejection ratio, comprising a feedforward ripple circuit, an error amplifier, a summing circuit, a drive circuit, a power transistor, and a feedback network. The power transistor and the feedback network are respectively connected to the error amplifier and the drive circuit, and the summing circuit is respectively connected to the feedforward ripple circuit, the error amplifier, and the drive circuit.

[0006] Furthermore, the feedforward ripple circuit includes an operational amplifier chip OP. The non-inverting input of the operational amplifier chip OP is connected to one end of resistor R1 and one end of resistor R2, respectively. Its inverting input is connected to the reference voltage VREF2. Its output is connected to the gate of NMOS transistor N3 and the summing circuit, respectively. The other end of resistor R1 is connected to the power supply voltage VIN. The other end of resistor R2 is connected to the drain of NMOS transistor N3, the drain of NMOS transistor N2, and the drain of PMOS transistor P4, respectively. The source of NMOS transistor N3 is grounded, the source of NMOS transistor N2 is grounded, and its gate is connected to the gate bias voltage NB1. The source of PMOS transistor P4 is connected to the drain of PMOS transistor P3, and its gate is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P2, and the drain of NMOS transistor N1, respectively. The gate of NMOS transistor N1 is connected to the gate voltage V of the power transistor. G The source of PMOS transistor P3 generates the output voltage VOUT. The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P1, the drain of PMOS transistor P1, and the source of PMOS transistor P2, respectively. The source of PMOS transistor P3 and the source of PMOS transistor P1 are both connected to the front-stage charge pump voltage LV.

[0007] Furthermore, the error amplifier includes an error amplifier chip EA. The non-inverting input of the error amplifier chip EA is connected to the reference voltage VREF1, its inverting input is connected to the power transistor and the feedback network, and its output is connected to the summing circuit.

[0008] Furthermore, the summing circuit includes NMOS transistors N4, NMOS transistor N5, and NMOS transistor N6. The drain of NMOS transistor N4 is connected to the front-end charge pump voltage LV, its gate is connected to the output terminal of the error amplifier chip EA, and its source is connected to the drain of NMOS transistor N5 and the driving circuit, respectively. The gate of NMOS transistor N5 is connected to the gate bias voltage NB2, its source is connected to the drain of NMOS transistor N6, the source of NMOS transistor N6 is grounded, and its gate is connected to the output terminal of the operational amplifier chip OP.

[0009] Furthermore, the driving circuit includes PMOS transistors P5, P6, P7, P8, and NMOS transistor N7. The sources of PMOS transistors P5 and P6 are both connected to the front-end charge pump voltage LV. The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P5 and the gate of PMOS transistor P6, respectively, and grounded. The drain of PMOS transistor P6 is connected to the source of PMOS transistor P7, the power transistor, and the feedback network, respectively. The gate of PMOS transistor P7 is connected to the source of NMOS transistor N4, and its drain is connected to the source of PMOS transistor P8. The gate of PMOS transistor P8 is connected to the gate bias voltage PB4, and its drain is connected to the drain of NMOS transistor N7 and the gate of NMOS transistor N7, respectively. The source of NMOS transistor N7 is grounded.

[0010] Furthermore, the power transistor and feedback network include power transistor N Power power transistor N Power The drain of the transistor is connected to the power supply voltage VIN, its gate is connected to the drain of the PMOS transistor P6, and its source is connected to one end of resistor Rf1, ground resistor RL and ground capacitor CL respectively, generating the output voltage VOUT. The other end of resistor Rf1 is connected to ground resistor Rf2 and the inverting input terminal of error amplifier chip EA respectively.

[0011] The beneficial effects of this invention are: This invention forms a negative feedback loop through an error amplifier, a power transistor, and a feedback network, making the output voltage VOUT proportional to the reference voltage at the non-inverting input of the error amplifier. The ripple on the power supply is processed by a feedforward ripple circuit and then injected into the gate of the power transistor through a summing circuit, thereby improving the power supply rejection ratio of the low dropout linear regulator circuit. Attached Figure Description

[0012] Figure 1 The diagram shown is a low dropout linear regulator circuit with high power supply rejection ratio provided in an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached diagram: 101-Feedforward ripple circuit, 102-Error amplifier, 103-Summarizing circuit, 104-Driver circuit, 105-Power transistor and feedback network. Detailed Implementation

[0014] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.

[0015] This invention provides a low-dropout linear regulator circuit with high power supply rejection ratio, such as... Figure 1As shown, it includes a feedforward ripple circuit 101, an error amplifier 102, a summing circuit 103, a drive circuit 104, and a power transistor and feedback network 105. The power transistor and feedback network 105 are connected to the error amplifier 102 and the drive circuit 104, respectively. The summing circuit 103 is connected to the feedforward ripple circuit 101, the error amplifier 102, and the drive circuit 104, respectively.

[0016] like Figure 1 As shown, the feedforward ripple circuit 101 includes an operational amplifier chip OP. The non-inverting input of the operational amplifier chip OP is connected to one end of resistor R1 and one end of resistor R2, respectively. Its inverting input is connected to the reference voltage VREF2. Its output is connected to the gate of NMOS transistor N3 and the summing circuit 103, respectively. The other end of resistor R1 is connected to the power supply voltage VIN. The other end of resistor R2 is connected to the drain of NMOS transistor N3, the drain of NMOS transistor N2, and the drain of PMOS transistor P4, respectively. The source of NMOS transistor N3 is grounded, the source of NMOS transistor N2 is grounded, and its gate is connected to the gate bias voltage NB1. The source of PMOS transistor P4 is connected to the drain of PMOS transistor P3, and its gate is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P2, and the drain of NMOS transistor N1, respectively. The gate of NMOS transistor N1 is connected to the gate voltage V of the power transistor. G The source of PMOS transistor P3 generates the output voltage VOUT. The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P1, the drain of PMOS transistor P1, and the source of PMOS transistor P2, respectively. The source of PMOS transistor P3 and the source of PMOS transistor P1 are both connected to the front-stage charge pump voltage LV.

[0017] like Figure 1 As shown, the error amplifier 102 includes an error amplifier chip EA. The non-inverting input of the error amplifier chip EA is connected to the reference voltage VREF1, its inverting input is connected to the power transistor and the feedback network 105, and its output is connected to the summing circuit 103.

[0018] like Figure 1 As shown, the summing circuit 103 includes NMOS transistors N4, NMOS transistor N5, and NMOS transistor N6. The drain of NMOS transistor N4 is connected to the front-end charge pump voltage LV, its gate is connected to the output terminal of the error amplifier chip EA, and its source is connected to the drain of NMOS transistor N5 and the driving circuit 104, respectively. The gate of NMOS transistor N5 is connected to the gate bias voltage NB2, its source is connected to the drain of NMOS transistor N6, the source of NMOS transistor N6 is grounded, and its gate is connected to the output terminal of the operational amplifier chip OP.

[0019] like Figure 1As shown, the driving circuit 104 includes PMOS transistors P5, P6, P7, P8, and NMOS transistor N7. The sources of PMOS transistors P5 and P6 are connected to the front-end charge pump voltage LV. The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P5 and the gate of PMOS transistor P6, and is grounded. The drain of PMOS transistor P6 is connected to the source of PMOS transistor P7, the power transistor, and the feedback network 105. The gate of PMOS transistor P7 is connected to the source of NMOS transistor N4, and its drain is connected to the source of PMOS transistor P8. The gate of PMOS transistor P8 is connected to the gate bias voltage PB4, and its drain is connected to the drain of NMOS transistor N7 and the gate of NMOS transistor N7. The source of NMOS transistor N7 is grounded.

[0020] like Figure 1 As shown, the power transistor and feedback network 105 includes power transistor N. Power power transistor N Power The drain of the transistor is connected to the power supply voltage VIN, its gate is connected to the drain of the PMOS transistor P6, and its source is connected to one end of resistor Rf1, ground resistor RL and ground capacitor CL respectively, generating the output voltage VOUT. The other end of resistor Rf1 is connected to ground resistor Rf2 and the inverting input terminal of error amplifier chip EA respectively.

[0021] The following is combined with Figure 1 The working principle and process of this invention are described in detail below.

[0022] In this embodiment of the invention, the basic LDO loop consists of error amplifier chip EA, NMOS transistor N4, PMOS transistor P7, and power transistor N. Power The circuit consists of a feedback network, where resistor RL and capacitor CL are the load resistor and load capacitor, respectively. The non-inverting input of error amplifier chip EA is connected to VREF1, a reference voltage provided by the bandgap reference voltage source from the preceding stage. Based on the virtual short characteristic of error amplifier chip EA, the voltage VFB at its inverting input is equal to VREF1, thus yielding the formula for the output voltage VOUT: The feedback process of the loop is analyzed as follows: When the load of the LDO changes, taking the change from light load to heavy load as an example, the output voltage VOUT decreases, VFB decreases, and the output voltage VEA of the error amplifier chip EA increases. After passing through the two source followers, NMOS transistor N4 and PMOS transistor P7, the NMOS power transistor N... Power The gate voltage rises, thereby pulling the output voltage VOUT high, forming negative feedback.

[0023] The formula for calculating the power supply rejection ratio (PSRR) of an LDO is: in Indicates loop gain. This represents the feedforward transfer function from the power supply voltage VIN to the output voltage VOUT. This represents a complex frequency variable. As the formula shows, to obtain a high PSRR, one can either increase the loop gain or minimize the feedforward path from the power supply voltage VIN to the output voltage VOUT. This embodiment of the invention employs the latter approach, which will be analyzed in detail below.

[0024] There are two noise paths from the power supply voltage VIN to the output voltage VOUT. Path one starts from the power transistor N. Power From the drain to the output voltage VOUT, path two passes through the feedforward ripple circuit 101, the summing circuit 103, and the drive circuit 104, from the power transistor N. Power From the gate to the output voltage VOUT, the feedforward transfer function from the power supply voltage VIN to the output voltage VOUT can be obtained as follows: in Indicates power transistor N Power The output conductance, Indicates the equivalent output impedance. This indicates the gain of the feedforward ripple circuit 101. This represents the gain of the summing circuit 103, which is -1 in this embodiment of the invention. Indicates power transistor N Power transconductance, Indicates power transistor N Power The intrinsic gain. The formulas for calculating some of the parameters are as follows: in Indicates power transistor N Power The output resistance. Therefore, as long as the gain of the feedforward ripple circuit 101 is adjusted... For intrinsic gain The reciprocal of the gain of the feedforward ripple circuit 101 can cancel out the ripple in the feedforward path, thereby improving the PSRR. It can be represented as: in This indicates the gate potentials of NMOS transistors N3 and N6. This represents the drain of NMOS transistor N3, which is... Figure 1 The potential at node B in the middle This represents the intrinsic gain of NMOS transistor N3. By setting resistor R1 = R2, V can be obtained.B / VIN=-1, therefore we have ,Right now Therefore, the design goal of the feedforward ripple circuit 101 can be simplified to: enabling the NMOS transistor N3 to have the same characteristics as the power transistor N. Power The same intrinsic gain. The intrinsic gain is ,in Indicates the transconductance of the MOSFET. This indicates the output resistance of the MOSFET. This indicates the leakage current of the MOSFET. This represents the overdrive voltage of the MOSFET. This represents the channel length modulation effect coefficient of the MOSFET; therefore, the NMOS transistor N3 needs to be compared with the power transistor N. Power There are the same and NMOS transistor N1 replicates power transistor N at a certain ratio. Power The current is mirrored to NMOS transistor N3, and NMOS transistor N3 is the power transistor N. Power By reducing the number of transistors by the same proportion, we obtain (NMOS transistor N3 and power transistor N). Power (The aspect ratio of each transistor remains consistent). VREF2 is a reference voltage. By setting its value to VIN-1 / (2*VOUT), and considering the condition R1=R2, we know that VB=VIN-VOUT, that is, the drain-source voltage of NMOS transistor N3 is equal to that of power transistor N. Power Equal. Combining the above points, the same current density and drain-source voltage make NMOS transistor N3 and power transistor N... Power There are the same Due to the short-channel effect, the same channel length makes NMOS transistor N3 and power transistor N... Power There are the same Therefore, This achieves the effect of feedforward ripple and improves PSRR.

[0025] As mentioned earlier, the summing circuit 103 needs to achieve a gain of -1. Figure 1 As shown, the gain of the summing circuit Approximately: in and These represent the transconductances of NMOS transistors N4 and N6, respectively. Therefore, by setting the dimensions of NMOS transistor N6 to be the same as those of NMOS transistor N4, the desired result can be achieved. .

[0026] The functions of the other MOSFETs are as follows: NMOS transistor N2 consumes the current along the path of resistors R1 and R2, preventing it from affecting NMOS transistor N3. PMOS transistor P7 is a source follower, acting as a pole separator to improve loop stability to some extent. PMOS transistor P6 drives power transistor N. Power The gate, together with PMOS transistor P8 and NMOS transistor N7, provides a current path for PMOS transistor P7.

[0027] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A low-dropout linear regulator circuit with high power supply rejection ratio, characterized in that, It includes a feedforward ripple circuit (101), an error amplifier (102), a summing circuit (103), a driving circuit (104), and a power transistor and feedback network (105). The power transistor and feedback network (105) are connected to the error amplifier (102) and the driving circuit (104), respectively. The summing circuit (103) is connected to the feedforward ripple circuit (101), the error amplifier (102), and the driving circuit (104), respectively.

2. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 1, characterized in that, The feedforward ripple circuit (101) includes an operational amplifier chip OP. The non-inverting input of the operational amplifier chip OP is connected to one end of resistor R1 and one end of resistor R2, respectively. Its inverting input is connected to a reference voltage VREF2. Its output is connected to the gate of NMOS transistor N3 and a summing circuit (103), respectively. The other end of resistor R1 is connected to the power supply voltage VIN. The other end of resistor R2 is connected to the drain of NMOS transistor N3, the drain of NMOS transistor N2, and the drain of PMOS transistor P4, respectively. The source of NMOS transistor N3 is grounded, the source of NMOS transistor N2 is grounded, and its gate is connected to the gate bias voltage NB1. The source of PMOS transistor P4 is connected to the drain of PMOS transistor P3, and its gate is connected to the gate of PMOS transistor P2, the drain of PMOS transistor P2, and the drain of NMOS transistor N1, respectively. The gate of NMOS transistor N1 is connected to the power transistor gate voltage VIN. G The source of the PMOS transistor generates the output voltage VOUT. The gate of the PMOS transistor P3 is connected to the gate of the PMOS transistor P1, the drain of the PMOS transistor P1, and the source of the PMOS transistor P2. The source of the PMOS transistor P3 and the source of the PMOS transistor P1 are both connected to the front-stage charge pump voltage LV.

3. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 2, characterized in that, The error amplifier (102) includes an error amplifier chip EA. The non-inverting input of the error amplifier chip EA is connected to the reference voltage VREF1, the inverting input is connected to the power transistor and the feedback network (105), and the output is connected to the summing circuit (103).

4. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 3, characterized in that, The summing circuit (103) includes NMOS transistors N4, NMOS transistor N5 and NMOS transistor N6. The drain of NMOS transistor N4 is connected to the front-end charge pump voltage LV, its gate is connected to the output terminal of error amplifier chip EA, and its source is connected to the drain of NMOS transistor N5 and the driving circuit (104) respectively. The gate of NMOS transistor N5 is connected to the gate bias voltage NB2, its source is connected to the drain of NMOS transistor N6, the source of NMOS transistor N6 is grounded, and its gate is connected to the output terminal of operational amplifier chip OP.

5. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 4, characterized in that, The driving circuit (104) includes PMOS transistors P5, P6, P7, P8 and NMOS transistor N7. The source of PMOS transistor P5 and the source of PMOS transistor P6 are both connected to the front-stage charge pump voltage LV. The gate of PMOS transistor P5 is connected to the drain of PMOS transistor P5 and the gate of PMOS transistor P6 and grounded. The drain of PMOS transistor P6 is connected to the source of PMOS transistor P7 and the power transistor and feedback network (105). The gate of PMOS transistor P7 is connected to the source of NMOS transistor N4 and its drain is connected to the source of PMOS transistor P8. The gate of PMOS transistor P8 is connected to the gate bias voltage PB4 and its drain is connected to the drain of NMOS transistor N7 and the gate of NMOS transistor N7. The source of NMOS transistor N7 is grounded.

6. The low dropout linear regulator circuit with high power supply rejection ratio according to claim 5, characterized in that, The power transistor and feedback network (105) include power transistor N Power The power transistor N Power The drain of the transistor is connected to the power supply voltage VIN, its gate is connected to the drain of the PMOS transistor P6, and its source is connected to one end of resistor Rf1, ground resistor RL and ground capacitor CL respectively, generating the output voltage VOUT. The other end of resistor Rf1 is connected to ground resistor Rf2 and the inverting input terminal of error amplifier chip EA respectively.

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