A bandgap reference circuit with exponential current compensation for high order curvature

Abstract

The application discloses a band gap reference circuit with exponential current compensation high-order curvature, comprising: a start-up circuit, a band gap reference core circuit, a current extraction circuit and an exponential curvature compensation circuit connected in sequence; the start-up circuit is used for inputting initial current to make the circuit deviate from the degenerate point; the band gap reference core circuit is used for making the voltage across VM and VP equal, then adding V BE and AV BE on the resistors respectively to obtain I CTAT and I PTAT current, and copying the current to the subsequent high-order compensation circuit through a current mirror for compensation; the current extraction circuit is used for stabilizing the base current of the PNP transistor; the exponential curvature compensation circuit is used for offsetting the high-order term of V BE by using the exponential relationship between the current flowing through the MOS device working in the sub-threshold region and the temperature T, so that the exponential current in the sub-threshold region is offset. Compared with the first-order band gap reference circuit, the application greatly improves the stability of the output reference voltage V REF in a wide temperature range.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a bandgap reference circuit for exponential current compensation of higher-order curvature. Background Technology

[0002] Reference circuits can be categorized into voltage references and current references based on the physical quantities they generate, and they have wide applications in fields such as mixed-signal integrated circuits. The technology for bandgap reference circuits has been developing for many years. Traditional bandgap reference circuits rely on the fact that the base-emitter voltage VBE of a bipolar junction transistor (BJT) is negatively correlated with temperature, i.e., it has a negative temperature coefficient; while the difference ΔVBE between the VBEs of two BJTs operating at different current densities is positively correlated with temperature, i.e., it has a positive temperature coefficient.

[0003] Traditional bandgap reference circuits can only compensate for the first-order term of VBE, and VBE has higher-order terms, which the first-order compensated bandgap reference cannot compensate for. As a result, when performing temperature coefficient simulation on the first-order bandgap reference circuit, a parabolic image with the opening facing downwards is obtained, which shows a certain "curvature" and seriously affects the accuracy of the reference voltage over a wide temperature range.

[0004] Modern mixed-signal integrated circuits have increasingly stringent requirements for bandgap references. To adapt to the development of integrated circuits, various techniques exist for compensating for second-order and even higher-order terms of VBE: 1. Additional temperature-dependent terms, such as the early effect of transistors, substrate bias effect, and temperature coefficient of resistors, can be used to offset the second-order term of VBE. However, higher-order curvature still exists, and the effectiveness of this compensation depends on device matching and is sensitive to changes in process and voltage.

[0005] 2. Beta compensation technology is used, which utilizes the exponential temperature characteristic of the forward bias current gain of NPN transistors to correct the nonlinear component of diode voltage. However, this technology suffers from problems such as high process sensitivity of the beta value, the need to introduce multiple additional components, amplification of noise, and increased power consumption.

[0006] 3. Using digital auxiliary compensation technology, temperature information is collected through an on-chip temperature sensor and combined with a digital calibration circuit to correct high-order curvature in real time. This technology requires complex calibration algorithms and a large number of storage units, which greatly increases the cost.

[0007] The technology for compensating for the high-order curvature of bandgap reference circuits has been developed for many years, but problems still exist, such as the high complexity of high-order curvature compensation circuits and performance degradation under process deviations and voltage fluctuations. Summary of the Invention

[0008] This invention aims to address the shortcomings of existing technologies and provides the following solutions: A bandgap reference circuit for exponential current compensation of high-order curvature includes: a startup circuit, a bandgap reference core circuit, a current extraction circuit, and an exponential curvature compensation circuit connected in sequence. The startup circuit is used to input an initial current to bring the circuit away from its degeneracy point; The core circuitry of the bandgap reference is used to make the voltages across VM and VP equal, and then by passing V... BE and ΔV BE When applied to the resistors respectively, I is obtained. CTAT and I PTAT The current is then copied through a current mirror to a subsequent higher-order compensation circuit for compensation. The current extraction circuit is used to stabilize the base current of the PNP transistor. The exponential curvature compensation circuit utilizes the exponential relationship between the current flowing through a MOS device and temperature T when it operates in the subthreshold region to cancel the exponential current V in the subthreshold region. BE The higher-order term.

[0009] Preferably, the startup circuit includes: transistors M1, M2, M12, M13, M14, M68, M11, M24, M30, M31, M33, M34, M35, M69, and M70. The gate of transistor M1 is connected to the applied low-level active enable signal ENN, its source is connected to the power supply voltage VDD, and its drain is connected to the drain of transistor M11, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M2 is connected to the drain of transistor M31, its source is connected to the power supply voltage VDD, and its drain is connected to the source of transistor M14. The gate of transistor M11 is connected to the low-level active enable signal ENN, its source is connected to GND, and its drain is connected to the drain of transistor M1, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M12 is connected to GND, the source to the power supply voltage VDD, and the drain to the drain of transistor M24. The gate of transistor M13 is connected to the drain of transistor M13, the gate of transistor M14, and the drain of transistor M68; the source is connected to the power supply voltage VDD; and the drain is connected to the gate of transistor M13, the drain of transistor M30, and the drain of transistor M34. The gate of transistor M14 is connected to the gate of transistor M13 and the drain of transistor M68; the source is connected to the drain of transistor M2; and the drain is connected to the drain of transistor M35. The voltage output V... BIAS1The following transistors are connected: the gate of M24 is connected to the gate of M68, the source is connected to the gate of M30 and the drain of M33, and the drain is connected to the drain of M12; the gate of M30 is connected to the source of M24, the gate of M31, the drain of M33, and the drain of M69, the source is connected to GND, and the drain is connected to the drain of M13 and the drain of M34; the gate of M31 is connected to the source of M24, the gate of M30, the drain of M33, and the drain of M69, the source is connected to GND, and the drain is connected to the gate of M2; the gate of M33 is connected to the gate of M34, the source is connected to GND, and the drain is connected to the source of M24, the gate of M30, and the drain of M69.

[0010] Preferably, the core circuit of the bandgap reference includes: operational amplifier OP1, operational amplifier OP2, transistors M6, M7, M18, M19, M32, M37, M71, M72, M73, M74, M75, M76, M77, M78, transistor Q1, Q2, Q3, Q4, Q6, resistors R1, R2, R3, R5, and R6; The gate of transistor M6 is connected to the gates of transistors M71 and M7, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M18. The gate of transistor M7 is connected to the gates of transistors M6 and M71, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M19. The gate of transistor M18 is connected to its drain, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, the upper end of resistor R2, the gate of transistor M19, and the drain of transistor M75. Its source is connected to the drain of transistor M6, and its drain is connected to the gate of transistor M18, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, and the drain of transistor R2. The upper end of transistor 2 is connected to the gate of transistor M19 and the drain of transistor M75; the gate of transistor M19 is connected to the gate and drain of transistor M18, and its source is connected to the drain of transistor M7. The drain is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, and the upper end of resistor R3; the gate of transistor M32 is connected to the output terminal of operational amplifier OP2, its source is connected to VDD, and its drain is connected to the source of transistor M37; the gate of transistor M37 is connected to the drain of transistor M37, the VP2 terminal of operational amplifier OP2, and the upper end of resistor R5, its source is connected to the drain of transistor M32, and its drain is connected to the gate of transistor M37; the gate of transistor M71 is connected to the gates of transistors M6 and M7, and the output terminal of operational amplifier OP1. The gate of transistor M72 is connected to VDD, and its drain is connected to the source of transistor M72. The gate of transistor M72 is connected to the gate of transistor M14 in the startup circuit, its source is connected to the drain of transistor M71, and its drain is connected to the drain of transistor M73 and the emitter of transistor Q6. The gate of transistor M73 is connected to the gate of transistor M74, its source is connected to VDD, and its drain is connected to the drain of transistor M72 and the emitter of transistor Q6. The gate of transistor M74 is connected to the gate of transistor M73 and the drain of transistor M74, its source is connected to VDD, and its drain is connected to the gate of transistor M74 and the drain of transistor M78. The gate of transistor M75 is connected to the gate of transistor M74, its source is connected to VDD, and its drain is connected to the drain of transistor M18, the VM1 terminal of operational amplifier OP1, and the emitter of transistor Q1. The following connections are made: M76's gate is connected to M75's gate, its source to VDD, and its drain to the lower end of resistor R3 and the emitter of Q3; M77's gate is connected to M78's gate and drain, its source to GND, and its drain to the base of Q6; M78's gate is connected to M77's gate, its source to GND, and its drain to M74's drain; Q1's emitter is connected to the upper end of resistor R1 and R2, the drain of M18, and the VM1 terminal of operational amplifier OP1; its base is connected to Q2's emitter, and its collector to GND; Q2's emitter is connected to Q1's base, its base to GND, and its collector to GND.The emitter of transistor Q3 is connected to the lower end of resistor R3 and the drain of transistor M76; its base is connected to the emitter of transistor Q4; and its collector is connected to GND. The emitter of transistor Q4 is connected to the base of transistor Q3, and its base and collector are both connected to GND. The emitter of transistor Q6 is connected to the drains of transistors M72 and M73; its base is connected to the drain of transistor M77; and its collector is connected to GND. Resistor R1 is connected to the emitter of transistor Q1 and GND. Resistor R2 is connected to the emitter of transistor Q1 and GND. Resistor R3 is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, the drain of transistor M19, the emitter of transistor Q3, and the drain of transistor M76. Resistor R5 is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, the drain of transistor M19, the emitter of transistor Q3, and the drain of transistor M76. The VP2 terminal of P2, the drain of M37 transistor, the voltage divider output terminal VB, and the upper end of resistor R6 are connected; the two ends of resistor R6 are connected to the lower end of resistor R5, the voltage divider output terminal VB, and GND, respectively; the VM1 terminal of operational amplifier OP1 is connected to the drain of M18 transistor, the emitter of Q1 transistor, the drain of M75 transistor, the upper end of resistor R1, and the upper end of resistor R2; the VP1 terminal is connected to the drain of M19 transistor, the upper end of resistor R3, and the VM2 terminal of operational amplifier OP2; the output terminal VOUT1 is connected to the gate of M7 transistor; the VM2 terminal of operational amplifier OP2 is connected to the VP1 terminal of operational amplifier OP1, the drain of M19 transistor, and the upper end of resistor R3; the VP2 terminal is connected to the drain of M37 transistor and the upper end of resistor R5; the output terminal VOUT2 is connected to the gate of M32 transistor.

[0011] Preferably, the operational amplifier OP1 includes: transistors M38, M9, M40, M41, M42, M43, M44, M45, and M46; The gate of transistor M38 is connected to the drain of transistor M38 and the gate of transistor M39; its source is connected to VDD; and its drain is connected to the gate of transistor M38 and the drain of transistor M42. The gate of transistor M39 is connected to the gate of transistor M38; its source is connected to VDD; and its drain is connected to the gate of transistor M40, the drain of transistor M43, and the output terminal VOUT1. The gate of transistor M40 is connected to the drain of transistor M39; its source is connected to VDD; and its drain is connected to the gates and drains of transistors M41, M42, and M43. The gate of transistor M41 is connected to the drain of transistor M41 and the gate of transistor M42; and its source is connected to the drain of transistor M46. The drain of transistor M42 is connected to the gate of transistor M41 and the drain of transistor M40; the gate of transistor M42 is connected to the gate of transistor M41, the source is connected to the drain of transistor M44, and the drain of transistor M38; the gate of transistor M43 is connected to the gate of transistor M42, the source is connected to the drain of transistor M45, and the drain of transistor M39, the gate of transistor M40, and the output terminal VOUT1; the gate of transistor M44 is connected to terminal VP1, the source is connected to the drain of transistor M46, and the drain of transistor M42; the gate of transistor M45 is connected to terminal VM1, the source is connected to the drain of transistor M46, and the drain of transistor M43; the gate of transistor M46 is connected to the voltage output V. BIAS1 The source is connected to GND, and the drain is connected to the source of transistors M41, M44, and M45.

[0012] Preferably, the operational amplifier OP2 includes: transistors M47, M48, M49, M50, M51, M52, M53, M54, and M55; The gate of transistor M47 is connected to the drain of transistor M47 and the gate of transistor M48; its source is connected to VDD; and its drain is connected to the gate of transistor M47 and the drain of transistor M51. The gate of transistor M48 is connected to the gate of transistor M47; its source is connected to VDD; and its drain is connected to the gate of transistor M49, the drain of transistor M52, and the output terminal VOUT2. The gate of transistor M49 is connected to the drain of transistor M48, the drain of transistor M52, and the output terminal VOUT2; its source is connected to VDD; and its drain is connected to the drain of transistor M50. The gate of transistor M50 is connected to the drain of transistor M50 and the gate of transistor M51; and its source is connected to the drain of transistor M55. The drain of transistor M51 is connected to the gate of transistor M50 and the drain of transistor M49; the gate of transistor M51 is connected to the gate of transistor M50, the source is connected to the drain of transistor M53, and the drain of transistor M47; the gate of transistor M52 is connected to the gate of transistor M51, the source is connected to the drain of transistor M54, and the drain of transistor M48, the gate of transistor M49, and the output terminal VOUT2; the gate of transistor M53 is connected to terminal VP2, the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M51; the gate of transistor M54 is connected to terminal VM2; the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M52; the gate of transistor M55 is connected to the voltage output V. BIAS1The source is connected to GND, and the drain is connected to the source of the M50, M53, and M54 transistors.

[0013] Preferably, the current extraction circuit includes: a current extraction main circuit, a logic control unit, and transistors M3, M4, M5, M15, M16, M17, and M36; the current extraction main circuit includes: transistors M56, M57, M58, M59, M60, M61, M62, M63, M64, M65, M66, and M67. The gate of transistor M3 is connected to the gate of transistor M4, its source is connected to VDD, and its drain is connected to the source of transistor M15. The gate of transistor M4 is connected to the gates of both transistors M3 and M5, its source is connected to VDD, and its drain is connected to the source of transistor M16. The gate of transistor M5 is connected to the gate of transistor M4, its source is connected to VDD, and its drain is connected to the source of transistor M17. The gate of transistor M15 is connected to the gate of transistor M16, its source is connected to the drain of transistor M3, and its drain is connected to the drain of transistor M36. The gate of transistor M16 is connected to the gates of both transistors M15 and M17, its source is connected to the drain of transistor M4, and its drain is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M17 is connected to the gate of transistor M16, and its source is connected to the drain of transistor M5. The drain is connected to the output I of the current extraction circuit. BIAS2 Connected; the gate of the M36 transistor is connected to the drain of the M36 transistor, and the input V of the current extraction circuit is connected. BIAS2 The drain of transistor M15 is connected to the drain of transistor M15, and the source is connected to GND; the gate of transistor M56 is connected to CTRL1, the source is connected to the drain of transistor M64, and the drain is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M57 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M64 is connected to the drain of transistor M58; the gate of transistor M58 is connected to CTRL1, and the source is connected to the drain of transistor M65. The drain of M58 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M59 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M60 is connected to the drain of transistor M65; the gate of transistor M60 is connected to CTRL1, and its source is connected to the drain of transistor M66. The drain of M60 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M61 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M62 is connected to the drain of transistor M66; the gate of transistor M62 is connected to CTRL1, and its source is connected to the drain of transistor M67. The drain of M62 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M63 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2The drain of transistor M64 is connected to the drain of transistor M67; the gate of transistor M64 is connected to the input V of the current extraction circuit. BIAS2 The source of transistor M55 is connected to GND, and the drain is connected to the source of transistor M56 and the drain of transistor M57. The gate of transistor M65 is connected to the input V of the current extraction circuit. BIAS2 The source of transistor M66 is connected to GND, and the drain is connected to the source of transistor M58 and the drain of transistor M59. The gate of transistor M66 is connected to the input V of the current extraction circuit. BIAS2 The source of transistor M67 is connected to GND; the drain of M67 is connected to the source of transistor M60 and the drain of transistor M61; the gate of transistor M67 is connected to the input V of the current extraction circuit. BIAS2 The source is connected to GND, and the drain is connected to the source of the M62 transistor and the drain of the M63 transistor. The three input ports of the logic control unit are the external control signals CTRL0, VDD and GND, and the two output ports are CTRL1 and CTRL2.

[0014] Preferably, the compensation circuit includes: transistors M8, M9, M10, M20, M21, M22, M23, M25, M26, M27, M28, M29, Q5, resistors R4, R7, R8, R9, and R10. The gate of transistor M8 is connected to the gates of transistors M9 and M10, its source is connected to VDD, and its drain is connected to the source of transistor M20. The gate of transistor M9 is connected to the gates of transistors M8 and M10, its source is connected to VDD, and its drain is connected to the source of transistor M21. The gate of transistor M10 is connected to the gates of transistors M8 and M9, its source is connected to VDD, and its drain is connected to the sources of transistors M22 and M23. The gate of transistor M20 is connected to the gate of transistor M21, its source is connected to the drain of transistor M8, and its drain is connected to the upper end of resistor R4 and the voltage signal V. A Connected; the gate of transistor M21 is connected to the gate of transistor M20, and its source is connected to the drain of transistor M9. The drain is connected to the upper end of resistor R7 and the voltage signal V. REF The drain of transistor M26 is connected to the gate of transistor M22, which is connected to the voltage signal V. REF01 The source of transistor M23 is connected to the drain of transistor M10, and the drain is connected to the upper end of resistor R10; the gate of transistor M23 is connected to the voltage signal V. B The source of transistor M25 is connected to the drain of transistor M10, and the drain is connected to GND. The gate of transistor M25 is connected to the gate of transistor M32 in the bandgap reference core circuit, the source is connected to VDD, and the drain is connected to the source of transistor M26. The gate of transistor M26 is connected to the gate and drain of transistor M37 in the bandgap reference core circuit, the source is connected to the drain of transistor M25, and the drain is connected to the upper end of resistor R7 and the voltage signal V. REFThe drain of transistor M21 is connected to the drain of transistor M27; the gate of transistor M27 is connected to the gate of transistor M25 and the gate of transistor M32 in the bandgap reference core circuit, the source of M32 is connected to VDD, and the drain of M27 is connected to the source of transistor M28 and the source of transistor M29; the gate of transistor M28 is connected to the voltage signal VDD. REF02 The source of transistor M23 is connected to the drain of transistor M27, and the drain is connected to the upper end of resistor R10; the gate of transistor M23 is connected to the voltage signal V. A Connect the source to the drain of transistor M27, and connect the drain to GND; connect the upper end of resistor R4 to the drain of transistor M20, and connect the voltage output V. A The lower end is connected to GND; the upper end of resistor R7 is connected to the drain of transistor M21, the drain of transistor M26, and the voltage output V. REF The lower end is connected to the voltage output V. REF01 The upper end of resistor R8 is connected to the voltage output V. REF01 The lower end is connected to the voltage output V. REF02 The upper end of resistor R9 is connected to the voltage output V. REF02 The lower end is connected to the drain of transistor M22, the drain of transistor M28, and the upper end of resistor R10; the upper end of resistor R10 is connected to the drain of transistor M22, the drain of transistor M28, and the lower end of resistor R9, and the lower end of resistor R9 is connected to the emitter of transistor Q5; the emitter of transistor Q5 is connected to the lower end of resistor R10, the base is connected to GND, and the collector is connected to GND.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The bandgap reference circuit of this invention uses a current extraction circuit to stabilize the base current of the PNP transistor, while using a current mirror circuit to cancel the offset voltage effect at the input of the operational amplifier. The compensation circuit utilizes the exponential relationship between the subthreshold current of the MOSFET and temperature T, and generates a higher-order voltage after flowing through a resistor. This voltage is then weighted and summed to cancel the VCTAT of VBE. Compared with the first-order bandgap reference circuit, this greatly improves the stability of the output reference voltage VREF over a wide temperature range, providing a reliable reference voltage for high-performance integrated circuits. If applied to an ADC circuit, it can reduce the code loss rate of the digital output code. Attached Figure Description

[0016] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the circuit structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the startup circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal circuit structure of the operational amplifier OP1 according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the internal circuit structure of the operational amplifier OP2 according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit structure of the bandgap reference core circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit structure of the current extraction circuit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the circuit structure of the current extraction main circuit according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the circuit structure of the exponential current curvature compensation circuit according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Example In this embodiment, as Figure 1 As shown, a bandgap reference circuit with exponential current compensation for higher-order curvature includes: a startup circuit, a bandgap reference core circuit, a current extraction circuit, and an exponential curvature compensation circuit connected in sequence.

[0021] The startup circuit is used to input an initial current to bring the circuit away from its degeneracy point.

[0022] In this embodiment, because all transistors in the bandgap reference circuit transmit zero current when the power supply is first applied, i.e., the circuit is at its degenerate operating point, the circuit cannot enter the working state. An external injection of initial current is required to bring the circuit out of the degenerate point. This problem can be solved by adding a startup circuit. To reduce static power consumption, the startup circuit cuts off its own power supply after startup is complete.

[0023] like Figure 2As shown, the startup circuit includes: PMOS transistors: M1, M2, M12, M13, M14 and M68, and NMOS transistors: M11, M24, M30, M31, M33, M34, M35, M69 and M70.

[0024] The gate of transistor M1 is connected to the applied low-level active enable signal ENN, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of transistor M11, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M2 is connected to the drain of transistor M31, the source is connected to the power supply voltage VDD, and the drain is connected to the source of transistor M14. The gate of transistor M11 is connected to the low-level active enable signal ENN, the source is connected to GND, and the drain is connected to the drain of transistor M1, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M12 is connected to GND, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of transistor M24. The gate of transistor M13 is connected to the drain of transistor M13, the gate of transistor M14, and the drain of transistor M68, the source is connected to the power supply voltage VDD, and the drain is connected to the gate of transistor M13, the drain of transistor M30, and the drain of transistor M34. The gate of transistor M14 is connected to the gate of transistor M13 and the drain of transistor M68. Its source is connected to the drain of transistor M2, and its drain is connected to the drain of transistor M35. The voltage output V... BIAS1 The following transistors are connected: the gate of M24 is connected to the gate of M68, the source is connected to the gate of M30 and the drain of M33, and the drain is connected to the drain of M12; the gate of M30 is connected to the source of M24, the gate of M31, the drain of M33, and the drain of M69, the source is connected to GND, and the drain is connected to the drain of M13 and the drain of M34; the gate of M31 is connected to the source of M24, the gate of M30, the drain of M33, and the drain of M69, the source is connected to GND, and the drain is connected to the gate of M2; the gate of M33 is connected to the gate of M34, the source is connected to GND, and the drain is connected to the source of M24, the gate of M30, and the drain of M69.

[0025] The working principle of this startup circuit is as follows: when the low-level active enable signal ENN is low, transistor M1 is turned on, resulting in a drain voltage V of transistor M1. D,M1The voltage rises to approximately VDD, causing the gate voltage of transistor M24 to rise to VDD, thus turning it on. Since the gate of transistor M12 is connected to GND, transistor M12 turns on, consuming the overdrive voltage of two MOSFETs and transferring it to the source of transistor M24. This causes the gate voltages of transistors M30 and M31 to rise and turn on, pulling their drain voltages down to GND. Because the gate and drain of transistor M13 are connected, the low level at the drain of transistor M30 turns on M13, resulting in a low gate voltage for transistor M14, which then turns on. The low drain voltage of transistor M31 turns on transistor M2, and VDD consumes the overdrive voltage of two MOSFETs. OD (V) OD =V GS -V TH The current is then transmitted to the gates of transistors M33, M34, and M35, turning them on. The low-level drain of transistor M31 is transmitted to the gate of the PMOS current source in the subsequent bandgap reference core circuit, injecting current into the core circuit, escaping the zero-current initial state, and entering normal operation. After the core circuit starts normally, a high-level signal is input to the ENN input, causing the gate voltage of transistor M24 to decrease, turning it off, and transistor M68 to turn on. This causes the gate voltages of transistors M13 and M14 to rise to approximately VDD, turning them off. The increased gate voltage of transistors M69 and M70 turns them on, pulling the gate voltages of transistors M30, M31, M33, M34, and M35 down to GND, turning them off. At this point, the entire startup circuit is shut down and no longer consumes operating current.

[0026] The core circuitry of the bandgap reference is used to make the voltages across VM and VP equal, and then by passing V... BE and ΔV BE When applied to the resistors respectively, I is obtained. CTAT and I PTAT The current is then copied through a current mirror to subsequent higher-order compensation circuits for compensation.

[0027] In this embodiment, the core circuit of the bandgap reference adopts current-mode technology, mainly utilizing the "virtual short" characteristic of the operational amplifier input to make the voltages across VM and VP equal, and then by... BE and ΔV BE When applied to the resistors respectively, we obtain... ICTAT and I PTAT The current is then copied through a current mirror to subsequent higher-order compensation circuits for compensation.

[0028] The operational amplifiers OP1 and OP2 in this invention employ the same simple cascode structure, which features high output impedance and high voltage gain, while exhibiting low thermal and flicker noise. Regarding frequency characteristics, the dominant pole of this circuit is located at the output node, and the secondary pole frequency is relatively high, resulting in a large phase margin. Figure 3 and Figure 4 These are the internal circuits of operational amplifiers OP1 and OP2 in the bandgap reference core, respectively. Figure 3 For example, the operating principle of operational amplifier OP1 is as follows: VP1 and VM1 are the input signals to transistors M44 and M45, respectively. Transistor M38, connected by a diode, is in operation. VOUT1 serves as the output of the op-amp, feeding back two current branches through transistors M40 and M41 (connected by a diode) to provide bias voltages for transistors M42 and M43. Transistor M46 is the tail current source, and its gate voltage is determined by the external V... BIAS1 A bias is provided. This design ensures high stability and high gain for the op-amp.

[0029] like Figure 5 As shown, the core circuit of the bandgap reference includes: operational amplifiers OP1 and OP2, PMOS transistors: M6, M7, M18, M19, M32, M37, M71, M72, M73, M74, M75 and M76, NMOS transistors: M77 and M78, PNP transistors: Q1, Q2, Q3, Q4 and Q6, and resistors R1, R2, R3, R5 and R6; The gate of transistor M6 is connected to the gates of transistors M71 and M7, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M18. The gate of transistor M7 is connected to the gates of transistors M6 and M71, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M19. The gate of transistor M18 is connected to its drain, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, the upper end of resistor R2, the gate of transistor M19, and the drain of transistor M75. Its source is connected to the drain of transistor M6, and its drain is connected to the gate of transistor M18, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, and the drain of transistor R2. The upper end of transistor 2 is connected to the gate of transistor M19 and the drain of transistor M75; the gate of transistor M19 is connected to the gate and drain of transistor M18, and its source is connected to the drain of transistor M7. The drain is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, and the upper end of resistor R3; the gate of transistor M32 is connected to the output terminal of operational amplifier OP2, its source is connected to VDD, and its drain is connected to the source of transistor M37; the gate of transistor M37 is connected to the drain of transistor M37, the VP2 terminal of operational amplifier OP2, and the upper end of resistor R5, its source is connected to the drain of transistor M32, and its drain is connected to the gate of transistor M37; the gate of transistor M71 is connected to the gates of transistors M6 and M7, and the output terminal of operational amplifier OP1. The gate of transistor M72 is connected to VDD, and its drain is connected to the source of transistor M72. The gate of transistor M72 is connected to the gate of transistor M14 in the startup circuit, its source is connected to the drain of transistor M71, and its drain is connected to the drain of transistor M73 and the emitter of transistor Q6. The gate of transistor M73 is connected to the gate of transistor M74, its source is connected to VDD, and its drain is connected to the drain of transistor M72 and the emitter of transistor Q6. The gate of transistor M74 is connected to the gate of transistor M73 and the drain of transistor M74, its source is connected to VDD, and its drain is connected to the gate of transistor M74 and the drain of transistor M78. The gate of transistor M75 is connected to the gate of transistor M74, its source is connected to VDD, and its drain is connected to the drain of transistor M18, the VM1 terminal of operational amplifier OP1, and the emitter of transistor Q1. The following connections are made: M76's gate is connected to M75's gate, its source to VDD, and its drain to the lower end of resistor R3 and the emitter of Q3; M77's gate is connected to M78's gate and drain, its source to GND, and its drain to the base of Q6; M78's gate is connected to M77's gate, its source to GND, and its drain to M74's drain; Q1's emitter is connected to the upper end of resistor R1 and R2, the drain of M18, and the VM1 terminal of operational amplifier OP1; its base is connected to Q2's emitter, and its collector to GND; Q2's emitter is connected to Q1's base, its base to GND, and its collector to GND.The emitter of transistor Q3 is connected to the lower end of resistor R3 and the drain of transistor M76; its base is connected to the emitter of transistor Q4; and its collector is connected to GND. The emitter of transistor Q4 is connected to the base of transistor Q3, and its base and collector are both connected to GND. The emitter of transistor Q6 is connected to the drains of transistors M72 and M73; its base is connected to the drain of transistor M77; and its collector is connected to GND. Resistor R1 is connected to the emitter of transistor Q1 and GND. Resistor R2 is connected to the emitter of transistor Q1 and GND. Resistor R3 is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, the drain of transistor M19, the emitter of transistor Q3, and the drain of transistor M76. Resistor R5 is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, the drain of transistor M19, the emitter of transistor Q3, and the drain of transistor M76. The VP2 terminal of P2, the drain of M37 transistor, the voltage divider output terminal VB, and the upper end of resistor R6 are connected; the two ends of resistor R6 are connected to the lower end of resistor R5, the voltage divider output terminal VB, and GND, respectively; the VM1 terminal of operational amplifier OP1 is connected to the drain of M18 transistor, the emitter of Q1 transistor, the drain of M75 transistor, the upper end of resistor R1, and the upper end of resistor R2; the VP1 terminal is connected to the drain of M19 transistor, the upper end of resistor R3, and the VM2 terminal of operational amplifier OP2; the output terminal VOUT1 is connected to the gate of M7 transistor; the VM2 terminal of operational amplifier OP2 is connected to the VP1 terminal of operational amplifier OP1, the drain of M19 transistor, and the upper end of resistor R3; the VP2 terminal is connected to the drain of M37 transistor and the upper end of resistor R5; the output terminal VOUT2 is connected to the gate of M32 transistor.

[0030] like Figure 3As shown, operational amplifier OP1 includes: PMOS transistors: M38, M9, and M40; and NMOS transistors: M41, M42, M43, M44, M45, and M46. The gate of transistor M38 is connected to the drain of transistor M38 and the gate of transistor M39; its source is connected to VDD; and its drain is connected to the gate of transistor M38 and the drain of transistor M42. The gate of transistor M39 is connected to the gate of transistor M38; its source is connected to VDD; and its drain is connected to the gate of transistor M40, the drain of transistor M43, and the output terminal VOUT1. The gate of transistor M40 is connected to the drain of transistor M39; its source is connected to VDD; and its drain is connected to the gates and drains of transistors M41, M42, and M43. The gate of transistor M41 is connected to the drain of transistor M41 and the gate of transistor M42; and its source is connected to the drain of transistor M46. The drain of transistor M42 is connected to the gate of transistor M41 and the drain of transistor M40; the gate of transistor M42 is connected to the gate of transistor M41, the source is connected to the drain of transistor M44, and the drain of transistor M38; the gate of transistor M43 is connected to the gate of transistor M42, the source is connected to the drain of transistor M45, and the drain of transistor M39, the gate of transistor M40, and the output terminal VOUT1; the gate of transistor M44 is connected to terminal VP1, the source is connected to the drain of transistor M46, and the drain of transistor M42; the gate of transistor M45 is connected to terminal VM1, the source is connected to the drain of transistor M46, and the drain of transistor M43; the gate of transistor M46 is connected to the voltage output V. BIAS1 The source is connected to GND, and the drain is connected to the source of transistors M41, M44, and M45.

[0031] The operating principle of the internal circuit of operational amplifier OP2 is the same as that of OP1, such as... Figure 4As shown, the transistors include: POMS transistors: M47, M48, and M49; and NMOS transistors: M50, M51, M52, M53, M54, and M55. The gate of transistor M47 is connected to the drain of transistor M47 and the gate of transistor M48; its source is connected to VDD; and its drain is connected to the gate of transistor M47 and the drain of transistor M51. The gate of transistor M48 is connected to the gate of transistor M47; its source is connected to VDD; and its drain is connected to the gate of transistor M49, the drain of transistor M52, and the output terminal VOUT2. The gate of transistor M49 is connected to the drain of transistor M48 and the drain of transistor M52, and the output terminal VOUT2; its source is connected to VDD; and its drain is connected to the drain of transistor M50. The gate of transistor M50 is connected to the drain of transistor M50 and the gate of transistor M51; and its source is connected to the drain of transistor M55. The drain of transistor M51 is connected to the gate of transistor M50 and the drain of transistor M49; the gate of transistor M51 is connected to the gate of transistor M50, the source is connected to the drain of transistor M53, and the drain of transistor M47; the gate of transistor M52 is connected to the gate of transistor M51, the source is connected to the drain of transistor M54, and the drain of transistor M48, the gate of transistor M49, and the output terminal VOUT2; the gate of transistor M53 is connected to terminal VP2, the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M51; the gate of transistor M54 is connected to terminal VM2; the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M52; the gate of transistor M55 is connected to the voltage output V. BIAS1 The source is connected to GND, and the drain is connected to the source of the M50, M53, and M54 transistors.

[0032] The working principle of this reference core circuit is as follows: Due to the "virtual short" characteristic of the input terminal of operational amplifier OP1, the voltages of VP1 and VM1 are equal, where: Among them, V BE,Q1 This represents the base-emitter voltage drop of BJT transistor Q1, V BE,Q2 V represents the base-emitter voltage drop of BJT transistor Q2. BE,Q3 This represents the base-emitter voltage drop of BJT transistor Q3, V. BE,Q4 I represents the base-emitter voltage drop of BJT transistor Q4. R3 Let represent the current flowing through resistor R3, and R3 represent the resistance value of resistor R3; since VP1 = VM1, then: The emitter junction area A of transistors Q3, Q4, Q2, and Q1 is designed proportionally as follows: A Q3 =A Q4 A Q1 =A Q2 A Q3 :AQ1 =M:1, and the ratio of the current density I1 in the branch containing transistors Q1 and Q2 to the current density I2 in the branch containing transistors Q3 and Q4 is designed to be 1:N, then: Among them, V T Represents thermal voltage, typically taken as 26mV, I S This represents the saturation current of the BJT transistor when it is operating in the forward active region; according to existing technology, ΔV BE It is positively correlated with temperature, i.e., ΔV BE T 1 Therefore, the current flowing through resistor R3 is the current I with a positive temperature coefficient. PTAT Since transistors M18 and M19 act as current mirrors, the current flowing through both transistors M18 and M19 is I. PTAT .

[0033] For a current I with a negative temperature coefficient CTAT VP1 is connected to the VM2 terminal of operational amplifier OP2. Due to the "virtual short" characteristic of OP2, VP2 = VM2, thus changing the voltage across transistors Q1 and Q2. BE The voltage is copied to the VP2 terminal. The VP2 terminal will then receive the copied voltage. BE When a voltage is applied across resistors R5 and R6, the following occurs: Among them, I R5 I represents the current flowing through resistor R5. R6 This represents the current flowing through resistor R6, where R5 represents the resistance of resistor R5, and R6 represents the resistance of resistor R6; according to existing technology, V BE It is negatively correlated with temperature, therefore the current flowing through resistors R5 and R6 is a current I with a negative temperature coefficient. CTAT The output VOUT2 of operational amplifier OP2 is applied to the gate of transistor M32, causing M32 to conduct. Simultaneously, transistor M37, connected via a diode, also conducts. The current flowing through the entire branch consisting of transistors M32 and M37, resistor R5, and resistor R6 is I. CTAT .

[0034] The current extraction circuit is used to stabilize the base current of the PNP transistor.

[0035] like Figure 5 As shown, the current extraction circuit includes: a main current extraction circuit, a logic control unit, and PMOS transistors: M3, M4, M5, M15, M16, M17, and M36. The main current extraction circuit is as follows: Figure 6As shown, the NMOS transistors include: M56, M57, M58, M59, M60, M61, M62, M63, M64, M65, M66 and M67.

[0036] The gate of transistor M3 is connected to the gate of transistor M4, its source is connected to VDD, and its drain is connected to the source of transistor M15. The gate of transistor M4 is connected to the gates of both transistors M3 and M5, its source is connected to VDD, and its drain is connected to the source of transistor M16. The gate of transistor M5 is connected to the gate of transistor M4, its source is connected to VDD, and its drain is connected to the source of transistor M17. The gate of transistor M15 is connected to the gate of transistor M16, its source is connected to the drain of transistor M3, and its drain is connected to the drain of transistor M36. The gate of transistor M16 is connected to the gates of both transistors M15 and M17, its source is connected to the drain of transistor M4, and its drain is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M17 is connected to the gate of transistor M16, and its source is connected to the drain of transistor M5. The drain is connected to the output I of the current extraction circuit. BIAS2 Connected; the gate of the M36 transistor is connected to the drain of the M36 transistor, and the input V of the current extraction circuit is connected. BIAS2 The drain of transistor M15 is connected to the drain of transistor M15, and the source is connected to GND; the gate of transistor M56 is connected to CTRL1, the source is connected to the drain of transistor M64, and the drain is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M57 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M64 is connected to the drain of transistor M58; the gate of transistor M58 is connected to CTRL1, and the source is connected to the drain of transistor M65. The drain of M58 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M59 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M60 is connected to the drain of transistor M65; the gate of transistor M60 is connected to CTRL1, and its source is connected to the drain of transistor M66. The drain of M60 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M61 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M62 is connected to the drain of transistor M66; the gate of transistor M62 is connected to CTRL1, and its source is connected to the drain of transistor M67. The drain of M62 is connected to the output I of the current extraction circuit. BIAS1 Connected; the gate of transistor M63 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 The drain of transistor M64 is connected to the drain of transistor M67; the gate of transistor M64 is connected to the input V of the current extraction circuit. BIAS2 The source of transistor M55 is connected to GND, and the drain is connected to the source of transistor M56 and the drain of transistor M57. The gate of transistor M65 is connected to the input V of the current extraction circuit.BIAS2 The source of transistor M66 is connected to GND, and the drain is connected to the source of transistor M58 and the drain of transistor M59. The gate of transistor M66 is connected to the input V of the current extraction circuit. BIAS2 The source of transistor M67 is connected to GND; the drain of M67 is connected to the source of transistor M60 and the drain of transistor M61; the gate of transistor M67 is connected to the input V of the current extraction circuit. BIAS2 The source is connected to GND, and the drain is connected to the source of the M62 transistor and the drain of the M63 transistor. The three input ports of the logic control unit are the external control signals CTRL0, VDD and GND, and the two output ports are CTRL1 and CTRL2.

[0037] In this embodiment, the working principle of the current extraction circuit is as follows: external logic control signals CTRL1 and CTRL2 respectively regulate the on or off state of transistors M56 to M63, and the V supplied by transistor M36... BIAS2 The bias voltage controls the tail current of transistors M64 to M67, and the NMOS transistors are turned on or off. Figure 4 In this circuit, the output of the current extraction circuit is connected to the bases of Q1 and Q3, and the emitters of Q2 and Q4. When the current of these PNP transistors fluctuates, the current extraction circuit will conduct part of the branch according to the control logic to ensure that the PNP transistors operate in the amplification region. Furthermore, the offset voltage Voffset at the input terminals of operational amplifiers OP1 and OP2 is transmitted to the emitters of Q1 and Q3, causing a deviation in the reference voltage. This abnormal voltage change triggers the current extraction circuit to activate, converting the voltage error into current through the gate-source voltage drop of the MOSFETs and transmitting it to GND, thereby offsetting the error.

[0038] The exponential curvature compensation circuit utilizes the exponential relationship between the current flowing through a MOS device and temperature T when it operates in the subthreshold region to cancel the exponential current V in the subthreshold region. BE The higher-order term.

[0039] like Figure 7 As shown, the compensation circuit includes: PMOS transistors: M8, M9, M10, M20, M21, M22, M23, M25, M26, M27, M28, and M29; PNP transistor: Q5; and resistors R4, R7, R8, R9, and R10. The gate of transistor M8 is connected to the gates of transistors M9 and M10, its source is connected to VDD, and its drain is connected to the source of transistor M20. The gate of transistor M9 is connected to the gates of transistors M8 and M10, its source is connected to VDD, and its drain is connected to the source of transistor M21. The gate of transistor M10 is connected to the gates of transistors M8 and M9, its source is connected to VDD, and its drain is connected to the sources of transistors M22 and M23. The gate of transistor M20 is connected to the gate of transistor M21, its source is connected to the drain of transistor M8, and its drain is connected to the upper end of resistor R4 and the voltage signal V. A Connected; the gate of transistor M21 is connected to the gate of transistor M20, and its source is connected to the drain of transistor M9. The drain is connected to the upper end of resistor R7 and the voltage signal V. REF The drain of transistor M26 is connected to the gate of transistor M22, which is connected to the voltage signal V. REF01 The source of transistor M23 is connected to the drain of transistor M10, and the drain is connected to the upper end of resistor R10; the gate of transistor M23 is connected to the voltage signal V. B The source of transistor M25 is connected to the drain of transistor M10, and the drain is connected to GND. The gate of transistor M25 is connected to the gate of transistor M32 in the bandgap reference core circuit, the source is connected to VDD, and the drain is connected to the source of transistor M26. The gate of transistor M26 is connected to the gate and drain of transistor M37 in the bandgap reference core circuit, the source is connected to the drain of transistor M25, and the drain is connected to the upper end of resistor R7 and the voltage signal V. REF The drain of transistor M21 is connected to the drain of transistor M25; the gate of transistor M27 is connected to the gate of transistor M25, the source is connected to VDD, and the drain is connected to the source of transistor M28 and the source of transistor M29; the gate of transistor M28 is connected to the voltage signal VDD. REF02 The source of transistor M23 is connected to the drain of transistor M27, and the drain is connected to the upper end of resistor R10; the gate of transistor M23 is connected to the voltage signal V. A Connect the source to the drain of transistor M27, and connect the drain to GND; connect the upper end of resistor R4 to the drain of transistor M20, and connect the voltage output V. A The lower end is connected to GND; the upper end of resistor R7 is connected to the drain of transistor M21, the drain of transistor M26, and the voltage output V. REF The lower end is connected to the voltage output V. REF01 The upper end of resistor R8 is connected to the voltage output V. REF01 The lower end is connected to the voltage output V. REF02 The upper end of resistor R9 is connected to the voltage output V. REF02 The lower end is connected to the drain of transistor M22, the drain of transistor M28, and the upper end of resistor R10; the upper end of resistor R10 is connected to the drain of transistor M22, the drain of transistor M28, and the lower end of resistor R9, and the lower end of resistor R9 is connected to the emitter of transistor Q5; the emitter of transistor Q5 is connected to the lower end of resistor R10, the base is connected to GND, and the collector is connected to GND.

[0040] In this embodiment, based on 180nm CMOS technology, an exponential current curvature compensation method for higher-order VBE terms is used, taking advantage of the fact that when the MOS device operates in the subthreshold region, the current flowing through it has an exponential relationship with the temperature T: Where ID represents the leakage current flowing through the MOSFET. A value greater than 1 indicates a non-ideal factor. The Taylor expansion of the exponential current in the subthreshold region at Tr yields T2, T3, and higher-order terms. These higher-order terms are then weighted and superimposed with the higher-order terms of VBE to cancel out the higher-order terms of VBE.

[0041] The working principle of this compensation circuit is as follows: the M18 transistor in the reference core circuit acts as a current mirror, and the M21 transistor replicates the positive temperature coefficient current IPTAT in the core circuit to the branch composed of the M9 and M21 transistors at a certain ratio. Where, gate length L represents the lateral dimension of the gate along the source-drain channel in the MOSFET, and the gate width W is the dimension perpendicular to it. α2 represents the ratio of the width-to-length ratio of the M21 transistor to that of the M18 transistor; such that: Where ID,M9 represents the drain current flowing through transistor M9, and ID,M21 represents the drain current flowing through transistor M21; transistors M37 and M26 act as current mirrors, with transistor M26 replicating the CTAT current from the branches of transistors M32, M37, resistor R5, and resistor R6 to the branches of transistors M25 and M26. Where α1 represents the ratio of the width-to-length ratio of the M26 tube to that of the M37 tube; such that: Where ID,M25 represents the drain current flowing through transistor M25, and ID,M26 represents the drain current flowing through transistor M26; then the current flowing through resistors R7, R8, and R9 is α1ICTAT + α2IPTAT. To prevent α2IPTAT from injecting some current into the source of transistor M26, the width-to-length ratio (W / L) of transistor M26 needs to be designed to be very large. In the circuit: Where R8 represents the resistance value of resistor R8, R9 represents the resistance value of resistor R9, R10 represents the resistance value of resistor R10, ICO represents the sum of compensation currents, and VBE,Q5 represents the base-emitter voltage drop of BJT transistor Q5; where: Where R4 represents the resistance value of resistor R4, R6 represents the resistance value of resistor R6, and α3 represents the proportion of IPTAT in the M20 transistor replicating the M18 transistor branch in the current mirror circuit, that is: For the ICO1 generation circuit, transistors M10, M22, and M23 form a simple differential pair. M10 acts as the current source for this pair, providing operating current to M22 and M23. The small size of M10 allows M22 and M23 to operate in the subthreshold region. The gate voltage VREF01 of M22 is compared with the gate voltage VB of M23. When VREF01 is greater than VB, almost all the current flows through M10, and the compensation current ICO1 is very small. When VREF01 is less than VB, the compensation current ICO1 is at its maximum. Based on the exponential relationship between current and temperature T, we can conclude that: Where ID,M10 represents the drain current flowing through transistor M10; for the ICO2 generation circuit, transistors M27, M28, and M29 form a simple differential pair. Transistor M27 acts as the current source for the differential pair, providing operating current to transistors M28 and M29. The small size of transistor M27 allows transistors M28 and M29 to operate in the subthreshold region. The gate voltage VREF02 of transistor M28 is compared with the gate voltage VA of transistor M29. When VREF02 is greater than VA, almost all of ID,M27 flows through transistor M29, and the compensation current ICO2 is very small; when VREF02 is less than VA, the compensation current ICO2 is at its maximum. Based on the exponential relationship between the current and temperature T, it can be concluded that: Where ID,M27 represents the drain current flowing through transistor M27; the sum of the compensation currents provided by the two differential pairs, ICO, ultimately flows through resistor R10 to generate compensation voltage VCOMP.

[0042] After compensation by the compensation circuit, the reference voltage VREF output by the overall circuit can be expressed as: Where R7 represents the resistance value of resistor R7, and VFIRST represents the uncompensated first-order bandgap reference voltage value; the temperature drift coefficient of the bandgap reference circuit can be given by the following formula: Where Vmean represents the final stable value of the bandgap reference output voltage VREF, Vmax represents the maximum value of the bandgap reference circuit output voltage VREF within the simulated temperature range of -40℃ to 125℃, Vmin represents the minimum value of VREF within this temperature range, Tmax represents the lower limit of the simulated temperature range, and Tmin represents the upper limit of the simulated temperature range. Based on the temperature coefficient simulation results and the calculation using the above formula, the temperature drift coefficient of the bandgap reference circuit in this embodiment is TC = 10.4272ppm / ℃.

[0043] When this embodiment is applied to an analog-to-digital converter chip, an output buffer circuit needs to be connected after the VREF output to enhance the driving capability and isolate the impact of the output load on the stability of the bandgap reference circuit. For example... Figure 8 As shown, after the bandgap reference circuit generates the VREF voltage signal, it passes through the buffer circuit and is then connected to the ADC circuit to provide a stable voltage reference for the ADC's internal digital-to-analog converter (DAC), comparator circuit (COMP), internal bias circuit, and other modules.

[0044] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A bandgap reference circuit for exponential current compensation of higher-order curvature, characterized in that, include: The startup circuit, bandgap reference core circuit, current extraction circuit, and exponential curvature compensation circuit are connected in sequence. The startup circuit is used to input an initial current to bring the circuit away from its degeneracy point; The core circuitry of the bandgap reference is used to make the voltages across VM and VP equal, and then by passing V... BE and ΔV BE When applied to the resistors respectively, I is obtained. CTAT and I PTAT The current is then copied through a current mirror to a subsequent higher-order compensation circuit for compensation. The current extraction circuit is used to stabilize the base current of the PNP transistor. The exponential curvature compensation circuit utilizes the exponential relationship between the current flowing through a MOS device and temperature T when it operates in the subthreshold region to cancel the exponential current V in the subthreshold region. BE The higher-order terms.

2. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 1, characterized in that, The startup circuit includes: transistors M1, M2, M12, M13, M14, M68, M11, M24, M30, M31, M33, M34, M35, M69, and M70. The gate of transistor M1 is connected to the applied low-level active enable signal ENN, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of transistor M11, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M2 is connected to the drain of transistor M31, the source is connected to the power supply voltage VDD, and the drain is connected to the source of transistor M14. The gate of transistor M11 is connected to the low-level active enable signal ENN, the source is connected to GND, and the drain is connected to the drain of transistor M1, the gate of transistor M24, and the gate of transistor M68. The gate of transistor M12 is connected to GND, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of transistor M24. The gate of transistor M13 is connected to the drain of transistor M13, the gate of transistor M14, and the drain of transistor M68. The source is connected to the power supply voltage VDD, and the drain is connected to the gate of transistor M13, the drain of transistor M30, and the drain of transistor M34. The gate of transistor M14 is connected to the gate of transistor M13 and the drain of transistor M68. Its source is connected to the drain of transistor M2, and its drain is connected to the drain of transistor M35. The voltage output V... BIAS1 Connected; The gate of transistor M24 is connected to the gate of transistor M68, the source is connected to the gate of transistor M30 and the drain of transistor M33, and the drain is connected to the drain of transistor M12. The gate of transistor M30 is connected to the source of transistor M24, the gate of transistor M31, the drain of transistor M33, and the drain of transistor M69. The source is connected to GND, and the drain is connected to the drain of transistor M13 and the drain of transistor M34. The gate of transistor M31 is connected to the source of transistor M24, the gate of transistor M30, the drain of transistor M33, and the drain of transistor M69. The source is connected to GND, and the drain is connected to the gate of transistor M2. The gate of transistor M33 is connected to the gate of transistor M34, the source is connected to GND, and the drain is connected to the source of transistor M24, the gate of transistor M30, and the drain of transistor M69.

3. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 1, characterized in that, The core circuit of the bandgap reference includes: operational amplifier OP1, operational amplifier OP2, transistors M6, M7, M18, M19, M32, M37, M71, M72, M73, M74, M75, M76, M77, M78, Q1, Q2, Q3, Q4, Q6, resistors R1, R2, R3, R5, and R6; The gate of transistor M6 is connected to the gate of transistor M71, the gate of transistor M7, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M18. The gate of transistor M7 is connected to the gate of transistor M6, the gate of transistor M71, and the output of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M19. The gate of transistor M18 is connected to the drain of transistor M18, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, the upper end of resistor R2, the gate of transistor M19, and the drain of transistor M75. The source is connected to the drain of transistor M6, and the drain is connected to the gate of transistor M18, the VM1 terminal of operational amplifier OP1, the emitter of transistor Q1, the upper end of resistor R1, the upper end of resistor R2, the gate of transistor M19, and the drain of transistor M75. The gate of transistor M19 is connected to the gate and drain of transistor M18, the source is connected to the drain of transistor M7, and the drain is connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, and the upper end of resistor R3. The gate of transistor M32 is connected to the output of operational amplifier OP2, its source is connected to VDD, and its drain is connected to the source of transistor M37. The gate of transistor M37 is connected to the drain of transistor M37, the VP2 terminal of operational amplifier OP2, and the upper end of resistor R5. The source is connected to the drain of transistor M32, and the drain is connected to the gate of transistor M37. The gate of transistor M71 is connected to the gates of transistors M6 and M7, and the output terminal of operational amplifier OP1. Its source is connected to VDD, and its drain is connected to the source of transistor M72. The gate of transistor M72 is connected to the gate of transistor M14 in the startup circuit, the source is connected to the drain of transistor M71, and the drain is connected to the drain of transistor M73 and the emitter of transistor Q6. The gate of transistor M73 is connected to the gate of transistor M74, the source is connected to VDD, and the drain is connected to the drain of transistor M72 and the emitter of transistor Q6. The gate of transistor M74 is connected to the gate of transistor M73 and the drain of transistor M74. The source is connected to VDD, and the drain is connected to the gate of transistor M74 and the drain of transistor M78. The gate of transistor M75 is connected to the gate of transistor M74, the source is connected to VDD, and the drain is connected to the drain of transistor M18, the VM1 terminal of operational amplifier OP1, and the emitter of transistor Q1. The gate of transistor M76 is connected to the gate of transistor M75, the source is connected to VDD, and the drain is connected to the lower end of resistor R3 and the emitter of transistor Q3. The gate of transistor M77 is connected to the gate of transistor M78 and the drain of transistor M77. The source is connected to GND and the drain is connected to the base of transistor Q6. The gate of transistor M78 is connected to the gate of transistor M77, the source is connected to GND, and the drain is connected to the drain of transistor M74. The emitter of transistor Q1 is connected to the upper end of resistor R1, the upper end of resistor R2, the drain of transistor M18, and the VM1 terminal of operational amplifier OP1. The base is connected to the emitter of transistor Q2, and the collector is connected to GND. The emitter of transistor Q2 is connected to the base of transistor Q1, the base is connected to GND, and the collector is connected to GND. The emitter of transistor Q3 is connected to the lower end of resistor R3 and the drain of transistor M76, the base is connected to the emitter of transistor Q4, and the collector is connected to GND. The emitter of transistor Q4 is connected to the base of transistor Q3, the base is connected to GND, and the collector is connected to GND. The emitter of transistor Q6 is connected to the drain of transistors M72 and M73, the base is connected to the drain of transistor M77, and the collector is connected to GND. The two ends of resistor R1 are connected to the emitter of transistor Q1 and GND, respectively; The two ends of resistor R2 are connected to the emitter of transistor Q1 and GND, respectively; The two ends of resistor R3 are connected to the VP1 terminal of operational amplifier OP1, the VM2 terminal of operational amplifier OP2, the drain of transistor M19, the emitter of transistor Q3, and the drain of transistor M76, respectively. The two ends of resistor R5 are connected to the VP2 terminal of operational amplifier OP2, the drain of transistor M37, the voltage divider output terminal VB, and the upper end of resistor R6, respectively. The two ends of resistor R6 are connected to the lower end of resistor R5, the voltage divider output terminal VB, and GND, respectively. The VM1 terminal of operational amplifier OP1 is connected to the drain of transistor M18, the emitter of transistor Q1, the drain of transistor M75, the upper end of resistor R1, and the upper end of resistor R2. The VP1 terminal is connected to the drain of transistor M19, the upper end of resistor R3, and the VM2 terminal of operational amplifier OP2. The output terminal VOUT1 is connected to the gate of transistor M7. The VM2 terminal of operational amplifier OP2 is connected to the VP1 terminal of operational amplifier OP1, the drain of transistor M19, and the upper end of resistor R3; the VP2 terminal is connected to the drain of transistor M37 and the upper end of resistor R5; and the output terminal VOUT2 is connected to the gate of transistor M32.

4. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 3, characterized in that, Operational amplifier OP1 includes: transistors M38, M9, M40, M41, M42, M43, M44, M45, and M46; The gate of transistor M38 is connected to the drain of transistor M38 and the gate of transistor M39. The source is connected to VDD, and the drain is connected to the gate of transistor M38 and the drain of transistor M42. The gate of transistor M39 is connected to the gate of transistor M38, the source is connected to VDD, and the drain is connected to the gate of transistor M40, the drain of transistor M43, and the output terminal VOUT1. The gate of transistor M40 is connected to the drain of transistor M39, the source is connected to VDD, and the drain is connected to the gate and drain of transistor M41, the gate of transistor M42, and the gate of transistor M43. The gate of transistor M41 is connected to the drain of transistor M41 and the gate of transistor M42. The source is connected to the drain of transistor M46, and the drain is connected to the gate of transistor M41 and the drain of transistor M40. The gate of transistor M42 is connected to the gate of transistor M41, the source is connected to the drain of transistor M44, and the drain is connected to the drain of transistor M38. The gate of transistor M43 is connected to the gate of transistor M42, the source is connected to the drain of transistor M45, and the drain is connected to the drain of transistor M39, the gate of transistor M40, and the output terminal VOUT1. The gate of transistor M44 is connected to VP1, the source is connected to the drain of transistor M46, and the drain is connected to the source of transistor M42. The gate of transistor M45 is connected to terminal VM1, the source is connected to the drain of transistor M46, and the drain is connected to the source of transistor M43. The gate voltage output of the M46 transistor is V. BIAS1 The source is connected to GND, and the drain is connected to the source of transistors M41, M44, and M45.

5. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 3, characterized in that, Operational amplifier OP2 includes: transistors M47, M48, M49, M50, M51, M52, M53, M54, and M55; The gate of transistor M47 is connected to the drain of transistor M47 and the gate of transistor M48. The source is connected to VDD, and the drain is connected to the gate of transistor M47 and the drain of transistor M51. The gate of transistor M48 is connected to the gate of transistor M47, the source is connected to VDD, and the drain is connected to the gate of transistor M49, the drain of transistor M52, and the output terminal VOUT2. The gate of transistor M49 is connected to the drain of transistor M48, the drain of transistor M52, and the output terminal VOUT2. The source is connected to VDD, and the drain is connected to the drain of transistor M50. The gate of transistor M50 is connected to the drain of transistor M50 and the gate of transistor M51. The source is connected to the drain of transistor M55. The drain is connected to the gate of transistor M50 and the drain of transistor M49. The gate of transistor M51 is connected to the gate of transistor M50, the source is connected to the drain of transistor M53, and the drain is connected to the drain of transistor M47. The gate of transistor M52 is connected to the gate of transistor M51, the source is connected to the drain of transistor M54, and the drain is connected to the drain of transistor M48, the gate of transistor M49, and the output terminal VOUT2. The gate of transistor M53 is connected to VP2, the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M51. The gate of transistor M54 is connected to the VM2 terminal; the source is connected to the drain of transistor M55, and the drain is connected to the source of transistor M52. The gate voltage output V of the M55 transistor BIAS1 The source is connected to GND, and the drain is connected to the source of the M50, M53, and M54 transistors.

6. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 1, characterized in that, The current extraction circuit includes: the current extraction main circuit, the logic control unit, transistors M3, M4, M5, M15, M16, M17 and M36; The main circuit for current extraction includes: transistors M56, M57, M58, M59, M60, M61, M62, M63, M64, M65, M66, and M67. The gate of transistor M3 is connected to the gate of transistor M4, the source is connected to VDD, and the drain is connected to the source of transistor M15. The gate of transistor M4 is connected to the gates of transistors M3 and M5, the source is connected to VDD, and the drain is connected to the source of transistor M16. The gate of transistor M5 is connected to the gate of transistor M4, the source is connected to VDD, and the drain is connected to the source of transistor M17. The gate of transistor M15 is connected to the gate of transistor M16, the source is connected to the drain of transistor M3, and the drain is connected to the drain of transistor M36. The gate of transistor M16 is connected to the gates of transistors M15 and M17, its source is connected to the drain of transistor M4, and its drain is connected to the output I of the current extraction circuit. BIAS1 Connected; The gate of transistor M17 is connected to the gate of transistor M16, and its source is connected to the drain of transistor M5. The drain is connected to the output I of the current extraction circuit. BIAS2 Connected; The gate and drain of the M36 transistor, and the input V of the current extraction circuit. BIAS2 The drain is connected to the drain of the M15 transistor, and the source is connected to GND. The gate of transistor M56 is connected to CTRL1, and its source is connected to the drain of transistor M64. The drain is connected to the output I of the current extraction circuit. BIAS1 Connected; The gate of transistor M57 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 Connected, the drain is connected to the drain of the M64 transistor; The gate of transistor M58 is connected to CTRL1, and its source is connected to the drain of transistor M65. The drain is connected to the output I of the current extraction circuit. BIAS1 Connected; The gate of transistor M59 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 Connected, the drain is connected to the drain of the M65 transistor; The gate of transistor M60 is connected to CTRL1, and its source is connected to the drain of transistor M66. The drain is connected to the output I of the current extraction circuit. BIAS1 Connected; The gate of transistor M61 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 Connected, the drain is connected to the drain of the M66 transistor; The gate of transistor M62 is connected to CTRL1, and its source is connected to the drain of transistor M67. The drain is connected to the output I of the current extraction circuit. BIAS1 Connected; The gate of transistor M63 is connected to CTRL2, and its source is connected to the output I of the current extraction circuit. BIAS2 Connected, the drain is connected to the drain of the M67 transistor; The gate of the M64 transistor and the input V of the current extraction circuit BIAS2 The source is connected to GND, and the drain is connected to the source of transistor M56 and the drain of transistor M57. The gate of the M65 transistor and the input V of the current extraction circuit BIAS2 The source is connected to GND, and the drain is connected to the source of the M58 transistor and the drain of the M59 transistor. The gate of the M66 transistor is connected to the input V of the current extraction circuit. BIAS2 The source is connected to GND; the drain is connected to the source of transistor M60 and the drain of transistor M61. The gate of the M67 transistor and the input V of the current extraction circuit BIAS2 The source is connected to GND, and the drain is connected to the source of transistor M62 and the drain of transistor M63. The logic control unit has three input ports for external control signals CTRL0, VDD, and GND, and two output ports for CTRL1 and CTRL2.

7. The bandgap reference circuit for exponential current compensation of higher-order curvature according to claim 1, characterized in that, The compensation circuit includes: transistors M8, M9, M10, M20, M21, M22, M23, M25, M26, M27, M28, M29, Q5, resistors R4, R7, R8, R9, and R10. The gate of transistor M8 is connected to the gates of transistors M9 and M10, the source is connected to VDD, and the drain is connected to the source of transistor M20. The gate of transistor M9 is connected to the gates of transistors M8 and M10, the source is connected to VDD, and the drain is connected to the source of transistor M21. The gate of transistor M10 is connected to the gate of transistors M8 and M9, the source is connected to VDD, and the drain is connected to the source of transistors M22 and M23. The gate of transistor M20 is connected to the gate of transistor M21, and its source is connected to the drain of transistor M8. The drain is connected to the upper end of resistor R4 and the voltage signal V. A Connected; The gate of transistor M21 is connected to the gate of transistor M20, and its source is connected to the drain of transistor M9. The drain is connected to the upper end of resistor R7 and the voltage signal V. REF The drains of the M26 transistor are connected; The gate of the M22 transistor and the voltage signal V REF01 The source is connected to the drain of transistor M10, and the drain is connected to the upper end of resistor R10. The gate of transistor M23 and voltage signal V B The source is connected to the drain of transistor M10, and the drain is connected to GND. The gate of transistor M25 is connected to the gate of transistor M32 in the bandgap reference core circuit, the source is connected to VDD, and the drain is connected to the source of transistor M26. The gate of transistor M26 is connected to the gate and drain of transistor M37 in the bandgap reference core circuit, and its source is connected to the drain of transistor M25. The drain is connected to the upper end of resistor R7 and the voltage signal V. REF The drains of the M21 transistor are connected; The gate of transistor M27 is connected to the gate of transistor M25, the source is connected to VDD, and the drain is connected to the source of transistor M28 and the source of transistor M29. The gate of the M28 transistor and the voltage signal V REF02 The source is connected to the drain of transistor M27, and the drain is connected to the upper end of resistor R10. The gate of transistor M23 and voltage signal V A The source is connected to the drain of the M27 transistor, and the drain is connected to GND. The upper end of resistor R4 is connected to the drain of transistor M20, and the voltage output V. A The lower end is connected to GND; The upper end of resistor R7 is connected to the drain of transistor M21, the drain of transistor M26, and the voltage output V. REF The lower end is connected to the voltage output V. REF01 ; The upper end of resistor R8 is connected to the voltage output V. REF01 The lower end is connected to the voltage output V. REF02 ; The upper end of resistor R9 is connected to the voltage output V. REF02 The lower end is connected to the drain of the M22 transistor, the drain of the M28 transistor, and the upper end of the resistor R10; The upper end of resistor R10 is connected to the drain of transistor M22 and the drain of transistor M28, and the lower end of resistor R9 is connected to the emitter of transistor Q5. The emitter of transistor Q5 is connected to the lower end of resistor R10, the base is connected to GND, and the collector is connected to GND.

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