An all-optical matrix computing unit and chip based on a Chinese character ternary instruction set

Abstract

The application discloses a kind of full light matrix computing unit and chip based on Chinese character ternary instruction set, belong to photonic computing and computer architecture technical field.The full light matrix computing unit includes: Chinese character instruction decoder, for decoding Chinese character ternary instruction into ternary light field control signal;Coherent light source array, for generating N-way coherent light beam;Tri-state light modulator array receives the ternary light field control signal, and each coherent light beam is independently modulated as positive phase state, zero phase state or negative phase state, correspondingly three states of ternary logic;Optical matrix multiplication network is formed by cascaded directional coupler and phase shifter network, and matrix multiplication operation is carried out on the modulated multi-channel light beam;Balanced photodetector array is used to convert the optical signal of operation result into electrical signal and output.The application realizes ternary matrix computing architecture with Chinese character as native instruction and photon as computing carrier, and the calculation delay is only limited to photon transit time, and the energy efficiency of matrix multiplication operation is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of photonic computing and computer architecture technology, specifically relating to a ternary matrix computing architecture that uses Chinese characters as native instructions and photons as the computing carrier, applicable to fields such as artificial intelligence acceleration, scientific computing, and holographic information processing. Background Technology

[0002] Current mainstream computing chips are all based on an electron-binary architecture. Electronic chips face RC latency bottlenecks in large-scale parallel computing tasks such as matrix multiplication, and their energy efficiency deteriorates significantly with increasing integration density. Photonic computing uses photons instead of electrons as information carriers, offering advantages such as light-speed propagation, extremely low power consumption, and inherent parallelism. Existing optical neural network chips mostly employ binary or analog modulation methods, utilizing Mach-Zehnder interferometer networks combined with singular value decomposition to accelerate matrix multiplication.

[0003] However, existing photonic computing schemes have two fundamental limitations: First, all photonic computing architectures use binary instruction sets or analog encoding, limiting their information representation capabilities to two states and failing to leverage the inherent symmetry and higher information density of ternary encoding for photonic computing. Second, existing instruction sets are based on traditional binary machine code and lack a native interface mechanism with multidimensional semantic symbol systems represented by Chinese characters, making it impossible to directly use Chinese semantics as computational primitives to drive the photonic computing process. At the encoding theory level, ternary encoding has an information density of log23, approximately 58.5% higher than binary, and its three-state logic has a natural correspondence with photonic characteristics.

[0004] Therefore, there is an urgent need for a novel computing architecture that deeply integrates the Chinese character ternary instruction set with photonic computing to overcome the bottlenecks in instruction expression capabilities and semantic nativeness of existing photonic computing. The technical concept of this invention is inspired by ancient Chinese numerology and symbolism, and combined with modern integrated photonics technology. Summary of the Invention

[0005] This invention provides an all-optical matrix computing unit based on a Chinese character ternary instruction set, characterized by comprising: a Chinese character instruction decoder for decoding Chinese character ternary instructions into ternary optical field control signals; a coherent light source array for generating N coherent light beams; a three-state optical modulator array for receiving the ternary optical field control signals and independently modulating each coherent light beam into a positive phase state, a zero phase state, or a negative phase state; an optical matrix multiplication network, composed of a cascaded directional coupler and a phase shifter network, for performing matrix multiplication operations on the modulated multi-beams; and a balanced photodetector array for converting the optical signals of the calculation results into electrical signals and outputting them.

[0006] Further, the Chinese character instruction decoder has a built-in Chinese character - ternary mapping table, which stores the correspondence between 45 core Chinese character instructions and ternary control codes. Each core Chinese character instruction corresponds to a 6-bit ternary control code. The three-state optical modulator is a Mach-Zehnder interferometer type optical modulator, and the switching of three modulation states of positive phase state, zero phase state and negative phase state is realized by adjusting the bias voltage. The optical matrix multiplication network uses the singular value decomposition method to realize arbitrary matrix multiplication.

[0007] The present invention also provides an all-optical matrix calculation chip based on a Chinese character ternary instruction set, which integrates all components of the above all-optical matrix calculation unit on a single silicon-based photon chip. Detailed implementation manners

[0008] The technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can refer to the implementation.

[0009] The Chinese character instruction decoder is the instruction parsing core of the system, which is implemented by a field programmable gate array or an application specific integrated circuit, and the Chinese character - ternary mapping logic is固化 inside. The Chinese character ternary instruction set consists of 45 core Chinese characters, including "person", "this", "yuan", "zhong", "tong", "heng", "li", "zhen", "sheng", "cheng", etc. Each Chinese character instruction represents a specific matrix operation micro-operation. The Chinese character - ternary mapping table is stored in the read-only memory inside the decoder. Each record includes three fields: the Chinese character Unicode code point, the operation code semantic description, and the corresponding 6-bit ternary control code. Each bit of the 6-bit ternary control code can take three values of "-1", "0", and "+1".

[0010] Taking two specific mappings as examples: The operation code semantic corresponding to the Chinese character instruction "person" in the mapping table is "activate the first channel and set the rest channels to zero", and the corresponding 6-bit ternary control code is (+1, 0, 0, 0, 0, 0). The operation code semantic corresponding to the Chinese character instruction "this" in the mapping table is "activate the sixth channel to the negative phase and set the rest channels to zero", and the corresponding 6-bit ternary control code is (0, 0, 0, 0, 0, -1).

[0011] When the decoder receives a sequence of Chinese character instructions, the working process is as follows: (1) Instruction reading: Take out a Chinese character instruction in sequence from the instruction queue; (2) Table look-up mapping: Use the Unicode code point of the Chinese character as an index to look up the corresponding 6-bit ternary control code in the mapping table; (3) Control signal generation: Convert the 6-bit ternary control code into 6 groups of ternary optical field control signals, and each group includes three output terminals of a positive phase control signal, a zero phase control signal and a negative phase control signal; (4) Signal output: Output the generated 6 groups of control signals in parallel to the corresponding channels of the three-state optical modulator array.

[0012] The 6-bit ternary code can distinguish 3. 6 =729 different instructions, fully covering all the basic operations required for all-optical matrix computation, including but not limited to matrix multiplication initialization, channel selection, coefficient loading, result reading and cascading control.

[0013] Each of the three-state optical modulators in the three-state optical modulator array employs a Mach-Zehnder interferometer structure and is fabricated on a silicon-on-insulator platform using standard CMOS-compatible processes. The modulator operates as follows: The Mach-Zehnder interferometer splits the input coherent beam into two equal-power beams, which enter the upper and lower modulation arms, respectively. Each modulation arm has a pn-junction phase shifter; by applying a bias voltage to change the refractive index of the waveguide, the phase difference between the two beams is adjusted. After modulation, the two beams combine at the output and interfere.

[0014] The switching logic for the three modulation states is shown in the table below:

[0015] Where V0 is the reference bias voltage, and V_π is the voltage required to shift the phase by π, typically around 3.5V. Switching between the three states is achieved by changing the combination of bias voltages on the upper and lower arms, with a switching time of less than 100 picoseconds and a modulation bandwidth exceeding 10GHz. The input of each three-state optical modulator is connected to the corresponding output of the coherent light source array via an on-chip silicon waveguide, and the output is connected to the corresponding input of the optical matrix multiplication network via an on-chip silicon waveguide.

[0016] The optical matrix multiplication network is the core of the system's computation, employing an optical matrix multiplication architecture based on singular value decomposition (SVD). According to SVD theory, any M×N real matrix A can be decomposed into A = U·Σ·Vᵀ, where U is an M×M unitary matrix, Σ is an M×N diagonal matrix, and Vᵀ is the transpose of an N×N unitary matrix. Accordingly, the optical matrix multiplication network consists of three cascaded optical subnetworks: The first stage is the first unitary matrix optical network, which implements U-matrix multiplication. This network consists of M×(M-1) / 2 Mach-Zehnder interferometers cascaded in a rectangular grid topology. Each interferometer includes two input ports, two output ports, an internal phase shifter, and an external phase shifter. By adjusting the bias voltages of the internal and external phase shifters of each interferometer, the network can be configured to achieve arbitrary M×M unitary matrix transformations.

[0017] The second stage is a diagonal matrix optical network that implements Σ matrix multiplication operations. This network is composed of M adjustable optical attenuators connected in parallel. Each attenuator adopts a Mach-Zehnder interferometer structure, and the optical intensity attenuation ratio of the output port is controlled by adjusting the internal phase of the interferometer. The attenuation coefficient directly corresponds to the diagonal matrix elements in the singular value decomposition.

[0018] The third stage is the second unitary matrix optical network that implements Vᵀ matrix multiplication operations. The topological structure of this network is exactly the same as that of the first unitary matrix optical network, but with different parameter configurations, which is used to implement any N×N unitary matrix transformation.

[0019] Taking 2×2 matrix multiplication as an example, the specific working process is as follows: (1) The system receives a sequence of Chinese character instructions, and the Chinese character instruction decoder sequentially analyzes five Chinese character instructions: "left intersection", "person", "prosperity", "benefit", and "sincerity"; (2) The decoder generates corresponding ternary optical field control signals to control the ternary optical modulator array to modulate two coherent light beams into preset ternary phase combinations respectively; (3) The two modulated light beams enter the first unitary matrix optical network and complete the linear unitary transformation through cascaded Mach-Zehnder interferometers; (4) The transformed light beams enter the diagonal matrix optical network, and the light beams in each channel complete the singular value scaling through adjustable optical attenuators; (5) The scaled light beams enter the second unitary matrix optical network to complete the second linear unitary transformation; (6) The final output light beam is received by the balanced photodetector array, which converts the optical signal into an electrical signal to complete the readout of the matrix multiplication operation.

[0020] The entire process is completed entirely in the optical domain without optical-to-electrical conversion. The calculation delay is only limited by the transit time of photons from the input port to the output port, which is about 67 picoseconds for a centimeter-scale optical path.

[0021] Taking 64×64 matrix multiplication as an example, the specific working process is as follows: (1) The system receives a sequence of Chinese character instructions, and the decoder analyzes it into 64 groups of ternary optical field control signals; (2) The coherent light source array generates 64 equal-power coherent light beams through a 1×64 multimode interference beam splitter; (3) The 64 light beams pass through 64 ternary optical modulators respectively and are modulated into preset ternary combinations; (4) The 64 modulated light beams sequentially pass through the first 64×64 unitary matrix optical network, the 64-channel diagonal matrix optical network, and the second 64×64 unitary matrix optical network; (5) 64 pairs of balanced photodetectors receive the output optical signals in parallel and convert them into electrical signals. In the 64×64 scale, the total number of cascaded interferometers in the optical matrix multiplication network is 64×63 = 4032, and the chip area is about 25 square millimeters.

[0022] The all-optical matrix calculation chip is fabricated on a silicon-on-insulator platform with a 220nm top silicon, and the process node is compatible with the standard CMOS production line. The detailed integration scheme of this chip includes the following components and parameters: (1) Coherent light source coupling module: An on-chip vertical grating coupler is used, with a coupling efficiency of not less than 50% and a coupling wavelength range of 1528nm to 1565nm (C-band). The laser source is an off-chip distributed feedback laser with an output power of 100mW, a center wavelength of 1550nm, and a linewidth of less than 1MHz. The laser is coupled into the on-chip 1×N multimode interference beam splitter via a single-mode fiber and a vertical grating coupler.

[0023] (2) 1×N multimode interference beam splitter (N=64): Designed based on the self-image principle, the multimode interference region has a width of 24 micrometers and a length of 580 micrometers. The input end is a single-mode waveguide, and the output end is 64 equally spaced single-mode waveguides. The insertion loss is less than 0.5dB, and the power non-uniformity of the 64 output channels is less than 0.3dB.

[0024] (3) Three-state optical modulator array (64 units): The difference in length between the two arms of the Mach-Zehnder interferometer for each modulator is zero, the length of the modulation arm is 500 micrometers, and the doping concentration of the pn junction phase shifter is 1×10¹ 8 cm⁻³. Modulation bandwidth 10GHz, half-wave voltage V_π 3.5V, insertion loss less than 2dB.

[0025] (4) Optical matrix multiplication network: including a first unitary matrix network, a diagonal matrix network, and a second unitary matrix network. The internal phase shifter of each Mach-Zehnder interferometer is a thermo-optical phase shifter with a heater length of 100 micrometers, a power consumption of approximately 20 milliwatts, and a response time of approximately 20 microseconds. The external phase shifter adopts the same structure. Adjacent interferometers are connected by an S-shaped bent waveguide with a bending radius of 5 micrometers and a bending loss of less than 0.02 dB / 90°.

[0026] (5) Balanced photodetector array (64 pairs): Heterogeneous integration on silicon waveguide using germanium-silicon epitaxial material. Each pair of detectors includes two photodiodes with a responsivity of approximately 1.1 A / W (at 1550 nm), dark current less than 50 nA, and 3 dB bandwidth exceeding 20 GHz.

[0027] (6) On-chip metal interconnect: The Chinese character instruction decoder is located on one side of the tri-state optical modulator array and is connected to the electrodes of each modulator through on-chip metal interconnect. The metal interconnect adopts a two-layer aluminum wiring process with a line width of 2 micrometers and an electrode pad size of 100 micrometers × 100 micrometers.

[0028] (7) Packaging and Interface: The chip size is 5 mm × 5 mm, and the thickness is 200 micrometers. It is packaged on a ceramic substrate using flip-chip bonding. The electrical signal interface includes 64 high-frequency signal output ports, 45 Chinese character instruction input ports, and power and ground interfaces. The optical signal interface includes 1 input fiber optic interface and 64 output fiber optic interfaces.

[0029] At a communication wavelength of 1550nm, with a laser power of 100 milliwatts, the photon transit time for a single 64×64 matrix multiplication operation is approximately 67 picoseconds, and the theoretical computational throughput is approximately 2 quadrillion operations per second. The total power consumption of the chip is approximately 3.2 watts, of which the laser source consumes 1.5 watts, the thermo-optical phase shifter array consumes approximately 1.5 watts, and the detector array consumes approximately 0.2 watts.

[0030] The Chinese character instructions of this invention support all-optical computing with multiple instruction cascading, enabling pipelined execution of complex matrix operations. The specific workflow is as follows: (1) First stage: The system receives the first set of Chinese character instruction sequences. The Chinese character instruction decoder parses them into the first set of ternary light field control signals, controls the three-state light modulator array to modulate N beams, completes the first matrix operation through the optical matrix multiplication network, and outputs the first stage electrical signal result by the balanced photodetector array.

[0031] (2) Intermediate stage: The electrical signal output from the first stage is converted into a digital signal by an analog-to-digital converter, which serves as the modulation parameter for the ternary optical field control signal corresponding to the second set of Chinese character instructions. Specifically, the digital signal value output from the first stage is used to adjust the bias voltage offset of the second-stage three-state optical modulator, thereby changing the phase angle of the modulation state. For example, if the output value of the first stage is +0.3, the positive phase state of the corresponding channel in the second stage will shift by +0.3π; if the output value of the first stage is -0.2, the negative phase state of the corresponding channel in the second stage will shift by -0.2π. This cascade mechanism allows for matrix chain multiplication operations of arbitrary complexity.

[0032] (3) Last stage: Repeat the above cascading process until all Chinese character instruction sequences have been executed. Since there is only a conversion delay (on the order of nanoseconds) between each stage, the throughput of the entire pipeline is mainly limited by the transit time of the optical matrix multiplication network, rather than the data transmission delay between each stage.

[0033] To verify the technical effectiveness of this invention, a comparative simulation of matrix multiplication operations was conducted on the same simulation platform between the ternary modulation scheme of this invention and the existing binary modulation scheme. The simulation conditions were as follows: matrix size 64×64, operating wavelength 1550nm, and laser power 100mW. The comparison metrics included single-operation delay, theoretical computational throughput, and energy efficiency ratio.

[0034] Simulation results show that, under the same matrix size and manufacturing process conditions, the single-operation latency of the ternary modulation scheme of this invention is approximately 67 picoseconds, while that of the existing binary modulation scheme is approximately 72 picoseconds; the theoretical computational throughput of this invention is approximately 2 quadrillion operations per second, while that of the existing scheme is approximately 1.8 quadrillion operations per second; the energy efficiency ratio of this invention is approximately 6.3 quadrillion operations per second per watt, while that of the existing scheme is approximately 5.7 quadrillion operations per second per watt. The ternary scheme outperforms the binary scheme in all three aspects: latency, throughput, and energy efficiency ratio. Attached Figure Description

[0035] Figure 1 Overall architecture diagram of the all-optical matrix computing unit; Figure 2 : Schematic diagram of the internal structure of the Chinese character instruction decoder; Figure 3 Schematic diagram of the working state of a three-state optical modulator; Figure 4 Schematic diagram of optical matrix multiplication network structure; Figure 5 Layout diagram of all-optical matrix computing chip Beneficial effects

[0036] This invention achieves, for the first time, a deep integration of Chinese character ternary instruction sets and photonic computing, constructing a novel computing paradigm with Chinese characters as the native semantic instructions and photons as the physical computing carrier. The ternary three-state logic naturally corresponds to the three modulation states of a photonic Mach-Zehnder interferometer, with no conversion loss between the physical and logic layers. Matrix multiplication computation latency is limited only by photon transit time, resulting in significantly better energy efficiency than existing electronic matrix computing schemes. Integrated into a single silicon-based photonic chip, it is compatible with CMOS processes and has the potential for large-scale mass production.

Claims

1. A method for calculating an all-optical matrix based on a Chinese character ternary instruction set, characterized in that, Includes the following steps: S1: Chinese character instruction decoding steps - Receive the Chinese character ternary instruction sequence, decode each Chinese character instruction into a set of ternary optical field control signals, the ternary optical field control signals include positive phase control signals, zero phase control signals and negative phase control signals; S2: Light source beam splitting step - N coherent beams are generated from a coherent light source array, where N is a positive integer greater than or equal to 2; S3: Three-state optical modulation step - Input each coherent beam into the corresponding three-state optical modulator, and independently modulate the coherent beam into a positive phase state, a zero phase state, or a negative phase state according to the ternary optical field control signal. The positive phase state and the negative phase state have opposite phases and equal amplitudes, and the zero phase state has zero amplitude. S4: Optical matrix operation steps—The modulated N beams are input into the optical matrix multiplication network, and matrix multiplication is performed on the N beams through a cascaded directional coupler network and a phase shifter network; S5: Photoelectric conversion output step - The optical signal resulting from the matrix multiplication operation is converted into an electrical signal and output by a balanced photodetector array.

2. The all-optical matrix calculation method according to claim 1, characterized in that, The Chinese character instruction decoding step in step S1 is performed according to a preset Chinese character-ternary mapping table. The Chinese character-ternary mapping table is stored in a read-only memory. Each record includes the Chinese character Unicode code point, the operation code semantic description, and the corresponding 6-bit ternary control code. Each bit of the 6-bit ternary control code can take three values: "-1", "0", and "+1". At least 729 different instructions can be distinguished through the 6-bit ternary encoding.

3. The all-optical matrix calculation method according to claim 2, characterized in that, The Chinese character instruction decoding step in step S1 includes the following sub-steps: (1) Instruction reading: take out a Chinese character instruction in sequence from the instruction queue; (2) Table lookup mapping: use the Unicode code point of the Chinese character as the index to find the corresponding 6-bit ternary control code in the Chinese character-ternary mapping table; (3) Control signal generation: convert the 6-bit ternary control code into 6 sets of ternary optical field control signals, each set including a positive phase control signal output terminal, a zero phase control signal output terminal and a negative phase control signal output terminal; (4) Signal output: output the generated 6 sets of control signals in parallel to the corresponding channels of the three-state optical modulator array.

4. The all-optical matrix calculation method according to claim 1, characterized in that, The three-state optical modulator mentioned in step S3 is a Mach-Zehnder interferometer type optical modulator. It splits the input coherent beam into two equal-power beams, which enter the upper and lower modulation arms respectively. By adjusting the bias voltages on the upper and lower modulation arms, the phase difference between the two beams is changed, and the beams are combined and interfered at the output. The switching logic for the three modulation states is as follows: Positive phase: The upper arm bias voltage is the reference voltage V0, the lower arm bias voltage is the reference voltage V0, the phase difference between the two arms is 0, and the output amplitude is normalized to +1; Zero phase state: The upper arm bias voltage is V0 + half-wave voltage V_π, the lower arm bias voltage is V0, the phase difference between the two arms is π, the output ends interfere and cancel each other out, and the output light intensity is zero; Negative phase state: The upper arm bias voltage is V0, the lower arm bias voltage is V0+V_π, the phase difference between the two arms is π, and the output amplitude is normalized to -1; where V_π is the voltage value required to shift the phase by π.

5. The all-optical matrix calculation method according to claim 1, characterized in that, The optical matrix multiplication network described in step S4 uses singular value decomposition to perform matrix multiplication. The optical matrix multiplication network consists of a first unitary matrix optical network, a diagonal matrix optical network, and a second unitary matrix optical network cascaded sequentially. Both the first and second unitary matrix optical networks are constructed by cascading multiple Mach-Zehnder interferometers in a rectangular grid topology. Each interferometer includes two input ports, two output ports, an internal phase shifter, and an external phase shifter. The diagonal matrix optical network is constructed by connecting multiple tunable optical attenuators in parallel.

6. The all-optical matrix calculation method according to claim 1, characterized in that, The method supports the nested combination execution of Chinese character instructions: the electrical signal output by the previous level Chinese character instruction in step S5 is converted from analog to digital and used as the bias voltage offset of the three-state optical modulator corresponding to the next level Chinese character instruction. The multi-instruction cascaded all-optical matrix chain multiplication operation is realized by changing the phase angle of the modulation state.

7. A full-optical matrix calculation unit based on a Chinese character ternary instruction set, used to execute the full-optical matrix calculation method according to any one of claims 1 to 6, characterized in that, include: The Chinese character instruction decoder (101) has a built-in Chinese character-ternary mapping table, which is used to receive Chinese character ternary instruction sequences and decode each Chinese character instruction into a set of ternary light field control signals; A coherent light source array (102) is used to generate N coherent beams, where N is a positive integer greater than or equal to 2; The three-state optical modulator array (103) is connected to the Chinese character instruction decoder (101) and the coherent light source array (102) respectively, and includes N three-state optical modulators. Each three-state optical modulator receives a coherent light beam and a set of corresponding ternary optical field control signals, and modulates the coherent light beam into a positive phase state, a zero phase state or a negative phase state according to the ternary optical field control signals. An optical matrix multiplication network (104), connected to the three-state optical modulator array (103), is composed of a cascaded directional coupler network and a phase shifter network, and is used to perform matrix multiplication operations on the modulated N beams; A balanced photodetector array (105) is connected to the optical matrix multiplication network (104) to convert the optical signal of the matrix multiplication operation result into an electrical signal and output it.

8. The all-optical matrix computing unit according to claim 7, characterized in that, The Chinese character instruction decoder (101) has a built-in Chinese character-ternary mapping table stored in a read-only memory. Each record includes the Chinese character Unicode code point, the operation code semantic description and the corresponding 6-bit ternary control code. No less than 729 different instructions can be distinguished through the 6-bit ternary encoding.

9. The all-optical matrix computing unit according to claim 7, characterized in that, Each of the three-state optical modulators in the three-state optical modulator array (103) is a Mach-Zehnder interferometer type optical modulator. The switching of three modulation states—positive phase, zero phase, and negative phase—is achieved by adjusting the bias voltage combination on the modulation arm: the positive phase corresponds to a phase difference of 0 between the two arms, the zero phase corresponds to the interference cancellation at the output end, and the negative phase corresponds to a phase difference of π between the two arms.

10. The all-optical matrix computing unit according to claim 7, characterized in that, The optical matrix multiplication network (104) uses the singular value decomposition method to realize matrix multiplication, including a first unitary matrix optical network, a diagonal matrix optical network and a second unitary matrix optical network cascaded in sequence; the first unitary matrix optical network and the second unitary matrix optical network are both composed of multiple Mach-Zehnder interferometers cascaded in a rectangular grid topology; the diagonal matrix optical network is composed of multiple tunable optical attenuators connected in parallel.

11. A fully optical matrix computing chip based on a Chinese character ternary instruction set, characterized in that, All components of the all-optical matrix computing unit as described in any one of claims 7 to 10 are integrated on a single silicon-based photonic chip; the Chinese character instruction decoder (101), coherent light source array (102), three-state optical modulator array (103), optical matrix multiplication network (104), and balanced photodetector array (105) are optically interconnected via on-chip silicon waveguides; the Chinese character instruction decoder (101) is connected to each electrode of the three-state optical modulator array (103) via on-chip metal interconnects.

12. The all-optical matrix computing chip according to claim 11, characterized in that, The chip is fabricated on a 220nm top-layer silicon-on-insulator platform, with a chip size of 5 mm × 5 mm and a thickness of 200 micrometers. It is packaged on a ceramic substrate using flip-chip bonding. The laser source of the coherent light source array (102) is an off-chip distributed feedback laser with an output power of 100 mW, a center wavelength of 1550 nm, and a linewidth of less than 1 MHz. It is coupled into a 1×N multimode interference beamsplitter via an on-chip vertical grating coupler. The multimode interference region of the 1×N multimode interference beamsplitter (N=64) has a width of 24 micrometers and a length of 580 μm. The three-state optical modulator array (103) has a modulation arm length of 500 micrometers, a modulation bandwidth of 10 GHz, a half-wave voltage of 3.5 V, and an insertion loss of less than 2 dB. The balanced photodetector array (105) is heterogeneously integrated on a silicon waveguide using germanium-silicon epitaxial material. Each pair of detectors includes two photodiodes with a response of about 1.1 A / W, a dark current of less than 50 nA, and a 3 dB bandwidth of more than 20 GHz.

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