Light detection device

Abstract

This invention provides a photodetector including SPADs, which significantly reduces substrate fabrication costs compared to InGaAs, resulting in fewer residual pulses and suppressed DCR. The photodetector of this invention detects incident light from an object and includes: (i) a P-type silicon (Si) substrate; (ii) a P-type germanium (Ge) layer formed by epitaxial growth on a first surface of the P-type silicon (Si) substrate; (iii) a P-type thin-film silicon (Si) layer formed on the P-type germanium (Ge) layer; and (iv) the P-type thin-film silicon (Si) layer is divided into a first region and a second region by shallow trench isolation, wherein a plurality of single-photon detection diodes (SPADs) arranged in an array are formed in the first region, and a CMOS transistor circuit driving the SPADs is formed in the second region.

Description

Technical Field

[0001] The present invention relates to a light detection device, which has a plurality of light detection elements and a driving circuit for driving the light detection elements. The plurality of light detection elements detect incident light from an object, particularly single photons of infrared light with a wavelength of about 0.9 μm to 1.6 μm. Background Technology

[0002] Previously, photodetectors capable of detecting single photons were typically implemented in the form of single-photon avalanche diodes (SPADs) using silicon (see Patent Document 1).

[0003] However, due to the inherent bandgap of silicon (Eg ≒ 1.12 eV), only photons with wavelengths (λ) shorter than approximately 1 μm can be detected. To detect infrared photons with wavelengths greater than 1 μm, a semiconductor with a narrower bandgap than silicon is needed as the detection element. Therefore, indium gallium arsenide (InGaAs) or germanium (Ge) is typically used to detect infrared photons with wavelengths greater than 1 μm.

[0004] Regarding InGaAs, it is known that it has many crystal defects, especially traps with deep energy levels, which results in a large amount of after-pulse ("noise") when it is used as an avalanche photodiode (APD).

[0005] Moreover, InGaAs cannot be manufactured in single crystal form; it is usually formed by epitaxial growth on an InP substrate through metal-organic chemical vapor deposition (MOCVD).

[0006] Therefore, it has the disadvantage of making the substrate manufacturing cost expensive.

[0007] Consequently, it becomes difficult to fully improve the quality of crystallization.

[0008] Furthermore, it is impossible to integrate the drive circuitry used to amplify or process signals from the APD into the same chip as the APD.

[0009] Regarding the latter, Ge, an avalanche region must be formed within Ge. Because Ge has a narrow band gap as described above, it readily generates thermally excited carriers. These carriers cause avalanche multiplication, resulting in "photon" counting even in the absence of light. This is called the Dark Count Rate (DCR), and there is a problem with the DCR becoming high.

[0010] Furthermore, when using optical detection devices as long-range subject detection systems (Laser Imaging Detection and Ranging, LiDAR), two-dimensional distance information is required, necessitating the arrangement of multiple SPADs in an array. However, when using InGaAs or Ge detection devices, it is difficult to arrange multiple SPADs in an array within the same chip.

[0011] Non-Patent Document 1 discloses the formation of a single-photon detection diode (SPAD) on a germanium (Ge) layer formed on a silicon substrate.

[0012] Non-Patent Document 2 discloses a multiplication avalanche photodiode (SACM-APD) comprising a Ge absorption layer and a Si multiplication layer and being separated from a p-doped Si charge layer.

[0013] However, the SPAD disclosed in Non-Patent Documents 1 and 2 is a single diode structure, and is not a structure in which multiple diodes are arranged in an array. Moreover, the circuit for driving the SPAD is not formed on the same substrate.

[0014] Non-Patent Document 3 discloses an N-type LiDAR receiver used in a near-infrared (NIR) LiDAR receiver. + The circuit for active reset of the P-type single-ended SPAD is described. However, how to mount the SPAD and the reset circuit on the same substrate is not disclosed in detail.

[0015] Non-Patent Document 4 discloses the epitaxial growth of germanium (Ge) on silicon (001) cut at 0° and 6°, and the results of its characteristic evaluation.

[0016] Non-patent document 5 discloses a two-stage process for epitaxial growth of germanium (Ge) thin films on silicon (100).

[0017] Non-patent documents 4 and 5 only evaluate the characteristics of the Ge layer epitaxially grown on the silicon layer, without disclosing any information about the structure of the photodetector.

[0018] [Existing Technical Documents]

[0019] [Patent Literature]

[0020] Patent Document 1: Japanese Patent Application Publication No. 2021-150359

[0021] [Non-patent literature]

[0022] Non-patent literature 1: "High performance planar germanium-on-silicon single-photon avalanche diode detectors", Peter Vines et al., "Nature Communications", (2019) 10; 1086

[0023] Non-Patent Document 2: "Modeling Ge / Si Avalanche Photodiodes", F. Gity et al., "Under Grand Science Foundation Ireland (SFI) Project 07 / SRC / 11173"

[0024] Non-Patent Document 3: "Active-Reset for the N+P Single-Ended SPAD Used in the NIR LiDAR Receivers", A. Katz et al., "IE3 TRANSACTIONS ON ELECTRONDEIVES", Vol. 66, No. 12, December 2019.

[0025] Non-Patent Literature 4: "Comparative Studies of the Growth and Characterization of Germanium Epitaxial Film on Silicon(001) with 0° and 6° offcut", Kwang Hong Lee et al., "Journal of Electronic Materials", vol.42, No.6, 2013

[0026] Non-Patent Literature 5: Epitaxial Germanium-thin films of Silicon (100) using a two-step process, Saloni Chaurasia et al., “VTC from IEEE Xplore” Summary of the Invention

[0027] [The problem the invention aims to solve]

[0028] The purpose of this invention is to provide a photodetector including SPAD and a method for manufacturing the same, wherein the photodetector significantly reduces substrate manufacturing costs compared to InGaAs, has fewer residual pulses, and suppresses DCR.

[0029] Furthermore, the present invention also aims to provide a photodetector and a method for manufacturing the same, wherein the photodetector can arrange silicon-based complementary metal-oxide-semiconductor (CMOS) transistor circuits on the same substrate, wherein the silicon-based CMOS transistor circuits drive a plurality of SPADs arranged in an array.

[0030] [Technical means to solve the problem]

[0031] The photodetector of the present invention detects incident light from an object and includes: a P-type silicon substrate; a P-type germanium layer formed on a first surface of the P-type silicon substrate by epitaxial growth; and a P-type thin-film silicon layer formed on the P-type germanium layer, the P-type thin-film silicon layer being divided into a first region and a second region by shallow trench isolation, a plurality of single-photon avalanche diodes arranged in an array in the first region serving as single-photon detection diodes, and a complementary metal-oxide-semiconductor transistor circuit for driving the single-photon avalanche diodes formed in the second region.

[0032] The photodetector of the present invention is for a P-type silicon (Si) substrate and a P-type germanium (Ge) layer formed on the silicon (Si) substrate by epitaxial growth, wherein the P-type silicon (Si) is bonded on the germanium (Ge) layer by surface activation bonding, and the P-type silicon (Si) is fabricated based on the following structure: it is thinned to a thickness of 0.8 μm to 1.2 μm by using a smart cut technique with hydrogen ion implantation.

[0033] In thin-film P-type silicon (Si), multiple SPADs arranged in an array are formed by ion implantation to detect infrared light, and a CMOS transistor circuit is formed to drive the SPADs to amplify and process the detected signal.

[0034] In the avalanche diode portion of the P-type silicon (Si), an APD P-well layer doped by implanting ions of group III impurities such as boron, and an APD N-well layer doped by implanting ions of group V impurities such as phosphorus, are formed. In the APD N-well layer, N-type impurities highly doped with group V impurities such as arsenic are formed to sufficiently reduce contact resistance. + Diffusion layer. Furthermore, in the N... + Around the diffusion layer, an NW protective ring layer is formed by ion implantation to prevent edge breakdown.

[0035] In the N-channel transistor section, there is a P-well layer formed by implanting group III ions such as boron. Within the P-well layer, there are N-channel transistors formed by implanting group V ions such as arsenic, which constitute the source and drain of the transistor. + A diffusion layer. Furthermore, a P-type diffusion layer, derived from boron or the like, is also formed for contact with the P-well layer. + Diffusion layer. Similarly, in the P-channel transistor section, an N-well layer and a P-channel layer are formed by ion implantation. + diffusion layer, N + Diffusion layer.

[0036] The method of forming these transistors is based on the existing manufacturing method of Large Scale Integration (LSI), which makes the manufacturing of the photodetector of the present invention easier and reduces the manufacturing cost.

[0037] [The effects of the invention]

[0038] According to the photodetector of the present invention, charge carriers can be generated within the germanium depletion layer via the photoelectric effect caused by infrared radiation, and the generated charge carriers avalanche occurs at the PN junction within high-quality silicon. This reduces the noise DCR of the SPAD and also reduces residual pulses. Furthermore, since the avalanche diodes are separated one by one, multiple avalanche diodes can be configured into an array, enabling the fabrication of a two-dimensional image sensor using a single chip.

[0039] Furthermore, conventional silicon CMOS circuits can be easily integrated into the chip, thus enabling the integration of not only sensor diodes but also circuitry that amplifies and processes the electrical signals output from the sensor into a single chip, thereby reducing the size and cost of the device.

[0040] Furthermore, the manufacturing method of the photodetector of the present invention is largely based on conventional CMOS logic processes, ensuring ease of manufacturing and cost reduction. Attached Figure Description

[0041] Figure 1 The diagrams shown are schematic diagrams of the optical detection device according to an embodiment of the present invention. (a) is a plan view and (b) is a cross-sectional view.

[0042] Figure 2 To indicate Figure 1 A detailed schematic cross-sectional view of the cross-sectional structure shown in (b).

[0043] Figure 3 The diagram illustrates a method for manufacturing a wafer, which serves as the basic material for manufacturing the photodetector capable of detecting infrared single photons according to the present invention.

[0044] Figure 4(a) is a schematic cross-sectional view (one) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0045] Figure 4(b) is a schematic cross-sectional view illustrating the wafer fabrication process of an infrared single-photon detection device (Part II).

[0046] Figure 4(c) is a schematic cross-sectional view (third one) illustrating the wafer fabrication process of an infrared single-photon detection device.

[0047] Figure 4(d) is a schematic cross-sectional view (fourth) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0048] Figure 4(e) is a schematic cross-sectional view (fifth) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0049] Figure 4(f) is a schematic cross-sectional view (sixth) illustrating the wafer fabrication process of an infrared single-photon detection device.

[0050] Figure 4(g) is a schematic cross-sectional view (seventh) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0051] Figure 4(h) is a schematic cross-sectional view (eighth) illustrating the wafer fabrication process of an infrared single-photon detection device.

[0052] Figure 4(i) is a schematic cross-sectional view (nine) illustrating the wafer fabrication process of an infrared single-photon photodetector.

[0053] Figure 4(j) is a schematic cross-sectional view (tenth) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0054] Figure 4(k) is a schematic cross-sectional view (eleventh) illustrating the wafer fabrication process of an infrared single-photon photodetector.

[0055] Figure 4(l) is a schematic cross-sectional view (twelfth) illustrating the wafer fabrication process of an infrared single-photon photodetector.

[0056] Figure 4(m) is a schematic cross-sectional view (thirteenth in the series) illustrating the wafer fabrication process of an infrared single-photon detection device.

[0057] Figure 4(n) is a schematic cross-sectional view (fourteenth) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0058] Figure 4(o) is a schematic cross-sectional view (xv) illustrating the wafer fabrication process of an infrared single-photon detection device.

[0059] Figure 4(p) is a schematic cross-sectional view (sixteenth) illustrating the wafer fabrication process of an infrared single-photon photon detection device.

[0060] Figure 5 A graph showing the carrier concentration distribution of the main part of the APD, obtained from process simulation.

[0061] Figure 6 This is an illustration of surface illumination and back-side illumination of incident light.

[0062] [Explanation of Symbols]

[0063] 1: Silicon chip

[0064] 2: pixels

[0065] 3: Metal wiring

[0066] 4. 201: CMOS transistor circuit

[0067] 4-1: Horizontal control circuit

[0068] 4-2: Column Control Circuit

[0069] 4-3: Signal Processing Circuit

[0070] 10: Optical Detection Device

[0071] 101, 301: P-type silicon substrate

[0072] 102, 302: P-type germanium epitaxial layer

[0073] 103: P-type thin-film silicon layer

[0074] 104: STI layer

[0075] 105, 409: APD P-well layer

[0076] 106, 410: APD N-well layer

[0077] 107, 411: Protective ring N-well layer

[0078] 108, 419: N+ diffusion layer

[0079] 109, 420: P+ diffusion layer

[0080] 110, 111: Trap layer

[0081] 112, 415: Gate electrode

[0082] 114: Electrode plug

[0083] 115: Metal wiring

[0084] 120: Visible light blocking filter

[0085] 202: Photodiode

[0086] 303: P-type silicon substrate, P-type silicon layer

[0087] 401: Silicon

[0088] 402: Germanium

[0089] 403: Silicon film

[0090] 404: Oxide film

[0091] 405: Silicon nitride film

[0092] 406: Photoresist

[0093] 407: STI oxide film

[0094] 408: Sacrificial oxide film

[0095] 412: Logical P-well layer

[0096] 413: Logical N-well layer

[0097] 414: Gate oxide film

[0098] 416: n-part

[0099] 417: p-part

[0100] 418: Sidewall spacer

[0101] 422: Silicon oxide film

[0102] 423: Interlayer insulating film

[0103] 424: Tungsten plug

[0104] 425: Wiring layer Detailed Implementation

[0105] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0106] Figure 1 The diagrams shown are schematic diagrams of the light detection device 10 according to an embodiment of the present invention. (a) shows a plan view and (b) shows a cross-sectional view.

[0107] In the optical detection device 10 of the present invention, the pixels 2 of a plurality of single photon detection diodes (SPADs) are arranged in an array on the same silicon chip 1, and a CMOS transistor circuit 4 is formed around it. The CMOS transistor circuit 4 includes a row control circuit 4-1, a column control circuit 4-2, and a signal processing circuit 4-3 for driving the pixels 2.

[0108] The thin-film silicon (Si) layer on the surface of silicon chip 1 is divided into a first region and a second region by shallow trench isolation (STI), which will be described in detail below. Pixels 2 arranged in an array are formed in the first region, and CMOS transistor circuits 4 are formed in the second region.

[0109] Each pixel 2 is connected to the other pixels and to the row control circuit 4-1 and the column control circuit 4-2 by metal wiring 3.

[0110] Figure 2 To indicate Figure 1 A detailed schematic cross-sectional view of the cross-sectional structure shown in (b).

[0111] This photodetector uses a wafer sandwiched between a P-type doped Germanium epitaxial layer 102 and a P-type doped silicon substrate 101 and a P-type thin-film silicon layer 103 as raw material for wafer fabrication. By performing ion implantation and heat treatment, a photodiode (SPAD) 202 for detecting infrared single photons and a CMOS transistor circuit 201 for amplifying and processing the signal from the photodiode 202 are formed.

[0112] also, Figure 2 The CMOS transistor circuit 201 and photodiode (SPAD) 202 are only illustrated in unit numbers, but in actual light detection devices, such as... Figure 1 As shown, a CMOS transistor circuit for driving SPAD202 is formed by multiple SPAD202 arranged in an array and multiple CMOS transistor circuits201 combined.

[0113] Furthermore, by utilizing existing manufacturing processes to form the components within the photodiode 202, the components within the CMOS transistor circuit 201, and the wiring between the photodiode 202 and the CMOS transistor circuit 201, an integrated infrared single-photon detection device is realized, comprising an amplifier capable of signal amplification or a CMOS transistor circuit 201 capable of signal processing.

[0114] A photodiode (SPAD) 202 is formed on a p-type silicon substrate 101. The p-type silicon substrate 101 is a general-purpose silicon wafer, doped with group III impurities such as boron, and its carrier concentration is 1×10⁻⁶. 15 cm -3 Up to 1×10 19 cm -3 Ideally, it should be 1×10 18 cm -3 .

[0115] The p-type germanium epitaxial layer 102 is formed on the silicon substrate 101 by epitaxial growth and is p-type doped with a concentration of 1×10⁻⁶. 15 cm -3 Up to 1×10 16 cm -3 Ideally, it should be 7×10 15 cm -3 The thickness ranges from 4μm to 7μm, with 5.5μm being ideal.

[0116] A P-type thin-film silicon layer 103 is formed on the P-type germanium epitaxial layer 102, and the concentration of this P-type thin-film silicon layer 103 is 1×10⁻⁶. 15 cm -3 Up to 1×10 16 cm -3 Ideally, it should be 7×10 15 cm -3 The thickness is 0.8 μm to 1.2 μm, ideally 1.0 μm. This P-type thin-film silicon layer 103 is bonded to the P-type germanium epitaxial layer 102 in a vacuum at room temperature through surface activation bonding.

[0117] Moreover, the P-type thin-film silicon layer 103 is achieved in the form of a thin and uniform film thickness by using a smart stripping technique of hydrogen ion implantation.

[0118] In the photodiode 202 portion, an APD P-well layer 105, an APD N-well layer 106, and an N-well layer 107 are formed from deep within the P-type thin-film silicon layer 103 using conventional ion implantation techniques. + Diffusion layer 108, to surround N + The diffusion layer 108 is configured with a protective ring N-well layer 107.

[0119] The APD P-well layer 105 is located at a depth of 0.7 μm to 0.8 μm from the surface of the P-type thin-film silicon layer 103, and has a concentration of 1 × 10⁻⁶. 16 cm -3 Up to 1×10 17 cm -3 The ideal value is 7×10 16 cm -3 The P-type diffusion layer is used to control the electric field at the junction of the P-type thin-film silicon layer 103 and the P-type germanium epitaxial layer 102, thereby reducing the dark current generated at this interface.

[0120] The APD N-well layer 106 is located at a depth of 0.2 μm to 0.7 μm from the surface of the P-type thin-film silicon layer 103, and has a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 16 cm -3 The ideal value is 7×10 15 cm -3 The N-type diffusion layer.

[0121] Both the APD P-well layer 105 and the APD N-well layer 106 form PN junctions, and a sufficiently high electric field is applied to their junction portions in a manner that enables avalanche multiplication.

[0122] In order to be electrically connected to the APD N-well layer 106 and to contact the metal wiring 3 with a sufficiently low resistance value, a 1×10⁻⁶ concentration of silicon is formed at a depth of 0.2 μm from the surface of the P-type thin-film silicon layer 103. 19 cm -3 Up to 1×10 21 cm -3 N + Diffusion layer 108. This N + The diffusion layer 108 can also be used with the N-type transistors in the CMOS transistor circuit 201 described below. + The diffusion layer 108 is formed simultaneously.

[0123] Furthermore, in the N of the photodiode + Around the diffusion layer 108, a concentration of 1×10⁻⁶ is configured to prevent edge breakdown. 17 cm -3 Up to 1×10 19 cm -3 The protective ring N-well layer 107.

[0124] Furthermore, a shallow trench isolation (STI) layer 104 is provided around each photodiode 202 for electrical separation.

[0125] The CMOS transistor circuit 201 is basically fabricated within a P-type thin-film silicon layer 103 using existing CMOS manufacturing techniques.

[0126] Figure 2 110 and 111 are respectively a P-well layer containing an N-channel transistor and an N-well layer containing a P-channel transistor. Within each well layer, N-channel transistors, which serve as high-concentration diffusion layers constituting the source and drain, are disposed. + Diffusion layer 108 and P + Diffusion layer 109.

[0127] Moreover, N + Diffusion layer 108 and P + The diffusion layer 109 becomes a well contact connected to the well layers 110 and 111 with low resistance. The gate electrode of the metal-oxide-semiconductor field-effect transistor (MOSFET) is 112. The electrodes of the transistor are electrically connected through electrode plugs 114, and the circuit structure of the photodetector is formed by metal wiring 115.

[0128] Figure 3 The method of manufacturing a wafer is described, wherein the wafer is the basic material for manufacturing the optical detection device of the present invention capable of detecting infrared single photons.

[0129] First, such as Figure 3 As shown in (a), in the existing 1×10 15 cm -3 Up to 1×10 19 cm -3 Ideally, it should be 1×10 18 cm -3 A P-type silicon substrate 301 doped with boron and other group III impurities is epitaxially grown to form a P-type germanium epitaxial layer 302.

[0130] At this time, the carrier concentration of the p-type germanium epitaxial layer 302 is 1×10⁻⁶. 15 cm -3 Up to 1×10 16 cm -3 Ideally, it should be 7×10 15 cm -3 The thickness ranges from 4μm to 7μm, with 5.5μm being ideal.

[0131] On the other hand, such as Figure 3 As shown in (b), for the existing 1×10 15 cm -3 Up to 1×10 16 cm -3 The ideal value is 7×10 15cm -3 The concentration of P-type silicon substrate 303 doped with group III impurities such as boron is 1×10 16 cm -3 Up to 1×10 17 cm -3 Ideally, it should be 5×10 16 cm -3 The dose is injected with hydrogen ions at an energy of 110 keV (H). + ).

[0132] like Figure 3 As shown in (c), the two substrates 301 and 303 are bonded in a vacuum using surface activation bonding technology. In the surface activation bonding, the two substrates are introduced into a vacuum chamber (not shown), and their respective surfaces are sputtered with argon (Ar) ions to bond them together. A pressure of about 300N is applied for about 60 seconds, thereby mechanically bonding the two substrates.

[0133] By annealing the bonded substrates at a temperature of 400°C to 600°C, it is possible to achieve the desired result. Figure 3 As shown in (d), cleavage occurs at the hydrogen ion implantation site, forming a P-type silicon layer 303 of about 1 μm on the P-type germanium epitaxial layer 302.

[0134] Furthermore, chemical mechanical polishing (CMP) is performed to planarize the surface of the P-type silicon layer 303, followed by wet etching to remove surface damage, such as... Figure 3 The wafer is completed as shown in (e), and this wafer becomes the raw material for the wafer fabrication of an infrared single-photon photodetector.

[0135] Figure 4 is a schematic cross-sectional view illustrating the wafer fabrication process of an optical detection device capable of detecting infrared single photons.

[0136] A wafer of germanium 402 held between silicon 401 and 403 is used as the starting material. After cleaning the wafer by Radio Company of America (RCA) or similar methods, a 10 nm to 30 nm pad oxide film 404 is grown by thermal oxidation. Then, a silicon nitride film 405 of about 100 nm to 200 nm is deposited using a reduced-pressure CVD method. Finally, the silicon nitride film 405 and the pad oxide film 404 are patterned using existing photolithography techniques and etching with photoresist 406 as a mask, thereby obtaining the structure shown in Figure 4(a).

[0137] Then, the photoresist 406 is removed, and shallow trenches are formed on the silicon film 403 by etching the silicon nitride film 405 as a hard mask. After performing RCA cleaning, a silicon oxide film of 10 nm to 20 nm is formed on the surface of the trench by thermal oxidation. Then, a silicon oxide film of 500 nm to 700 nm is deposited by high-density plasma (HDP)-CVD, and planarized by chemical mechanical polishing (CMP), thereby forming an STI oxide film 407 embedded in the trench for device separation, and obtaining the cross-sectional structure shown in FIG4(b).

[0138] The silicon nitride film 405 is removed using hot phosphoric acid, and the pad oxide film 404 is removed using hydrofluoric acid, making the height of the STI oxide film consistent with the silicon surface. Then, sacrificial oxidation of 10nm to 20nm is performed by thermal oxidation, thereby obtaining the structure shown in Figure 4(c). Up to this step, the process follows typical CMOS logic (LOGIC) technology. This is followed by an additional step specific to photodetectors capable of detecting single infrared photons.

[0139] First, in order to form the APD P-well layer 409, a photoresist 406 is used as a mask with an acceleration energy of 310 keV and a dose of 6 × 10⁻⁶ using conventional photolithography techniques. 11 cm -2 Boron ions were implanted (Figure 4(d)). Then, photoresist 406 was removed.

[0140] Similarly, to form the APD N-well layer 410, a photoresist 406 is used as a mask with an acceleration energy of 330 keV and a dose of 7 × 10⁻⁶ using conventional photolithography techniques. 11 cm -2 And accelerating energy of 90 keV and dose of 2 × 10 15 cm -2 Phosphorus ions were injected (Figure 4(e)). Then, photoresist 406 was removed.

[0141] Subsequently, in order to form the protective ring N-well layer 411, conventional photolithography was used, with photoresist 406 as a mask to accelerate to an energy of 70 keV and a dose of 4 × 10⁻⁶. 11 cm -2 And accelerating energy of 200 keV and dose of 4 × 10 11 cm -2 Phosphorus ions were injected (Figure 4(f)). Then the photoresist 406 was removed.

[0142] From the APD P-well lithography process up to this step, these are additional steps to the conventional CMOS logic process required to manufacture an infrared single-photon detection device. Following this step, the conventional CMOS logic process proceeds sequentially, therefore detailed specifications are omitted.

[0143] First, to form an N-channel transistor, boron ion implantation is performed using conventional photolithography techniques and a photoresist 406 as a mask to form a logic P-well layer 412 (Figure 4(g)). This process also includes boron or BF2 ion implantation to adjust the threshold of the N-channel transistor. After ion implantation, the photoresist 406 is removed.

[0144] Furthermore, in order to form a P-channel transistor, phosphorus ion implantation is performed using conventional photolithography techniques and with photoresist 406 as a mask to form a logic N-well layer 413 (Figure 4(h)). This process also includes phosphorus ion implantation to adjust the threshold of the P-channel transistor. After ion implantation, the photoresist 406 is removed.

[0145] Then, the sacrificial oxide film 408 is removed using hydrofluoric acid or the like. After pre-cleaning with RCA or the like, the gate oxide film 414 is formed by thermal oxidation. Polysilicon is deposited to form the gate electrode 415 by depressurized CVD, and the gate electrode 415 is patterned using conventional photolithography and etching techniques. The photoresist 406 is removed, thereby obtaining the structure shown in FIG4(i).

[0146] Next, in order to form an n-channel transistor to mitigate the drain field and suppress short-channel effects, - Section 416, after forming the photoresist 406 of the N-channel transistor section through an opening pattern using conventional photolithography as shown in FIG4(j), performs arsenic ion implantation and boron or BF2 ion implantation, and removes the photoresist 406. The arsenic ion implantation is used to form a lightly doped drain (LDD) to mitigate the drain field, and the BF2 ion implantation is used to create a pocket to mitigate the short-channel effect.

[0147] Similarly, in order to form p as shown in Figure 4(k) - In section 417, after the photoresist 406 forming the P-channel transistor section is patterned with an opening, BF2 ion implantation as LDD and phosphorus ion implantation as a pocket are performed to remove the photoresist 406. Then, a silicon oxide film is formed by CVD, and sidewall spacers 418 are formed on the sidewall of the gate electrode 415 by anisotropic etching as shown in FIG4(l).

[0148] Next, in order to form the N-channel transistor, + A diffusion layer 419 is formed as shown in Figure 4(m) to create a photoresist 406 pattern with an opening in the N-channel transistor section. At this time, in order to simultaneously form the N-channel of the APD... +A diffusion layer 419 is formed, and a photoresist opening is also made on the upper part of the APD. Arsenic ions are implanted using this photoresist 406 as a mask, thereby forming the source and drain of the N-channel transistor and the N-channel of the APD. + Diffusion layer 419.

[0149] Similarly, in order to form the source and drain of the P-channel transistor and the P-channel... + A diffusion layer 420 is formed as shown in FIG4(n) to create a photoresist 406 pattern with an opening in the P-channel transistor section. This photoresist 406 is used as a mask for BF2 ion implantation, and then the photoresist 406 is removed. Next, a silicon oxide film is formed over the entire surface using a CVD method or the like, and the pattern is created such that a silicon oxide film 422 remains in areas where silicide formation is not desired in the subsequent silicide process for low resistance reduction.

[0150] The area where silicide is not desired to form is specifically the APD portion in this invention, but even in the APD portion, the structure shown in FIG4(o) is designed such that silicide will be formed in the portion where contact will be formed later.

[0151] Then, cobalt is sputtered, and the cobalt reacts with silicon at a relatively low temperature of around 500°C. The cobalt on the unreacted silicon oxide film is removed by selective etching. Subsequently, silicide formation is achieved by heat treatment to create a low-resistivity silicide layer.

[0152] Then, the structure shown in FIG. 4(p) is obtained by forming the existing interlayer insulating film 423, the contacts and the tungsten plugs 424 in the contacts, and the first wiring layer 425. Although not shown here, a multilayer metal wiring structure is then obtained by forming a metal interlayer film, a via, and an upper metal wiring layer. Furthermore, a protective film is formed on the uppermost metal layer to protect the chip, and the protective film on the pad is removed to achieve electrical conduction. After these processes, back-side grinding is performed to set the wafer to the required thickness, and back-side boron implantation is performed to reduce the resistance of the back side, forming the P-type back side. + The diffusion layer is then used to complete the wafer fabrication of the photodetector of the present invention.

[0153] Furthermore, in the aforementioned embodiment, the P-type thin-film silicon layer 103 is as follows: Figure 3 As shown, it is formed by surface activation bonding technology and smart stripping technology using hydrogen ion implantation, but the present invention is not limited to this. It can also be formed by growing silicon epitaxially to a thickness of about 1 μm on a P-type germanium epitaxial layer 102.

[0154] Figure 5 The figure shows the carrier concentration distribution of the main portion of the APD formed by the aforementioned process, obtained from process simulation. The horizontal axis represents the depth from the surface of silicon film 403, and the vertical axis represents the concentration of the diffusion layer. It can be seen that... Figure 2 The structure shown can be roughly realized by the manufacturing method of the present invention.

[0155] Furthermore, methods for irradiating a SPAD to detect incident light from an object include surface irradiation and back-side irradiation. In the SPAD of the present invention, such as... Figure 6 As shown, the n of the surface + The bonding layer 108 is as thin as 0.5 μm, and within the underlying P-type germanium epitaxial layer 102, there exists a depletion layer that generates the photoelectric effect. The P-type thin-film silicon layer 103 absorbs visible light, but its thickness of only 0.5 μm makes it difficult to absorb all visible light. Therefore, in the case of surface irradiation, a visible light blocking filter 120 is required to block visible light.

[0156] Next, we will examine the situation under back illumination.

[0157] The P-type germanium epitaxial layer 102 is as thin as about 5 μm, while the underlying P-type silicon substrate 101 needs to be at least 200 μm thick to ensure the mechanical strength of the chip. Even without a visible light filter on the back side, the thick P-type silicon substrate absorbs visible light and prevents it from reaching the depletion layer formed on the P-type germanium epitaxial layer 102.

[0158] In contrast, infrared light with a wavelength of around 1.1 μm passes through silicon (Si) and reaches the depletion layer. Therefore, SPADs that selectively sense only infrared light can be achieved even without visible light blocking filters. Consequently, the process of fabricating filters is eliminated, thus simplifying the process or reducing costs.

Claims

1. A light detection device for detecting incident light from an object, comprising: P-type silicon substrate; A P-type germanium layer is formed on the first surface of the P-type silicon substrate by epitaxial growth; as well as A P-type thin-film silicon layer is formed on the P-type germanium layer. The P-type thin-film silicon layer is divided into a first region and a second region by shallow trench isolation. In the first region, a plurality of single-photon avalanche diodes, which serve as single-photon detection diodes, are formed in an array. In the second region, a complementary metal-oxide-semiconductor transistor circuit that drives the single-photon avalanche diodes is formed.

2. The optical detection device according to claim 1, characterized in that, The P-type thin-film silicon layer is formed using surface activation bonding technology and intelligent stripping technology utilizing hydrogen ion implantation.

3. The optical detection device according to claim 1, characterized in that, The P-type thin-film silicon layer is formed on the P-type germanium layer by epitaxial growth of silicon.

4. The light detection device according to any one of claims 1 to 3, wherein, It is configured to receive incident light from the second side, which is the back side, of the P-type silicon substrate.

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