A module-level targeted energy saving control method for a modular data center

Abstract

The application discloses a module-level targeted energy-saving control method of a modular data center, and is based on a pure hardware solidified multi-hardware parallel autonomous bottom hardware patent technical scheme and a modular cluster architecture implementation previously submitted by the applicant; a pure hardware solidified hardware targeted scheduling unit collects load state signals in real time through a solidified monitoring circuit built in a module, completes load level determination through pure hardware logic, triggers targeted power-off, deep hibernation or full-power wake-up operations for modules with different load levels, and completes task scheduling between modules through pure hardware layer atomic hardware jumping, and no software is involved in the whole core process. The application realizes module-level full-link linkage energy saving, greatly reduces data center power use efficiency, and is realized by pure hardware in the whole process, has no tampering and intrusion risk, and is fully suitable for the core requirements of high safety and low energy consumption of various data centers.

Description

Technical Field

[0001] This invention relates to the field of data center energy-saving control technology, specifically to a modular data center module-level targeted energy-saving control method based on a hardware autonomous architecture. It is applicable to energy consumption management and power usage efficiency optimization of various large data centers and intelligent computing centers, and is highly synergistic with modular cluster architecture and cooling and power supply collaborative control methods. Background Technology

[0002] The industry has imposed mandatory requirements on the power efficiency (EER) values ​​of newly built data centers. The EER of newly built data centers in the eastern region must not exceed 1.25, and in the western region, it must not exceed 1.2. Under the dual carbon targets, energy conservation and consumption reduction of data centers have become a rigid requirement.

[0003] Existing data center energy-saving control solutions have the following core defects: First, the core control links rely 100% on software algorithms and firmware programs. Load determination and power consumption regulation are achieved through baseboard management controller scripts, kernel-mode programs, and machine learning models. This poses risks of tampering, intrusion, and software crashes leading to control failures, and cannot meet the high security requirements of core data centers. Second, most solutions use server-level power consumption regulation, which cannot achieve unified targeted management at the module level. This results in fine-grained regulation, high scheduling latency, and significant computing power loss. Third, cooling and power supply auxiliary units cannot achieve hardware-level linkage with server loads, resulting in ineffective energy consumption such as "server hibernation and cooling full-power operation," failing to achieve optimal energy efficiency. Fourth, task scheduling relies on software virtual machine migration, which poses risks of business interruption and data loss, and cannot achieve seamless power consumption regulation.

[0004] Currently available technical solutions cannot simultaneously meet the core requirements of high security, high reliability, and extreme energy efficiency, nor can they adapt to the mandatory management and control requirements of data centers across all scenarios. Summary of the Invention

[0005] Purpose of the invention The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a module-level targeted energy-saving control method for modular data centers. This method achieves the entire process of load acquisition, level determination, power consumption regulation, and task scheduling through pure hardware logic, without any software involvement. It realizes module-level full-link linkage energy saving, significantly reduces the power consumption efficiency of data centers, and meets the high security and high reliability requirements of various core data centers. Technical solution

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A module-level targeted energy-saving control method for a modular data center is proposed, based on the applicant's prior patented underlying hardware technology, which is centered on pure hardware-based fixed logic and multi-hardware parallel autonomy, and the aforementioned hardware grouping cluster architecture of the modular data center. The cluster architecture incorporates a hardware-targeted scheduling unit, implemented using pure hardware gate circuits, which collects the load status signals of each standardized hardware module in real time through monitoring hardware circuits embedded in the hardware circuits of each standardized hardware module. The hardware-targeted scheduling unit performs hardware-level determination of module load levels using pure hardware gate circuit logic, with no software algorithms / firmware programs involved in the entire execution path of load determination. For standardized hardware modules determined to be idle / low-load, the hardware-targeted scheduling unit directly triggers hardware-level targeted power-off or deep sleep operations, synchronously regulating the power consumption of the corresponding server, power supply unit, and cooling sub-unit within the module. For standardized hardware modules determined to be high-load, the hardware-targeted scheduling unit directly triggers hardware-level full-power wake-up operations. Task scheduling between modules is completed through atomic hardware jumps implemented at the pure hardware layer, with no software instructions involved in the entire execution path of the core control. Beneficial effects

[0007] Compared with the prior art, the present invention has the following key beneficial effects: 1. The entire process is implemented in pure hardware, which significantly improves the security and reliability of the system: The entire process of load acquisition, judgment, control and scheduling is implemented through pure hardware gate circuits. There is no software algorithm or firmware program involved, and there is no risk of tampering, intrusion or downtime. It is fully compatible with the high security requirements of various core data centers.

[0008] 2. Module-level end-to-end linkage significantly reduces energy consumption and power usage efficiency: It realizes unified targeted management and control at the module level, and synchronously regulates servers, power supply and cooling units, completely eliminating the ineffective energy consumption of "server hibernation and auxiliary units running at full power", which can reduce the power usage efficiency of data centers to below 1.15, fully meeting the dual carbon mandatory requirements.

[0009] 3. Pure hardware atomic jump ensures continuous and stable business operations: Task scheduling is achieved through pure hardware atomic jumps, eliminating the delays and interruption risks associated with software virtual machine migration. Business operations are uninterrupted and data is not lost, ensuring continuous and stable operation of data center services while achieving energy-saving control.

[0010] 4. Zero-latency response for precise control: The control process is implemented with pure hardware logic, with a response latency of ≤1 millisecond. It is completely synchronized with changes in module load, without any lag, achieving precise power consumption control and avoiding risks caused by over-control or untimely control. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments.

[0012] This embodiment is based on a modular cluster architecture of a large hub node data center. The underlying hardware architecture is the prior patented underlying hardware technology solution submitted by the applicant, which is based on pure hardware solidified logic and multi-hardware parallel autonomy. The cluster architecture is the hardware grouping cluster architecture of the modular data center described in claim 1 above.

[0013] In this embodiment, the cluster's built-in hardware targeted scheduling unit is implemented through pure hardware gate circuits and deployed in the cluster's core hardware management cabinet. Each standardized hardware module has a built-in monitoring hardware circuit embedded in the hardware circuit. It collects the module's load status signals in real time through high-precision hardware sensors, including server CPU utilization, memory usage, power consumption data, power supply unit output power data, and cooling subunit operating power data. The acquisition frequency is 100 Hz, and the collected data is synchronized to the hardware targeted scheduling unit in real time through a dedicated point-to-point hardware link.

[0014] The hardware-targeted scheduling unit uses pure hardware gate circuit logic and fixed load level thresholds embedded in the hardware circuit to complete the hardware-level determination of the module load level, dividing the module into three levels: high load (load rate ≥ 70%), low load (30% ≤ load rate < 70%), and idle (load rate < 30%). The entire execution path of load determination is carried out without any software algorithm or firmware program participation, and without the intervention of the central processing unit.

[0015] For standardized hardware modules determined to be idle, the hardware-targeted scheduling unit directly outputs a hardware level signal to trigger a hardware-level targeted power-off operation. Through hardware logic, it synchronously cuts off the main power supply to the server, auxiliary power supply to the power supply unit, and main power supply to the cooling subunit within the module, retaining only the minimum standby power supply to the monitoring circuit, thereby minimizing module power consumption. For standardized hardware modules determined to be under low load, a hardware-level deep sleep operation is triggered, synchronously reducing the server's main frequency, the output power of the power supply unit, and the fan speed of the cooling subunit to achieve extreme energy saving under low load. For standardized hardware modules determined to be under high load, a hardware-level full-power wake-up operation is directly triggered to ensure full-load computing power supply to the module.

[0016] Before the module goes into hibernation or is powered off, the hardware-targeted scheduling unit seamlessly migrates all running tasks and business data in the target module to available modules in the cluster through atomic hardware jumps at the pure hardware layer. The jump process is done without software involvement, with no business interruption or data loss, and the entire execution path of the core control is executed without any software instructions.

[0017] The energy-saving control method in this embodiment can achieve module-level full-link energy saving, reducing the data center power efficiency from the industry average of 1.4 to below 1.15. At the same time, it is implemented entirely in hardware, with no security risks, and fully meets the mandatory requirements of various data centers.

Claims

1. A module-level targeted energy-saving control method for a modular data center, characterized in that, Based on the applicant's prior patented underlying hardware technology solution, which is based on pure hardware solidified logic and multi-hardware parallel autonomy, and the hardware grouping cluster architecture of the modular data center described in claim 1; The cluster architecture has a built-in hardware targeted scheduling unit that is implemented with pure hardware gate circuits. Through the monitoring hardware circuits built into each standardized hardware module and solidified in the hardware circuits, the load status signals of each standardized hardware module are collected in real time. The hardware-targeted scheduling unit completes the hardware-level determination of the module load level through pure hardware gate circuit logic. The entire execution path of the load determination is without any software algorithm / firmware program involved. For standardized hardware modules that are determined to be idle / low load, the hardware targeted scheduling unit directly triggers hardware-level targeted power-off or deep sleep operations, and synchronously regulates the power consumption of the corresponding server, power supply unit, and cooling sub-unit within the module. For standardized hardware modules identified as being under high load, the hardware-targeted scheduling unit directly triggers a hardware-level full-power wake-up operation; Task scheduling between modules is accomplished through atomic hardware jumps implemented at the pure hardware layer, and the entire execution path of the core control is completed without any software instructions involved.

2. The method according to claim 1, characterized in that, The load status signal is the full-link load status signal of the server, power supply unit, and cooling subunit within the module.

3. The method according to claim 1, characterized in that, The determination of the module load level is based on a fixed load level threshold embedded in the hardware circuit.

4. The method according to claim 1, characterized in that, The targeted power-off or deep sleep operation synchronously cuts off / reduces the power consumption of the entire unit within the corresponding module through hardware logic, without software relay.

5. The method according to claim 1, characterized in that, The atomic hardware jump is implemented in a pure hardware layer without software involvement, ensuring uninterrupted service and no data loss.