Random number generator and random number generation method based on a three-sided ring oscillator

Abstract

The application provides a random number generator and a random number generation method based on a three-edge ring oscillator, which can be applied to the technical field of random number generation. The random number generator comprises a three-edge ring oscillator module configured to start an oscillation mode under the control of a control signal and output an oscillation signal in the oscillation mode; an entropy extraction module configured to extract original bits and an effective indication signal based on the oscillation signal; a detection module configured to detect the state of the oscillation signal and output a collapse signal to a control module in the case that the state of the oscillation signal represents that a collapse event occurs in the oscillation signal; the control module is configured to output the control signal to the three-edge ring oscillator module and control the three-edge ring oscillator module to restart the oscillation mode in the case that the collapse signal is received, store the original bits and obtain an original bit sequence; and a conversion module configured to convert the original bit sequence into a target random number.

Description

Technical Field

[0001] This application relates to the field of random number generation technology, and more specifically, to a random number generator and a random number generation method based on a triangular ring oscillator. Background Technology

[0002] Random numbers are numerical sequences that cannot be predicted and statistically follow a uniform or specific distribution. Random numbers can be divided into true random numbers and pseudo-random numbers. Pseudo-random numbers are generated from an initial seed using mathematical algorithms, exhibit periodicity, and can be reproduced. True random numbers, on the other hand, are generated based on unpredictable phenomena such as physical noise, cannot be reproduced, and have higher unpredictability. Random numbers are fundamental in statistical simulation experiments; for example, Monte Carlo simulations require random number generators to produce random molecular configurations. However, current random number generators have low throughput and cannot operate continuously. Summary of the Invention

[0003] In view of this, embodiments of this application provide a random number generator and a random number generation method based on a three-sided ring oscillator.

[0004] One aspect of this application provides a random number generator based on a triangular ring oscillator, comprising: a triangular ring oscillator module configured to activate an oscillation mode under the control of a control signal and output an oscillation signal in the oscillation mode; an entropy extraction module connected to the triangular ring oscillator module configured to extract the original bit and a valid indication signal based on the oscillation signal; a detection module connected to the triangular ring oscillator module configured to detect the state of the oscillation signal and output a collapse signal to the control module when the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal; a control module connected to the triangular ring oscillator module, the entropy extraction module, and the detection module configured to output a control signal to the triangular ring oscillator module, control the triangular ring oscillator module to restart the oscillation mode when a collapse signal is received, and store the original bit to obtain an original bit sequence when the valid indication signal indicates that the original bit is valid; and a conversion module connected to the control module configured to convert the original bit sequence into a target random number.

[0005] Another aspect of this application provides a random number generation method, comprising: using a triangular ring oscillator module to activate an oscillation mode under the control of a control signal, and outputting an oscillation signal in the oscillation mode; using an entropy extraction module to extract the original bit and a valid indication signal based on the oscillation signal; using a detection module to detect the state of the oscillation signal, and outputting a collapse signal to a control module when the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal; using the control module to output a control signal to the triangular ring oscillator module, and controlling the triangular ring oscillator module to restart the oscillation mode when the collapse signal is received, and storing the original bit to obtain an original bit sequence when the valid indication signal indicates that the original bit is valid; and using a conversion module to convert the original bit sequence into a target random number.

[0006] According to embodiments of this application, an oscillation signal is output through a three-sided ring oscillator module. This module can directly extract the randomness of the oscillation signal based on its three jitter edges, without waiting for a detection module to detect a crash event before extracting the randomness. This improves the extraction efficiency of the random number generator and increases its throughput. Furthermore, the detection module detects whether a crash event has occurred in the oscillation signal. In the event of a crash event, the control module can restart the oscillation mode of the three-sided ring oscillator module, ensuring the continuity of the random number generator's operation. Attached Figure Description

[0007] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings, which will be explained in conjunction with the drawings.

[0008] Figure 1 A block diagram of a random number generator based on a triangular ring oscillator according to an embodiment of this application is shown.

[0009] Figure 2 A circuit diagram of a three-sided ring oscillator module according to an embodiment of this application is shown.

[0010] Figure 3 A circuit diagram of an entropy extraction module according to an embodiment of this application is shown.

[0011] Figure 4 A schematic diagram illustrating the principle of the entropy extraction module extracting raw bits according to an embodiment of this application is shown.

[0012] Figure 5 A circuit diagram of a detection module according to an embodiment of this application is shown.

[0013] Figure 6 A schematic diagram illustrating the detection principle of the detection module according to an embodiment of this application is shown.

[0014] Figure 7 A schematic diagram illustrating the working state and switching process of the control module according to an embodiment of this application is shown.

[0015] Figure 8 A flowchart of a random number generation method according to an embodiment of this application is shown. Detailed Implementation

[0016] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0018] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0019] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0020] Random numbers are used in various applications, including CAPTCHA generation, lotteries, and the generation of random elements in games. Random number generators (RNGs) are used to generate session keys, initialization vectors, authentication scheme incentives, and masks to resist side-channel attacks in cryptographic technologies and security authentication protocols. Random numbers are critical data in security systems, whose security is built on the assumption that the random number generator produces unbiased, uncorrelated, and unpredictable keys. In encryption protocols, all information except the key is public knowledge. Therefore, if the key is stolen or compromised by an attacker, the entire encryption system will fail. It is essential to ensure that attackers cannot compute the key; that is, the key must be random.

[0021] Secure systems can encrypt pseudo-random numbers generated by pseudo-random number generators (PRNGs). A PRNG generator is essentially a complex deterministic algorithm (finite state machine) where the sole source of entropy comes from the initial seed. The PRNG generator's role is simply to expand the initial seed into a long sequence with good statistical properties; however, this long sequence is a predictable periodic sequence. Therefore, secure systems that rely solely on PRNG generators for random number generation are vulnerable to attack, making PRNGs unsuitable for many encryption applications. In contrast, the output of a true random number generator (TRNG) provides no information for predicting random numbers; therefore, even if an attacker knows the actual circuit structure of the entropy source, they cannot predict the generated random numbers. Compared to the untrustworthiness of complex algorithms using PRNG generators, TRNG generators can achieve physically unpredictable random phenomena through simple circuit structures.

[0022] However, TRNG generators in related technologies typically use single-edge oscillators to generate entropy sources, resulting in low throughput due to the simplistic nature of the entropy source. Furthermore, TRNG generator crashes are treated as faults and cannot be actively recovered from. Additionally, the output random numbers conform to a uniform distribution, limiting their application scope.

[0023] In view of this, this application provides a random number generator based on a three-sided ring oscillator. By outputting an oscillation signal through a three-sided ring oscillator module, the randomness of the oscillation signal can be directly extracted based on the three jitter edges, without waiting for a detection module to detect a crash event before extracting the randomness. This improves the extraction efficiency and increases the throughput of the random number generator. Furthermore, the detection module detects whether a crash event has occurred in the oscillation signal. In the event of a crash event, the control module can restart the oscillation mode of the three-sided ring oscillator module, ensuring the continuous operation of the random number generator.

[0024] Figure 1 A block diagram of a random number generator based on a triangular ring oscillator according to an embodiment of this application is shown.

[0025] like Figure 1 As shown, the random number generator 100 based on a triangular ring oscillator may include a triangular ring oscillator module 110, an entropy extraction module 120, a detection module 130, a control module 140, and a conversion module 150.

[0026] The three-sided ring oscillator module 110 can be configured to activate the oscillation mode under the control of a control signal and output an oscillation signal in the oscillation mode.

[0027] The entropy extraction module 120 is connected to the three-sided ring oscillator module 110. The entropy extraction module 120 can be configured to extract the original bit and the valid indication signal based on the oscillation signal.

[0028] The detection module 130 is connected to the three-sided ring oscillator module 110. The detection module 130 can be configured to detect the state of the oscillation signal, and output a collapse signal to the control module when the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal.

[0029] The control module 140 is connected to the triangular ring oscillator module 110, the entropy extraction module 120, and the detection module 130. The control module 140 can be configured to output a control signal to the triangular ring oscillator module, control the triangular ring oscillator module to restart the oscillation mode when a crash signal is received, and store the original bit to obtain the original bit sequence when a valid indication signal indicates that the original bit is valid.

[0030] The conversion module 150 is connected to the control module 140, and the conversion module 150 can be configured to convert the original bit sequence into a target random number.

[0031] The control module can send control signals to the three-sided ring oscillator module, thereby controlling the module to start oscillation mode and output an oscillation signal under the control of the control signals. The three-sided ring oscillator module can also stop oscillation mode under the control of the control signals.

[0032] The oscillation mode of the three-sided ring oscillator module can be achieved by injecting three signal edges into the module under the control of a control signal to form an oscillation loop. The injection positions of the three signal edges can be different, thus giving them different initial phases within the three-sided ring oscillator module. An oscillation signal is generated through the competition and random jitter of the three signal edges within the module. This oscillation signal can serve as the entropy source of a random number generator. The random jitter of the three signal edges refers to the tiny and unpredictable fluctuations generated during the propagation of each signal edge due to physical factors such as thermal noise and shot noise within the random number generator's circuitry. The competition among the three signal edges refers to the dynamic process of mutual chasing, caused by the random differences in their propagation speeds, resulting in constantly changing relative distances between adjacent signal edges.

[0033] The entropy extraction module extracts random jitter from the oscillating signal to obtain the raw bits. The raw bits can be single binary values ​​extracted directly from the oscillating signal without any processing. For example, the raw bits can be binary 0 or 1. A valid indicator signal can be used to indicate whether the raw bits are valid or invalid. The entropy extraction module can transmit the raw bits and the valid indicator signal to the control module.

[0034] The detection module can detect the state of the oscillation signal of the three-sided ring oscillator module. A collapse event can occur when the oscillation signal fails to meet the requirements for extracting random numbers. For example, if a signal edge aligns with the previous signal edge, the two signal edges will annihilate, leaving only one signal edge. The detection module can output a collapse signal to the control module when a collapse event occurs in the oscillation signal, indicating that a collapse event has occurred in the oscillation signal.

[0035] The control module can control the three-sided ring oscillator module to restart the oscillation mode based on the crash signal, so that the random number generator does not stop working due to the crash event.

[0036] The control module can also store the original bit when a valid indication signal indicates that the original bit is valid. The control module can arrange the stored original bits according to the extraction time to obtain the original bit sequence. The original bit sequence can be a sequence of 0s and 1s.

[0037] The conversion module can convert the original bit sequence to obtain the target random number. For example, the original bit sequence can be a binary sequence of 0s and 1s. A segment of the original bit sequence of a preset length can be selected and combined into a binary integer, and then converted to decimal to obtain the target random number.

[0038] According to embodiments of this application, an oscillation signal is output through a three-sided ring oscillator module. This module can directly extract the randomness of the oscillation signal based on its three jitter edges, without waiting for a detection module to detect a crash event before extracting the randomness. This improves the extraction efficiency of the random number generator and increases its throughput. Furthermore, the detection module detects whether a crash event has occurred in the oscillation signal. In the event of a crash event, the control module can restart the oscillation mode of the three-sided ring oscillator module, ensuring the continuity of the random number generator's operation.

[0039] Figure 2 A circuit diagram of a three-sided ring oscillator module according to an embodiment of this application is shown.

[0040] like Figure 2 As shown, the three-sided ring oscillator module includes three-stage inverting units and three-stage gate units. Figure 2 Taking each stage of the inverting unit as an example, which includes three inverters, the inverting unit can also be equipped with other numbers of inverters according to actual needs.

[0041] exist Figure 2 In this configuration, the output of the first-stage inverting unit 211 is connected to the input of the first-stage gate unit 221, the output of the first-stage gate unit 221 is connected to the input of the second-stage inverting unit 212, the output of the second-stage inverting unit 212 is connected to the input of the second-stage gate unit 222, the output of the second-stage gate unit 222 is connected to the input of the third-stage inverting unit 213, the output of the third-stage inverting unit 213 is connected to the input of the third-stage gate unit 223, and the output of the third-stage gate unit 223 is connected to the input of the first-stage inverting unit 211.

[0042] The first-stage gate unit 221 is configured to output the first-stage output sub-oscillation signal under the control signal RUN. The second-stage gate unit 222 is configured to output the second-stage output sub-oscillation signal under the control signal. The third-stage gate unit 223 is configured to output the third-stage output sub-oscillation signal under the control signal.

[0043] The gate unit can include a tri-state gate. The control terminal of the gate unit can be connected to a control signal. Under the action of the control signal, the three signal edges can be injected into the three gate units simultaneously, forming a three-competitive-edge oscillation loop in the three-sided ring oscillator module. The three-sided ring oscillator module can output the oscillation signal from the oscillation loop formed by the three signal edges as the first-stage output sub-oscillation signal, the second-stage output sub-oscillation signal, and the third-stage output sub-oscillation signal respectively through three levels of gate units. Because of the consistency of the transmission path of each edge in the three-competitive-edge oscillation loop, the randomness is generated by the jitter difference between adjacent edges. Therefore, it reduces the problem of obtaining oscillation signals through coupling of multiple ring oscillators, and also reduces the uncertainty in the quality of random number generation caused by changes in parameters such as process angle, voltage, and temperature of the random number generator.

[0044] Figure 3 A circuit diagram of an entropy extraction module according to an embodiment of this application is shown.

[0045] like Figure 3 As shown, the signal source for the entropy extraction module can be in Figure 2 The module consists of a three-sided ring oscillator and control signals. The entropy extraction module may include a selector unit 310, a sampling trigger unit 320, and an entropy processing unit 330. The selector unit may include 2^n selectors, and the sampling trigger unit may include n sampling triggers, where n is a positive even number. Figure 3 In this example, a sampling flip-flop is used as a falling edge flip-flop for explanation. Here, D represents the input of the falling edge flip-flop, Q represents the output of the falling edge flip-flop, and C represents the clock input of the falling edge flip-flop.

[0046] In this embodiment, the selection terminal S of the first selector is connected to the output terminal of the second-stage gate unit, the first input terminal of the first selector is connected to the output terminal of the third-stage gate unit, and the second input terminal of the first selector is connected to a high-level signal. In this embodiment, the high-level signal is 1, and the low-level signal is 0. The first input terminal of the selector can be the input terminal corresponding to the high-level signal (i.e., 1), and the second input terminal of the selector can be the input terminal corresponding to the low-level signal (i.e., 0).

[0047] The selection terminal S of the (n+1)th selector is connected to a high-level signal, the first input terminal of the (n+1)th selector is connected to the output terminal of the nth selector, and the second input terminal of the (n+1)th selector is connected to a low-level signal.

[0048] The input of the nth sampling flip-flop is connected to the output of the 2nth selector, the clock of the nth sampling flip-flop is connected to the output of the second-stage gate unit, and the output of the nth sampling flip-flop is connected to the entropy processing unit.

[0049] Each sampling trigger can serve as a sampling node. The entropy extraction module can use delay lines as digitization elements to leverage the independent timing jitter at the edges of the three signal edges, achieving higher throughput because randomness can be extracted from the jittered edges of the three signal edges earlier than waiting for the oscillating signal to crash.

[0050] According to an embodiment of this application, the entropy processing unit is configured to determine the original bit based on the parity of the number of sampling flip-flops that output a low-level signal relative to the total number of sampling flip-flops among the n sampling flip-flops.

[0051] The output of the first sampling trigger can be C0, the output of the second sampling trigger can be C1, and the output of the nth sampling trigger can be C... n-1 The original bit can be represented by the following formula.

[0052] (1);

[0053] Wherein, Raw Bit represents the original bit. This indicates that the outputs of n sampled triggers are XORed. Specifically, if the number of sampled triggers with an output of 0 is even, the original bit is 0; if the number of sampled triggers with an output of 1 is odd, the original bit is 1. C i This represents the output of the i-th sampling trigger among n sampling triggers, where 0 ≤ i ≤ n-1, and i is an integer.

[0054] A single sampling flip-flop may tend to output 0 or 1 due to the circuit bias of the random number generator, but by combining the parity of multiple sampling flip-flops, the circuit bias can be effectively offset, making the distribution of 0 and 1 in the original bits closer to the ideal uniform distribution, thereby improving the quality of random numbers.

[0055] According to an embodiment of this application, the entropy processing unit is further configured to determine that the valid indication signal characterizes the original bit as valid when the outputs of the first sampling trigger and the nth sampling trigger are both high-level signals, and the output of at least one of the sampling triggers between the first and nth sampling triggers is a low-level signal.

[0056] After outputting the original bit, the valid indicator signal of the original bit can also be determined, as shown in the following formula (2).

[0057] (2);

[0058] Where Raw Bit Valid indicates a valid signal, and C0 represents the output of the first sampling trigger. This means that the outputs of the 2nd to (n-2nd)th sampled triggers are inverted, ORed, and then ANDed with the outputs of the 1st and (n-2nd)th sampled triggers.

[0059] like Figure 3 As shown, the entropy processing unit also includes two output ports. One output port, P1, is used to output the raw bit, and the other output port, P2, is used to output a valid indication signal. Each of the two output ports of the entropy processing unit can be connected to a falling-edge flip-flop, which outputs the raw bit and valid indication signal to the control module. The enable terminal (EN) of the two falling-edge flip-flops can be connected to the control signal (RUN), the clock terminal can be connected to the system clock (CLK), and the output terminal can be connected to the control module. Under the control of the control signal, the two falling-edge flip-flops can output the raw bit and valid indication signal to the control module respectively.

[0060] Figure 4 A schematic diagram illustrating the principle of the entropy extraction module extracting raw bits according to an embodiment of this application is shown.

[0061] like Figure 4 As shown, α represents the edge containing the last rising edge of the second-stage output sub-oscillation signal OUT2 from the second-stage gate unit before the oscillation mode is stopped in the triangular ring oscillator module, and γ represents the edge containing the last falling edge of the second-stage output sub-oscillation signal OUT2. β represents the edge containing the last rising edge of the third-stage output sub-oscillation signal OUT3 from the third-stage gate unit before the oscillation mode is stopped in the triangular ring oscillator module.

[0062] By setting the control signal RUN to a high level (1), the three-sided ring oscillator module can be enabled within the time period Tacc. The length of the time period Tacc is controlled so that the three output sub-oscillators accumulate sufficient jitter within Tacc. Since the clock input of the sampling trigger is connected to the second-stage output sub-oscillator signal OUT2, the output of the third-stage output sub-oscillator signal OUT3 in the delay line (i.e., the entropy extraction module) is enabled by edge α. Because the second-stage and third-stage output sub-oscillators have an approximately 90° phase difference, the third-stage output sub-oscillator signal is lower, and the sampling node in the delay line will begin to transition from 1 to 0. When edge β appears at the third-stage output sub-oscillator signal, the selector in the delay line, previously set to 0, transitions to 1 starting from edge α, causing the delay line to output the state of the third-stage output sub-oscillator signal. Finally, edge γ triggers the corresponding sampling trigger to sample the state of the third-stage output sub-oscillator signal in the delay line. In this way, the effects of all edges α, β, and γ are sampled by the sampling triggers. Figure 4The waveform below the graph shows combinations of 0s and 1s, where each column represents the output of the selector at the corresponding time, and each row represents the output of the selector at different times. Column 2 can be the output of the selector at the time corresponding to edge α, column 7 can be the output of the selector at the time corresponding to edge β, and column 8 can be the output of the selector at the time corresponding to edge γ.

[0063] The sampled output of the sampling trigger is then encoded into a raw bit and a valid indicator signal using formulas (1) and (2). After the time period Tacc, the triangular ring oscillator module can be disabled for one clock cycle. This reset clock cycle ensures the independence between consecutive raw bits and allows sufficient time to properly evaluate the raw bit and its validity. On the next rising edge of the control signal, the triangular ring oscillator module can be restarted to generate the next raw bit and transmit the previous raw bit and valid indicator signal to the control module for storage.

[0064] Figure 5 A circuit diagram of a detection module according to an embodiment of this application is shown.

[0065] like Figure 5 As shown, the detection module includes eight detection triggers, denoted as REG1, REG2, REG3, REG4, REG5, REG6, REG7, and REG8. Figure 5 In this diagram, the detection triggers can be falling-edge triggers, with D representing the input, Q representing the output, C representing the clock input, and CLR representing the reset input. OUT1, OUT2, and OUT3 represent the first-stage, second-stage, and third-stage output sub-oscillation signals, respectively. Collapse indicates a crash event. The reset inputs of the eight detection triggers are connected to the reset signal RST_N. The clock inputs of the first, second, third, fourth, and fifth detection triggers REG1, REG2, REG3, REG4, and REG5 are connected to the third-stage output sub-oscillation signal OUT3. The clock inputs of the sixth, seventh, and eighth detection triggers REG6, REG7, and REG8 are connected to the system clock CLK.

[0066] The second-stage output sub-oscillation signal OUT2 can be ANDed with the first-stage output sub-oscillation signal OUT1 after passing through an inverter, and then connected to the input of the first detection trigger REG1. The output of the first detection trigger REG1 is connected to the input of the second detection trigger REG2. The output of the second detection trigger REG2 is connected to the input of the third detection trigger REG3. The output of the third detection trigger REG3 is connected to the input of the fourth detection trigger REG4. The outputs of the second detection trigger REG2, the third detection trigger REG3, and the fourth detection trigger REG4 are ANDed and then connected to the input of the fifth detection trigger REG5. The output of the fifth detection trigger REG5 is connected to the input of the sixth detection trigger REG6. The output of the sixth detection trigger REG6 is connected to the input of the seventh detection trigger REG7. The output of the seventh detection trigger REG7 is connected to the input of the eighth detection trigger REG8. The outputs of the seventh detection trigger REG7 and the eighth detection trigger REG8 are ANDed and then output to show the detection result. The detection result can be whether a collapse event has occurred in the state of the oscillation signal. If the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal, a collapse signal can be output to the control module.

[0067] The first detection trigger REG1, the second detection trigger REG2, the sixth detection trigger REG6, and the seventh detection trigger REG7 can form a synchronizer for cross-clock domain synchronization. This detection module can simultaneously detect the first-stage output sub-oscillation signal, the second-stage output sub-oscillation signal, and the third-stage output sub-oscillation signal, detecting whether a collapse event has occurred based on the output differences of these signals before and after a collapse event. The detection module of this embodiment has a simple structure, no reference clock, no glitches, no error detection output, can fully utilize the output differences before and after a collapse event, and is easy to implement.

[0068] According to an embodiment of this application, the detection module is further configured to determine the state of the oscillation signal to characterize a collapse event occurring in the oscillation signal when the signals corresponding to multiple consecutive rising edges of the first-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are high-level signals and the signals corresponding to multiple consecutive rising edges of the second-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are low-level signals.

[0069] The state of the oscillation signal can be determined when the signals corresponding to the three consecutive rising edges of the first-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are high-level signals, and the signals corresponding to the three consecutive rising edges of the second-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are low-level signals, thus indicating that a collapse event has occurred in the oscillation signal.

[0070] Figure 6 A schematic diagram illustrating the detection principle of the detection module according to an embodiment of this application is shown.

[0071] like Figure 6 As shown, OUT1, OUT2, and OUT3 represent the first-stage output sub-oscillation signal, the second-stage output sub-oscillation signal, and the third-stage output sub-oscillation signal, respectively. Edge1 at OUT3, Edge2 at OUT3, and Edge3 at OUT3 represent the signals separated from the third-stage output sub-oscillation signal corresponding to their respective signal edges. Collapse indicates a collapse event. Before a collapse event occurs, the first-stage and second-stage output sub-oscillation signals will not be 1 or 0 for three consecutive rising edges during the three consecutive rising edges of the third-stage output sub-oscillation signal of the three-sided ring oscillator module. Figure 6 As shown, if the first and second stage output sub-oscillators are 1 and 0 three times consecutively during the three consecutive rising edges of the third stage output sub-oscillator signal, the moment when the first and second stage output sub-oscillators are 1 and 0 three times consecutively during the three consecutive rising edges of the third stage output sub-oscillator signal can be determined as the moment when the collapse event Collapse occurs. Before the collapse event Collapse occurs, there is no situation where the first and second stage output sub-oscillators are 1 and 0 three times consecutively during the six consecutive rising edges of the third stage output sub-oscillator signal.

[0072] The control module mainly performs the function of temporarily storing the original bit sequence and sending it to the conversion module as needed, and restarting the oscillation mode of the three-sided ring oscillator module when the detection module detects a crash event, so as to ensure the randomness of the entropy source.

[0073] Figure 7 A schematic diagram illustrating the working state and switching process of the control module according to an embodiment of this application is shown.

[0074] like Figure 7As shown, the control module's states can include states S0 to S6, as follows: State S0 is the idle state, meaning no random number generation is required. State S1 controls the three-sided ring oscillator module to start oscillation mode. State S2 controls the three-sided ring oscillator module to stop oscillation mode. State S3 determines whether the original bit is valid. State S4 stores the valid original bit in memory. State S5 segments the original bit sequence in memory as needed. State S6 sends the segmented original bit sequence to the conversion module. Jumps can occur between states under certain conditions. The jump conditions are as follows: Jump condition 1: The control signal is high. Jump condition 2: A crash event occurs. Jump condition 3: A crash event occurs and the control signal is high. Jump condition 4: The control signal is low and no crash event occurs. Jump condition 5: A valid original bit indicator signal indicates that the original bit is invalid. Jump condition 6: A valid original bit indicator signal indicates that the original bit is valid. Jump condition 7 specifies the input read signal and the number of bits to be read from the conversion module. Jump condition 8 is the default jump.

[0075] According to an embodiment of this application, the conversion module is further configured to convert the original bit sequence into a target random number by means of Gaussian approximation when the Poisson distribution parameter is greater than a preset threshold, and to convert the original bit sequence into a target random number by means of inverse transformation when the Poisson distribution parameter is less than or equal to the preset threshold.

[0076] The transformation module is responsible for converting the generated uniformly distributed original sequence into target random numbers with a Poisson distribution. For cases where the Poisson distribution parameter λ is small, the inverse transformation method can be used. The inverse transformation method is a classic algorithm for generating random numbers conforming to a specific probability distribution. Its core idea is to use the inverse function of the cumulative distribution function of the target distribution to transform the uniformly distributed random numbers. For cases where the Poisson distribution parameter λ is large, the inverse transformation method may be inefficient because it requires multiple iterations to find the target random numbers that meet the conditions, so it is not suitable for this situation. For cases where the Poisson distribution parameter λ is large, the Gaussian approximation method can be used to take advantage of the characteristic that the Poisson distribution approaches a normal distribution when the Poisson distribution parameter is large. By generating Gaussian random numbers and discretizing them, the target random numbers with a Poisson distribution can be generated efficiently. Using a hybrid method to generate Poisson distribution random numbers can meet the needs of different Poisson distribution parameters.

[0077] According to an embodiment of this application, the conversion module is further configured to determine a first uniform random number and a second uniform random number based on the original bit sequence when the Poisson distribution parameter is greater than a preset parameter threshold, convert the first uniform random number and the second uniform random number into a standard normal random number through a normal distribution, and perform a linear transformation on the standard normal random number according to the Poisson distribution parameter and then round it to obtain the target random number.

[0078] When the Poisson distribution parameter is greater than a preset threshold, since the original bit sequence is uniform, a first uniform random number U1 and a second uniform random number U2 can be randomly determined based on the original bit sequence. The first and second uniform random numbers are then converted into standard normal random numbers Z using a normal distribution.

[0079] A linear transformation is performed on the standard normal random number Z based on the Poisson distribution parameters to obtain an intermediate random number Y with mean and variance λ. The intermediate random number Y is then rounded to obtain the target random number X.

[0080] According to an embodiment of this application, the conversion module is further configured to obtain a cumulative distribution table based on the Poisson distribution parameter when the Poisson distribution parameter is less than or equal to a preset parameter threshold, obtain a third uniform random number based on the original bit sequence, and determine a target random number from the cumulative distribution table based on the third uniform random number.

[0081] First, a cumulative distribution table F(k) conforming to the target distribution can be calculated based on the Poisson distribution parameters. The target distribution can be the type of probability distribution that the random numbers ultimately output by the random number generator should follow. The cumulative distribution table can include the possible values ​​of the Poisson distribution and the correspondence between the cumulative probability values ​​at each possible value. A uniformly distributed third uniform random number U3 can be randomly obtained based on the original bit sequence. The third uniform random number U3 can be in the interval (0,1). Based on the third uniform random number U3, the smallest random number k is found in the cumulative distribution table such that the probability distribution F(k) ≥ U3. The smallest random number k is determined as the target random number.

[0082] Figure 8 A flowchart of a random number generation method according to an embodiment of this application is shown.

[0083] like Figure 8 As shown, the method includes operations S810 to S850.

[0084] When operating the S810, the three-sided ring oscillator module is used to start the oscillation mode under the control of the control signal, and the oscillation signal is output in the oscillation mode.

[0085] When operating the S820, the entropy extraction module is used to extract the original bit and the valid indication signal based on the oscillation signal.

[0086] When operating S830, the detection module detects the state of the oscillation signal. If the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal, a collapse signal is output to the control module.

[0087] When operating the S840, the control module outputs a control signal to the three-sided ring oscillator module. In the event of a crash signal, the three-sided ring oscillator module is controlled to restart the oscillation mode. When the valid indication signal indicates that the original bit is valid, the original bit is stored to obtain the original bit sequence.

[0088] When operating the S850, the conversion module is used to convert the original bit sequence into the target random number.

[0089] Operations S810 to S850 can be described in other embodiments of this application, and will not be repeated here.

[0090] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations are not explicitly described in this application. In particular, without departing from the spirit and teachings of this application, the features described in the various embodiments of this application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of this application.

[0091] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A random number generator based on a triangular ring oscillator, characterized in that, include: The three-sided ring oscillator module is configured to activate the oscillation mode under the control of a control signal, and output an oscillation signal in the oscillation mode. An entropy extraction module, connected to the triangular ring oscillator module, is configured to extract the original bit and the valid indication signal based on the oscillation signal. The detection module is connected to the three-sided ring oscillator module and is configured to detect the state of the oscillation signal. If the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal, the detection module outputs a collapse signal to the control module. A control module, connected to the triangular ring oscillator module, the entropy extraction module, and the detection module, is configured to output the control signal to the triangular ring oscillator module, control the triangular ring oscillator module to restart the oscillation mode when the collapse signal is received, and store the original bit to obtain the original bit sequence when the valid indication signal indicates that the original bit is valid. The conversion module, connected to the control module, is configured to convert the original bit sequence into a target random number.

2. The random number generator according to claim 1, characterized in that, The triangular ring oscillator module includes a three-stage inverting unit and a three-stage gate unit; In this configuration, the output of the first-stage inverting unit is connected to the input of the first-stage gate unit, the output of the first-stage gate unit is connected to the input of the second-stage inverting unit, the output of the second-stage inverting unit is connected to the input of the second-stage gate unit, the output of the second-stage gate unit is connected to the input of the third-stage inverting unit, the output of the third-stage inverting unit is connected to the input of the third-stage gate unit, and the output of the third-stage gate unit is connected to the input of the first-stage inverting unit. The first-stage gate unit is configured to output a first-stage output sub-oscillation signal under the action of the control signal; The second-level gate unit is configured to output a second-level output sub-oscillation signal under the action of the control signal; The third-level gate unit is configured to output a third-level output sub-oscillation signal under the action of the control signal.

3. The random number generator according to claim 2, characterized in that, The entropy extraction module includes 2n selectors, n sampling triggers, and an entropy processing unit, where n is a positive even number; In this configuration, the selection terminal of the first selector is connected to the output terminal of the second-stage gate unit, the first input terminal of the first selector is connected to the output terminal of the third-stage gate unit, and the second input terminal of the first selector is connected to a high-level signal. The selection terminal of the (n+1)th selector is connected to a high-level signal, the first input terminal of the (n+1)th selector is connected to the output terminal of the nth selector, and the second input terminal of the (n+1)th selector is connected to a low-level signal. The input of the nth sampling flip-flop is connected to the output of the 2nth selector, the clock terminal of the nth sampling flip-flop is connected to the output of the second-stage gate unit, and the output of the nth sampling flip-flop is connected to the entropy processing unit.

4. The random number generator according to claim 3, characterized in that, The entropy processing unit is configured to determine the original bit based on the parity of the number of sampling triggers that output a low-level signal relative to the total number of sampling triggers among the n sampling triggers.

5. The random number generator according to claim 4, characterized in that, The entropy processing unit is further configured to determine that the valid indication signal characterizes the original bit as valid when the outputs of the first sampling trigger and the nth sampling trigger are both high-level signals, and at least one of the sampling triggers between the first and nth sampling triggers has a low-level signal.

6. The random number generator according to any one of claims 2 to 5, characterized in that, The detection module is further configured to determine the state of the oscillation signal to indicate that a collapse event has occurred in the oscillation signal when the signals corresponding to multiple consecutive rising edges of the first-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are high-level signals and the signals corresponding to multiple consecutive rising edges of the second-stage output sub-oscillation signal and the third-stage output sub-oscillation signal are low-level signals.

7. The random number generator according to any one of claims 1 to 5, characterized in that, The conversion module is further configured to convert the original bit sequence into the target random number using the Gaussian approximation method when the Poisson distribution parameter is greater than a preset threshold, and to convert the original bit sequence into the target random number using the inverse transformation method when the Poisson distribution parameter is less than or equal to the preset threshold.

8. The random number generator according to claim 7, characterized in that, The conversion module is further configured to, when the Poisson distribution parameter is greater than a preset parameter threshold, determine a first uniform random number and a second uniform random number based on the original bit sequence, convert the first uniform random number and the second uniform random number into a standard normal random number through a normal distribution, and then perform a linear transformation on the standard normal random number according to the Poisson distribution parameter and round it to obtain the target random number.

9. The random number generator according to claim 7, characterized in that, The conversion module is further configured to, when the Poisson distribution parameter is less than or equal to a preset parameter threshold, obtain a cumulative distribution table based on the Poisson distribution parameter, obtain a third uniform random number based on the original bit sequence, and determine the target random number from the cumulative distribution table based on the third uniform random number.

10. A method for generating random numbers, characterized in that, include: The three-sided ring oscillator module is used to start the oscillation mode under the control of the control signal, and the oscillation signal is output in the oscillation mode; The entropy extraction module is used to extract the original bit and the valid indication signal based on the oscillation signal; The state of the oscillation signal is detected by the detection module, and if the state of the oscillation signal indicates that a collapse event has occurred in the oscillation signal, a collapse signal is output to the control module. The control module outputs the control signal to the three-sided ring oscillator module. When the crash signal is received, the three-sided ring oscillator module is controlled to restart the oscillation mode. When the valid indication signal indicates that the original bit is valid, the original bit is stored to obtain the original bit sequence. The original bit sequence is converted into a target random number using a conversion module.

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