Reciprocal operation device and processor

Abstract

The present disclosure relates to a reciprocal operation apparatus and a processor. The reciprocal operation apparatus includes a lookup table circuit configured to find out a second operand which is a reciprocal of a first operand from a preset reciprocal operation table according to the first operand, wherein the preset reciprocal operation table includes a plurality of entries, each of which is configured to represent an operand and a reciprocal of the operand.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and more specifically, to a reciprocal arithmetic device and processor. Background Technology

[0002] With the development of large language models and Transformer models, reciprocal operations have become increasingly important in processors, especially artificial intelligence (AI) processors. Current reciprocal operation devices are typically based on... Figure 1 The divider 110' shown can generate the reciprocal 1 / A of operand A by performing a division operation. However, such a reciprocal operation device suffers from drawbacks such as complex circuit structure, large footprint, high power consumption, and long latency, which severely restrict the performance improvement of the processor. Therefore, it is necessary to improve the reciprocal operation device. Summary of the Invention

[0003] One of the purposes of this disclosure is to provide a reciprocal calculation device and processor.

[0004] According to a first aspect of this disclosure, a reciprocal counting apparatus is provided, comprising: A lookup table circuit is configured to look up a second operand, which is the reciprocal of the first operand, from a preset reciprocal operation table based on the first operand. The preset reciprocal operation table includes multiple entries, each of which is configured to represent an operand and its reciprocal.

[0005] In some embodiments, the reciprocal calculation device further includes: A first shift circuit, communicatively connected to the input of the lookup table circuit, is configured to shift the third operand to the right by a first preset number of bits in response to the least significant bit of the third operand being zero, to generate the first operand, wherein the third operand is an even multiple of the first operand, and the first preset number of bits is less than or equal to the number of consecutive least significant bits of the third operand that are zero; and... A second shift circuit is communicatively connected to the output of the lookup table circuit, and the second shift circuit is configured to shift the second operand to the right by the first preset number of bits to generate a fourth operand, wherein the second operand is an even multiple of the fourth operand, and the fourth operand is the reciprocal of the third operand.

[0006] In some embodiments, the least significant bit of the first operand is not zero, and, The preset reciprocal operation table does not include even number entries, wherein even number entries are configured to represent operands that are even numbers and their reciprocals.

[0007] In some embodiments, the first shift circuit includes a shift sub-circuit or includes a plurality of cascaded shift sub-circuits; and / or, The second shift circuit includes a shift sub-circuit or a plurality of shift sub-circuits connected in cascade.

[0008] In some embodiments, in a plurality of cascaded shift sub-circuits, a subsequent shift sub-circuit is configured to shift the operand to the right by a second preset number of bits in response to the least significant bit of the operand generated by the preceding shift sub-circuit being zero, wherein the second preset number of bits is one bit.

[0009] In some embodiments, in a plurality of cascaded shift sub-circuits, the subsequent shift sub-circuit is configured as follows: In response to the fact that the consecutive least significant bits of the operand generated by the preceding shift sub-circuit are greater than or equal to the corresponding second preset number of bits in the subsequent shift sub-circuit, the operand is shifted to the right by the second preset number of bits; and, If the number of consecutive low-order bits of the operand generated by the previous shift sub-circuit is less than the second preset number of bits, the operand is not shifted. In this circuit, the second preset number of bits corresponding to the previous stage shift sub-circuit is twice the second preset number of bits corresponding to the next stage shift sub-circuit.

[0010] In some embodiments, the shift sub-circuit includes a multiplexer, a first input of which is configured to receive a fifth operand, a second input of which is configured to receive the result of shifting the fifth operand to the right by a second preset number of bits, and the multiplexer is configured to select a sixth operand from the operands received at the first and second inputs according to a control signal from the control terminal of the multiplexer, and output the sixth operand through the output terminal of the multiplexer.

[0011] In some embodiments, the shift sub-circuit includes a logic arithmetic unit, wherein a first input terminal of the logic arithmetic unit is configured to receive a fifth operand, a first control terminal of the logic arithmetic unit is configured to receive a control signal, a second input terminal of the logic arithmetic unit is configured to receive the result of shifting the fifth operand to the right by a second preset number of bits, the second control terminal of the logic arithmetic unit is configured to receive the inverted result of the control signal, and the logic arithmetic unit is configured to calculate a sixth operand of the logic arithmetic unit based on the inputs of all control terminals and input terminals, and output the sixth operand through the output terminal of the logic arithmetic unit.

[0012] In some embodiments, the logic unit includes at least one of an AO22 circuit and an AOI22 circuit, and the total number of AOI22 circuits in the reciprocal operation device is even.

[0013] According to a second aspect of this disclosure, a processor is also provided, the processor including a plurality of reciprocal calculation devices, wherein at least some of the reciprocal calculation devices are reciprocal calculation devices as described above.

[0014] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0015] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0016] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 A schematic diagram of a reciprocal calculation device is shown. Figure 2 A schematic diagram of the reciprocal calculation device according to an exemplary embodiment of the present disclosure is shown; Figure 3 A schematic diagram of the reciprocal calculation apparatus according to another exemplary embodiment of the present disclosure is shown; Figure 4 A schematic diagram of the structure of a first shift circuit in a reciprocal arithmetic apparatus according to a specific embodiment of the present disclosure is shown; Figure 5 It shows Figure 4 A schematic diagram of the operational logic in the first shift circuit; Figure 6 A schematic diagram of the structure of the first shift circuit in a reciprocal operation apparatus according to another specific embodiment of the present disclosure is shown; Figure 7 It shows Figure 6 A schematic diagram of the operational logic in the first shift circuit; Figure 8 A schematic diagram of the shift sub-circuit in a reciprocal arithmetic apparatus according to a specific embodiment of the present disclosure is shown; Figure 9 A schematic diagram of the shift sub-circuit in a reciprocal arithmetic apparatus according to another specific embodiment of the present disclosure is shown; Figure 10 A schematic diagram of the shift sub-circuit in a reciprocal arithmetic apparatus according to yet another specific embodiment of the present disclosure is shown; Figure 11A schematic block diagram of a processor according to an exemplary embodiment of the present disclosure is shown.

[0017] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0018] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0019] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0020] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0021] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0022] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0023] This disclosure provides a reciprocal calculation apparatus. In an exemplary embodiment of this disclosure, as... Figure 2As shown, the reciprocal calculation device 100 may include a lookup table circuit 110, which can be configured to look up a second operand A2, which is the reciprocal of the first operand, from a preset reciprocal calculation table based on the first operand A1. The preset reciprocal calculation table may include multiple entries, each of which can be configured to represent an operand and its reciprocal. Specifically, the lookup table circuit 110 can use the received first operand A1 as an index, or generate an index based on the received first operand A1, and use this index as an address to find the data stored at the corresponding address, i.e., the second operand A2, which is the reciprocal of the first operand. Various forms of lookup table circuits, both currently known and those developed in the future, can be used to implement the lookup operation.

[0024] Understandably, the size of the pre-defined reciprocal arithmetic table can be determined based on the value range of the first operand A1. In a specific example, the first operand A1 is 8 bits long, and the second operand A2 is 16 bits long. Accordingly, a pre-defined reciprocal arithmetic table with a width of 16 bits and a depth of 255 (where the reciprocal of 0 does not exist) can be constructed, as shown in Table 1 below. Each entry (occupying one row in Table 1) includes an operand and its reciprocal. In the specific example in Table 1, fixed-point numbers can be used to represent each operand and its reciprocal. In the reciprocal arithmetic device, the hardware design does not need to focus on the position of the decimal point in the fixed-point number; instead, the position of the decimal point in the output second operand can be inferred from the input first operand. However, it is understandable that in other cases, other forms of numbers (such as floating-point numbers) can also be used to represent each operand and its reciprocal. Furthermore, for ease of representation, the numbers in Table 1 are represented in decimal. However, it is understood that the numbers directly processed by the lookup table circuit 110 and the first shift circuit, second shift circuit, etc., in the reciprocal operation device described below can be binary numbers. In some cases, the operands input to the reciprocal operation device can be pre-converted to binary numbers for processing. Additionally, the binary operands output by the reciprocal operation device can be converted to numbers in other bases for subsequent processing.

[0025] First operand A1 <![CDATA[Second operand A2 (2 16 / A1)]]> 1 65536 2 32768 3 21845 4 16384 5 13107 6 10922 7 9362 8 8192 9 7281 10 6553 11 5957 12 5461 13 5041 14 4681 15 4369 16 4096 17 3855 18 3640 19 3449 20 3276 21 3120 22 2978 23 2849 24 2730 25 2621 26 2520 27 2427 28 2340 29 2259 30 2184 31 2114 32 2048 33 1985 34 1927 35 1872 36 1820 37 1771 38 1724 39 1680 40 1638 41 1598 42 1560 43 1524 44 1489 45 1456 46 1424 47 1394 48 1365 49 1337 50 1310 51 1285 52 1260 53 1236 54 1213 55 1191 56 1170 57 1149 58 1129 59 1110 60 1092 61 1074 62 1057 63 1040 64 1024 65 1008 66 992 67 978 68 963 69 949 70 936 71 923 72 910 73 897 74 885 75 873 76 862 77 851 78 840 79 829 80 819 81 809 82 799 83 789 84 780 85 771 86 762 87 753 88 744 89 736 90 728 91 720 92 712 93 704 94 697 95 689 96 682 97 675 98 668 99 661 100 655 101 648 102 642 103 636 104 630 105 624 106 618 107 612 108 606 109 601 110 595 111 590 112 585 113 579 114 574 115 569 116 564 117 560 118 555 119 550 120 546 121 541 122 537 123 532 124 528 125 524 126 520 127 516 128 512 129 508 130 504 131 500 132 496 133 492 134 489 135 485 136 481 137 478 138 474 139 471 140 468 141 464 142 461 143 458 144 455 145 451 146 448 147 445 148 442 149 439 150 436 151 434 152 431 153 428 154 425 155 422 156 420 157 417 158 414 159 412 160 409 161 407 162 404 163 402 164 399 165 397 166 394 167 392 168 390 169 387 170 385 171 383 172 381 173 378 174 376 175 374 176 372 177 370 178 368 179 366 180 364 181 362 182 360 183 358 184 356 185 354 186 352 187 350 188 348 189 346 190 344 191 343 192 341 193 339 194 337 195 336 196 334 197 332 198 330 199 329 200 327 201 326 202 324 203 322 204 321 205 319 206 318 207 316 208 315 209 313 210 312 211 310 212 309 213 307 214 306 215 304 216 303 217 302 218 300 219 299 220 297 221 296 222 295 223 293 224 292 225 291 226 289 227 288 228 287 229 286 230 284 231 283 232 282 233 281 234 280 235 278 236 277 237 276 238 275 239 274 240 273 241 271 242 270 243 269 244 268 245 267 246 266 247 265 248 264 249 263 250 262 251 261 252 260 253 259 254 258 255 257

[0026] In another exemplary embodiment of this disclosure, in order to further reduce the size of the preset reciprocal operation table (i.e., reduce the depth of the preset reciprocal operation table) and simplify the structure of the lookup table circuit 110, such as Figure 3As shown, the reciprocal operation device 100 may further include a first shift circuit 120 and a second shift circuit 130. The first shift circuit 120 is communicatively connected to the input of the lookup table circuit 110, and is configured to shift the third operand A3 to the right by a first preset number of bits N1 in response to the least significant bit of the third operand A3 being zero, to generate a first operand A1, wherein the third operand A3 is an even multiple of the first operand A1, and the first preset number of bits N1 is less than or equal to the number of consecutive least significant bits of the third operand A3 being zero. Furthermore, the second shift circuit 130 is communicatively connected to the output of the lookup table circuit 110, and is configured to shift the second operand A2 to the right by a first preset number of bits N1, to generate a fourth operand A4, wherein the second operand A2 is an even multiple of the fourth operand A4, and the fourth operand A4 is the reciprocal of the third operand A3.

[0027] Specifically, if one or more consecutive least significant bits of the third operand A3 are zero, a shift operation can be used to convert the third operand A3 into the first operand A1, where... N1 is the first preset number of bits to shift the third operand A3 to the right; then, after determining the second operand A2 (i.e., the reciprocal of the first operand) by looking up the table based on the first operand A1, the second operand A2 can be converted into the fourth operand A4 through the same shift operation, where, N1 is the first preset number of bits to shift the second operand A2 to the right. It can be seen that in... In this case, .

[0028] Specifically, when A3 is an unsigned number, shifting the third operand A3 to the right by a first preset number of bits N1 means shifting the third operand A3 to the right by a first preset number of bits N1 and filling the high-order bits of the shifted operand with the value of the original third operand A3. Using this shifting method, the third operand before the shift is an even multiple of the first operand obtained after the shift.

[0029] In some embodiments, to minimize the depth of the preset reciprocal operand table, the least significant bit of the first operand A1 obtained by shifting the third operand A3 is not zero (or the least significant bit of the first operand A1 is one). Accordingly, the preset reciprocal operand table may not include even-numbered entries, where even-numbered entries are configured to represent operands that are even numbers and their reciprocals. That is, the preset reciprocal operand table may only include odd-numbered entries, where odd-numbered entries are configured to represent operands that are odd numbers and their reciprocals, while the reciprocals of even numbers can be obtained through shift operations combined with a lookup table. In this way, the depth of the preset reciprocal operand table can be reduced by nearly half, as shown in Table 2 below.

[0030] First operand A1 <![CDATA[Second operand A2 (2 16 / A1)]]> 1 65536 3 21845 5 13107 7 9362 9 7281 11 5957 13 5041 15 4369 17 3855 19 3449 21 3120 23 2849 25 2621 27 2427 29 2259 31 2114 33 1985 35 1872 37 1771 39 1680 41 1598 43 1524 45 1456 47 1394 49 1337 51 1285 53 1236 55 1191 57 1149 59 1110 61 1074 63 1040 65 1008 67 978 69 949 71 923 73 897 75 873 77 851 79 829 81 809 83 789 85 771 87 753 89 736 91 720 93 704 95 689 97 675 99 661 101 648 103 636 105 624 107 612 109 601 111 590 113 579 115 569 117 560 119 550 121 541 123 532 125 524 127 516 129 508 131 500 133 492 135 485 137 478 139 471 141 464 143 458 145 451 147 445 149 439 151 434 153 428 155 422 157 417 159 412 161 407 163 402 165 397 167 392 169 387 171 383 173 378 175 374 177 370 179 366 181 362 183 358 185 354 187 350 189 346 191 343 193 339 195 336 197 332 199 329 201 326 203 322 205 319 207 316 209 313 211 310 213 307 215 304 217 302 219 299 221 296 223 293 225 291 227 288 229 286 231 283 233 281 235 278 237 276 239 274 241 271 243 269 245 267 247 265 249 263 251 261 253 259 255 257

[0031] For example, when calculating the reciprocal of "6" using the reciprocal operation device, the first shift circuit 120 first determines the result of shifting "6", that is, shifting it one bit to the right to get "3". Then, the lookup table circuit 110 looks up the table to determine the reciprocal of "3" "1 / 3" (represented by the fixed-point number "21845" in Table 2). Finally, the second shift circuit 130 shifts "21845" one bit to the right (for example, by performing a right shift operation based on the binary representation of "21845") to obtain the reciprocal of "6" "1 / 6" (represented by the fixed-point number "10922").

[0032] As described above, in the same reciprocal operation device, the first shift circuit 120 and the second shift circuit 130 can perform the same shift operation on the operands input to them, respectively. Therefore, in some embodiments, the first shift circuit 120 and the second shift circuit 130 can have the same circuit structure. However, in other embodiments, the first shift circuit 120 and the second shift circuit 130 can also be implemented with different circuit structures. Different circuit structures can also be used to perform the same shift operation on the operands, as specifically exemplified below, and are not limited here.

[0033] In some embodiments, such as Figure 4 and Figure 6 As shown, the first shift circuit 120 may include a shift sub-circuit 101 or a plurality of shift sub-circuits 101 cascaded together. In the case of a plurality of shift sub-circuits 101 cascaded together, the input of the subsequent shift sub-circuit 101 may be communicatively connected to the output of the preceding shift sub-circuit 101, so that the operand output by the preceding shift sub-circuit 101 is used as the operand input to the subsequent shift sub-circuit 101.

[0034] Similarly, the second shift circuit 130 may include a shift sub-circuit or a plurality of shift sub-circuits cascaded together. In the case of a plurality of shift sub-circuits cascaded together, the input of the subsequent shift sub-circuit may be communicatively connected to the output of the preceding shift sub-circuit, so that the operand output by the preceding shift sub-circuit is used as the operand input by the subsequent shift sub-circuit.

[0035] In one specific embodiment, such as Figure 4 As shown, the first shift circuit 120 may include a plurality of cascaded shift sub-circuits 101. A subsequent shift sub-circuit 101 may be configured to shift the operand to the right by a second preset number of bits in response to the least significant bit of the operand generated by the preceding shift sub-circuit 101 being zero. That is, each shift sub-circuit 101 in the first shift circuit 120 may be configured to shift its received operand to the right by at most one bit. Accordingly, the number of shift sub-circuits 101 included in the first shift circuit 120 is at least the maximum possible number of consecutive least significant bits of the third operand A3 that are zero. For example, if the third operand A3, which is non-zero, has 8 bits, and there are no other restrictions on the range of values ​​for the third operand A3, the number of shift sub-circuits 101 included in the first shift circuit 120 may be 7. Depending on the value of the least significant bit of the operand received by the shift sub-circuit 101, the shift sub-circuit 101 may not shift the operand, or may shift the operand one bit to the right at most. Figure 4 The operational logic in the first shift circuit 120 can be as follows: Figure 5 As shown, each shift subcircuit 101 can be configured to execute one loop, so the seven shift subcircuits 101 can execute a total of seven loops. In each loop, if the least significant bit A[0] of the operand A received by the corresponding shift subcircuit 101 is zero, then the shift subcircuit 101 shifts the operand A one bit to the right; otherwise, the shift subcircuit 101 does not shift the operand A, that is, it keeps the operand A unchanged. Each shift subcircuit 101 can transmit its generated operand to the next shift subcircuit 101 for further processing, until all loops are completed. It can be understood that as the number of bits of the third operand A3 increases, the number of shift subcircuits 101 contained in the first shift circuit 120 also increases accordingly.

[0036] In another specific embodiment, in order to further reduce the number of shift sub-circuits 101 required to be included in the first shift circuit 120, such as Figure 6As shown, the first shift circuit 120 may include a plurality of cascaded shift sub-circuits 101. A subsequent shift sub-circuit 101 may be configured to: shift the operand to the right by a second preset number of bits in response to the operand generated by the preceding shift sub-circuit 101 having consecutive low-order bits of zero value greater than or equal to the corresponding second preset number of bits in the subsequent shift sub-circuit 101; and not shift the operand in response to the operand generated by the preceding shift sub-circuit 101 having consecutive low-order bits of zero value less than the second preset number of bits. The second preset number of bits in response to the preceding shift sub-circuit 101 can be twice the second preset number of bits in response to the subsequent shift sub-circuit 101. In other words, in the first shift circuit 120, the maximum possible number of bits that each shift sub-circuit 101 can shift are different from each other. Specifically, the second preset number of bits in response to the preceding shift sub-circuit 101 can be twice the second preset number of bits in response to the subsequent shift sub-circuit 101, to ensure that the third operand A3 with various values ​​can be shifted as desired. In a specific example, when the third operand A3, which has a non-zero value, has 8 bits and there are no other restrictions on the range of values ​​of the third operand A3, the number of shift sub-circuits 101 included in the first shift circuit 120 can be 3. The first-level shift sub-circuit 101 can be configured to shift the received operand four bits to the right or not shift the operand at all. The middle-level shift sub-circuit 101 can be configured to shift the received operand two bits to the right or not shift the operand at all. The last-level shift sub-circuit 101 can be configured to shift the received operand one bit to the right or not shift the operand at all. Figure 6 The operational logic in the first shift circuit 120 shown can be as follows: Figure 7As shown. Specifically, when the lowest four bits of operand A0 received by the first-level shift sub-circuit 101 are all zero (i.e., A0[3:0]=0), the first-level shift sub-circuit 101 shifts operand A0 four bits to the right; otherwise, it does not shift operand A0, meaning operand A0 remains unchanged. Then, the intermediate-level shift sub-circuit 101 receives the operand generated by the first-level shift sub-circuit 101. When the lowest two bits of operand A1 received by the intermediate-level shift sub-circuit 101 are all zero (i.e., A1[1:0]=0),... Next, the intermediate shift sub-circuit 101 shifts the operand A1 two bits to the right; otherwise, it does not shift the operand A1, meaning the operand A1 remains unchanged. Then, the final shift sub-circuit 101 receives the operand generated by the intermediate shift sub-circuit 101. If the least significant bit of the operand A2 received by the final shift sub-circuit 101 is zero (i.e., A2[0]=0), the final shift sub-circuit 101 shifts the operand A2 one bit to the right; otherwise, it does not shift the operand A2, meaning the operand A2 remains unchanged. It can be understood that as the number of bits in the third operand A3 increases, the number of shift sub-circuits 101 contained in the first shift circuit 120 also increases accordingly. However, compared to the case where each shift sub-circuit 101 can only shift one bit at most, by setting multiple shift sub-circuits 101 that can shift a maximum of different numbers of bits, the increase in the number of shift sub-circuits 101 in the first shift circuit 120 is significantly reduced.

[0037] Similarly, the second shift circuit 130 can be adopted as follows: Figure 4 or Figure 6 The circuit structure shown can be used, or other shift circuit structures can be employed. Furthermore, as the number of bits in the third operand A3 increases, the number of shift sub-circuits 101 included in the second shift circuit 130 can be increased accordingly, as detailed above regarding the first shift circuit 120, and will not be repeated here.

[0038] In some embodiments, such as Figure 8 As shown, the shift sub-circuit 101 may include a multiplexer (MUX) 102. The first input of the multiplexer 102 can be configured to receive a fifth operand (IN1), and the second input can be configured to receive the result of shifting the fifth operand to the right by a second preset number of bits (IN2). The multiplexer can also be configured to select a sixth operand (O) from the operands (IN1 and IN2) received from the first and second inputs according to a control signal (C) from its control terminal, and output the sixth operand (O) through its output terminal. In other words, the multiplexer can be configured to achieve the following: Figure 5 or Figure 7In each judgment and corresponding selection shown, the control signal (C) can be generated based on the value of the lower bit of the second preset number of the fifth operand (IN1) received by the multiplexer. When the lower bit of the second preset number of the fifth operand (IN1) is zero, the multiplexer 102 can choose to output the result of shifting the fifth operand to the right by the second preset number of bits (IN2) as the sixth operand (O). Otherwise, the multiplexer 102 can choose to output the fifth operand (IN1) itself as the sixth operand (O).

[0039] In other embodiments, such as Figure 9 and Figure 10 As shown, the shift sub-circuit 101 may include a logic unit. The first input terminal of the logic unit may be configured to receive a fifth operand (IN00), the first control terminal of the logic unit may be configured to receive a control signal (IN01), the second input terminal of the logic unit may be configured to receive the result of shifting the fifth operand to the right by a second preset number of bits (IN10), the second control terminal of the logic unit may be configured to receive the inverted result of the control signal (IN11), and the logic unit may be configured to calculate the sixth operand (O) of the logic unit based on the inputs (IN00, IN01, IN10 and IN11) of all control terminals and input terminals, and output the sixth operand (O) through the output terminal of the logic unit.

[0040] In some specific examples, such as Figure 9 As shown, the logic unit may include an AO22 circuit 103, which can be configured to perform operations. ,in," " represents the AND operation, and "+" represents the OR operation. Or, in other specific examples, such as Figure 10 As shown, the logic unit may include an AOI22 circuit 104, which can be configured to perform operations. ,in," "+" represents AND operation, "~" represents OR operation, and "~" represents NOT operation. Similar to multiplexer 102, the logic unit can select the desired shift operation result based on the corresponding control signal. The control signal (IN01) is generated based on the value of the lower bits of the second preset number of the fifth operand (IN00) received by the logic unit. When the lower bits of the second preset number of the fifth operand (IN00) are all zero, the result of the logic unit's operation can be either shifting the fifth operand to the right by the second preset number of bits or... This is the inversion of the result of shifting the fifth operand to the right by a second preset number of bits; otherwise, the result of the logic unit operation can be either the fifth operand (IN00) or the inversion of the fifth operand (IN00). Furthermore, to ensure the correctness of the final calculation result, the total number of AOI22 circuits in the reciprocal operation device can be even. For example, the number of AOI22 circuits in the first shift circuit 120 and the second shift circuit 130 can each be even, or the total number of AOI22 circuits in the first shift circuit 120 and the second shift circuit 130 can be even.

[0041] According to another aspect of this disclosure, a processor, such as Figure 11 As shown, the processor 200 may include a plurality of reciprocal calculation devices 100, wherein at least some of the reciprocal calculation devices 100 may be the reciprocal calculation devices 100 described above. The processor 200 in this embodiment may be an AI processor, for example, used to train large language models, Transformer models, etc., or used to perform calculations related to large language models, Transformer models, etc., or it may be a neural network processor. Alternatively, the processor 200 in this embodiment may also be a central processing unit, coprocessor, digital signal processor, dedicated instruction processor, or other types of processors.

[0042] The processor 200 can perform various actions and processes according to instructions stored in the memory. Specifically, the processor 200 can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor, and can be an x86 architecture or an ARM architecture, etc.

[0043] In the technical solution of this disclosure, the reciprocal operation is implemented by setting a lookup table circuit, which helps to simplify the structure of the reciprocal operation device, reduce its footprint, reduce power consumption, and improve latency. Furthermore, in at least some embodiments, the reciprocal operation device may also include a shift circuit. By combining shift operations with a lookup table, the depth of the preset reciprocal operation table that the lookup table circuit needs to call can be further reduced, thereby helping to simplify the structure or computational complexity of the lookup table circuit and further improving the performance of the reciprocal operation device. Accordingly, a processor incorporating the reciprocal operation device of this disclosure can have more efficient computing power.

[0044] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0045] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0046] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0047] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0048] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0049] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0050] Additionally, when used in this disclosure, the terms “here,” “above,” “below,” “below,” “in the preceding text,” and similar terms should refer to the entirety of this disclosure and not any particular part thereof. Furthermore, unless expressly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as “may,” “possibly,” “for example,” “like,” etc., is generally intended to express that certain embodiments include, while other embodiments do not, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0051] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, and therefore "providing an object" includes, but is not limited to, "purchasing," "preparing / manufacturing," "arranging / setting up," "installing / assembling," and / or "ordering" an object. Furthermore, in this disclosure, the terms "circuit," "unit," and "module" are used interchangeably.

[0052] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0053] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in various different ways.

[0054] The various embodiments of this disclosure can be described in a progressive manner, with references made to similar or identical parts between embodiments. Each embodiment focuses on describing the differences from other embodiments. In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0055] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A reciprocal calculation device, characterized in that, The reciprocal calculation device includes: A lookup table circuit is configured to look up a second operand, which is the reciprocal of the first operand, from a preset reciprocal operation table based on a first operand, wherein the preset reciprocal operation table includes multiple entries, each entry being configured to represent an operand and its reciprocal; A first shift circuit, communicatively connected to the input of the lookup table circuit, is configured to shift the third operand to the right by a first preset number of bits in response to the least significant bit of the third operand being zero, to generate the first operand, wherein the third operand is an even multiple of the first operand, and the first preset number of bits is less than or equal to the number of consecutive least significant bits of the third operand that are zero; and A second shift circuit is communicatively connected to the output of the lookup table circuit, and the second shift circuit is configured to shift the second operand to the right by the first preset number of bits to generate a fourth operand, wherein the second operand is an even multiple of the fourth operand, and the fourth operand is the reciprocal of the third operand.

2. The reciprocal calculation device according to claim 1, characterized in that, The least significant bit of the first operand is not zero, and The preset reciprocal operation table does not include even number entries, wherein even number entries are configured to represent operands that are even numbers and their reciprocals.

3. The reciprocal calculation device according to claim 1, characterized in that, The first shift circuit includes a shift sub-circuit or a plurality of shift sub-circuits cascaded together; and / or The second shift circuit includes a shift sub-circuit or a plurality of shift sub-circuits connected in cascade.

4. The reciprocal calculation device according to claim 3, characterized in that, In a series of cascaded shift sub-circuits, the subsequent shift sub-circuit is configured to shift the operand to the right by a second preset number of bits in response to the least significant bit of the operand generated by the preceding shift sub-circuit being zero. The second preset number of bits is one bit.

5. The reciprocal counting device according to claim 3, characterized in that, In a cascaded series of shift sub-circuits, the subsequent shift sub-circuit is configured as follows: In response to the fact that the number of consecutive low bits of the operand generated by the previous shift sub-circuit is greater than or equal to the corresponding second preset number of bits of the subsequent shift sub-circuit, the operand is shifted to the right by the second preset number of bits. as well as If the number of consecutive low-order bits of the operand generated by the previous shift sub-circuit is less than the second preset number of bits, the operand is not shifted. In this circuit, the second preset number of bits corresponding to the previous stage shift sub-circuit is twice the second preset number of bits corresponding to the next stage shift sub-circuit.

6. The reciprocal counting device according to claim 3, characterized in that, The shift sub-circuit includes a multiplexer, a first input of which is configured to receive a fifth operand, a second input of which is configured to receive the result of shifting the fifth operand to the right by a second preset number of bits, and the multiplexer is configured to select a sixth operand from the operands received from the first and second inputs according to a control signal from the control terminal of the multiplexer, and output the sixth operand through the output terminal of the multiplexer.

7. The reciprocal calculation device according to claim 3, characterized in that, The shift sub-circuit includes a logic arithmetic unit. The first input terminal of the logic arithmetic unit is configured to receive a fifth operand. The first control terminal of the logic arithmetic unit is configured to receive a control signal. The second input terminal of the logic arithmetic unit is configured to receive the result of shifting the fifth operand to the right by a second preset number of bits. The second control terminal of the logic arithmetic unit is configured to receive the inverted result of the control signal. The logic arithmetic unit is configured to calculate a sixth operand based on the inputs of all control terminals and input terminals, and output the sixth operand through the output terminal of the logic arithmetic unit.

8. The reciprocal calculation device according to claim 7, characterized in that, The logic unit includes at least one of AO22 circuit and AOI22 circuit, and the total number of AOI22 circuits in the reciprocal operation device is even.

9. A processor, characterized in that, The processor includes a plurality of reciprocal calculation devices, wherein at least some of the reciprocal calculation devices are reciprocal calculation devices according to any one of claims 1 to 8.

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