Techniques for mitigating voltage droop and current spikes using a distributed throttling architecture

Abstract

This disclosure relates to techniques for mitigating voltage droops and current spikes using a distributed throttling architecture. These examples include using circuitry distributed to portions of an instruction execution pipeline circuit that can be arranged to perform one or more pipeline stages at a processor core, the circuitry to cause a throttling indication to be sent to the portions of the instruction execution pipeline circuit based on received information indicating energy events at the portions of the instruction execution pipeline circuit over a period of time.

Description

Technical Field

[0001] The examples described in this article generally involve techniques associated with distributed throttle circuitry, which are used to detect and mitigate potential voltage supply drops and current spikes in different parts of the processor core. Background Technology

[0002] Wide out-of-order computing or processor cores (“wide cores”) can have a large number of decoding clusters, multiple execution units, and other types of instruction execution pipeline circuitry, allowing these types of cores to execute more instructions per clock cycle. Wide cores may require high memory bandwidth to feed data to the multiple execution units included in the instruction execution pipeline circuitry. Due to the large number of decoding clusters, multiple execution units, and other types of instruction execution pipeline circuitry, these wide cores may consume a significant amount of current in multiple different physical regions.

[0003] Based on some examples, when a wide core switches from an idle power state or low load power state to a high load power state / peak activity state, it draws a large amount of current across a wide range of locations or physical areas of the wide core's instruction execution pipeline circuitry within a very short time. Due to impedance changes on the wide core, this sudden current draw can produce localized voltage drops with different time constants in different parts of the wide core's power delivery network. The impedance changes depend on the structure of the power delivery network, which can be modeled as an impedance, and the number and location of capacitors placed within that network. For example, a localized fast effect in the decoder cluster, execution unit, or memory included in the wide core's instruction execution pipeline circuitry can be represented as a first voltage drop. This first voltage drop is typically a relatively short time constant, approximately 3–5 nanoseconds (ns). Once the first layer of capacitors in the power delivery network is depleted, the first voltage drop can eventually produce a second voltage drop over a larger area of ​​the wide core's instruction execution pipeline circuitry. This second voltage drop has a longer time constant, approximately 20–40 ns. Prolonged high-power operation of the instruction execution pipeline in a wide-core architecture can eventually deplete the larger capacitors in the next layer of the power delivery network, potentially causing a global voltage drop across all regions of the instruction execution pipeline. This global voltage drop can be referred to as a third voltage drop. The third voltage drop can have a time constant of approximately 180-200 ns, much longer than the first or second voltage drop. These three different voltage drops can depend on the resonant frequency mode of the power delivery network, and also on the resistance (R), inductance (L), or capacitance (C) of the power delivery network. Therefore, the first, second, and third voltage drops have corresponding time constants, which can vary widely depending on the core intellectual property (IP), process technology type, and implementation method. Summary of the Invention

[0004] According to one aspect of this application, an apparatus is provided, comprising: one or more control registers configured to maintain a first threshold and a second threshold; and circuitry located at or adjacent to a portion of an instruction execution pipeline circuitry configured to execute one or more pipeline stages at a processor core, the circuitry being configured to: receive information indicating that an energy event has occurred at the portion of the instruction execution pipeline circuitry; generate a weighted event value for the energy event and add the weighted event value to one or more weighted event values ​​generated within a first time period to generate a weighted event sum; determine a moving average based on the weighted event sum; compare the moving average with the first threshold; and if the moving average is greater than the first threshold, send a throttling instruction to the portion of the instruction execution pipeline circuitry.

[0005] According to another aspect of this application, a method is provided, comprising: receiving at a circuit indicating that an energy event has occurred at a portion of an instruction execution pipeline circuit, the circuit being located at or adjacent to the portion of the instruction execution pipeline circuit, the instruction execution pipeline circuit being configured to execute one or more pipeline stages at a processor core; generating a weighted event value for the energy event; adding the weighted event value to one or more weighted event values ​​generated within a first time period to generate a weighted event sum; determining a moving average based on the weighted event sum; comparing the moving average with the first threshold; and if the moving average is greater than the first threshold, sending a throttling instruction to the portion of the instruction execution pipeline circuit.

[0006] According to another aspect of this application, a system is provided, comprising: an instruction execution pipeline circuit capable of being arranged to execute one or more pipeline stages at a processor core; and a global throttling device coupled to a plurality of portions of the instruction execution pipeline circuit, the global throttling device including circuitry configured to: receive information indicating a weighted event sum, the weighted event sum being based on energy events occurring at a first portion of the plurality of portions of the instruction execution pipeline circuit; add the weighted event sum to one or more weighted event sums received within a first time period to aggregate the weighted event sum; determine a moving average based on the aggregated weighted event sum; compare the moving average with the first threshold; and if the moving average is greater than the first threshold, send a throttling instruction to the plurality of portions of the instruction execution pipeline circuit. Attached Figure Description

[0007] Figure 1 The diagram illustrates an example system with a distributed throttling architecture.

[0008] Figure 2 The illustration shows an example scenario of voltage drop.

[0009] Figure 3 The diagram illustrates an example table of mitigation actions used to alleviate voltage drops and current spikes.

[0010] Figure 4 The diagram illustrates an example of local detection and throttling circuitry in a distributed throttling architecture.

[0011] Figure 5 The illustration shows an example of exponentially weighted moving average (EWMA) logic included in a local detection and throttling circuit.

[0012] Figure 6 The illustration shows an example of local throttling logic included in a local detection and throttling circuit.

[0013] Figure 7 The diagram illustrates an example global throttling mechanism within a distributed throttling architecture.

[0014] Figure 8 The first example logic flow is illustrated.

[0015] Figure 9 The second example logic flow is illustrated.

[0016] Figure 10 The example computing system is illustrated.

[0017] Figure 11 The diagram illustrates a block diagram of an example processor and / or system-on-a-chip (SoC), which may have one or more cores and an integrated memory controller.

[0018] Figure 12 The block diagram illustrates a computing system configured to implement one or more aspects of the examples described herein.

[0019] Figure 13A An example of a parallel processor is illustrated.

[0020] Figure 13B An example of a block diagram of a partition unit is shown.

[0021] Figure 13C An example block diagram of a processing cluster within a parallel processing unit is shown.

[0022] Figure 13D An example of a graphics multiprocessor is illustrated, in which the graphics multiprocessor is coupled to a pipeline manager of a processing cluster.

[0023] Figures 14A-14C The illustration shows the additional graphics multiprocessor based on the example.

[0024] Figure 15 Parallel computing systems are shown based on some examples.

[0025] Figures 16A-16B The illustration shows a hybrid logic / physical view of a decomposed parallel processor based on the example described herein.

[0026] Figure 17A The block diagram illustrates both the example ordered pipeline and the example register renaming, out-of-order issue / execution pipeline, based on the example.

[0027] Figure 17B The block diagram illustrates, based on the example, both the example ordered architecture core and the example register renaming, out-of-order issue / execution architecture core to be included in the processor.

[0028] Figure 18 Examples of one or more execution unit circuits are illustrated.

[0029] Figure 19 It is a block diagram of a register architecture based on some examples.

[0030] Figure 20 An example of the instruction format is shown in the diagram.

[0031] Figure 21 The illustration shows an example of an addressing information field.

[0032] Figures 22(A)-22(B) An example of the first prefix is ​​illustrated.

[0033] Figures 23(A)-23(D) The illustration shows an example of how to use the R, X, and B fields with the first prefix.

[0034] Figures 24A-24B An example of the second prefix is ​​illustrated.

[0035] Figure 25 An example of the third prefix is ​​illustrated.

[0036] Figures 26A-26B The illustration shows the thread execution logic of an array of processing elements employed in a graphics processor core, as described in the example herein.

[0037] Figure 27 The diagram illustrates an additional execution unit based on an example.

[0038] Figure 28 The block diagram illustrates the graphics processor instruction format according to some examples.

[0039] Figure 29 This is a block diagram of another example of a graphics processor.

[0040] Figure 30A The block diagram illustrates the graphics processor command format according to some examples.

[0041] Figure 30B The block diagram illustrates a sequence of graphics processor commands based on an example.

[0042] Figure 31 The block diagram illustrates the use of a software instruction converter, as shown in the example, for converting binary instructions in a source ISA into binary instructions in a target ISA.

[0043] Figure 32 The block diagram illustrates an IP core development system based on some examples, which can be used to manufacture integrated circuits to perform operations. Detailed Implementation

[0044] Based on some examples, pre-mitigating first, second, or third voltage drops can allow for the appropriate scaling of each stage of the power delivery network for a given wide-core IP or a set of wide-core IPs to reduce cost and improve performance. Pre-mitigation may be particularly important as the proportion of transistors that are typically toggling in various modern wide-core IPs continues to decline (with gray silicon area increasing with Moore's law). This lower proportion of transistor toggling puts additional stress on the power delivery network to deliver increasingly higher peak current capabilities for a given typical current.

[0045] Based on some examples, the goal of preemptively mitigating the first, second, and third voltage drops or current spikes in a wide-core IP can include reducing or minimizing the peak current at each relevant time constant for a given typical current consumption of the corresponding wide-core IP of the processor. In modern CPUs that include wide-core IP, the instruction pipeline to be executed by pipeline circuitry typically includes 20 or more pipeline stages. These modern CPUs with wide-core IP can utilize digital mechanisms that associate energy with counters placed across pipeline stages and focus on throttling the scheduler to mitigate the first, second, and third voltage drops. Focusing on throttling only the scheduler can be reactive rather than preemptive, because this type of throttling mechanism reacts to energy consumed in the past. Therefore, the time required to create a throttling signal for the instruction execution pipeline circuitry may mean that mitigating throttling may be delayed by several cycles. Furthermore, because the buffer sizes in various parts of the instruction execution pipeline are large, throttling only the scheduler cannot throttle the activity in many parts of the wide-core instruction execution pipeline. This forces the throttler to react very abruptly to adequately reduce the load at the scheduler, thereby adequately mitigating current spikes and voltage drops in all or at least part of the instruction execution pipeline.

[0046] As described in this disclosure, techniques for preemptively mitigating voltage drops and current spikes can be implemented by inserting local detection and throttling circuitry, including counters, at the head of at least some critical sections of the instruction execution pipeline circuitry in a wide-core processor. This detection and throttling circuitry, cooperating with a global throttling mechanism, can be part of a distributed throttling architecture for a wide-core IP of a processor (e.g., for a central processing unit (CPU) or a graphics processing unit (GPU)). The distributed throttling architecture can attempt to predict or anticipate future current / power loads at at least a portion of some critical sections of the instruction execution pipeline circuitry in a given wide-core IP, rather than reacting to past current / power loads. Anticipating or predicting future current / power loads allows for control of the current through the power delivery network in response to relatively short time constants of voltage drops or current spikes, and this can allow for a reaction / mitigation before the first voltage drop occurs.

[0047] According to this disclosure, a significant difference compared to previous methods that attempted to throttle only the scheduler by reacting to past current / power loads at current protectors is the use of a distributed throttling architecture capable of anticipating or predicting future current / power loads in at least a portion of a wide-core instruction execution pipeline. In contrast, the techniques used in this disclosure for employing a distributed throttling architecture can induce throttling at critical buffers or other parts of the instruction execution pipeline, thereby desynchronizing each region of the instruction execution pipeline and the corresponding energy associated with events representing future activity. For example, when an instruction is sent in a systolic pipeline, the energy required for that instruction to travel along the next six stages of that systolic pipeline can be considered in the first cycle. Therefore, by the time a throttling signal can be determined, the effects of the energy to be sent along the six stages of the systolic pipeline have not yet occurred. By having distributed throttling points, at least some portions of the instruction execution pipeline can be throttled individually when needed. Therefore, relatively less aggressive throttling can be achieved to mitigate current spikes and voltage drops. In summary, distributed throttling architecture allows for proactive control of current / power consumption at distributed locations within the instruction execution pipeline circuitry of wide cores, while minimizing performance impact when attempting to mitigate anticipated or predicted current spikes or voltage drops.

[0048] Figure 1 The illustration shows an example system 100. In some examples, system 100 can be used in a distributed throttling architecture implemented at core 101, cooperating with an associated global throttler 140. For example, core 101 can be configured as a wide-core IP implemented in a wide out-of-order processor. For these examples, such as... Figure 1As shown, core 101 may include a branch prediction unit 112, an instruction cache 114, a decoding cluster 116, or an instruction decoding queue 118, as part of the front end 110 of the instruction execution pipeline circuit. Furthermore, core 101 may also include an out-of-order unit 122, an integer execution cluster 124, or a vector execution cluster 126, as part of the execution engine 120 of the instruction execution pipeline circuit. Additionally, core 101 may include an L0 cache 132, an L1 cache 134, or an L2 cache 136, as part of the memory subsystem 130 of the instruction execution pipeline circuit.

[0049] Based on some examples, as described in more detail below, the local (loc.) detection (det.) and throttling (thrtl.) circuitry 102 can be distributed or instantiated in different parts of the instruction execution pipeline circuitry of core 101. For example, as... Figure 1 As shown, the local detection and throttling circuits 102-1 to 102-8 can be located at or together with the following items: branch prediction unit 112, instruction decoding queue 118, out-of-order unit 122, integer execution cluster 124, vector execution cluster 126, L0 cache 132, L1 cache 134, and L2 cache 136. For Figure 1As illustrated, these locations within the instruction execution pipeline circuitry of core 101, which have local detection and throttling circuits 102, can be associated with pulsating portions of the pipeline to be executed by the instruction execution pipeline circuitry of core 101, which can be paused or throttled. Aggregation of energy events can occur individually at local detection and throttling circuits 102-1, 102-2, 102-3, 102-4, 102-5, 102-6, 102-7, or 102-8. The aggregation of energy events can be used by logic and / or functions individually located at each local detection and throttling circuit 102 to anticipate or predict future or subsequent high-energy activity in the instruction execution pipeline circuitry of core 101 via the portion where the local detection and throttling circuit 102 is located. To mitigate voltage drops and / or current spikes caused by predicted or anticipated high-energy activity, the logic and / or functions of local detection and throttling circuit 102 can throttle or pause execution / dispatch of the portion of the instruction execution pipeline circuitry from core 101 where that particular local detection and throttling circuit 102 is located. For example, local detection and throttling circuit 102-1 at branch prediction unit 112 can throttle or pause execution / dispatch from branch prediction unit 112 to instruction cache 114 based on predicted or anticipated high-energy activity (which could cause a first voltage drop at branch prediction unit 112 with a relatively short time constant of 3-5 ns). This pre-pause before the high-energy activity that could cause the first voltage drop at branch prediction unit 112 can reduce or minimize the first voltage drop and any associated current spikes.

[0050] In some examples, as described above, system 100 can be used in a distributed throttling architecture implemented at the instruction execution pipeline circuitry of core 101, in cooperation with the associated global throttler 140. For these examples, such as... Figure 1As shown, individual weighted event sums (WES) 103-1 to 103-8 from the respective local detection and throttling circuits 102-1, 102-2, 102-3, 102-4, 102-5, 102-6, 102-7, or 102-8 can be sent to the global throttling unit 140. For these examples, the weighted event sum from each local detection and throttling circuit 102 can be an aggregated value generated by each local detection and throttling circuit 102, and those aggregated values ​​included in WES 103-1 to 103-8 can be further aggregated by the global event aggregator circuit 142 at the global throttling unit 140. The global event aggregator circuit 142 can provide the aggregated values ​​based on WES 103-1 to 103-8 to the logic and / or functions of both the short-window throttling circuit 144 and the long-window throttling circuit 146. As described in more detail below, the short-window throttling circuit 144 can be configured to send a global throttling signal 143 and a global throttling ratio signal 145 to the respective local detection and throttling circuits 102 at core 101 to facilitate mitigation of the second voltage drop and the associated current spike in the power transmission network of core 101 in response to the second voltage drop. Furthermore, as described in more detail below, the long-window throttling circuit 146 can be configured to send a global throttling signal 147 and a global throttling ratio signal 149 to the respective local detection and throttling circuits 102 at core 101 to facilitate mitigation of the third voltage drop and the associated current spike in the power transmission network of core 101 in response to the third voltage drop. The second voltage drop can have a time constant of approximately 20-40 ns, and the third voltage drop can have a time constant of approximately 180-200 ns. Therefore, the time window for the short-window throttling circuit 144 to predict or anticipate the second voltage drop is a relatively short window, while the time window for the long-window throttling circuit 146 to predict or anticipate the third voltage drop is a relatively long window.

[0051] Figure 2 The illustration depicts example scenario 200. Based on some examples, such as... Figure 2As shown, scenario 200 illustrates the relative timing of three voltage drops 210, 220, and 230 associated with high-energy activity that could affect the power delivery network of a wide-core such as core 101. For these examples, the first voltage drop 210 could respond to a sudden current draw in core 101 within a relatively fast time constant of approximately 3-5 ns, caused, for example, by a switch from an idle or low-power state to a high-load power state / peak activity. This switch could affect at least some portions of the instruction execution pipeline circuitry of core 101, such as branch prediction unit 112, instruction decoding queue 118, out-of-order unit 122, integer execution cluster 124, vector execution cluster 126, L0 cache 132, L1 cache 134, or L2 cache 136. As described above, the local detection and throttling circuitry 102 located in these portions of the instruction execution pipeline circuitry of core 101 attempts to anticipate or predict voltage drops, such as a first voltage drop 210, to mitigate potential impacts on the power delivery network of at least these portions of the instruction execution pipeline circuitry of core 101. Furthermore, a second voltage drop 220 follows the first voltage drop 210 with a time constant of approximately 40 ns, and then a third voltage drop 230 follows the second voltage drop with a time constant of approximately 200 ns. The second and third voltage drops may have a global impact on the instruction execution pipeline circuitry of core 101. Also as described above, a global throttling device, such as a global throttling device 140, can work in conjunction with the distributed local detection and throttling circuitry 102 to anticipate or predict subsequent voltage drops, such as the second voltage drop 220 or the third voltage drop 230, to mitigate potential impacts on the global power delivery network of core 101.

[0052] The first voltage drop 210, the second voltage drop 220, and the third voltage drop 230 can depend on the resonant frequency mode of the power transmission network of core 101, and can also depend on the resistance (R), inductance (L), or capacitance (C) of the power transmission network. Therefore, the examples are not limited to those described above. Figure 2 As shown in the diagram and the descent time mentioned above for scenario 200.

[0053] Figure 3Example table 300 is illustrated. According to some examples, table 300 includes mitigation actions to mitigate voltage drops and current spikes at various points in the instruction execution pipeline circuitry of core 101, which may include local detection and throttling circuitry 102. For example, throttling or pausing caused by local detection and throttling circuitry 102-1 at branch prediction unit 112 can throttle / pause dispatches from branch prediction unit 112 to instruction cache 114. Throttling or pausing caused by local detection and throttling circuitry 102-2 at instruction decoding queue 118 can throttle / pause dispatches from instruction decoding queue 118 to out-of-order unit 122. Throttling or pausing caused by local detection and throttling circuitry 102-3 at out-of-order unit 122 can throttle / pause out-of-order assignments to integer execution cluster 124 or vector execution cluster 126. Throttling or pausing caused by local detection and throttling circuitry 102-4 at integer execution cluster 124 can throttle / pause integer dispatches to memory subsystem 130. Throttling or pausing caused by local detection and throttling circuitry 102-4 at integer execution cluster 124 can throttle / pause integer dispatches to caches (e.g., L0 cache 132) of memory subsystem 130. Throttling or pausing caused by local detection and throttling circuitry 102-5 at vector execution cluster 126 can throttle / pause vector dispatches to caches (e.g., L0 cache 132) of memory subsystem 130. Throttling or pausing caused by local detection and throttling circuitry 102-6 at L0 cache 132 can throttle / pause load dispatches from L0 cache 132. Throttling or pausing caused by local detection and throttling circuitry 102-7 at L1 cache 134 can throttle / pause load pipeline dispatches from L1 cache 134. The throttling or pause caused by the local detection and throttling circuit 102-8 at L2 cache 136 can throttle / pause the L2 pipeline dispatch from L2 cache 136 or the L2 fill dispatch.

[0054] Figure 4 The illustration shows an example local detection and throttling circuit 102. Based on some examples, such as... Figure 4 As shown, the local detection and throttling circuit 102 may include a local event aggregator 410, a raw accumulator 420, an exponentially weighted moving average (EWMA) logic 430, or a local throttling logic 440. For these examples, Figure 4 The logic and / or functions shown can be configured to detect local energy events at a given portion of the instruction execution pipeline circuitry of core 101 (which may include local detection and throttling circuitry 102), and can cause that given portion of core 101 to throttle / pause its operation to mitigate or avoid the effects that may be caused by a first, second, or third voltage drop.

[0055] Based on some examples, the local event aggregator 410 can detect events 412 including E0 to En, where " n " is any positive integer greater than 1. The local event aggregator 410 can be configured to multiply event 412 by a unique weight included in event weight 414 for each event. For example, W(E0) is the unique weight for event E0. Each unique weight can be associated with a specific impact of the event on the power delivery network of core 101 (which may cause, for example, a first voltage drop). In some examples, once the power delivery network serving core 101 is designed (e.g., before silicon wafer production), the weights can be determined based on a machine learning model trained with simulation data. Event 412 can be specific to a portion of the instruction execution pipeline circuitry of core 101, through which local detection and throttling circuitry 102 can be deployed or located. For example, if it is related to the entire The number execution cluster 124 or the vector execution cluster 126 are located together, and the event 412 can be characterized, at least in part, based on the micro-operations (Uops) to be executed by these parts of the instruction execution pipeline circuitry of core 101 as ultra-high power Uops, medium power Uops, or low power Uops. Ultra-high power Uops can have the highest event weights. Meanwhile, low power Uops can have the lowest event weights. Examples are not limited to events based on the characterized Uops; this disclosure also envisions other types of events that can consume variable power. The aggregated events 412 are multiplied by the event weights 414 to generate event values, which are then summed or added and output as a weighted event sum to the original accumulator 420, and output via WES 103, as described above for... Figure 1 As mentioned, each local detection and throttling circuit 102 included in the instruction execution pipeline circuit of core 101 sends to the global throttling device 140.

[0056] In some examples, the raw accumulator 420 accumulates the aggregated weighted event sum over a time period, which can be based on a programmable period value (e.g., 4 to 64 clock cycles) set by the period program signal 422. This time period should be configured such that the aggregated weighted event sum can be accumulated within a time constant of the first voltage drop (e.g., within 3-5 ns). Based on this programmable period value, the raw accumulator 420 outputs the accumulated aggregated events to the EWMA logic 430.

[0057] According to some examples, EWMA logic 430 can be configured to calculate an exponentially weighted moving average using the sum of aggregated weighted events received from the original accumulator 420. EWMA logic 430 can use a combination of subtractors and shifters to calculate the exponentially weighted moving average. EWMA logic 430 can calculate the exponentially weighted moving average according to example formula (1).

[0058] (1) EWMA n = CurrentRawAccumulatorOutput * α + (1 - α) *EWMA n-1 = EWMA n-1 – (EWMA n-1 – CurrentRawAccumulatorOutput ) * α In example formula (1), the calculation of α (alpha) is implemented as a shifter. For example, ½ shifts right by 1 bit, ¼ shifts right by 2 bits, and so on. The smaller the value of α, the more it assigns... CurrentRawAccumulatorOutput The smaller the weight, the greater the weight assigned to past outputs from the original accumulator 420. Specific examples of α values ​​are 1–1 / 256 (shifted 0–8 bits).

[0059] In some examples, the calculated exponentially weighted moving average is output to local throttling logic 440. The logic and / or function of local throttling logic 440 can be configured to compare the exponentially weighted moving average with thresholds 0 and 1 included in throttling thresholds 444. Threshold 0 can be set to a first value that will be compared with the exponentially weighted moving average. If the exponentially weighted moving average reaches or exceeds the first value, local throttling logic 440 can send a throttling signal 445 to the portion of the instruction execution pipeline circuitry of core 101 where the local detection and throttling circuitry 102 is located or located therewith, to instruct that portion of the instruction execution pipeline circuitry of core 101 to begin throttling. A throttling ratio signal 446 can also be sent, indicating a ratio based on the number of paused clock cycles relative to the total number of clock cycles. For example, the ratio is... m / n ,in m It can be in total n The number of configurable pauses per clock cycle. Threshold 1 can be set to a second value, which is lower than the first value of threshold 0. Therefore, if the subsequent exponentially weighted moving average is lower than the second value of threshold 1, the local throttling logic 440 will stop sending the throttling signal 445 and the throttling ratio signal 446, and that part of the instruction execution pipeline circuitry of core 101 will stop throttling or pause.

[0060] According to some examples, the comparison between the exponentially weighted moving average and the throttling threshold 444 can be overridden by global throttling signals 143 or 147. Global throttling signals 143 or 147 can cause local throttling logic 440 to send a throttling signal 445 and a throttling ratio signal 446 based on global throttling ratio signals 145 or 149. In other words, even if the exponentially weighted moving average is below thresholds 0 and 1, global throttling can still cause global throttling 140 to send throttling signal 445 and throttling ratio signal 446. (As mentioned above regarding...) Figure 1As mentioned, the short-window throttling circuit 144 or long-window throttling circuit 146 of the global throttling unit 140 can be configured to send global throttling signals 143 / 147 and throttling ratio signals 145 / 149 based on the sum of accumulated weighted events received from distributed local detection and throttling circuit 102 within the instruction execution pipeline circuitry of core 101. The throttling ratio signals 145 / 149 can be the same ratio configured for use by the local throttling logic 440 when the exponentially weighted moving average reaches or exceeds a threshold of 0, or they can be different ratios. In other words, the global throttling ratio signals 145 or 149... m / n In the ratio m The configurable values ​​can be the same or different.

[0061] Figure 5 The diagram illustrates an example EWMA logic 430. Based on some examples, such as... Figure 5 As shown, the EWMA logic 430 includes subtractors 510-1 and 510-2, a right shifter 520, a rolling average accumulator 530, and an average EWMA status register 540. (As mentioned above regarding...) Figure 4 As mentioned in the EWMA logic 430 shown, the EWMA logic 430 can be configured to calculate an exponentially weighted moving average using the accumulation aggregation events received from the original accumulator 420. In some examples, such as Figure 5 As shown, these accumulation events can be included in the CurrentRawAccumulatorOutput 501. The accumulation events included in CurrentRawAccumulatorOutput 501 can be used as inputs to calculate the exponentially weighted moving average using subtractor 510-1, right shifter 520, and subtractor 510-2 according to example formula (1). The α configuration signal 503 can set the value of α assigned to the accumulation events included in CurrentRawAccumulatorOutput 501. The rolling average accumulator 530 can accumulate one or more calculated exponentially weighted moving averages (e.g., over a programmable number of clock cycles) and then output the accumulated one or more calculated exponentially weighted moving averages as one or more EWMA outputs 502.

[0062] Figure 6 An example of local throttling logic 440 is illustrated. Based on some examples, such as... Figure 6 As shown, the local throttling logic 440 includes a greater than comparator 610, a less than comparator 620, a throttling unit 630, an AND gate 640, an OR gate 650, a throttling ratio multiplexer (mux) 660, a throttling counter 670, and a throttling dwell 680. As described above regarding... Figure 4As mentioned in the local throttling logic 440, the logic and / or function of throttling logic 440 can be configured to compare the EWMA (e.g., included in one or more EWMA outputs 502 of EWMA logic 430) with a first value of threshold 0 or a second value of threshold 1 to determine whether to send or stop sending the throttling signal 445 and the throttling ratio signal 446. Furthermore, as described above, the global throttling signal 143 or 147 from the global throttler can cause the local throttling logic 440 to send the throttling signal 445 and, based on the global throttling ratio signal 145 or 149, send the throttling ratio signal 446.

[0063] In some examples, such as Figure 6 As shown, threshold 0 or threshold 1 can be obtained from control register 605 and provided to greater than comparator 610 and less than comparator 620, respectively. For example, control register 605 can be configured to maintain a first value for threshold 0 and a second value for threshold 1, respectively. In these examples, the first value will be greater than the second value. If greater than comparator 610 determines that the EWMA included in EWMA(one or more) EWMA outputs 502 is greater than the first value of threshold 0, greater than comparator 610 can cause throttle 630 to be set / activated. However, if less than comparator 620 determines that the EWMA included in EWMA(one or more) EWMA outputs 502 is less than the second value of threshold 1, less than comparator 620 can cause throttle 630 to be reset / deactivated. If throttle 630 has been set / activated and the local throttling enable / disable (En / Dis) signal 600 is valid, AND gate 640 allows the throttle signal to be transmitted through OR gate 650, and OR gate 650 can then cause the throttle signal 445 to be sent. If no global throttling signal 143 or 147 is present, the local throttling ratio value 607 maintained in control register 605 can be routed through throttling ratio multiplexer 660 and sent via throttling ratio signal 446. An indication can also be sent to global throttler 140 each time a throttling signal 445 is sent. Furthermore, throttling counter 670 allows maintaining a throttling counter in control register 605 for each throttling signal 445 that has been sent to a specific portion of the instruction execution pipeline circuitry of core 101, which includes local detection and throttling circuitry 102. Throttling residency 680 allows maintaining information in control register 605 to indicate how long (e.g., how many cycles) one or more throttling signals 445 have been continuously sent by local throttling logic 440. In other words, how long EWMA exceeds threshold 0 before falling below threshold 1.

[0064] According to some examples, the comparison of the EWMA included in (one or more) EWMA outputs 502 with thresholds 0 and 1 can be overridden by global throttling signals 143 or 147, which can cause local throttling logic 440 to send a throttling signal 445 and a throttling ratio signal 446 based on global throttling ratio signals 145 or 149. In other words, even if the EWMA is below thresholds 0 and 1, global throttling logic 140 can still send throttling signal 445 and throttling ratio signal 446. Figure 6 An example is shown below: how global throttling signals 143 or 147 can be routed to gate 650 so that throttling signal 445 is sent, and routed to throttling ratio multiplexer 660 so that global throttling ratio signals 145 or 149 indicate the throttling ratio to be sent using throttling ratio signal 446.

[0065] Figure 7 The illustration shows an example global throttle 140. In some examples, it is... Figure 1 Similar to the example shown, Figure 7 The global throttling circuit 140 is shown to include a global event aggregator circuit 142, a short-window throttling circuit 144, and a long-window throttling circuit 146. As mentioned above and as... Figure 1 As shown, the global throttler 140 can work in conjunction with a distributed throttling architecture implemented at core 101, and individual WES 103-1 to 103-8 from the respective local detection and throttling circuits 102-1, 102-2, 102-3, 102-4, 102-5, 102-6, 102-7, or 102-8 can be sent to the global throttler 140. Figure 7 In some examples, WES 103-1 to 103-8 are shown to be included in the weighted event summation 712 and aggregated by the global event aggregator circuit 142.

[0066] According to some examples, WES 103-1 to 103-8 aggregated by the global event aggregator circuit 142 can be forwarded to the EWMA logic 720 of the short window throttling circuit 144. For these examples, the EWMA logic 720 can be configured in a manner similar to... Figure 4 and Figure 5 Similar to the EWMA logic 430 shown above. In this respect, the logic and / or function of the EWMA logic 720 can be arranged to use WES 103-1 to 103-8 forwarded from the global event aggregator circuit 142 as input to the example formula (1) and to calculate the exponentially weighted moving average using a programmable α value. The calculated exponentially weighted moving average is not intended to mitigate or reduce the first voltage drop (see...). Figure 2Instead of focusing on the impact of the second voltage drop, it attempts to help anticipate or predict when to throttle to mitigate or reduce the effects of the second voltage drop, which can have a relatively long time constant, approximately 20-40 ns.

[0067] In some examples, the calculated exponentially weighted moving average is output to global throttling logic 730. The logic and / or function of global throttling logic 730 can be similar to... Figure 4 and Figure 6 The local throttling logic 440 shown has logical and / or functionalities and can be configured to compare an exponentially weighted moving average with thresholds 0 and 1 included in the short-window throttling threshold 732 (e.g., maintained in the control register of core 101). Threshold 0 can be set to a first value that will be compared with the exponentially weighted moving average. If the exponentially weighted moving average reaches or exceeds the first value, the global throttling logic 730 can send a global throttling signal 143 to the local detection and throttling circuits 102-1 to 102-8 located together with or at some part of the instruction execution pipeline circuitry of core 101, as described above. A global throttling ratio signal 145 can also be sent, indicating a ratio based on the number of paused clock cycles to the total number of clock cycles.

[0068] According to some examples, WES 103-1 to 103-8 aggregated by the global event aggregator circuit 142 can also be forwarded to the original accumulator 740 of the long window throttling circuit 146. For these examples, the original accumulator 740 can be programmed to accumulate WES 103-1 to 103-8 based on a programmable period value (e.g., up to 64 clock cycles) set by the period program signal 742. The long window throttling circuit 146 may include the original accumulator 740 because the time constant of the third voltage drop is approximately 180-200 ns, compared to the time constant of approximately 20-40 ns for the second voltage drop; therefore, the time required to attempt to anticipate or predict when throttling will occur to mitigate or reduce the effects of the third voltage drop is significantly longer (see [link to relevant documentation]). Figure 2 ).

[0069] In some examples, WES 103-1 to 103-8 accumulated by the original accumulator 740 can be forwarded to the EWMA logic 750. For these examples, the EWMA logic 750 can be configured in a manner similar to... Figure 4 and Figure 5Similar to the EWMA logic 430 shown above. In this respect, the logic and / or function of the EWMA logic 750 can be configured to use the accumulated WES 103-1 to 103-8 forwarded from the original accumulator 740 as input to the example formula (1) and to calculate the exponentially weighted moving average using a programmable α value. The calculated exponentially weighted moving average is not intended to mitigate or reduce the first voltage drop (see...). Figure 2 The goal is not to assess the impact of voltage drops, but rather to help anticipate or predict when to implement throttling to mitigate or reduce the effects of third voltage drops, which can have a time constant of approximately 180-200 ns.

[0070] In some examples, the calculated exponentially weighted moving average is output to global throttling logic 760. The logic and / or function of global throttling logic 760 can be similar to... Figure 4 and Figure 6 The local throttling logic 440 shown has logical and / or functions and can be configured to compare an exponentially weighted moving average with thresholds 0 and 1 included in a long-window throttling threshold 762. Threshold 0 can be set to a first value that will be compared with the exponentially weighted moving average. If the exponentially weighted moving average reaches or exceeds the first value, the global throttling logic 760 can send a global throttling signal 147 to local detection and throttling circuits 102-1 to 102-8 located together with or at some part of the instruction execution pipeline circuitry of core 101, as described above. A global throttling ratio signal 149 can also be sent, indicating a ratio based on the number of paused clock cycles to the total number of clock cycles.

[0071] According to some examples, by aggregating WES received from each individual distributed local detection and throttling circuit 102 into a global throttling unit 140, this hierarchical approach can implement a mechanism that can scale to large IPs or groups of IPs within a second or third voltage drop time constant and control the demand for external power delivery. The modular nature of this hierarchical approach allows local detection and throttling circuits to be distributed across the instruction execution pipeline circuitry of the processor core and then aggregated outside the boundaries of the processor core's instruction execution pipeline circuitry. Therefore, this approach is not limited to the core instruction execution pipeline circuitry implemented in the central processing unit (CPU) and can also be extended to other types of processors, such as graphics processors or neural processors.

[0072] Figure 8 The illustration shows an example logic flow 800. Logic flow 800 represents an operation implemented by logic and / or functionality of a portion of the instruction execution pipeline circuitry located in or associated with that portion of the processor core. For example, as... Figure 1 As shown and in Figures 4 to 6 The logic and / or functions of the local detection and throttling circuit 102, which are shown and described in more detail in the document, are located at or together with the following: branch prediction unit 112, instruction decoding queue 118, out-of-order unit 122, integer execution cluster 124, vector execution cluster 126, L0 cache 132, L1 cache 134 or L2 cache 136.

[0073] In some examples, such as Figure 8 As shown, logic flow 800 at block 802 can perform the following operations: receive information at a circuit indicating that an energy event has occurred at or near a portion of the instruction execution pipeline circuit, which can be arranged to execute one or more pipeline stages at the processor core. For example, local event aggregator 410 can receive this information from various portions of the instruction execution pipeline circuit of core 101.

[0074] Based on some examples, logic flow 800 can generate a weighted event sum for energy events at block 804. For example, local event aggregator 410 can use the weights assigned to energy events to generate a weighted event sum.

[0075] In some examples, logic flow 800 at block 806 may add a weighted event value to one or more weighted event values ​​generated within a first time period to generate a weighted event sum. For example, local event aggregator 410 may add a weighted event value to one or more weighted event values ​​generated within a first time period based on a time constant of a first voltage drop (e.g., 3-5 ns).

[0076] In some examples, logic flow 800 can determine a moving average based on the weighted sum of events at block 808. For example, the logical AND / OR function of EWMA logic 430 can determine the moving average.

[0077] According to some examples, logic flow 800 can compare the moving average with a first threshold at block 810. For example, the greater than comparator 610 of local throttling logic 440 can compare the moving average with a first threshold obtained from control register 605.

[0078] In some examples, logic flow 800 at block 812 may perform the following operation: if the moving average is greater than a first threshold, a throttling indication is sent to that portion of the instruction execution pipeline circuitry. For example, local throttling logic 440 may cause the throttling indication to be sent to the portion of the instruction execution pipeline circuitry of core 101 where the local throttling logic 440 is located or is located together.

[0079] Figure 9The illustration depicts an example logic flow 900. Logic flow 900 represents an operation implemented by the circuitry, logic, and / or functionality of a global throttle, coupled to multiple portions of an instruction execution pipeline circuit that can be arranged to execute one or more pipeline stages at the processor core. For example, as... Figure 1 As shown and in Figure 7 The circuitry, logic, and / or functions of the global throttle 140, shown and described in more detail, are coupled to local detection and throttling circuitry 102 located at or together with multiple portions of the instruction execution pipeline circuitry of core 101, including branch prediction unit 112, instruction decoding queue 118, out-of-order unit 122, integer execution cluster 124, vector execution cluster 126, L0 cache 132, L1 cache 134, or L2 cache 136.

[0080] In some examples, such as Figure 9 As shown, logic flow 900 at block 902 can perform the following operations: receiving information indicating a weighted event sum at a global throttle coupled to multiple sections of the instruction execution pipeline circuitry, which can be arranged to execute one or more pipeline stages at the processor core, the weighted event sum being based on energy events that have occurred at a first of the multiple sections of the instruction execution pipeline circuitry. For example, global event aggregator circuitry 142 of global throttle 140 can receive this information.

[0081] According to some examples, logic flow 900 at block 904 can add the weighted event sum to one or more weighted event sums received within a first time period to aggregate the weighted event sum. For example, if the first time period is based on a second voltage drop time constant of approximately 20-40 ns, the global event aggregator circuit 142 of global throttling circuit 140 can add the weighted event sum to one or more weighted event sums and provide it to the EWMA logic 720 of short-window throttling circuit 144. If the first time period is based on a third voltage drop time constant of approximately 180-200 ns, both the global event aggregator circuit 142 and the original accumulator 740 of long-window throttling circuit 146 can add the weighted event sum to one or more weighted event sums.

[0082] In some examples, logic flow 900 at block 906 can determine the moving average based on the aggregated weighted sum of events. For example, if it is a second voltage drop time constant, the EWMA logic 720 of the short window throttling circuit 144 determines the moving average. If it is a third voltage drop time constant, the EWMA logic 750 of the long window throttling circuit 146 determines the moving average.

[0083] In some examples, logic flow 900 can compare a moving average with a first threshold at block 908. For example, if it is a second voltage drop time constant, the global throttling logic 730 of the short-window throttling circuit 144 compares it based on threshold 0 of the short-window throttling threshold 732. If it is a third voltage drop time constant, the global throttling logic 760 of the long-window throttling circuit 146 compares it based on threshold 0 of the long-window throttling threshold 762.

[0084] According to some examples, logic flow 900 may perform the following operation at block 910: if the moving average is greater than a first threshold, a throttling indication is sent to the plurality of parts of the instruction execution pipeline circuit. For example, if it is a second voltage drop time constant, the global throttling logic 730 of the short window throttling circuit 144 sends a throttling indication. If it is a third voltage drop time constant, the global throttling logic 760 of the long window throttling circuit 146 sends a throttling indication.

[0085] Figure 8 or Figure 9 The illustrated logical flow may represent an example method for performing the novel aspects described in this disclosure. While one or more methods illustrated herein are shown and described as a series of actions for ease of explanation, those skilled in the art will understand and recognize that these methods are not limited by the order of actions. Therefore, some actions may occur in a different order than those shown and described herein, and / or simultaneously with other actions. For example, those skilled in the art will understand and recognize that a method may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all actions illustrated in the methods are necessary for a novel implementation.

[0086] The logical flow can be implemented in software, firmware, and / or hardware. In software and firmware embodiments, the software or logical flow can be implemented by computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium (e.g., optical, magnetic, or semiconductor storage device). Embodiments are not limited to this context.

[0087] Some examples are implemented in one or more computer architectures, cores, accelerators, graphics processing units, FPGAs, etc. Some examples are generated or IP cores. Some examples utilize simulation and / or conversion.

[0088] At least some examples of the disclosed techniques can be described with reference to the following examples.

[0089] Example 1. An example apparatus may include: one or more control registers configured to maintain a first threshold and a second threshold. The apparatus may further include circuitry located at or with a portion of an instruction execution pipeline circuitry configured to execute one or more pipeline stages at a processor core. The circuitry may receive information indicating that an energy event has occurred at the portion of the instruction execution pipeline circuitry. The circuitry may also generate a weighted event value for the energy event and add the weighted event value to one or more weighted event values ​​generated within a first time period to generate a weighted event sum. The circuitry may also perform the following operations: determine a moving average based on the weighted event sum; compare the moving average with the first threshold. The circuitry may also perform the following operations: if the moving average is greater than the first threshold, send a throttling instruction to the portion of the instruction execution pipeline circuitry.

[0090] Example 2. In the apparatus described in Example 1, the throttling indication can cause the portion of the instruction execution pipeline circuit to suspend the execution of the one or more pipeline stages.

[0091] Example 3. In the apparatus described in Example 2, the circuitry may further perform the following operation: if the moving average is greater than the first threshold, send a throttling ratio to the portion of the instruction execution pipeline circuitry. The throttling ratio may be based on the number of clock cycles in which execution of the one or more pipeline stages is paused, divided by the total number of clock cycles.

[0092] Example 4. In the apparatus of Example 1, the circuitry may further receive information indicating that a second energy event has occurred at the portion of the instruction execution pipeline circuitry. The circuitry may further generate a second weighted event value for the second energy event and add the second weighted event value to one or more weighted event values ​​generated within a second time period to generate a second weighted event sum. The circuitry may further determine a second moving average based on the second weighted event sum. The circuitry may further compare the second moving average with a second threshold, wherein the second threshold is less than a first threshold. The circuitry may further perform the following operation: if the second moving average is less than the second threshold, then stop sending the throttling instruction to the portion of the instruction execution pipeline circuitry.

[0093] Example 5. In the apparatus described in Example 4, the first time period may be equal to the second time period, and the first time period and the second time period may be based on a voltage drop time constant of 3 to 5 nanoseconds.

[0094] Example 6. In the apparatus described in Example 1, the portion of the instruction execution pipeline circuit may include a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

[0095] Example 7. In the apparatus described in Example 6, the portion of the instruction execution pipeline circuitry may include an integer execution cluster or a vector execution cluster, and the energy event is based on the expected energy usage of the micro-operation type performed by the integer execution cluster or the vector execution cluster.

[0096] Example 8. In the apparatus described in Example 1, the circuitry may further send the generated weighted event value to a global throttle coupled to the processor core. The global throttle may include circuitry capable of performing the following operation: at least in part based on the generated weighted event value, causing multiple portions of the instruction execution pipeline circuitry to suspend or delay the execution of one or more pipeline stages.

[0097] Example 9. An example method may include: receiving information at a circuit indicating that an energy event has occurred at or near a portion of an instruction execution pipeline circuit, the circuit being located at or adjacent to the portion of the instruction execution pipeline circuit, the instruction execution pipeline circuit being configured to execute one or more pipeline stages at a processor core. The method may further include: generating a weighted event value for the energy event; adding the weighted event value to one or more weighted event values ​​generated within a first time period to generate a weighted event sum. The method may further include determining a moving average based on the weighted event sum. The method may further include comparing the moving average to a first threshold. The method may further include: if the moving average is greater than the first threshold, sending a throttling instruction to the portion of the instruction execution pipeline circuit.

[0098] Example 10. As described in Example 9, the throttling indication can cause the portion of the instruction execution pipeline circuit to suspend the execution of the one or more pipeline stages.

[0099] Example 11. The method of Example 10 may further include: if the moving average is greater than the first threshold, sending a throttling ratio to the portion of the instruction execution pipeline circuit. The throttling ratio may be based on the number of clock cycles for pausing execution of the one or more pipeline stages divided by the total number of clock cycles.

[0100] Example 12. The method described in Example 11 may further include: receiving information indicating that a second energy event has occurred at the portion of the instruction execution pipeline circuit. The method may further include: generating a second weighted event value for the second energy event, and adding the second weighted event value to one or more weighted event values ​​generated within a second time period to generate a second weighted event sum. The method may further include: determining a second moving average based on the second weighted event sum; comparing the second moving average with a second threshold. The second threshold may be less than a first threshold. The method may further include: if the second moving average is less than the second threshold, stopping the transmission of the throttling indication to the portion of the instruction execution pipeline circuit.

[0101] Example 13. As described in Example 12, the first time period may be equal to the second time period, and the first time period and the second time period may be based on a voltage drop time constant of 3 to 5 nanoseconds.

[0102] Example 14. As described in Example 9, the portion of the instruction execution pipeline circuit may include a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

[0103] Example 15. As described in Example 14, the portion of the instruction execution pipeline circuit may be an integer execution cluster or a vector execution cluster, and the energy event may be based on the expected energy usage of the micro-operation type performed by the integer execution cluster or the vector execution cluster.

[0104] Example 16. The method described in Example 9 may further include sending the generated weighted event value to a global throttle coupled to the processor core, wherein the global throttle includes circuitry capable of performing the following operation: at least in part based on the generated weighted event value, causing multiple portions of the instruction execution pipeline circuitry to suspend or delay the execution of one or more pipeline stages.

[0105] Example 17. At least one machine-readable medium may include a plurality of instructions that, in response to being executed by a system, cause the system to perform the method according to any one of Examples 9 to 16.

[0106] Example 18. An example apparatus may include means for performing the method as described in any one of Examples 9 to 16.

[0107] Example 19. An example system may include: an instruction execution pipeline circuit capable of being arranged to execute one or more pipeline stages at a processor core. The system may further include: a global throttle coupled to multiple portions of the instruction execution pipeline circuit. The global throttle may include circuitry configured to: receive information indicating a weighted sum of events based on energy events occurring at a first portion of the multiple portions of the instruction execution pipeline circuit. The circuitry may also add the weighted sum of events to one or more weighted sums of events received within a first time period to aggregate the weighted sum of events. The circuitry may also determine a moving average based on the aggregated weighted sum of events. The circuitry may also compare the moving average to a first threshold. The circuitry may also perform the following operation: if the moving average is greater than the first threshold, send a throttle indication to the multiple portions of the instruction execution pipeline circuit.

[0108] Example 20. In the system described in Example 19, the throttling indication can cause the plurality of portions of the instruction execution pipeline circuit to suspend the execution of the one or more pipeline stages.

[0109] Example 21. In the system described in Example 20, the circuitry can also be configured to: if the moving average is greater than the first threshold, send a throttling ratio to the plurality of portions of the instruction execution pipeline circuitry. The throttling ratio may be based on the number of clock cycles in which execution of the one or more pipeline stages is paused, divided by the total number of clock cycles.

[0110] Example 22. In the system described in Example 19, the circuitry can further be configured to receive information indicating a second weighted event sum, the second weighted event sum being based on second energy events that have occurred at the first portion of the plurality of portions of the instruction execution pipeline circuitry. The circuitry can also add the second weighted event sum to one or more second weighted event sums received within a second time period to aggregate the second weighted event sum. The circuitry can further perform the following operations: determine a second moving average based on the aggregated second weighted event sum; compare the second moving average with a second threshold. The second threshold may be less than the first threshold. The circuitry can further perform the following operations: if the second moving average is less than the second threshold, stop sending the throttling indication to the plurality of portions of the instruction execution pipeline circuitry.

[0111] Example 23. In the system described in Example 22, the first time period may be equal to the second time period, and the first time period and the second time period may be based on a voltage drop time constant of 20 to 40 nanoseconds.

[0112] Example 24. In the system described in Example 22, the first time period may be equal to the second time period, and the first time period and the second time period may be based on a voltage drop time constant of 180 to 200 nanoseconds.

[0113] Example 25. In the system described in Example 19, the plurality of portions of the instruction execution pipeline circuit may include a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

[0114] Example 26. In the system described in Example 25, the first portion of the instruction execution pipeline circuitry may include an integer execution cluster or a vector execution cluster, and the energy event is based on the expected energy usage of the micro-operation type performed by the integer execution cluster or the vector execution cluster.

[0115] The example computer architecture is described in detail below. Other system designs and configurations known in the art for laptops, desktop computers, personal computers (PCs), personal digital assistants, engineering workstations, servers, discrete servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In summary, various systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0116] Example System Figure 10 The illustration depicts an example computing system. The multiprocessor system 1000 is an interface-based system and includes multiple processors or cores, including a first processor 1070 and a second processor 1080 coupled via an interface 1050 (e.g., a point-to-point (PP) interconnect, fabric, and / or bus). In some examples, the first processor 1070 and the second processor 1080 are homogeneous. In some examples, the first processor 1070 and the second processor 1080 are heterogeneous. While the example multiprocessor system 1000 is shown as having two processors, the system can have three or more processors, or it can be a single-processor system. In some examples, the computing system is a system-on-a-chip (SoC).

[0117] Processors 1070 and 1080 are shown to include integrated memory controller (IMC) circuitry 1072 and 1082, respectively. Processor 1070 also includes interface circuitry 1076 and 1078; similarly, the second processor 1080 includes interface circuitry 1086 and 1088. Processors 1070 and 1080 can exchange information via interface 1050 using interface circuitry 1078 and 1088. IMCs 1072 and 1082 couple processors 1070 and 1080 to their respective memories, namely memories 1032 and 1034, which may be part of the main memory locally attached to each processor.

[0118] Processors 1070 and 1080 can each use interface circuits 1076, 1094, 1086, and 1098 to exchange information with network interface (NWI / F) 1090 via interfaces 1052 and 1054. Network interface 1090 (e.g., one or more of interconnects, buses, and / or structures, in some examples a chipset) can optionally exchange information with coprocessor 1038 via interface circuit 1092. In some examples, coprocessor 1038 is a dedicated processor, such as a high-throughput processor, network or communication processor, compression engine, graphics processor, general-purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, security processor, cryptographic accelerator, matrix accelerator, in-memory analysis accelerator, dataflow accelerator, data graph manipulation, etc.

[0119] A shared cache (not shown) may be included in either of the processors 1070 or 1080, or may be located outside of the two processors but connected to them via an interface (e.g., PP interconnect), such that if one processor is placed in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0120] Network interface 1090 may be coupled to first interface 1016 via interface circuitry 1096. In some examples, first interface 1016 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, first interface 1016 is coupled to power control unit (PCU) 1017, which may include circuitry, software, and / or firmware to perform power management operations with respect to processors 1070, 1080, and / or coprocessor 1038. PCU 1017 provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate an appropriate regulated voltage. PCU 1017 also provides control information to control the generated operating voltage. In various examples, PCU 1017 may include various power management logic units (circuitry) to perform hardware-based power management. Such power management can be entirely controlled by the processor (e.g., controlled by various processor hardware and can be triggered by workload and / or power constraints, thermal constraints or other processor constraints), and / or power management can be performed in response to external sources (e.g., platform or power management sources or system software).

[0121] The PCU 1017 is illustrated as logic separate from the processor 1070 and / or processor 1080. In other cases, the PCU 1017 may execute on one or more cores of the processor 1070 or 1080 (not shown). In some cases, the PCU 1017 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code (sometimes called P-code). In still other examples, the power management operations to be performed by the PCU 1017 may be implemented externally to the processor, for example, by means of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by the PCU 1017 may be implemented within the BIOS or other system software.

[0122] Various I / O devices 1014 and a bus bridge 1018 can be coupled to a first interface 1016, which in turn couples the first interface 1016 to a second interface 1020. In some examples, one or more additional processors 1015 are coupled to the first interface 1016. Processors 1015 may include coprocessors, high-throughput many-integrated-core (MIC) processors, GPGPUs, accelerators (e.g., graphics accelerators or digital signal processing (DSP) units), field-programmable gate arrays (FPGAs), or any other processor. In some examples, the second interface 1020 may be a low-pin-count (LPC) interface. Various devices can be coupled to the second interface 1020, including, for example, a keyboard and / or mouse 1022, a communication device 1027, and storage circuitry 1028. Storage circuitry 1028 may be one or more non-transitory machine-readable storage media, such as disk drives or other mass storage devices, and may include instructions / code and data 1030. Additionally, the audio I / O 1024 can be coupled to the second interface 1020. Note that other architectures besides the point-to-point architecture described above are also possible. For example, a system such as the multiprocessor system 1000 can implement a multi-drop interface or other such architectures instead of a point-to-point architecture.

[0123] Example core architecture, processor, and computer architecture Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, these core implementations can include: 1) general-purpose ordered cores for general computing purposes; 2) high-performance general-purpose out-of-order cores for general computing purposes; and 3) dedicated cores primarily for graphics and / or scientific (throughput) computing purposes. Different processor implementations can include: 1) CPUs, comprising one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores for general computing purposes; and 2) coprocessors, comprising one or more dedicated cores primarily for graphics and / or scientific (throughput) computing purposes. These different processors lead to different computer system architectures, which can include: 1) coprocessors and CPUs on separate chips; 2) coprocessors and CPUs on separate dies within the same package; 3) coprocessors and CPUs on the same die (in this case, such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) system-on-a-chip (SoC), which can be included on the same die as the described CPU (sometimes referred to as application cores or application processors), the aforementioned coprocessors, and additional functionality. An example core architecture is described next, followed by a description of the example processor and computer architecture.

[0124] Figure 11 A block diagram of an example processor and / or SoC 1100 is illustrated, which may have one or more cores and an integrated memory controller. The processor and / or SoC 1100 illustrated by solid-line boxes has a single core 1102(A), system proxy unit circuitry 1110, and a set of one or more interface controller unit circuitry 1116, while alternative processors and / or SoCs 1100 can be illustrated by optional dashed-line boxes having multiple cores 1102(A)-(N), a set of one or more integrated memory control unit circuitry 1114 from the system proxy unit circuitry 1110, dedicated logic 1108, and a set of one or more interface controller unit circuitry 1116. Note that the processor and / or SoC 1100 may be… Figure 10 One of the processors 1070 or 1080 or the coprocessor 1038 or 1015.

[0125] Thus, different implementations of the processor and / or SoC 1100 may include: 1) a CPU, wherein dedicated logic 1108 is a high-throughput processor, network or communication processor, compression engine, graphics processor, general-purpose graphics processing unit (GPGPU), neural network processing unit (NPU), embedded processor, security processor, matrix accelerator, in-memory analysis accelerator, compression accelerator, data stream accelerator, data graph operations, etc. (which may include one or more cores, not shown), and cores 1102(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, wherein cores 1102(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, wherein cores 1102(A)-(N) are a large number of general-purpose ordered cores. Therefore, the processor and / or SoC 1100 can be a general-purpose processor, coprocessor, or special-purpose processor, such as a network or communication processor, compression engine, graphics processor, GPGPU (General-Purpose Graphics Processing Unit), high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), embedded processor, etc. The processor can be implemented on one or more chips. The processor and / or SoC 1100 can be part of one or more substrates and / or can be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0126] The memory hierarchy includes one or more levels of cache cell circuitry 1104(A)-(N) within cores 1102(A)-(N), a group of one or more shared cache cell circuitry 1106, and external memory (not shown) coupled to the group of integrated memory controller cell circuitry 1114. The group of one or more shared cache cell circuitry 1106 may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, such as the last-level cache (LLC), and / or combinations thereof. While in some examples interface network circuitry 1112 (e.g., a ring interconnect) interfaces to dedicated logic 1108 (e.g., integrated graphics logic), the group of shared cache cell circuitry 1106, and system agent cell circuitry 1110, alternative examples use any number of known techniques to interface to these units. In some examples, one or more circuits in the shared cache cell circuitry 1106 maintain consistency with cores 1102(A)-(N). In some examples, the interface controller unit circuit 1116 couples these cores 1102(A)-(N) to one or more other devices 1118, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networks, wired networks, etc.).

[0127] In some examples, one or more of cores 1102(A)-(N) have multi-threading capabilities. System agent unit circuitry 1110 includes those components that coordinate and operate cores 1102(A)-(N). System agent unit circuitry 1110 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of cores 1102(A)-(N) and / or dedicated logic 1108 (e.g., integrated graphics logic). Display unit circuitry is used to drive one or more externally connected displays.

[0128] Cores 1102(A)-(N) can be homogeneous in terms of instruction set architecture (ISA). Alternatively, cores 1102(A)-(N) can be heterogeneous in terms of ISA; that is, a subset of cores 1102(A)-(N) may be able to execute an ISA, while other cores may be able to execute only a subset of that ISA or be able to execute another ISA.

[0129] Figure 12The block diagram illustrates a computing system 1200 configured to implement one or more aspects of the examples described herein. The computing system 1200 includes a processing subsystem 1201 having one or more processors 1202, and a system memory 1204, which communicate via interconnect paths that may include a memory hub 1205. The memory hub 1205 may be a separate component within a chipset assembly or may be integrated within one or more processors 1202. The memory hub 1205 is coupled to an I / O subsystem 1211 via a communication link 1206. The I / O subsystem 1211 includes an I / O hub 1207 that enables the computing system 1200 to receive input from one or more input devices 1208. Furthermore, the I / O hub 1207 enables a display controller included in one or more processors 1202 to provide output to one or more display devices 1210A. In some examples, one or more display devices 1210A coupled to I / O hub 1207 may include local, internal, or embedded display devices.

[0130] For example, processing subsystem 1201 includes one or more parallel processors 1212 coupled to memory hub 1205 via a bus or communication link 1213. Communication link 1213 can be any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Fast, or it can be a vendor-specific communication interface or communication architecture. The one or more parallel processors 1212 can form a computationally centralized parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as many integrated core (MIC) processors. For example, the one or more parallel processors 1212 form a graphics processing subsystem that can output pixels to one or more display devices 1210A coupled via I / O hub 1207. The one or more parallel processors 1212 may also include a display controller and a display interface (not shown) for direct connection to one or more display devices 1210B.

[0131] Within the I / O subsystem 1211, system storage unit 1214 can be connected to I / O hub 1207 to provide storage for computing system 1200. I / O switch 1216 can be used to provide an interface mechanism to enable connectivity between I / O hub 1207 and other components (e.g., network adapter 1218 and / or wireless network adapter 1219 that can be integrated into the platform) and various other devices that can be added via one or more additional devices 1220. The additional devices 1220 may also include, for example, one or more external graphics processing units, graphics cards, and / or computing accelerators. Network adapter 1218 may be an Ethernet adapter or another wired network adapter. Wireless network adapter 1219 may include one or more of the following network devices: Wi-Fi, Bluetooth, near field communication (NFC), or one or more wireless radios.

[0132] The computing system 1200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1207. Figure 12The communication paths between various interconnected components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Fast), or any (one or more) other bus or point-to-point communication interface and / or protocol, such as NVLink High-Speed ​​Interconnect, Compute Express Link™ (CXL™) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), and Intel On-Chip System. Fabric (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variants thereof, or wired or wireless interconnect protocols known in the art. In some examples, protocols such as fabric-based non-volatile memory express (NVMe) (NVMe over Fabrics, NVMe-oF) or NVMe can be used to copy or store data to virtualized storage nodes.

[0133] One or more parallel processors 1212 may include circuitry optimized for graphics and video processing, such as video output circuitry, and constitute a graphics processing unit (GPU). Alternatively or additionally, one or more parallel processors 1212 may include circuitry optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. Components of the computing system 1200 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 1212, memory hub 1205, processor(s) 1202, and I / O hub 1207 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 1200 may be integrated into a single package to form a system-in-package (SIP) configuration. In some examples, at least a portion of the components of the computing system 1200 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to form a modular computing system.

[0134] It will be understood that the computing system 1200 shown herein is illustrative and can be varied and modified. The connection topology, including the number and arrangement of bridges, the number of processors(one or more) 1202, and the number of parallel processors(one or more) 1212, can be modified as needed. For example, system memory 1204 can be directly connected to processors(one or more) 1202 instead of via bridges, while other devices communicate with system memory 1204 via memory hub 1205 and processors(one or more) 1202. In other alternative topologies, parallel processors(one or more) 1212 are connected to I / O hub 1207 or directly to one of the processors(one or more) 1202 instead of memory hub 1205. In other examples, I / O hub 1207 and memory hub 1205 can be integrated into a single chip. Two or more sets of processors 1202 can also be attached via multiple sockets, which can couple to two or more instances of parallel processors(one or more) 1212.

[0135] Some specific components shown in this article are optional and may not be included in all implementations of the computing system 1200. For example, any number of add-on cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may differ depending on the specific implementation. Figure 12 The components shown use different terminology. For example, in some architectures, the memory hub 1205 may be referred to as the Northbridge, while the I / O hub 1207 may be referred to as the Southbridge.

[0136] Figure 13A An example of a parallel processor 1300 is illustrated. The parallel processor 1300 can be a GPU, GPGPU, etc., as described herein. Various components of the parallel processor 1300 can be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The parallel processor 1300 can be... Figure 12 One or more of the parallel processors 1212 shown.

[0137] Parallel processor 1300 includes parallel processing unit 1302. The parallel processing unit includes I / O unit 1304, which enables communication with other devices, including other instances of parallel processing unit 1302. I / O unit 1304 can be directly connected to other devices. For example, I / O unit 1304 can be connected to other devices using a hub or switch interface (e.g., memory hub 1205). The connection between memory hub 1205 and I / O unit 1304 forms a communication link 1213. Within parallel processing unit 1302, I / O unit 1304 is connected to host interface 1306 and memory crossbar 1316, wherein host interface 1306 receives commands for performing processing operations, and memory crossbar 1316 receives commands for performing memory operations.

[0138] When host interface 1306 receives a command buffer via I / O unit 1304, host interface 1306 can direct the work operations to execute these commands to front end 1308. In some examples, front end 1308 is coupled to scheduler 1310, which is configured to distribute commands or other work items to processing cluster array 1312. Before tasks are distributed to the processing clusters of processing cluster array 1312, scheduler 1310 ensures that processing cluster array 1312 is correctly configured and in an active state. Scheduler 1310 can be implemented via firmware logic executed on a microcontroller. Microcontroller-implemented scheduler 1310 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling fast preemption and context switching of threads executing on processing cluster array 1312. Preferably, host software can validate workloads via one of a plurality of graphics processing doorbells for scheduling on processing cluster array 1312. In other examples, polling for new workloads or interrupts can be used to identify or indicate the availability of work to be performed. Then, the scheduler 1310 logic within the scheduler microcontroller can automatically distribute the workload across the processing cluster array 1312.

[0139] Processing cluster array 1312 may include up to "N" processing clusters (e.g., clusters 1314A, 1314B to 1314N). Each cluster 1314A-1314N of processing cluster array 1312 can execute a large number of concurrent threads. Scheduler 1310 may use various scheduling and / or work distribution algorithms to allocate work to clusters 1314A-1314N of processing cluster array 1312, and these algorithms may vary depending on the workload present for each type of program or computation. Scheduling may be handled dynamically by scheduler 1310, or it may be partially assisted by compiler logic during the compilation of program logic configured for execution by processing cluster array 1312. Optionally, different clusters 1314A-1314N of processing cluster array 1312 may be assigned to process different types of programs or perform different types of computations.

[0140] The processing cluster array 1312 can be configured to perform various types of parallel processing operations. For example, the processing cluster array 1312 can be configured to perform general-purpose parallel computing operations. For example, the processing cluster array 1312 may include logic for performing processing tasks, such as filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0141] Processing cluster array 1312 is configured to perform parallel graphics processing operations. In this example where parallel processor 1300 is configured to perform graphics processing operations, processing cluster array 1312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Furthermore, processing cluster array 1312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 1302 may transfer data from system memory via I / O unit 1304 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1322) and then written back to system memory.

[0142] In an example where the parallel processing unit 1302 is used to perform graphics processing, the scheduler 1310 may be configured to divide the processing workload into tasks of approximately the same size to better distribute graphics processing operations across multiple clusters 1314A-1314N of the processing cluster array 1312. In some of these examples, portions of the processing cluster array 1312 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform subdivision and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 1314A-1314N may be stored in buffers to allow intermediate data to be transferred between the clusters 1314A-1314N for further processing.

[0143] During operation, the processing cluster array 1312 may receive processing tasks to be executed via a scheduler 1310, which receives commands defining the processing tasks from the front end 1308. For graphics processing operations, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., what program to execute). The scheduler 1310 may be configured to obtain an index corresponding to a task, or may receive an index from the front end 1308. The front end 1308 may be configured to ensure that the processing cluster array 1312 is configured to be active before the workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0144] Each of one or more instances of the parallel processing unit 1302 may be coupled to the parallel processor memory 1322. The parallel processor memory 1322 may be accessed via a memory crossbar 1316, which may receive memory requests from the processing cluster array 1312 and the I / O unit 1304. The memory crossbar 1316 may access the parallel processor memory 1322 via a memory interface 1318. The memory interface 1318 may include a plurality of partition units (e.g., partition units 1320A, 1320B, up to partition units 1320N), each partition unit may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1322. The number of partition units 1320A-1320N may be configured to be equal to the number of memory cells, such that a first partition unit 1320A has a corresponding first memory cell 1324A, a second partition unit 1320B has a corresponding second memory cell 1324B, and the Nth partition unit 1320N has a corresponding Nth memory cell 1324N. In other examples, the number of partition units 1320A-1320N may not be equal to the number of memory devices.

[0145] Memory cells 1324A-1324N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, memory cells 1324A-1324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that specific implementations of memory cells 1324A-1324N can vary widely and can be selected from a variety of conventional designs. Render targets (e.g., framebuffers or texture maps) can be stored across memory cells 1324A-1324N, allowing partitioning cells 1320A-1320N to write portions of each render target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1322. In some examples, a local instance of the parallel processor memory 1322 may not be omitted, and instead a unified memory design utilizing system memory combined with local cache memory may be employed.

[0146] Optionally, any of the clusters 1314A-1314N in the processing cluster array 1312 is capable of processing data to be written to any memory cell 1324A-1324N within the parallel processor memory 1322. The memory crossbar 1316 can be configured to transfer the output of each cluster 1314A-1314N to any partition cell 1320A-1320N or another cluster 1314A-1314N, which can perform additional processing on the output. Each cluster 1314A-1314N can communicate with the memory interface 1318 via the memory crossbar 1316 to read from or write to various external memory devices. In one example with memory crossbar 1316, memory crossbar 1316 has a connection to memory interface 1318 for communication with I / O unit 1304, and a connection to a local instance of parallel processor memory 1322, thereby enabling processing units within different processing clusters 1314A-1314N to communicate with system memory or other memory not local to parallel processing unit 1302. Generally, memory crossbar 1316 may, for example, be able to use virtual channels to separate traffic flows between clusters 1314A-1314N and partition units 1320A-1320N.

[0147] Although a single instance of the parallel processing unit 1302 is illustrated within the parallel processor 1300, any number of instances of the parallel processing unit 1302 may be included. For example, multiple instances of the parallel processing unit 1302 may be provided on a single add-on card, or multiple add-on cards may be interconnected. For example, the parallel processor 1300 may be an add-on device, such as... Figure 12 The additional device 1220 (one or more) can be a graphics card, such as a discrete graphics card including one or more GPUs, one or more memory devices, and device-to-device or network or architecture interfaces. Different instances of the parallel processing unit 1302 can be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. Optionally, some instances of the parallel processing unit 1302 may include floating-point units with higher precision relative to other instances. Systems containing one or more instances of the parallel processing unit 1302 or the parallel processor 1300 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. The coordinator can utilize one or more of the following to form composite nodes for workload execution: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

[0148] In some examples, the parallel processing unit 1302 can be partitioned into multiple instances. These instances can be configured to execute workloads associated with different clients in an isolated manner, thereby enabling the provision of a predetermined quality of service for each client. For example, each cluster 1314A-1314N can be separate and isolated from other clusters, allowing the processing cluster array 1312 to be divided into multiple compute partitions or instances. In this configuration, workloads executed on isolated partitions are protected from failures or errors associated with different workloads executed on different partitions. Partition units 1320A-1320N can be configured to provide dedicated and / or isolated paths to memory for clusters 1314A-1314N associated with each compute partition. This data path isolation allows compute resources within a partition to communicate with one or more assigned memory units 1324A-1324N without being affected by the activity of other partitions.

[0149] Figure 13B This is a block diagram of partition unit 1320. Partition unit 1320 can be... Figure 13A An example of one of the partitioning units 1320A-1320N. As shown, partitioning unit 1320 includes an L2 cache 1321, a frame buffer interface 1325, and a ROP 1326 (Raster Operation Unit). The L2 cache 1321 is a read / write cache configured to perform load and store operations received from memory crossbar 1316 and ROP 1326. Read errors and urgent write-back requests are output by the L2 cache 1321 to the frame buffer interface 1325 for processing. Updates can also be sent to the frame buffer for processing via the frame buffer interface 1325. In some examples, the frame buffer interface 1325 interfaces with one of the memory units in the parallel processor memory, for example... Figure 13A The memory cells 1324A-1324N (e.g., within the parallel processor memory 1322). The partition unit 1320 may additionally or alternatively also interface with one of the memory cells in the parallel processor memory via a memory controller (not shown).

[0150] In graphics applications, ROP 1326 is a processing unit that performs raster operations (e.g., stenciling, z-testing, blending, etc.). ROP 1326 then outputs processed graphics data, which is stored in graphics memory. In some examples, ROP 1326 includes or is coupled to codec 1327, which includes compression logic to compress depth or color data written to memory or L2 cache 1321 and to decompress depth or color data read from memory or L2 cache 1321. The compression logic can be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by codec 1327 can vary based on the statistical characteristics of the data to be compressed. For example, in some examples, incremental color compression is performed on a per-tile basis for both depth and color data. In some examples, codec 1327 includes compression and decompression logic that can compress and decompress computational data associated with machine learning operations. For example, codec 1327 can compress sparse matrix data used for sparse machine learning operations. Codec 1327 can also compress sparse matrix data encoded in sparse matrix formats (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and / or decoded before being processed by the processing element, or the processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing.

[0151] ROP 1326 can be included in each processing cluster (e.g., Figure 13A The data is stored within clusters 1314A-1314N, not within partition units 1320. In this example, read and write requests for pixel data are transmitted via memory crossbar 1316 instead of pixel fragment data. The processed graphics data can then be displayed on a display device, such as... Figure 12 One of one or more display devices 1210A-1210B is routed to be further processed by processor(s) 1202, or is routed to be... Figure 13A One of the processing entities within the parallel processor 1300 is further processed.

[0152] Figure 13C This is a block diagram of a processing cluster 1314 within a parallel processing unit. For example, the processing cluster is... Figure 13AAn instance of one of the processing clusters 1314A-1314N. Processing cluster 1314 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executing on a specific input dataset. Optionally, the parallel execution of a large number of threads can be supported using Single-Instruction, Multiple-Data (SIMD) instruction issuing techniques without providing multiple independent instruction units. Alternatively, the parallel execution of a large number of generally synchronous threads can be supported using Single-Instruction, Multiple-Thread (SIMT) techniques, where a shared instruction unit is used, configured to issue instructions to a set of processing engines within each processing cluster. Unlike SIMD execution mechanisms (where all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that SIMD processing mechanisms represent a subset of the functionality of SIMT processing mechanisms.

[0153] The operation of the processing cluster 1314 can be controlled via pipeline manager 1332, which distributes processing tasks to the SIMT parallel processors. Pipeline manager 1332... Figure 13A The scheduler 1310 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1334 and / or texture unit 1336. The graphics multiprocessor 1334 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included within the processing cluster 1314. One or more instances of the graphics multiprocessor 1334 may be included within the processing cluster 1314. The graphics multiprocessor 1334 can process data, and the data crossbar 1340 can be used to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 1332 facilitates the distribution of processed data by specifying destinations for the processed data to be distributed via the data crossbar 1340.

[0154] Each graphics multiprocessor 1334 within the processing cluster 1314 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions complete. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. Different operations can be performed using the same functional unit hardware, and arbitrary combinations of functional units are possible.

[0155] Instructions transmitted to the processing cluster 1314 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1334. The number of threads in a thread group may be less than the number of processing engines within the graphics multiprocessor 1334. When the number of threads in a thread group is less than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. The number of threads in a thread group may also be greater than the number of processing engines within the graphics multiprocessor 1334. When the number of threads in a thread group is greater than the number of processing engines within the graphics multiprocessor 1334, processing can be performed in consecutive clock cycles. Optionally, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1334.

[0156] The graphics multiprocessor 1334 may include an internal cache memory to perform load and store operations. Alternatively, the graphics multiprocessor 1334 may forgo the internal cache and use a cache memory within the processing cluster 1314 (e.g., a Level 1 (L1) cache 1348). Each graphics multiprocessor 1334 is also able to access partition units (e.g., Figure 13A The graphics multiprocessor 1334 has a Level 2 (L2) cache within its partitioned units 1320A-1320N, which is shared across all processing clusters 1314 and can be used to transfer data between threads. The graphics multiprocessor 1334 also has access to off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 1302 can be used as global memory. Embodiments of the processing cluster 1314 that include multiple instances of the graphics multiprocessor 1334 can share common instructions and data, which can be stored in the L1 cache 1348.

[0157] Each processing cluster 1314 may include an MMU 1345 (Memory Management Unit), which is configured to map virtual addresses to physical addresses. In other examples, one or more instances of the MMU 1345 may exist. Figure 13AThe memory interface 1318 is located within the MMU 1345. The MMU 1345 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses on tiles, and optionally also includes cache line indexes. The MMU 1345 may include address translation lookup buffers (TLBs) or caches, which may reside within the L1 cache 1348 of the graphics multiprocessor 1334 or the processing cluster 1314. Physical addresses are processed to distribute surface data access locations to allow efficient request interleaving between partition units. Cache line indexes can be used to determine whether a request for a cache line is a hit or a miss.

[0158] In graphics and computing applications, processing cluster 1314 may be configured such that each graphics multiprocessor 1334 is coupled to a texture unit 1336, which performs texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some examples from an L1 cache within the graphics multiprocessor 1334, and may be retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 1334 outputs processed tasks to a data crossbar 1340 to provide the processed tasks to another processing cluster 1314 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1316. A preROP 1342 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1334 and direct the data to a ROP unit, which may be coupled to a partitioning unit as described herein (e.g., Figure 13A The partition units 1320A-1320N are located together. The preROP 1342 unit can perform color blending optimization, organize pixel color data, and perform address translation.

[0159] It will be understood that the core architecture described herein is illustrative only and is subject to change and modification. Any number of processing units may be included within processing cluster 1314, such as graphics multiprocessors 1334, texture units 1336, preROP 1342, etc. Furthermore, although only one processing cluster 1314 is shown, the parallel processing units as described herein may include any number of instances of processing cluster 1314. Optionally, each processing cluster 1314 may be configured to operate independently of other processing clusters 1314 using separate and distinct processing units, L1 caches, L2 caches, etc.

[0160] Figure 13DAn example of a graphics multiprocessor 1334 is shown, wherein the graphics multiprocessor 1334 is coupled to a pipeline manager 1332 of a processing cluster 1314. The graphics multiprocessor 1334 has an execution pipeline including, but not limited to, an instruction cache 1352, an instruction unit 1354, an address mapping unit 1356, a register file 1358, one or more general purpose graphics processing unit (GPGPU) cores 1362, and one or more load / store units 1366. The GPGPU cores 1362 and the load / store units 1366 are coupled to a cache memory 1372 and a shared memory 1370 via a memory and cache interconnect 1368. The graphics multiprocessor 1334 may also include a tensor and / or ray tracing core 1363, which includes hardware logic for accelerating matrix and / or ray tracing operations.

[0161] Instruction cache 1352 receives a stream of instructions to be executed from pipeline manager 1332. These instructions are cached in instruction cache 1352 and executed by instruction unit 1354. Instruction unit 1354 can dispatch instructions as a group of threads (e.g., warped), with each thread in the group assigned to a different execution unit within GPGPU core 1362. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 1356 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 1366.

[0162] Register file 1358 provides a set of registers for the functional units of graphics multiprocessor 1334. Register file 1358 provides temporary storage for operational objects on data paths connected to functional units of graphics multiprocessor 1334 (e.g., GPGPU core 1362, load / store unit 1366). Register file 1358 can be partitioned among each functional unit, such that each functional unit can be allocated a dedicated portion of register file 1358. For example, register file 1358 can be partitioned among different warps performed by graphics multiprocessor 1334.

[0163] Each GPGPU core 1362 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1334. In some implementations, the GPGPU core 1362 may include hardware logic, which may otherwise reside within the tensor and / or ray tracing core 1363. The GPGPU cores 1362 may be architecturally similar or architecturally different. For example, in some examples, a first portion of the GPGPU core 1362 includes a single-precision FPU and an integer ALU, while a second portion includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 1334 may also include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. One or more GPGPU cores may also include fixed-function or special-function logic.

[0164] The GPGPU core 1362 may include SIMD logic capable of executing a single instruction on multiple sets of data. Optionally, the GPGPU core 1362 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions of the GPGPU core may be generated by a shader compiler at compile time, or automatically generated when executing programs written and compiled for single-program multiple data (SPMD) or SIMT architectures. Multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in some examples, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0165] The memory and cache interconnect 1368 is an interconnect network that connects each functional unit of the graphics multiprocessor 1334 to the register file 1358 and shared memory 1370. For example, the memory and cache interconnect 1368 is a crossbar interconnect that allows load / store units 1366 to perform load and store operations between shared memory 1370 and register file 1358. Register file 1358 can operate at the same frequency as the GPGPU core 1362, resulting in very low data transfer latency between the GPGPU core 1362 and register file 1358. Shared memory 1370 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1334. Cache memory 1372 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 1336. Shared memory 1370 can also be used as a program management cache. Shared memory 1370 and cache memory 1372 can be coupled to a data crossbar 1340 to enable communication with other components of the processing cluster. In addition to the automatically cached data stored in cache memory 1372, threads executing on GPGPU core 1362 can also programmatically store data in shared memory.

[0166] Figures 14A-14C The illustration shows the additional graphics multiprocessor based on the example. Figures 14A-14B The illustration shows the graphics multiprocessors 1425 and 1450, and their relationship with... Figure 13C The graphics multiprocessor 1334 is related to and can be used as an alternative to one of them. Therefore, any features disclosed herein in conjunction with graphics multiprocessor 1334 are also disclosed in corresponding combinations with graphics multiprocessors 1425 and 1450, but are not limited thereto. Figure 14C The illustration shows a graphics processing unit (GPU) 1480 comprising a set of dedicated graphics processing resources arranged in multi-core groups 1465A-1465N, which correspond to graphics multiprocessors 1425 and 1450. The illustrated graphics multiprocessors 1425 and 1450 and the multi-core groups 1465A-1465N can be streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0167] Compared to Figure 13D The graphics multiprocessor 1334, Figure 14AThe graphics multiprocessor 1425 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 1425 may include multiple instances of instruction units 1432A-1432B, register files 1434A-1434B, and (one or more) texture units 1444A-1444B. The graphics multiprocessor 1425 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 1436A-1436B, tensor cores 1437A-1437B, ray tracing cores 1438A-1438B) and multiple sets of load / store units 1440A-1440B. The execution resource units have a shared instruction cache 1430, a texture and / or data cache memory 1442, and a shared memory 1446.

[0168] Various components can communicate via interconnect structure 1427. Interconnect structure 1427 may include one or more crossbar switches to enable communication between various components of the graphics multiprocessor 1425. Interconnect structure 1427 may be a separate high-speed network structure layer on which each component of the graphics multiprocessor 1425 is stacked. Components of the graphics multiprocessor 1425 communicate with remote components via interconnect structure 1427. For example, cores 1436A-1436B, 1437A-1437B, and 1438A-1438B may each communicate with shared memory 1446 via interconnect structure 1427. Interconnect structure 1427 may arbitrate communication within the graphics multiprocessor 1425 to ensure fair bandwidth allocation among components.

[0169] Figure 14B The graphics multiprocessor 1450 includes multiple execution resources 1456A-1456D, each of which includes multiple instruction units, register files, GPGPU cores, and load memory units, such as... Figure 13D and Figure 14A As shown in the diagram. Execution resources 1456A-1456D can work in conjunction with one or more texture units 1460A-1460D for texture operations, while sharing instruction cache 1454 and shared memory 1453. For example, execution resources 1456A-1456D can share instruction cache 1454 and shared memory 1453, as well as multiple instances of texture and / or data caches 1458A-1458B. Various components can be connected via... Figure 14A The interconnect structure 1427 communicates with the similar interconnect structure 1452.

[0170] Those skilled in the art will understand that Figure 1 , Figures 13A-13D and Figures 14A-14BThe architecture described herein is descriptive only and does not limit the scope of the current examples. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), and one or more parallel processing units (e.g., Figure 13A Parallel processing unit 1302), and one or more graphics processors or special purpose processing units, without departing from the scope of the examples described herein.

[0171] As described herein, parallel processors or GPGPUs can be communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe, NVLink, or other known, standardized, or proprietary protocols). In other examples, the GPU can be integrated with the core in the same package or on the same chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0172] Figure 14C The illustration shows a graphics processing unit (GPU) 1480 comprising a set of dedicated graphics processing resources arranged in multi-core groups 1465A-1465N. While only details of a single multi-core group 1465A are provided, it will be understood that other multi-core groups 1465B-1465N may be equipped with the same or similar sets of graphics processing resources. The detailed description relating to multi-core groups 1465A-1465N also applies to any of the graphics multiprocessors 1334, 1425, and 1450 described herein.

[0173] As shown in the figure, the multi-core group 1465A may include a set of graphics cores 1470, a set of tensor cores 1471, and a set of ray tracing cores 1472. A scheduler / dispatcher 1468 schedules and dispatches graphics threads for execution on the various cores 1470, 1471, and 1472. A set of register files 1469 may store operand values ​​used by the cores 1470, 1471, and 1472 when executing graphics threads. These registers may include, for example, integer registers for storing integer values, floating-point registers for storing floating-point values, vector registers for storing compressed data elements (integer and / or floating-point data elements), and tile registers for storing tensor / matrix values. The tile registers may be implemented as a combined set of vector registers.

[0174] One or more combined Level 1 (L1) cache and shared memory units 1473 locally store graphics data such as texture data, vertex data, pixel data, ray data, bounded volume data, etc., within each multi-core group 1465A. One or more texture units 1474 can also be used to perform texture rendering operations, such as texture mapping and sampling. A Level 2 (L2) cache 1475 shared by all or a subset of multi-core groups 1465A-1465N can store graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 1475 can be shared among multiple multi-core groups 1465A-1465N. One or more memory controllers 1467 couple the GPU 1480 to memory 1466, which can be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0175] Input / output (I / O) circuitry 1463 couples GPU 1480 to one or more I / O devices 1462, such as a digital signal processor (DSP), network controller, or user input device. On-chip interconnects are used to couple I / O devices 1462 to GPU 1480 and memory 1466. One or more I / O memory management units (IOMMUs) 1464 of I / O circuitry 1463 directly couple I / O devices 1462 to system memory 1466. Optionally, IOMMU 1464 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 1466. I / O devices 1462, CPU(one or more) 1461, and GPU(one or more) 1480 can then share the same virtual address space.

[0176] In one implementation of the IOMMU 1464, the IOMMU 1464 supports virtualization. In this case, it can manage a first set of page tables to map guest / graphics virtual addresses to guest / graphics physical addresses, and a second set of page tables to map guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 1466). The base address of each set of the first and second set of page tables can be stored in a control register and swapped out during context switching (e.g., to allow the new context to access the relevant set of page tables). Although in Figure 14CThere is no illustration, but each core 1470, 1471, 1472 and / or multi-core group 1465A-1465N may include a translation lookaside buffer (TLB) to cache guest virtual to guest physical translation, guest physical to host physical translation, and guest virtual to host physical translation.

[0177] One or more CPUs 1461, GPUs 1480, and I / O devices 1462 may be integrated on a single semiconductor chip and / or chip package. The illustrated memory 1466 may be integrated on the same chip or coupled to the memory controller 1467 via an off-chip interface. In one implementation, memory 1466 includes GDDR6 memory that shares the same virtual address space with other physical system-level memories, but the underlying principles described herein are not limited to this particular implementation.

[0178] Tensor Core 1471 may include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used for performing deep learning operations. For example, synchronous matrix multiplication operations can be used for neural network training and inference. Tensor Core 1471 can perform matrix processing using various operand precisions, including single-precision floating-point (e.g., 32 bits), half-precision floating-point (e.g., 16 bits), integers (16 bits), bytes (8 bits), and half-bytes (4 bits). For example, neural network implementations may extract features from each rendered scene, possibly combining details from multiple frames, to construct a high-quality final image.

[0179] In deep learning implementations, parallel matrix multiplication can be scheduled to be performed on the Tensor Core 1471. Training neural networks, in particular, requires a large number of matrix dot product operations. To handle the inner product formulas of N x N x N matrix multiplications, the Tensor Core 1471 can include at least N dot product processing elements. Before matrix multiplication begins, a complete matrix is ​​loaded into a tile register, and at least one column of the second matrix is ​​loaded in each of the N cycles. In each cycle, N dot products are processed.

[0180] Matrix elements can be stored with different precisions depending on the specific implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the Tensor Core 1471 to ensure the most efficient precision is used for different workloads (e.g., inference workloads, which can tolerate quantization to bytes and nibbles). Supported formats also include 64-bit floating-point (FP64) and non-IEEE floating-point formats, such as bfloat16 (e.g., brain floating-point), a 16-bit floating-point format with one sign bit, eight exponent bits, and eight significant bits, of which seven bits are explicitly stored. One example includes a reduced-precision Tensor-Floating-Point (TF32) mode that performs computations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced-precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance than FP32 and higher precision than FP16. In some examples, one or more 8-bit floating-point formats (FP8) are supported.

[0181] In some examples, Tensor Core 1471 supports sparse operation modes for matrices, where the vast majority of values ​​are zero. Tensor Core 1471 includes support for sparse input matrices encoded in sparse matrix representations (e.g., Coordinate List Encoding (COO), Compacted Sparse Rows (CSR), Compacted Sparse Columns (CSC), etc.). Tensor Core 1471 also includes support for compressed sparse matrix representations where the sparse matrix representation can be further compressed. Compressed, encoded, and / or compressed and encoded matrix data, along with associated compressed and / or encoded metadata, can be read by Tensor Core 1471, and non-zero values ​​can be extracted. For example, for a given input matrix A, non-zero values ​​can be loaded from a compressed and / or encoded representation of at least a portion of matrix A. Based on the position of the non-zero value in matrix A (which can be determined from the index or coordinate metadata associated with the non-zero value), the corresponding value in input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), if the corresponding value is zero, the operation of loading values ​​from input matrix B can be bypassed. In some examples, the pairing of values ​​for certain operations (such as multiplication) can be pre-scanned by the scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the sizes of matrices A and B and the operations to be performed, the output matrix C can be dense or sparse. In the case where the output matrix C is sparse, depending on the configuration of the Tensor Core 1471, the output matrix C can be output in a compressed format, sparse coding, or compressed sparse coding.

[0182] Ray tracing core 1472 accelerates ray tracing operations for both real-time and non-real-time ray tracing implementations. Specifically, ray tracing core 1472 may include ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 1472 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or a similar arrangement). In one implementation, ray tracing core 1472 performs traversal and intersection operations in conjunction with an image denoising technique described herein, at least a portion of which may be executed on tensor core 1471. For example, tensor core 1471 may implement a deep learning neural network to perform denoising on frames generated by ray tracing core 1472. However, CPU(s) 1461, graphics core 1470, and / or ray tracing core 1472 may also implement all or part of the denoising and / or deep learning algorithms.

[0183] Furthermore, as mentioned above, a distributed denoising scheme can be employed, in which the GPU 1480 resides within a computing device coupled to other computing devices via a network or high-speed interconnect. In this distributed scheme, the interconnected computing devices can share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0184] Ray tracing core 1472 can handle all BVH traversals and / or ray primitive intersections, thus preventing graphics core 1470 from being overloaded by thousands of instructions per ray. For example, each ray tracing core 1472 includes a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and / or a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., for traversed intersecting rays). Thus, for example, a multi-core group 1465A can simply initiate ray probes, and ray tracing core 1472 independently performs ray traversal and intersections, returning hit data (e.g., hit, miss, multiple hits, etc.) to the thread context. While ray tracing core 1472 performs traversal and intersection operations, other cores 1470, 1471 are freed up to perform other graphics or computational tasks.

[0185] Optionally, each ray tracing core 1472 may include a traversal unit that performs BVH test operations and / or an intersection unit that performs ray-primitive intersection tests. The intersection unit generates a "hit," "miss," or "multiple hits" response and provides it to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 1470 and tensor core 1471) are freed up to perform other forms of graphics work.

[0186] In some of the examples described below, a hybrid rasterization / ray tracing scheme is used, where the work is distributed between graphics core 1470 and ray tracing core 1472.

[0187] Ray Tracing Core 1472 (and / or other Cores 1470, 1471) may include hardware support for ray tracing instruction sets, such as Microsoft's DirectX Ray Tracing (DXR), which includes DispatchRays commands, as well as ray generation, recent hit, arbitrary hit, and missed shaders, enabling the assignment of unique shader and texture sets to each object. Another ray tracing platform supported by Ray Tracing Core 1472, Graphics Core 1470, and Tensor Core 1471 is the Vulkan API (e.g., Vulkan versions 1.1.85 and later). However, it should be noted that the underlying principles described herein are not limited to any specific ray tracing ISA.

[0188] Generally, various cores 1472, 1471, and 1470 support a ray tracing instruction set, which includes instructions / functions for one or more of the following: ray generation, nearest hit, arbitrary hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exception. More specifically, some examples include ray tracing instructions for performing one or more of the following functions: - Ray generation — Ray generation instructions can be assigned to each pixel, sample, or other user-defined task.

[0189] - Closest Hit - Can execute the closest hit command to locate the nearest intersection point between the ray and a primitive in the scene.

[0190] - Random Hit — The Random Hit command identifies multiple intersections between a ray and primitives within the scene, potentially allowing the identification of new nearest intersections.

[0191] - Intersection — The intersection command performs a ray-primitive intersection test and outputs the result.

[0192] - Per-primitive bounding box construction — This instruction constructs bounding boxes around a given primitive or group of primitives (e.g., when constructing a new BVH or other accelerated data structure).

[0193] - Missed — Indicates that the light missed all geometry within the scene or a specified area of ​​the scene.

[0194] - Visit — Indicates the subvolume that the light ray will traverse.

[0195] - Exceptions — This includes various types of exception handlers (e.g., those invoked for various error conditions).

[0196] In some examples, the ray tracing core 1472 can be used to accelerate general-purpose computational operations that can be accelerated using computational techniques similar to ray intersection testing. A computational framework can be provided that allows shader programs to be compiled into low-level instructions and / or primitives that perform general-purpose computational operations via the ray tracing core. Typical computational problems that can benefit from computational operations performed on the ray tracing core 1472 include calculations involving the propagation of beams, waves, rays, or particles within coordinate space. The interactions associated with this propagation can be calculated relative to geometry or a mesh within coordinate space. For example, calculations associated with the propagation of electromagnetic signals through the environment can be accelerated by using instructions or primitives executed via the ray tracing core. The diffraction and reflection of signals by objects in the environment can be calculated as a direct ray tracing analogy.

[0197] Ray Tracing Core 1472 can also be used to perform computations not directly similar to ray tracing. For example, Ray Tracing Core 1472 can be used to accelerate mesh projection, mesh refinement, and volume sampling computations. It can also perform general coordinate space computations, such as nearest neighbor calculations. For instance, by defining a bounding box in the coordinate space around a given point, the set of points near that point can be discovered. Then, the BVH and ray probing logic within Ray Tracing Core 1472 can be used to determine the set of intersections within the bounding box. These intersections constitute the origin and its nearest neighbors. Computations performed using Ray Tracing Core 1472 can be executed in parallel with computations performed on Graphics Core 1472 and Tensor Core 1471. The shader compiler can be configured to compile computation shaders or other general graphics processing programs into low-level primitives that can be processed in parallel on Graphics Core 1470, Tensor Core 1471, and Ray Tracing Core 1472.

[0198] Building increasingly larger silicon dies is challenging for various reasons. As silicon dies become larger, manufacturing yields decrease, and the process technology requirements for different components may diverge. On the other hand, to achieve high-performance systems, key components must be interconnected through high-speed, high-bandwidth, and low-latency interfaces. These conflicting requirements present challenges to the development of high-performance chips.

[0199] The embodiments described herein provide techniques for decomposing the architecture of an on-chip integrated circuit system into multiple distinct chiplets, which can be packaged onto a shared chassis. In some examples, a graphics processing unit or parallel processor consists of separately manufactured, distinct silicon chiplets. A chiplet is an integrated circuit that is at least partially packaged, comprising different logic units that can be assembled with other chiplets into a larger package. Different groups of chiplets with different IP core logic can be assembled into a single device. Furthermore, active insertion techniques can be used to integrate chiplets into a substrate die or a substrate chiplet. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. The development of IP on different processes can be mixed. This avoids the complexity of converging multiple IPs—especially on large SoCs with diverse IP styles—on the same process.

[0200] This allows for the use of multiple process technologies, improving time-to-market and providing a cost-effective way to create multiple product SKUs. For customers, this means obtaining products that better meet their requirements in a cost-effective and timely manner. Furthermore, decomposed IP is better suited for independent power gating; components not used at a given workload can be de-energized, reducing overall power consumption.

[0201] Figure 15A parallel computing system 1500 is illustrated according to some examples. In some examples, the parallel computing system 1500 includes a parallel processor 1520, which may be a graphics processor or a computing accelerator as described herein. The parallel processor 1520 includes a global logic unit 1501, an interface 1502, a thread dispatcher 1503, a media unit 1504, a set of computing units 1505A-1505H, and a cache / memory unit 1506. The global logic unit 1501 includes, in some examples, global functions of the parallel processor 1520, including device configuration registers, a global scheduler, power management logic, etc. The interface 1502 may include a front-end interface of the parallel processor 1520. The thread dispatcher 1503 may receive workloads from the interface 1502 and dispatch threads of the workloads to the computing units 1505A-1505H. If the workload includes any media operations, at least a portion of these operations may be performed by the media unit 1504. The media unit may also offload some operations to computing units 1505A-1505H. The cache / memory unit 1506 may include cache memory (e.g., L3 cache) and local memory (e.g., HBM, GDDR) for the parallel processor 1520. The computing unit 1505 may include units for one or more of the following: network or communication processor, core, graphics processor, general-purpose graphics processing unit (GPGPU), neural network processing unit (NPU), embedded processor, security processor, cryptographic accelerator, matrix accelerator, in-memory analysis accelerator, compression accelerator, data stream accelerator, etc.

[0202] Figures 16A-16B The illustration shows a hybrid logic / physical view of a decomposed parallel processor based on the example described herein. Figure 16A The diagram illustrates the decomposed parallel computing system 1600. Figure 16B The illustration shows the chip 1630 of the decomposed parallel computing system 1600.

[0203] like Figure 16A As shown, the decomposed parallel computing system 1600 may include a parallel processor 1620, wherein various components of the parallel processor SOC are distributed across multiple granules. Each granule may be a different IP core designed independently, and the IP core is configured to communicate with other granules via one or more common interfaces. Granules include, but are not limited to, compute granule 1605, media granule 1604, and memory granule 1606. Each granule may be manufactured separately using different process technologies. For example, compute granule 1605 may be manufactured using the minimum or most advanced process technology available at the time of manufacture, while memory granule 1606 or other granules (e.g., I / O, networking, etc.) may be manufactured using a larger or less advanced process technology.

[0204] Various chips can be bonded to the substrate die 1610 and configured to communicate with each other and with the logic within the substrate die 1610 via interconnect layer 1612. In some examples, the substrate die 1610 may include global logic 1601, which may include scheduler 1611 and power management 1621 logic units, interface 1602, dispatch unit 1603, and interconnect structure 1608 coupled to or integrated with one or more L3 cache groups 1609A-1609N. Interconnect structure 1608 may be an inter-chip structure integrated into the substrate die 1610. Logic chips can use structure 1608 to pass messages between various chips. Furthermore, the L3 cache groups 1609A-1609N in the substrate die and / or the L3 cache groups within the memory chip 1606 can cache data read from and sent to the DRAM chips within the memory chip 1606 and to the system memory of the host.

[0205] In some examples, global logic 1601 is a microcontroller that executes firmware to perform scheduler 1611 and power management 1621 functions for the parallel processor 1620. The microcontroller executing the global logic can be customized according to the target use case of the parallel processor 1620. Scheduler 1611 can perform global scheduling operations for the parallel processor 1620. The power management 1621 function can be used to enable or disable individual cores within the parallel processor when they are not in use.

[0206] The various chips of the parallel processor 1620 can be designed to perform specific functions that would otherwise be integrated into a single die in existing designs. A set of computing chips 1605 may include a cluster of computing units (e.g., execution units, streaming multiprocessors, etc.) that include programmable logic for executing computations or graphics shader instructions. Media chips 1604 may include hardware logic to accelerate media encoding and decoding operations. Memory chips 1606 may include volatile memory (e.g., DRAM) and one or more SRAM cache memory libraries (e.g., L3 libraries).

[0207] like Figure 16BAs shown, each core 1630 may include common components and application-specific components. Core logic 1636 within core 1630 may include specific components of that core, such as an array of streaming multiprocessor arrays, compute units, or execution units as described herein. Core logic 1636 may be coupled to, or may include within cache or shared local memory 1638. Core 1630 may include a structure interconnect node 1642 that receives commands via an inter-core structure. Commands and data received via structure interconnect node 1642 may be temporarily stored in an interconnect buffer 1639. Data sent to and received from structure interconnect node 1642 may be stored in the interconnect cache 1640. Power control 1632 and clock control 1634 logic may also be included within the core. Power control 1632 and clock control 1634 logic may receive configuration commands via the structure, configuring dynamic voltage and frequency scaling for core 1630. In some examples, each chip can have an independent clock domain and power domain, and can be clock-gated and power-gated independently of other chips.

[0208] At least a portion of the component within the illustrated core 1630 may also be included in the embedded core. Figure 16A The logic within the substrate die 1610. For example, the logic within the substrate die that communicates with the structure may include a version of the structure interconnect node 1642. The substrate die logic that can be independently clocked or power-gated may include a version of the power control 1632 and / or clock control 1634 logic.

[0209] Therefore, while the various examples described herein use the term SOC to describe a device or system having a processor and associated circuitry (e.g., input / output (“I / O”) circuitry, power delivery circuitry, memory circuitry, etc.) monolithically integrated into a single integrated circuit (“IC”) die or chip, this disclosure is not limited in this respect. For example, in various examples of this disclosure, a device or system may have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., input / output (“I / O”) circuitry, power delivery circuitry, etc.) arranged in a disassembled collection of discrete dies, tiles, and / or chips (e.g., one or more discrete processor core dies arranged adjacent to one or more other dies (e.g., memory dies, I / O dies, etc.)). In such disassembled devices and systems, the various dies, tiles, and / or chips may be physically and electrically coupled together by a package structure, which includes, for example, various package substrates, inserts, active inserts, photonic inserts, interconnect bridges, etc. Discrete dies, tiles, and / or cores in a disassembled assembly can also be part of a system-in-package (“SoP”).

[0210] Example Core Architecture—Ordered and Out-of-Order Core Block Diagram Figure 17A The block diagram illustrates both the example ordered pipeline and the example register renaming, out-of-order issue / execution pipeline, based on the example. Figure 17B The block diagram illustrates, based on the example, both the example ordered architecture core and the example register renaming, out-of-order issue / execution architecture core to be included in the processor. Figures 17A-17B The solid boxes in the diagram illustrate ordered pipelines and ordered kernels, while the optional dashed boxes illustrate register renaming, out-of-order issue / execution pipelines, and kernels. Since ordered aspects are a subset of out-of-order aspects, out-of-order aspects will be described.

[0211] exist Figure 17A In this processor pipeline, 1700 includes a fetch phase 1702, an optional length-decode phase 1704, a decode phase 1706, an optional alloc phase 1708, an optional rename phase 1710, a scheduling (also called dispatch or issue) phase 1712, an optional register read / memory read phase 1714, an execution phase 1716, a write-back / memory write phase 1718, an optional exception handling phase 1722, and an optional commit phase 1724. One or more operations can be performed in each of these processor pipeline phases. For example, during the fetch phase 1702, one or more instructions are fetched from instruction memory, and during the decode phase 1706, the fetched instructions can be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) can be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) can be performed. In some examples, the decode phase 1706 and the register read / memory read phase 1714 can be combined into a single pipeline phase. In some examples, during execution phase 1716, decoded instructions can be executed, LSU address / data pipelined to the Advanced Microcontroller Bus (AMB) interface can be executed, multiplication and addition operations can be performed, arithmetic operations with branch results can be performed, and so on.

[0212] As an example, Figure 17BThe example register renaming, out-of-order issue / execution architecture core can implement pipeline 1700 in the following ways: 1) Instruction fetch circuit 1738 performs fetch and length decoding stages 1702 and 1704; 2) Decoding circuit 1740 performs decoding stage 1706; 3) Rename / allocator unit circuit 1752 performs allocation stage 1708 and rename stage 1710; 4) (one or more) scheduler circuit 1756 performs scheduling stage 1712; 5) (one or more) physical register file circuit 1758 and memory unit circuit 1770 perform register read / memory read stage 1714; (one or more) execution cluster 1760 performs execution stage 1716; 6) memory unit circuit 1770 and (one or more) physical register file circuit 1758 perform write-back / memory write stage 1718; 7) Various circuits may be involved in exception handling stage 1722; and 8) retirement unit circuit 1754 and (one or more) physical register file circuit 1758 perform commit stage 1724.

[0213] Figure 17B The processor core 1790 is shown to include a front-end unit circuit 1730 coupled to the execution engine unit circuitry 1750, and both are coupled to the memory unit circuitry 1770. The core 1790 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Alternatively, the core 1790 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0214] Front-end unit circuitry 1730 may include branch prediction circuitry 1732 coupled to instruction cache circuitry 1734, which is coupled to translation lookaside buffer (TLB) 1736, which is coupled to instruction fetch circuitry 1738, which is coupled to decode circuitry 1740. In some examples, instruction cache circuitry 1734 is included in memory unit circuitry 1770 instead of front-end unit circuitry 1730. Decoding circuitry 1740 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as outputs, which are decoded from, or otherwise reflect or are derived from, the original instruction. Decoding circuitry 1740 may also include address generation unit (AGU, not shown) circuitry. In some examples, the AGU uses the forwarded register port to generate the LSU address and can further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). Various different mechanisms can be used to implement the decoding circuit 1740. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In some examples, core 1790 includes a microcode ROM (not shown) or other medium that stores microcode for certain macro instructions (e.g., in the decoding circuit 1740 or otherwise within the front-end unit circuit 1730). In some examples, the decoding circuit 1740 includes micro-ops or operation caches (not shown) to save / cachive decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 1700. The decoding circuit 1740 may be coupled to the rename / allocator unit circuit 1752 in the execution engine unit circuit 1750.

[0215] The execution engine unit circuit 1750 includes a renaming / allocator unit circuit 1752, which is coupled to a retirement unit circuit 1754 and a set of one or more scheduler circuits 1756. The scheduler circuits 1756 represent any number of different schedulers, including reservation stations, central instruction windows, etc. In some examples, the scheduler circuit(s) 1756 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, etc. The scheduler circuit(s) 1756 are coupled to the physical register file circuit(s) 1758. Each of the physical register file circuits 1758 represents one or more physical register files, which store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In some examples, one or more physical register file circuits 1758 include vector register cell circuits, write mask register cell circuits, and scalar register cell circuits. These register cells can provide architectural vector registers, vector mask registers, general-purpose registers, and so on. One or more physical register file circuits 1758 are coupled to retirement cell circuits 1754 (also called retirement queues) to demonstrate various ways that can be used to implement register renaming and out-of-order execution (e.g., utilizing one or more reorder buffers (ROBs) and one or more retirement register files; utilizing one or more future heaps, one or more history buffers, and one or more retirement register files; utilizing register maps and register pools; and so on). Retirement cell circuits 1754 and one or more physical register file circuits 1758 are coupled to one or more execution clusters 1760. One or more execution clusters 1760 include a set of one or more execution cell circuits 1762 and a set of one or more memory access circuits 1764. One or more execution unit circuits 1762 can perform various arithmetic, logical, floating-point, or other types of operations (e.g., shift, addition, subtraction, multiplication) on various types of data (e.g., scalar integers, scalar floating-points, compressed integers, compressed floating-points, vector integers, vector floating-points). In some examples, execution unit circuits 1762 may include hardware to support the functionality of instructions for one or more of the following: compression engine, graphics processing, neural network processing, in-memory analysis, matrix operations, cryptographic operations, data stream operations, data graph operations, etc.

[0216] While some examples may include several execution units or execution unit circuits dedicated to a specific function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that perform all functions. One or more scheduler circuits 1756, one or more physical register file circuits 1758, and one or more execution clusters 1760 are shown as potentially multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each with its own scheduler circuit, one or more physical register file circuits, and / or execution clusters—and in the case of separate memory access pipelines, in some examples of implementations, only the execution cluster of that pipeline has one or more memory access unit circuits 1764). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be issued / executed out of order, while the rest are ordered.

[0217] In some examples, the execution engine unit circuit 1750 can perform load memory unit (LSU) address / data pipelined operations to the Advanced Microcontroller Bus (AMB) interface (not shown), as well as address phases and write-back, data phase load, store, and branch.

[0218] A set of memory access circuitry 1764 is coupled to memory cell circuitry 1770, which includes data TLB circuitry 1772, which is coupled to data cache circuitry 1774, which is coupled to Level 2 (L2) cache circuitry 1776. In some examples, memory access circuitry 1764 may include load cell circuitry, memory address cell circuitry, and memory data cell circuitry, each of which is coupled to data TLB circuitry 1772 in memory cell circuitry 1770. Instruction cache circuitry 1734 is further coupled to Level 2 (L2) cache circuitry 1776 in memory cell circuitry 1770. In some examples, instruction cache 1734 and data cache 1774 are combined into L2 cache circuitry 1776, Level 3 (L3) cache circuitry (not shown), and / or a single instruction and data cache (not shown) in main memory. L2 cache circuitry 1776 is coupled to one or more other levels of cache and ultimately coupled to main memory.

[0219] Core 1790 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions added with later versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions, such as NEON, etc.); RISC instruction set architecture), including one or more instructions described herein. In some examples, Core 1790 includes logic supporting compact data instruction set architecture extensions (e.g., AVX1, AVX2, AVX512, AMX, etc.), thereby allowing the use of compact data to perform operations used by many multimedia applications.

[0220] Example execution unit circuit Figure 18 Examples of execution unit circuits (one or more) are illustrated, such as Figure 17B The execution unit circuit (one or more) 1762. As shown, the execution unit circuit (one or more) 1762 may include one or more ALU circuits 1801, optional vector / single instruction multiple data (SIMD) circuits 1803, load / store circuits 1805, branch / jump circuits 1807, and / or floating-point unit (FPU) circuits 1809. The ALU circuits 1801 perform integer arithmetic and / or Boolean operations. The vector / SIMD circuits 1803 perform vector / SIMD operations on compressed data (e.g., SIMD / vector registers). The load / store circuits 1805 execute load and store instructions to load data from memory into registers or store data from registers into memory. The load / store circuits 1805 may also generate addresses. The branch / jump circuits 1807 cause a branch or jump to a memory address depending on the instruction. The FPU circuits 1809 perform floating-point arithmetic. The width of the (one or more) execution unit circuits 1762 varies depending on the example and can range from, for example, 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0221] Example Register Architecture Figure 19This is a block diagram of register architecture 1900 based on some examples. As shown, register architecture 1900 includes vector / SIMD registers 1910, with widths ranging from 128 bits to 1024 bits. In some examples, vector / SIMD register 1910 is physically 512 bits, and depending on the mapping, only some low-order bits are used. For example, in some examples, vector / SIMD register 1910 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. Therefore, register overriding exists. In some examples, the vector length field is chosen between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length. Scalar operations are performed on the lowest-order data element positions in the ZMM / YMM / XMM registers; higher-order data element positions are either preserved as they were before the instruction or zeroed out, depending on the example.

[0222] In some examples, the register architecture 1900 includes a write mask / predicate register 1915. For example, in some examples, there are eight write mask / predicate registers (sometimes referred to as k0 to k7), each with a size of 16 bits, 32 bits, 64 bits, or 128 bits. The write mask / predicate register 1915 may allow merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 1915 corresponds to a data element position in the destination. In other examples, the write mask / predicate register 1915 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0223] The Register Architecture 1900 includes several general-purpose registers 1925. These registers can be 16-bit, 32-bit, 64-bit, etc., and can be used for scalar operations. In some examples, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0224] In some examples, register architecture 1900 includes a scalar floating-point (FP) register file 1945, which is used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set architecture extension, or as an MMX register to perform operations on 64-bit compressed integer data, and to store operation objects for some operations performed between the MMX and XMM registers.

[0225] One or more flag registers 1940 (e.g., EFLAGS, RFLAGS, etc.) store status and control information used for arithmetic, comparison, and system operations. For example, one or more flag registers 1940 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 1940 are referred to as program status and control registers.

[0226] Segment register 1920 contains segment points used to access memory. In some examples, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0227] Model-specific registers (MSRs) 1935 control and report processor performance. Most MSRs 1935 handle system-related functions and are inaccessible to applications. For example, an MSR may provide control over one or more of the following: performance monitoring counters, debug extensions, memory type range registers, thermal management and power management, instruction-specific support, and / or processor feature / mode support. The Machine Check Register 1960 consists of control, status, and error reporting MSRs used for detecting and reporting hardware errors. One or more control registers 1955 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processors 1070, 1080, 1038, 1015, and / or 1100) and the characteristics of the currently executing task. In some examples, MSRs 1935 are a subset of control registers 1955.

[0228] One or more instruction pointer registers 1930 store instruction pointer values. Debug register 1950 controls and allows monitoring of debug operations on the processor or core.

[0229] The memory management registers 1965 specify the location of data structures used in protected-mode memory management. These registers may include the global descriptor table register (GDTR), the interrupt descriptor table register (IDTR), the task register, and the local descriptor table register (LDTR).

[0230] Alternative examples may use wider or narrower registers. Furthermore, alternative examples may use more, fewer, or different register files and registers. Register architecture 1900 may be used, for example, in registers or in physical register file circuitry 1758.

[0231] Instruction set architecture An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) to specify the operation to be performed (e.g., opcode) and the operand(s) to be performed on, and / or other data fields(e.g., mask), etc. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined as having different subsets of the fields of that instruction format (the included fields are usually in the same order, but at least some have different bit positions because fewer fields are included) and / or be defined as having given fields interpreted in different ways. Thus, each instruction in an ISA is expressed using a given instruction format (and, if defined, as a given instruction template in the instruction templates of that instruction format) and includes fields for specifying the operation and operand. For example, the sample ADD instruction has a specific opcode and instruction format, which includes an opcode field to specify the opcode and an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field that selects the specific operand. Furthermore, although the following description is made in the context of an x86 ISA, it is within the knowledge of those skilled in the art to apply the teachings of this disclosure to other ISAs.

[0232] Example instruction format Examples of the instructions(s) described herein can be implemented in different formats. Furthermore, example systems, architectures, and pipelines are detailed below. The examples of the instructions(s) can be executed on these systems, architectures, and pipelines, but are not limited to those detailed herein.

[0233] Figure 20 An example of an instruction format is illustrated. As shown, an instruction may include multiple components, including but not limited to one or more fields for: one or more prefixes, opcodes, addressing information (e.g., register identifiers, memory addressing information, etc.), offset values, and / or immediate values. Note that some instructions utilize some or all of the fields of this format, while others may use only the fields of opcode 2003. In some examples, the order shown is the order in which these fields are encoded; however, it should be understood that in other examples, these fields may be encoded in a different order, combined, etc.

[0234] One or more prefixes of 2001 modify instructions when used. In some examples, one or more prefixes are used for repeating string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), providing section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), performing bus locking operations, and / or changing the operand (e.g., 0x66) and address size (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered "traditional" prefixes. Other prefixes (one or more examples of which are detailed herein) indicate and / or provide further capabilities, such as specifying particular registers, etc. These other prefixes typically follow "traditional" prefixes.

[0235] The opcode field 2003 is used to at least partially define the operation to be performed during instruction decoding. In some examples, the main opcode encoded in the opcode field 2003 is one, two, or three bytes long. In other examples, the main opcode can be of other lengths. An additional 3-bit opcode field is sometimes encoded in another field.

[0236] The addressing information field 2005 is used to address one or more operands of an instruction, such as a location in memory or one or more registers. Figure 21An example of the addressing information field 2005 is illustrated. This illustration shows the optional MOD R / M byte 2102 and the optional Scale, Index, Base (SIB) byte 2104. The MOD R / M byte 2102 and SIB byte 2104 are used to encode up to two operands of an instruction, each operand being either a direct register or an effective memory address. Note that these fields are optional; that is, not all instructions include one or more of these fields. The MOD R / M byte 2102 includes the MOD field 2142, the register field 2144, and the R / M field 2146.

[0237] The contents of MOD field 2142 distinguish between memory access and non-memory access modes. In some examples, when MOD field 2142 has a binary value of 11 (11b), register direct addressing mode is used; otherwise, register indirect addressing mode is used.

[0238] Register field 2144 can encode a destination register operand or a source register operand, or it can encode an opcode extension without being used to encode any instruction operand. The contents of register field 2144 directly specify or are generated from an address to specify the location of the source or destination operand (in a register or in memory). In some examples, register field 2144 is supplemented with extra bits from a prefix (e.g., prefix 2001) to allow for larger addressing.

[0239] R / M field 2146 can be used to encode instruction operands that reference memory addresses, or it can be used to encode destination register operands or source register operands. Note that in some examples, R / M field 2146 can be combined with MOD field 2142 to specify the addressing mode.

[0240] SIB byte 2104 includes a scaling field 2152, an index field 2154, and a base field 2156 for address generation. The scaling field 2152 indicates a scaling factor. The index field 2154 specifies the index register to be used. In some examples, the index field 2154 is supplemented with extra bits from the prefix (e.g., prefix 2001) to allow for larger addressing. The base field 2156 specifies the base address register to be used. In some examples, the base field 2156 is supplemented with extra bits from the prefix (e.g., prefix 2001) to allow for larger addressing. In practice, the contents of the scaling field 2152 allow scaling of the contents of the index field 2154 for memory address generation (e.g., for addresses using 2...). 缩放 * Address generation from index + base address.

[0241] Some addressing schemes use bitwise shift values ​​to generate memory addresses. For example, they can be based on 2 缩放 * Memory addresses are generated using index + base address + offset, index * scaling + offset, r / m + offset, instruction pointer (RIP / EIP) + offset, register + offset, etc. The offset can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some examples, the offset field 2007 provides this value. Additionally, in some examples, the use of an offset factor is encoded in the MOD field of the addressing information field 2005, which indicates a compact offset scheme for which the offset value is calculated and stored in the offset field 2007.

[0242] In some examples, the Immediate Numeric field 2009 specifies an immediate numeric value for the instruction. Immediate numeric values ​​can be encoded as 1-byte values, 2-byte values, 4-byte values, and so on.

[0243] Figures 22(A)-22(B) An example of the first prefix 2001(A) is illustrated. Figure 22(A) illustrates a first example of the first prefix 2001(A). In some examples, the first prefix 2001(A) is an example of the REX prefix. Instructions using this prefix can specify general-purpose registers, 64-bit compact data registers (e.g., single instruction multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0244] Instructions using the first prefix 2001(A) can specify up to three registers using 3-bit fields, depending on the format: 1) using reg field 2144 and R / M field 2146 of MOD R / M byte 2102; 2) using MOD R / M byte 2102 with SIB byte 2104, including using reg field 2144 as well as base address field 2156 and index field 2154; or 3) using the register field of the opcode.

[0245] In the first prefix 2001(A), bit positions 7:4 of the payload byte are set to 0100. Bit position 3 (W) can be used to determine the operand size, but cannot determine the operand width alone. Therefore, when W = 0, the operand size is determined by the code segment descriptor (CS.D), while when W = 1, the operand size is 64 bits.

[0246] Note that adding another bit allows addressing 16(2) 4The MOD R / M reg field 2144 and MOD R / MR / M field 2146 can each address 8 registers, while the individual MOD R / M reg field 2144 and MOD R / MR / M field 2146 can each address 8 registers.

[0247] In the first prefix 2001(A), bit position 2(R) can be an extension of the MOD R / M reg field 2144, and can be used to modify the MOD R / M reg field 2144 when this field encodes a general-purpose register, a 64-bit compressed data register (e.g., an SSE register), or a control or debug register. R is ignored when the MOD R / M byte 2102 specifies other registers or defines extended opcodes.

[0248] Bit position 1 (X) can modify SIB byte index field 2154.

[0249] Setting bit position 0 (B) can modify the base address in the R / M field 2146 of MOD R / M or the SIB byte base address field 2156; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 1925).

[0250] Figure 22(B) illustrates a second example of the first prefix 2001(A). In some examples, prefix 2001(A) supports addressing of 32 general-purpose registers. In some examples, this prefix is ​​referred to as REX2.

[0251] In some examples, one or more instructions for increment, decrement, invert, addition, subtraction, AND, OR, XOR, arithmetic left shift, logical left shift, arithmetic right shift, logical right shift, left circular shift, right circular shift, multiplication, division, population counting, leading zero counting, total zero counting, etc., support flag suppression.

[0252] In some examples, one or more instructions for increment, decrement, NOT, invert, addition, addition with carry, integer subtraction with borrow, subtraction, AND, OR, XOR, arithmetic left shift, logical left shift, arithmetic right shift, logical right shift, left circular shift, right circular shift, multiplication, division, population counting, leading zero counting, total zero counting, unsigned integer addition of two operands with carry flag, unsigned integer addition of two operands with overflow flag, conditional move, pop, push, etc., support REX2.

[0253] As shown in the figure, REX2 has a format field 2203 in the first byte and 8 bits in the second byte (e.g., the payload byte). In some examples, the value of the format field 303 is 0xD5. In some examples, 0xD5 encodes the ASCII Adjust AX Before Division (AAD) instruction in 32-bit mode. In these examples, it is used as the first byte of the prefix in 64-bit mode, as shown in Figure 22(B).

[0254] The payload byte consists of several bits.

[0255] Bit position 0 (B3) can modify the base address in the R / M field 2146 of MOD R / M or the SIB byte base address field 2156; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 1925).

[0256] Bit position 1 (X3) can modify SIB byte index field 2154.

[0257] Bit position 2 (R3) can be used as an extension of MOD R / M reg field 2144, and can be used to modify MOD R / M reg field 2144 when this field encodes a general-purpose register, a 64-bit compressed data register (e.g., an SSE register), or a control or debug register. R3 can be ignored when MOD R / M byte 2102 specifies other registers or defines extended opcodes.

[0258] Bit position 3 (W) can be used to determine the size of the operand, but it cannot determine the width of the operand alone. Therefore, when W = 0, the size of the operand is determined by the code segment descriptor (CS.D), while when W = 1, the size of the operand is 64 bits.

[0259] Bit position 4 (B4) can further (together with B3) modify the base address in the R / M field 2146 of MOD R / M or the SIB byte base address field 2156; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 1925).

[0260] Bit position 5 (X4) can be further modified (together with X3) of SIB byte index field 2154.

[0261] Bit position 6 (R4) can be further used (together with R3) as an extension of MOD R / M reg field 2144, and can be used to modify MOD R / M reg field 2144 when the field encodes a general-purpose register, a 64-bit compressed data register (e.g., an SSE register), or a control or debug register.

[0262] In some examples, bit position 7 (M0) indicates the opcode pattern (e.g., 0 or 1).

[0263] R3, R4, X3, X4, B3, and B4 allow addressing of 32 GPRs. That is, the R, X, or B register identifier is extended by the R3, X3, and B3 bits and the R4, X4, and B4 bits in the REX2 prefix only if it encodes a GPR register. In some examples, vector (or any other type of) register is not encoded using these bits.

[0264] In some examples, REX2 must be the final prefix, and the bytes following it are interpreted as the major opcode byte indicated by M0 in the opcode diagram. Neither 0x0F escape bytes are required nor permitted. In some examples, prefixes that may precede REX2 include LOCK (0xF0), REPE / REP / REPZ (0xF3), REPNE / REPNZ (0xF2), operand size overrun (0x66), address size overrun (0x67), and segment overrun.

[0265] Generally, REX2 bits R4, X4, B4, R3, X3, and B3 are ignored when none are used. For example, X4 and X3 are ignored when there is no index register. Similarly, R4, X4, or B4 bits are ignored when the R, X, or B register identifier encodes a vector register. However, in some examples, there are one or two exceptions to this general rule: 1) attempting to access a non-existent control or debug register will trigger #UD; and 2) instructions with opcodes 0x50-0x5F (including POP and PUSH) use R4 to encode push-pop acceleration prompts.

[0266] Figures 23(A)-23(D)The figures illustrate examples of how the R, X, and B fields of the first prefix 2001(A) are used. Figure 23(A) illustrates how the R and B from the first prefix 2001(A) are used to extend the reg field 2144 and R / M field 2146 of the MOD R / M byte 2102 when SIB byte 2104 is not used for memory addressing. Figure 23(B) illustrates how the R and B from the first prefix 2001(A) are used to extend the reg field 2144 and R / M field 2146 of the MOD R / M byte 2102 (register-to-register addressing) when SIB byte 2104 is not used. Figure 23(C) illustrates how the R, X, and B from the first prefix 2001(A) are used to extend the reg field 2144, index field 2154, and base address field 2156 of the MOD R / M byte 2102 when SIB byte 2104 is used for memory addressing. Figure 23(D) illustrates that when the register is encoded in opcode 2003, the B from the first prefix 2001(A) is used to extend the reg field 2144 of the MOD R / M byte 2102. The R4 and R3 values ​​in Figure 22(B) can be used to extend rrr, B4 and B3 can be used to extend bbb, and X4 and X3 can be used to extend xxx.

[0267] Figures 24A-24B An example of the second prefix 2001(B) is illustrated. In some examples, the second prefix 2001(B) is an example of the VEX prefix. The second prefix 2001(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD register 1910) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 2001(B) provides a syntax for three operands (or more). For example, the previous two-operand instructions performed operations such as A = A + B, which overwrote the source operands. The use of the second prefix 2001(B) allows operands to perform non-destructive operations, such as A = B + C.

[0268] In some examples, the second prefix 2001(B) has two forms—two-byte and three-byte. The two-byte second prefix 2001(B) is mainly used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 2001(B) provides a compact replacement for 3-byte opcode instructions and the first prefix 2001(A).

[0269] Figure 24AAn example of the two-byte form of the second prefix 2001(B) is illustrated. In some examples, format field 2401 (byte 0 2403) contains the value C5H. In some examples, byte 1 2405 includes the value “R” in bit [7]. This value is the complement of the value of “R” in the first prefix 2001(A). Bit [2] is used to specify the length (L) of the vector (where the value of 0 is a scalar or a 128-bit vector, and the value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). The bits [6:3] shown as vvvv can be used to: 1) encode the first source register operand, which is specified in reverse (ones complement) form, for instructions with two or more source operands; 2) encode the destination register operand, which is specified in ones complement form, for some vector shift; or 3) not encode any operand, in which case the field is reserved and should contain a value such as 1111b.

[0270] Instructions using this prefix can use the MOD R / MR / M field 2146 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0271] Instructions using this prefix can use the MOD R / M reg field 2144 to encode either the destination register operand or the source register operand, or they can be treated as an opcode extension without being used to encode any instruction operand.

[0272] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 2146, and MOD R / M reg field 2144 encode three of the four operands. Then, bits [7:4] of the immediate value field 2009 are used to encode the third source register operand.

[0273] Figure 24B The diagram illustrates an example of the three-byte form of the second prefix 2001(B). In some examples, format field 2411 (bytes 0-2413) contains the value C4H. Byte 1 2415 includes “R”, “X”, and “B” in bits [7:5], which are the complements of these values ​​in the first prefix 2001(A). Bits [4:0] of byte 1 2415 (shown as mmmmm) include what is encoded to encode one or more implicit preamble opcode bytes as needed. For example, 00001 means 0FH preamble opcode, 00010 means 0F38H preamble opcode, 00011 means 0F3AH preamble opcode, and so on.

[0274] The use of bits [7] in byte 2 2417 is similar to that of W in the first prefix 2001(A), including helping to determine the size of the operand that can be promoted. Bit [2] is used to specify the length (L) of the vector (where the value of 0 is a scalar or a 128-bit vector, and the value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3] shown as vvvv can be used to: 1) encode the first source register operand, which is specified in reverse (ones complement) form, valid for instructions with two or more source operands; 2) encode the destination register operand, which is specified in ones complement form, for some vector shift; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0275] Instructions using this prefix can use the MOD R / MR / M field 2146 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0276] Instructions using this prefix can use the MOD R / M reg field 2144 to encode either the destination register operand or the source register operand, or they can be treated as an opcode extension without being used to encode any instruction operand.

[0277] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 2146, and MOD R / M reg field 2144 encode three of the four operands. Then, bits [7:4] of the immediate value field 2009 are used to encode the third source register operand.

[0278] Figure 25 The illustration shows an example of the third prefix 2001(C). In some examples, the third prefix 2001(C) is an example of the EVEX prefix. The third prefix 2001(C) is a four-byte prefix.

[0279] The third prefix 2001(C) enables the encoding of 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, write masks / operation masks are used (see the discussion of registers in the previous diagrams, e.g.) Figure 19Instructions that use predicates or operations utilize this prefix. Operation mask registers allow conditional processing or selection control. Operation mask instructions—whose source / destination operands are operation mask registers and whose contents are treated as a single value—are encoded using the second prefix 2001(B).

[0280] The third prefix 2001(C) can encode instruction class-specific features (e.g., a compact instruction with "load + operation" semantics can support embedded broadcast functionality, a floating-point instruction with rounding semantics can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics can support "suppress all exceptions" functionality, etc.).

[0281] The first byte of the third prefix 2001(C) is the format field 2511, which has a value of 62H in some examples. The subsequent bytes are called payload bytes 2515-2519, and together they form the 24-bit value of P[23:0], which provides specific capabilities in the form of one or more fields (detailed herein).

[0282] In some examples, P[1:0] of payload byte 2519 is the same as the two lower mm bits. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the high 16 vector register set when combined with P[7] and MOD R / M reg field 2144. P[6] can also provide access to the high 16 vector registers when SIB type addressing is not required. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general-purpose registers, and memory addressing, and when combined with MOD R / M register field 2144 and MOD R / MR / M field 2146, allows access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). P

[10] is a fixed value of 1 in some examples. P[14:11], shown as vvvv, can be used to: 1) encode the first source register operand, which is specified in reverse (ones complement) form, for instructions with two or more source operands; 2) encode the destination register operand, which is specified in ones complement form, for some vector shift; or 3) not encode any operand, in which case the field is reserved and should contain a value such as 1111b.

[0283] P

[15] is similar to W of the first prefix 2001(A) and the second prefix 2001(B), and can be used as an opcode extension bit or an operand size boost.

[0284] P[18:16] specifies the index of the register in the operation mask (write mask) register (e.g., write mask / predicate register 1915). In some examples, the specific value aaa = 000 has special behavior, implying that no operation mask is used for that particular instruction (this can be achieved in various ways, including using a hard-wired operation mask to all one or hardware that bypasses the masking hardware). When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and enhanced operations); in some other examples, the old value of each element in the destination is preserved at the element where the corresponding mask bit has a value of 0. In contrast, when zeroed out, the vector mask allows any set of elements in the destination to be zeroed out during the execution of any operation (specified by the basic and enhanced operations); in some examples, the elements in the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the length of the vector being operated on (i.e., the span of the modified elements, from the first to the last); however, the modified elements do not necessarily have to be contiguous. Thus, the operation mask field allows for some vector operations, including load, store, arithmetic, logical, and so on. While in the described example, the content of the operation mask field selects the one among several operation mask registers containing the operation mask to be used (thus the content of the operation mask field indirectly identifies the mask to be performed), alternatively or additionally, alternative examples allow the content of the mask write field to directly specify the mask to be performed.

[0285] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that allows access to the high 16 vector registers using P

[19] . P

[20] encodes various functions that differ across different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0286] The table below details examples of register encoding in instructions using the third prefix 2001(C).

[0287] Table 2: Encoding Register Specify in 32-bit Mode Table 3: Operation Mask Register Specifier Encoding Graphics Execution Unit Figures 26A-26BThe illustration shows thread execution logic 2600 of an array of processing elements employed in a graphics processor core, as described in this article. Figures 26A-26B Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 26A Represents the execution unit within a general-purpose graphics processing unit, while Figure 26B This represents an execution unit that can be used within a computing accelerator.

[0288] like Figure 26A As shown, in some examples, thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, a scalable execution unit array including multiple execution units 2608A-2608N, a sampler 2610, shared local memory 2611, a data cache 2612, and a data port 2614. In some examples, the scalable execution unit array can be dynamically scaled based on the computational requirements of the workload by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D through 2608N-1 and 2608N). In some examples, the included components are interconnected via an interconnect structure linking to each component. In some examples, thread execution logic 2600 includes one or more connections to memory (e.g., system memory or cache memory) via one or more of the instruction cache 2606, data port 2614, sampler 2610, and execution units 2608A-2608N. In some examples, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In various examples, the array of execution units 2608A-2608N can be scaled to include any number of individual execution units.

[0289] In some examples, execution units 2608A-2608N are primarily used to execute shader programs. Shader processor 2602 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2604. In some examples, the thread dispatcher includes logic for arbitrating thread requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units in execution units 2608A-2608N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some examples, thread dispatcher 2604 can also handle runtime thread derivation requests from executing shader programs.

[0290] In some examples, the instruction set supported by the Execution Units 2608A-2608N includes native support for many standard 3D graphics shader instructions, requiring only minimal translation when executing shader programs from graphics libraries such as Direct3D and OpenGL. The Execution Unit supports vertex and geometry processing (e.g., vertex routines, geometry routines, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the Execution Units 2608A-2608N is capable of multiple-issue single-instruction multiple-data (SIMD) execution and multi-threaded operation, enabling an efficient execution environment when faced with higher latency memory accesses. Each hardware thread within each Execution Unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issued to the pipeline per clock cycle, enabling integer, single-precision, and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or a shared function, the dependency logic within the execution unit 2608A-2608N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread sleeps, hardware resources can be used to process other threads. For example, during the latency associated with vertex shader operations, the execution unit can perform operations for pixel shaders, fragment shaders, or other types of shader programs, including different vertex shaders. Various examples can be applied to the use of execution by using Single Instruction Multithreading (SIMT) as an alternative to or an addition to SIMD. References to the SIMD core or operations can also be applied to SIMD or a combination of SIMD and SIMD.

[0291] Each execution unit in the 2608A-2608N operates on an array of data elements. The number of data elements is the "execution size," or the number of instruction channels. An execution channel is a logical execution unit used for data element access, masking, and flow control within instructions. The number of channels can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) of a particular graphics processor. In some examples, the 2608A-2608N execution units support both integer and floating-point data types.

[0292] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process each element based on its data size. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit will operate on the vector as four separate 64-bit compact data elements (four-word (QW) size data elements), eight separate 32-bit compact data elements (double-word (DW) size data elements), sixteen separate 16-bit compact data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0293] In some examples, one or more execution units can be combined into fused graphics execution units 2609A-2609N, which have thread control logic (2607A-2607N) shared by fused EUs. Multiple EUs can be fused into EU groups. Each EU in a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary depending on the example. Furthermore, various SIMD widths can be executed for each EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, fused execution unit 2609A includes a first EU 2608A, a second EU 2608B, and thread control logic 2607A shared by the first EU 2608A and the second EU 2608B. The thread control logic 2607A controls the threads executing on the fused graphics execution unit 2609A, allowing each EU within the fused execution units 2609A-2609N to use a shared instruction pointer register for execution.

[0294] The thread execution logic 2600 includes one or more internal instruction caches (e.g., 2606) to cache thread instructions for the execution unit. In some examples, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. Threads executing on the thread execution logic 2600 may also store explicitly managed data in shared local memory 2611. In some examples, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some examples, the sampler 2610 includes dedicated texture or media sampling functions to process texture or media data during the sampling process and then provide the sampled data to the execution unit.

[0295] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2600 via thread derivation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic within shader processor 2602 (e.g., pixel shader logic, fragment shader logic, etc.) is invoked to further compute output information and write the results to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some examples, the pixel shader or fragment shader computes values ​​for various vertex attributes to be interpolated on the rasterized objects. In some examples, the pixel processor logic within shader processor 2602 then executes the pixel or fragment shader program provided by the application programming interface (API). To execute the shader program, shader processor 2602 dispatches threads to execution units (e.g., 2608A) via thread dispatcher 2604. In some examples, shader processor 2602 uses texture sampling logic in sampler 2610 to access texture data in a texture map stored in memory. Arithmetic operations performed on texture data and input geometry data will calculate the pixel color data for each geometric fragment, or discard one or more pixels without further processing.

[0296] In some examples, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In some examples, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) to cache data for memory access via the data port.

[0297] In some examples, the execution logic 2600 may also include a ray tracer 2605, which can provide ray tracing acceleration capabilities. The ray tracer 2605 may support a ray tracing instruction set, which includes instructions / functions for ray generation.

[0298] Figure 26BThe illustration shows exemplary internal details of an execution unit 2608 according to an example. The graphics execution unit 2608 may include an instruction fetch unit 2637, a general register file array (GRF) 2624, an architectural register file array (ARF) 2626, a thread arbiter 2622, a send unit 2630, a branch unit 2632, a set of SIMD floating point units (FPUs) 2634, and, in some examples, a set of dedicated integer SIMD ALUs 2635. The GRF 2624 and ARF 2626 include a set of general register files and architectural register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2608. In some examples, the per-thread architectural state is maintained in the ARF 2626, while data used during thread execution is stored in the GRF 2624. The execution state of each thread, including the instruction pointer for each thread, may be stored in thread-specific registers within the ARF 2626.

[0299] In some examples, the architecture of the graphics execution unit 2608 is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). This architecture features a modular configuration that can be fine-tuned at design time based on a target number of concurrent threads and the number of registers per execution unit, where execution unit resources are divided among logic for executing multiple concurrent threads. The number of logical threads that the graphics execution unit 2608 can execute is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0300] In some examples, the graphics execution unit 2608 can issue multiple instructions collectively, each of which can be a different instruction. The thread arbiter 2622 of the graphics execution unit thread 2608 can dispatch instructions to one of the sending unit 2630, the branching unit 2632, or one or more SIMD FPUs 2634 for execution. Each execution thread can access 128 general-purpose registers within the GRF 2624, each register storing 32 bytes, which can be accessed as a SIMD 8-element vector of 32-bit data elements. In some examples, each execution unit thread can access 4KB of data within the GRF 2624, but this is not a limitation; more or fewer register resources may be available in other examples. In some examples, the graphics execution unit 2608 is partitioned into seven hardware threads, which can perform computational operations independently, but the number of threads per execution unit can vary depending on the example. For example, in some examples, up to 16 hardware threads are supported. In the example where seven threads can access 4KB, the GRF 2624 can store a total of 28KB. With 16 threads able to access 4KB, the GRF 2624 can store a total of 64KB. Its flexible addressing modes allow registers to be addressed together, enabling the efficient construction of wider registers or representations of straddle-shaped block data structures.

[0301] In some examples, memory operations, sampler operations, and other long-delay system communications are dispatched via “send” instructions, which are executed by message passing unit 2630. In some examples, branch instructions are dispatched to dedicated branch unit 2632 to facilitate SIMD divergence and eventual convergence.

[0302] In some examples, the graphics execution unit 2608 includes one or more SIMD FPUs 2634s to perform floating-point operations. In some examples, the FPU(s) 2634 also support integer calculations. In some examples, the FPU(s) 2634 can perform up to [number missing] SIMD operations. M A maximum of 32-bit floating-point (or integer) operations, or SIMD execution up to 2 M Each operation consists of 16-bit integer or 16-bit floating-point operations. In some examples, at least one of the FPUs provides extended mathematical capabilities to support high throughput beyond mathematical functions and double-precision 64-bit floating-point operations. In some examples, there is also a set of 8-bit integer SIMD ALUs 2635, and these ALUs are specifically optimized to perform operations associated with machine learning computations.

[0303] In some examples, an array of multiple instances of the graphics execution unit 2608 can be instantiated within a graphics sub-core group (e.g., a sub-slice). For scalability, the product architect can choose the exact number of execution units for each sub-core group. In some examples, the execution unit 2608 can execute instructions across multiple execution channels. In another example, each thread executing on the graphics execution unit 2608 executes on a different channel.

[0304] Figure 27 The illustration shows an additional execution unit 2700 according to one example. In some examples, execution unit 2700 includes a thread control unit 2701, a thread status unit 2702, an instruction fetch / prefetch unit 2703, and an instruction decoding unit 2704. Execution unit 2700 also includes a register file 2706 that stores registers that can be assigned to hardware threads within the execution unit. Execution unit 2700 also includes a send unit 2707 and a branch unit 2708. In some examples, the operation of send unit 2707 and branch unit 2708 may be similar to... Figure 26B The graphics execution unit 2608 includes a sending unit 2630 and a branching unit 2632.

[0305] The execution unit 2700 also includes a computation unit 2710, which comprises multiple functional units of different types. In some examples, the computation unit 2710 includes an ALU unit 2711, which includes an array of arithmetic logic units. The ALU unit 2711 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations can be performed simultaneously. The computation unit 2710 may also include a systolic array 2712 and a mathematical unit 2713. The systolic array 2712 includes... W Width D A deep network of data processing units (CPUs) that can be used to perform vector or other data-parallel operations in a systolic manner. In some examples, the systolic array 2712 may be configured to perform matrix operations, such as matrix dot product operations. In some examples, the systolic array 2712 supports 16-bit floating-point operations, as well as 8-bit and 4-bit integer operations. In some examples, the systolic array 2712 may be configured to accelerate machine learning operations. In such examples, the systolic array 2712 may be configured to support the bfloat 16-bit floating-point format. In some examples, a math unit 2713 may be included to perform a specific subset of mathematical operations in a more efficient and lower-powered manner than the ALU unit 2711. The math unit 2713 may include a variant of mathematical logic that can be found in the shared functional logic of the graphics processing engines provided in other examples. In some examples, the math unit 2713 may be configured to perform 32-bit and 64-bit floating-point operations.

[0306] The thread control unit 2701 includes logic for controlling the execution of threads within the execution unit. The thread control unit 2701 may include thread arbitration logic to start, stop, and preempt the execution of threads within the execution unit 2700. The thread state unit 2702 can be used to store the thread states of threads assigned to execute on the execution unit 2700. Storing thread states within the execution unit 2700 allows for rapid preemption of threads when they become blocked or idle. The instruction fetch / prefetch unit 2703 can retrieve instructions from the instruction cache of higher-level execution logic (e.g., such as...). Figure 26A The instruction cache 2606 shown in the diagram fetches instructions. The instruction fetch / prefetch unit 2703 can also issue a prefetch request to load instructions into the instruction cache based on analysis of the currently executing thread. The instruction decoding unit 2704 can be used to decode instructions to be executed by the computation unit. In some examples, the instruction decoding unit 2704 can be used as a two-level decoder to decode complex instructions into component micro-operations.

[0307] Execution unit 2700 also includes register file 2706, which can be used by hardware threads executing on execution unit 2700. Registers in register file 2706 can be partitioned within the computation unit 2710 of execution unit 2700 for the execution of multiple concurrent threads. The number of logical threads that execution unit 2700 can execute is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 2706 can vary between examples based on the number of supported hardware threads. In some examples, register renaming can be used to dynamically allocate registers to hardware threads.

[0308] Figure 28 The block diagram illustrates a graphics processor instruction format 2800 according to some examples. In one or more examples, the graphics processor execution unit supports an instruction set with multiple instruction formats. Solid lines indicate components typically included in execution unit instructions, while dashed lines indicate optional components or those included only in subsets of the instructions. In some examples, the instruction format 2800 described and illustrated are macro instructions because they are instructions provided to the execution unit, rather than micro-operations generated from instruction decoding once the instruction is processed.

[0309] In some examples, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 2810. Depending on the selected instruction, instruction options, and the number of operands, the 64-bit compact instruction format 2830 can be used for some instructions. The native 128-bit instruction format 2810 provides access to all instruction options, while the 64-bit compact format 2830 restricts some options and operations. The native instructions available in the 64-bit compact format 2830 vary from example to example. In some examples, a portion of the instruction is compressed using a set of index values ​​in the index field 2813. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instruction of the 128-bit instruction format 2810. Instructions of other sizes and formats are also possible.

[0310] For each format, instruction opcode 2812 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel on multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs simultaneous addition on each color channel representing a texture element or image element. By default, the execution unit executes each instruction on all data channels of the operand. In some examples, instruction control field 2814 enables control over certain execution options, such as channel selection (e.g., predicate) and data channel order (e.g., swizzle). For instruction 2810 in the 128-bit instruction format, execution size field 2816 limits the number of data channels that will be executed in parallel. In some examples, execution size field 2816 is not available for the 64-bit compact instruction format 2830.

[0311] Some execution unit instructions have up to three operands, including two source operands, src0 2820 and src1 2822, and one destination 2818. In some examples, the execution unit supports dual-destination instructions, where one destination is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2824), where the instruction opcode 2812 determines the number of source operands. The last source operand of an instruction may be an immediate value (e.g., hard-coded) passed with the instruction.

[0312] In some examples, the 128-bit instruction format 2810 includes an access / address mode field 2826, which, for example, specifies whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0313] In some examples, the 128-bit instruction format 2810 includes an access / address mode field 2826, which specifies the address mode and / or access mode of the instruction. In some examples, the access mode is used to define the data access alignment of the instruction. Some examples support access modes including 16-byte aligned access modes and 1-byte aligned access modes, where the byte alignment of the access mode determines the access alignment of the instruction's operands. For example, in the first mode, the instruction can use byte-aligned addressing for both the source and destination operands, while in the second mode, the instruction can use 16-byte aligned addressing for all source and destination operands.

[0314] In some examples, the address mode portion of the access / address mode field 2826 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, the bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0315] In some examples, instructions are grouped based on the opcode 2812-bit field to simplify opcode decoding 2840. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some examples, move and logic opcode group 2842 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some examples, move and logic opcode group 2842 shares five most significant bits (MSBs), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. Flow control instruction group 2844 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 2846 includes a mixture of instructions, including synchronization instructions in the form of 0011xxxxb (e.g., wait, send). Parallel math instruction group 2848 includes component-based arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math instruction group 2848 performs arithmetic operations in parallel across data channels. Vector math group 2850 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic operations, such as dot product calculations on vector operands. In some examples, the illustrated opcode decoder 2840 can be used to determine which part of the execution unit will be used to execute the decoded instructions. For example, some instructions may be specified as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0316] Graphics Pipeline Figure 29 This is a block diagram of another example of a graphics processor 2900. Figure 29 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0317] In some examples, the graphics processor 2900 includes a geometry pipeline 2920, a media pipeline 2930, a display engine 2940, thread execution logic 2950, ​​and a rendering output pipeline 2970. In some examples, the graphics processor 2900 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by writing to registers of one or more control registers (not shown), or by commands issued to the graphics processor 2900 via a ring interconnect 2902. In some examples, the ring interconnect 2902 couples the graphics processor 2900 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2902 are interpreted by a command stream processor 2903, which provides instructions to individual components of the geometry pipeline 2920 or the media pipeline 2930.

[0318] In some examples, command stream processor 2903 directs the operation of vertex acquirer 2905, which reads vertex data from memory and executes vertex processing commands provided by command stream processor 2903. In some examples, vertex acquirer 2905 provides vertex data to vertex shader 2907, which performs coordinate space transformation and lighting operations on each vertex. In some examples, vertex acquirer 2905 and vertex shader 2907 execute vertex processing instructions by dispatching execution threads to execution units 2952A-2952B via thread dispatcher 2931.

[0319] In some examples, execution units 2952A-2952B are arrays of vector processors with instruction sets for performing graphics and media operations. In some examples, execution units 2952A-2952B have attached L1 caches 2951, which may be per array or shared between arrays. The caches may be configured as data caches, instruction caches, or partitioned into single caches containing both data and instructions in different partitions.

[0320] In some examples, the geometry pipeline 2920 includes a subdivision component for performing hardware-accelerated subdivision of 3D objects. In some examples, a programmable shell shader 2911 configures the subdivision operation. A programmable domain shader 2917 provides backend evaluation of the subdivision output. A subdivision unit 2913 operates under the guidance of the shell shader 2911 and contains special-purpose logic to generate a set of detailed geometric objects based on a coarse geometry model provided as input to the geometry pipeline 2920. In some examples, the subdivision components (e.g., shell shader 2911, subdivision unit 2913, and domain shader 2917) can be bypassed if subdivision is not used.

[0321] In some examples, the entire geometry object can be processed by geometry shader 2919 via one or more threads dispatched to execution units 2952A-2952B, or it can go directly to pruner 2929. In some examples, the geometry shader operates on the entire geometry object, rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, geometry shader 2919 receives input from vertex shader 2907. In some examples, geometry shader 2919 can be programmed by a geometry shader program to perform geometry tessellation even when the tessellation unit is disabled.

[0322] Prior to rasterization, clipper 2929 processes vertex data. Clipper 2929 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functions. In some examples, the rasterizer and depth test component 2973 in the render output pipeline 2970 dispatch pixel shaders to convert the geometry into a per-pixel representation. In some examples, the pixel shader logic is included in thread execution logic 2950. In some examples, the application can bypass the rasterizer and depth test component 2973 and access the unrasterized vertex data via stream output unit 2923.

[0323] The graphics processor 2900 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some examples, execution units 2952A-2952B and associated logic units (e.g., L1 cache 2951, sampler 2954, texture cache 2958, etc.) are interconnected via data port 2956 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some examples, sampler 2954, caches 2951, 2958, and execution units 2952A-2952B each have separate memory access paths. In some examples, texture cache 2958 may also be configured as a sampler cache.

[0324] In some examples, the rendering output pipeline 2970 includes a rasterizer and a depth testing component 2973 that converts vertex-based objects into associated pixel-based representations. In some examples, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and linear rasterization. In some examples, associated rendering caches 2978 and depth caches 2979 are also available. Pixel manipulation component 2977 performs pixel-based operations on the data, but in some cases, pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 2941, or replaced by the display controller 2943 using an overlay display plane during display. In some examples, a shared L3 cache 2975 is available to all graphics components, allowing data to be shared without using main system memory.

[0325] In some examples, the media pipeline 2930 includes a media engine 2937 and a video front-end 2934. In some examples, the video front-end 2934 receives pipeline commands from a command stream processor 2903. In some examples, the media pipeline 2930 includes a separate command stream processor. In some examples, the video front-end 2934 processes media commands before sending them to the media engine 2937. In some examples, the media engine 2937 includes thread forging functionality to forge threads for dispatch to thread execution logic 2950 via a thread dispatcher 2931.

[0326] In some examples, the graphics processor 2900 includes a display engine 2940. In some examples, the display engine 2940 is external to the graphics processor 2900 and coupled to the graphics processor via a ring interconnect 2902 or some other interconnect bus or structure. In some examples, the display engine 2940 includes a 2D engine 2941 and a display controller 2943. In some examples, the display engine 2940 includes dedicated logic capable of operating independently of the 3D pipeline. In some examples, the display controller 2943 is coupled to a display device (not shown), which may be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0327] In some examples, the geometry pipeline 2920 and media pipeline 2930 can be configured to perform operations based on multiple graphics and media programming interfaces, rather than specifically targeting any one application programming interface (API). In some examples, the driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some examples, support is provided for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL), and / or the Vulkan graphics and computing API, all from the Khronos Group. In some examples, support is also provided for the Direct3D library from Microsoft. In some examples, combinations of these libraries are supported. Support is also provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if they can be mapped from future API pipelines to the graphics processor pipeline.

[0328] Graphics pipeline programming Figure 30A The block diagram illustrates the graphics processor command format 3000 according to some examples. Figure 30B The block diagram illustrates a graphics processor command sequence 3010 based on an example. Figure 30A The solid lines in the diagram represent components that are typically included in a drawing command, while the dashed lines represent optional components or components that are only included in a subset of the drawing command. Figure 30A The graphics processor command format 3000 includes a data field for identifying the client 3002, a command operation code (opcode) 3004, and command data 3006. Some commands also include a sub-opcode 3005 and a command size 3008.

[0329] In some examples, client 3002 specifies a client unit of the graphics device that processes command data. In some examples, the graphics processor command parser examines the client field of each command to determine the conditions for further command processing and routes the command data to the appropriate client unit. In some examples, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 3004 and—if present—a sub-opcode 3005 to determine the operation to be performed. The client unit executes the command using the information in the data field 3006. For some commands, an explicit command size 3008 is expected to specify the command size. In some examples, the command parser automatically determines the size of at least some commands based on the command opcode. In some examples, commands are aligned via multiples of double words. Other command formats may be used.

[0330] Figure 30B The flowchart illustrates a graphics processor command sequence 3010. In some examples, software or firmware of a data processing system characterized by an example of a graphics processor uses a version of the illustrated command sequence to set up, execute, and terminate a set of graphics operations. The example command sequence is shown and described only as an illustration, as the examples are not limited to these specific commands or this command sequence. Furthermore, commands can be issued as batch commands in a command sequence, so that the graphics processor will process the sequence of commands at least partially concurrently.

[0331] In some examples, the graphics processor command sequence 3010 may begin with pipeline flushing command 3012, causing any active graphics pipeline to complete the commands currently pending on that pipeline. In some examples, the 3D pipeline 3022 and the media pipeline 3024 do not operate concurrently. Pipeline flushing is performed to cause any pending commands on the active graphics pipeline to complete. In response to pipeline flushing, the graphics processor's command parser suspends command processing until the active graphics engine completes its pending operations and the relevant read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be flushed to memory. In some examples, pipeline flushing command 3012 may be used for pipeline synchronization or before placing the graphics processor in a low-power state.

[0332] In some examples, the pipeline selection command 3013 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some examples, unless the context issues commands for both pipelines, only one pipeline selection command 3013 is needed within the execution context before issuing pipeline commands. In some examples, the pipeline flushing command 3012 is required immediately before pipeline switching via the pipeline selection command 3013.

[0333] In some examples, pipeline control command 3014 configures the operation of the graphics pipeline and is used to program the 3D pipeline 3022 and the media pipeline 3024. In some examples, pipeline control command 3014 configures the pipeline state for the active pipeline. In some examples, pipeline control command 3014 is used for pipeline synchronization and clears data from one or more cache memories within the active pipeline before processing a batch of commands.

[0334] In some examples, the Return Buffer Status command 3016 is used to configure a set of return buffers for writing data to various pipelines. Some pipeline operations require allocating, selecting, or configuring one or more return buffers, which write intermediate data to these buffers during processing. In some examples, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some examples, the Return Buffer Status includes selecting the size and number of return buffers for a set of pipeline operations.

[0335] The remaining commands in the command sequence differ based on the active pipeline of the operation. Based on pipeline determination 3020, the command sequence is customized for either 3D pipeline 3022 starting from 3D pipeline state 3030 or media pipeline 3024 starting from media pipeline state 3040.

[0336] Commands for configuring 3D pipeline state 3030 include 3D state setting commands for configuring vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables before 3D primitive commands are processed. The values ​​of these commands are determined, at least in part, based on the specific 3D API being used. In some examples, 3D pipeline state 3030 commands can also selectively disable or bypass certain pipeline elements without using them.

[0337] In some examples, the 3D primitive 3032 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3032 command are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 3032 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some examples, the 3D primitive 3032 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 3022 dispatches the shader execution thread to the graphics processor execution unit.

[0338] In some examples, 3D pipeline 3022 is triggered by executing command 3034 or an event. In some examples, register writes trigger command execution. In some examples, execution is triggered via the "go" or "kick" command in a command sequence. In some examples, command execution is triggered using pipeline synchronization commands to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine shades the resulting pixels. Additional commands controlling pixel shading and pixel backend operations may also be included for these operations.

[0339] In some examples, the graphics processor command sequence 3010 follows the media pipeline 3024 path when performing media operations. Generally, the specific use and programming of the media pipeline 3024 depends on the media or computational operation to be performed. Specific media decoding operations can be offloaded to the media pipeline during media decoding. In some examples, the media pipeline can also be bypassed, and media decoding can be performed entirely or partially using resources provided by one or more general-purpose processing cores. In some examples, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor performs SIMD vector operations using computation shader programs that are not explicitly related to the rendering of graphics primitives.

[0340] In some examples, the configuration of media pipeline 3024 is similar to that of 3D pipeline 3022. A set of commands for configuring media pipeline state 3040 is dispatched or placed in the command queue before media object commands 3042. In some examples, the commands for media pipeline state 3040 include data used to configure media pipeline elements that will be used to process media objects. This includes data used to configure video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some examples, the commands for media pipeline state 3040 also support the use of one or more pointers to "indirect" state elements, which contain a set of state settings.

[0341] In some examples, media object command 3042 provides a pointer to a media object for media pipeline processing. The media object includes a memory buffer containing the video data to be processed. In some examples, all media pipeline states must be valid before media object command 3042 is issued. Once the pipeline states are configured and media object command 3042 is queued, media pipeline 3024 is triggered via execution command 3044 or an equivalent execution event (e.g., register write). The output from media pipeline 3024 can then be post-processed by operations provided by 3D pipeline 3022 or media pipeline 3024. In some examples, GPGPU operations are configured and executed similarly to media operations.

[0342] Program code can be applied to input information to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as a digital signal processor (DSP), microcontroller, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), microprocessor, or any combination thereof.

[0343] The program code can be implemented in a procedural or object-oriented high-level programming language to communicate with the processing system. Assembly or machine language can also be used if desired. In fact, the mechanisms described in this article are not limited to any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0344] Examples of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these approaches. The examples can be implemented as computer programs or program code, executing on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0345] These machine-readable storage media may include—but are not limited to—non-transient tangible arrangements of articles made or formed by machines or equipment, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of media suitable for storing electronic instructions.

[0346] Therefore, examples also include non-transitory tangible machine-readable media containing instructions or design data that defines the features of the structures, circuits, devices, processors, and / or systems described herein, such as Hardware Description Language (HDL). Such examples may also be referred to as program products.

[0347] Simulation (including binary translation, code transformation, etc.) In some cases, instruction translators can be used to translate instructions from a source instruction set architecture to a target instruction set architecture. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0348] Figure 31The block diagram illustrates the use of a software instruction converter according to an example, which is used to convert binary instructions in a source ISA into binary instructions in a target ISA. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 31 A program in high-level language 3102 is shown to be compiled using a first ISA compiler 3104 to generate first ISA binary code 3106, which can be natively executed by a processor 3116 having at least one first ISA core. A processor 3116 having at least one first ISA core represents any processor capable of performing substantially the same function as an Intel processor having at least one first ISA core by compatiblely executing or otherwise processing (1) a substantial portion of the first ISA or (2) a version of object code for an application or other software targeted to run on an Intel® processor having at least one first ISA core, in order to achieve substantially the same results as a processor having at least one first ISA core. The first ISA compiler 3104 represents a compiler operable to generate first ISA binary code 3106 (e.g., object code) that can be executed on a processor 3116 having at least one first ISA core, with or without additional linking processing. Similarly, Figure 31 A program in high-level language 3102 is shown to be compiled using an alternative ISA compiler 3108 to generate alternative ISA binary code 3110, which can be natively executed by a processor 3114 without a first ISA core. An instruction converter 3112 is used to convert the first ISA binary code 3106 into code that can be natively executed by a processor 3114 without a first ISA core. This converted code may not necessarily be identical to the alternative ISA binary code 3110; however, the converted code will implement the overall operation and consist of instructions from the alternative ISA. Thus, the instruction converter 3112 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation, or any other process, allows a processor or other electronic device without a first ISA processor or core to execute the first ISA binary code 3106.

[0349] IP core implementation At least some examples, one or more aspects, can be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions cause the machine to fabricate logic to perform the techniques described herein. This representation, referred to as an "IP core," is a reusable unit of logic for an integrated circuit, which can be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. This hardware model can be provided to various customers or manufacturing facilities, which load the hardware model onto fabrication machines that manufacture integrated circuits. Integrated circuits can be fabricated such that the circuit performs the operations described in connection with any of the examples described herein.

[0350] Figure 32 The block diagram illustrates an IP core development system 3200 according to some examples, which can be used to fabricate integrated circuits to perform operations. The IP core development system 3200 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to construct entire integrated circuits (e.g., SOC integrated circuits). Design facility 3230 can generate software simulations 3210 of the IP core designs in a high-level programming language (e.g., C / C++). Software simulation 3210 can be used to design, test, and verify the behavior of the IP cores using simulation model 3212. Simulation model 3212 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) designs 3215 can then be created or synthesized from simulation model 3212. RTL design 3215 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associative logic performed using the modeled digital signals. In addition to RTL design 3215, lower-level designs at the logic or transistor levels can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0351] The RTL design 3215 or its equivalent can also be synthesized by a design facility into a hardware model 3220, which may take the form of a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored and transferred to the fabrication facility 3265 using non-volatile memory 3240 (e.g., hard disk, flash memory, or any other non-volatile storage medium). Alternatively, the IP core design can be transferred via a wired connection 3250 or a wireless connection 3260 (e.g., via the Internet). The fabrication facility 3265 can then fabricate an integrated circuit at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations according to at least some of the examples described herein.

[0352] The use of phrases such as "some examples" or "one example" indicates that the described examples may include a specific feature, structure, or characteristic, but not every example may necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same example. Additionally, when an example is used to describe a specific feature, structure, or characteristic, it should be assumed that implementing that feature, structure, or characteristic in conjunction with other examples (whether explicitly described or not) is within the knowledge of someone skilled in the art.

[0353] Furthermore, in the various examples described above, unless otherwise specifically noted, selection language such as the phrase “at least one of A, B or C” or “A, B and / or C” should be understood to refer to A, B or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C).

[0354] Therefore, the specification and drawings should be considered exemplary rather than restrictive. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of this disclosure as set forth in the claims.

[0355] It is important to emphasize that this abstract is provided to comply with Section 1.72(b) of 37 CFR, which requires an abstract that will allow the reader a quick understanding of the nature of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are combined in a single example to simplify this disclosure. This method of disclosure should not be construed as reflecting an intention that the claimed example requires more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed example. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself a separate example. In the appended claims, the terms “comprising” and “wherein” are used as common English equivalents of the respective terms “including” and “wherein”. Furthermore, the terms “first,” “second,” “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

Claims

1. An apparatus comprising: One or more control registers can be configured to maintain a first threshold and a second threshold; as well as A circuit, located at or adjacent to a portion of the instruction execution pipeline circuitry, the instruction execution pipeline circuitry being configured to execute one or more pipeline stages at the processor core, the circuitry being used for: Receive information indicating that an energy event has occurred at the portion of the instruction execution pipeline circuit; For the energy event, a weighted event value is generated, and the weighted event value is added to one or more weighted event values ​​generated within the first time period to generate a weighted event sum; The moving average is determined based on the weighted sum of events; The moving average is compared with the first threshold; as well as If the moving average is greater than the first threshold, a throttling instruction is sent to the portion of the instruction execution pipeline circuit.

2. The apparatus of claim 1, wherein, The throttling instruction causes the portion of the instruction execution pipeline circuit to suspend the execution of the one or more pipeline stages.

3. The apparatus of claim 2, wherein, The circuit is also used for: If the moving average is greater than the first threshold, a throttling ratio is sent to the portion of the instruction execution pipeline circuit, wherein the throttling ratio is based on the number of clock cycles for pausing the execution of the one or more pipeline stages divided by the total number of clock cycles.

4. The apparatus according to any one of claims 1-3, wherein, The circuit is also used for: Receive information indicating that a second energy event has occurred at the portion of the instruction execution pipeline circuit; A second weighted event value is generated for the second energy event, and the second weighted event value is added to one or more weighted event values ​​generated during the second time period to generate a second weighted event sum; The second moving average is determined based on the second weighted sum of events; The second moving average is compared with the second threshold, wherein the second threshold is less than the first threshold; as well as If the second moving average is less than the second threshold, then the throttling instruction is stopped being sent to the portion of the instruction execution pipeline circuit.

5. The apparatus of claim 4, wherein, The first time period is equal to the second time period, and the first time period and the second time period are based on a voltage drop time constant of 3 to 5 nanoseconds.

6. The apparatus according to any one of claims 1-5, wherein, The instruction execution pipeline circuit includes: a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

7. The apparatus of claim 6, wherein, The portion of the instruction execution pipeline circuitry includes an integer execution cluster or a vector execution cluster, and the energy event is based on the expected energy usage for the type of microoperation performed by the integer execution cluster or the vector execution cluster.

8. The apparatus according to any one of claims 1-7, wherein, The circuit is also used for: The generated weighted event value is sent to a global throttle coupled to the processor core, wherein the global throttle includes circuitry capable of performing the following operation: at least in part based on the generated weighted event value, causing multiple portions of the instruction execution pipeline circuitry to suspend or delay the execution of one or more pipeline stages.

9. A method comprising: The circuit receives information indicating that an energy event has occurred at a portion of the instruction execution pipeline circuit, the circuit being located at or together with the portion of the instruction execution pipeline circuit, the instruction execution pipeline circuit being configured to execute one or more pipeline stages at the processor core; Generate weighted event values ​​for the energy events; The weighted event value is added to one or more weighted event values ​​generated within the first time period to generate a weighted event sum; The moving average is determined based on the weighted sum of events; The moving average is compared with a first threshold. as well as If the moving average is greater than the first threshold, a throttling instruction is sent to the portion of the instruction execution pipeline circuit.

10. The method of claim 9, wherein, The throttling instruction causes the portion of the instruction execution pipeline circuit to suspend the execution of the one or more pipeline stages.

11. The method of claim 10, further comprising: If the moving average is greater than the first threshold, a throttling ratio is sent to the portion of the instruction execution pipeline circuit, wherein the throttling ratio is based on the number of clock cycles for pausing the execution of the one or more pipeline stages divided by the total number of clock cycles.

12. The method of claim 11, further comprising: Receive information indicating that a second energy event has occurred at the portion of the instruction execution pipeline circuit; A second weighted event value is generated for the second energy event; The second weighted event value is added to one or more weighted event values ​​generated during the second time period to generate the second weighted event sum; The second moving average is determined based on the second weighted sum of events; The second moving average is compared with a second threshold, wherein the second threshold is less than the first threshold; as well as If the second moving average is less than the second threshold, then the throttling instruction is stopped being sent to the portion of the instruction execution pipeline circuit.

13. The method of claim 12, wherein, The first time period is equal to the second time period, and the first time period and the second time period are based on a voltage drop time constant of 3 to 5 nanoseconds.

14. The method according to any one of claims 9-13, wherein, The instruction execution pipeline circuit includes: a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

15. The method of claim 14, wherein, The portion of the instruction execution pipeline circuitry includes an integer execution cluster or a vector execution cluster, and the energy event is based on the expected energy usage for the type of microoperation performed by the integer execution cluster or the vector execution cluster.

16. The method of any one of claims 9-15, further comprising: The generated weighted event value is sent to a global throttle coupled to the processor core, wherein the global throttle includes circuitry capable of performing the following operation: at least in part based on the generated weighted event value, causing multiple portions of the instruction execution pipeline circuitry to suspend or delay the execution of one or more pipeline stages.

17. A system comprising: The instruction execution pipeline circuitry can be arranged to execute one or more pipeline stages at the processor core; as well as A global throttle, coupled to multiple portions of the instruction execution pipeline circuitry, the global throttle includes circuitry for: Receive information indicating a weighted sum of events, the weighted sum of events being based on energy events that have occurred at a first portion of the plurality of portions of the instruction execution pipeline circuit; The weighted event sum is added to the sum of one or more weighted events received within the first time period to aggregate the weighted event sum; The moving average is determined based on the aggregated weighted sum of events; The moving average is compared with a first threshold. as well as If the moving average is greater than the first threshold, a throttling instruction is sent to the plurality of parts of the instruction execution pipeline circuit.

18. The system of claim 17, wherein, The throttling instruction causes the plurality of portions of the instruction execution pipeline circuit to suspend the execution of one or more pipeline stages.

19. The system of claim 18, wherein, The circuit is also used for: If the moving average is greater than the first threshold, a throttling ratio is sent to the plurality of portions of the instruction execution pipeline circuit, wherein the throttling ratio is based on the number of clock cycles for pausing the execution of the one or more pipeline stages divided by the total number of clock cycles.

20. The system of claim 17, wherein, The circuit is also used for: Receive information indicating a second weighted event sum, the second weighted event sum being based on a second energy event that has occurred at the first portion of the plurality of portions of the instruction execution pipeline circuit; The second weighted event sum is added to the sum of one or more second weighted events received within the second time period to aggregate the second weighted event sum; The second moving average is determined based on the aggregated second-weighted sum of events; The second moving average is compared with a second threshold, wherein the second threshold is less than the first threshold; as well as If the second moving average is less than the second threshold, then the throttling instruction is stopped from being sent to the plurality of parts of the instruction execution pipeline circuit.

21. The system of claim 20, wherein, The first time period is equal to the second time period, and the first time period and the second time period are based on a voltage drop time constant of 20 to 40 nanoseconds.

22. The system of claim 20, wherein, The first time period is equal to the second time period, and the first time period and the second time period are based on a voltage drop time constant of 180 to 200 nanoseconds.

23. The system as claimed in any one of claims 17-22, wherein, The plurality of parts of the instruction execution pipeline circuit include: a branch prediction unit, an instruction decoding queue, an out-of-order unit, an integer execution cluster, a vector execution cluster, an L0 cache, an L1 cache, or an L2 cache.

24. The system of claim 23, wherein, The portion of the instruction execution pipeline circuitry includes an integer execution cluster or a vector execution cluster, and the energy event is based on the expected energy usage for the type of microoperation performed by the integer execution cluster or the vector execution cluster.

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