A re-timer and a rising channel implementation method and device of a low latency mode thereof

Abstract

The application provides a re-timer and a low-delay mode upgrade channel implementation method and equipment. A conventional signal processing path is used to control an N+i input end of a first path selection module and an i output end thereof to be turned on when it is monitored that a corresponding part of an i channel in a first physical layer exits electrical idle, directly control the i channel to exit the low-delay mode, generate an activation code stream, and transmit the activation code stream to a rear-end equipment through the i output end of the conventional signal processing path after passing through the first path selection module and a second physical layer, so that the corresponding part of the i channel in the physical layer of the rear-end equipment exits electrical idle before the rear-end equipment deletes an upgrade request, and the upgrade channel is completed. The i channel is a channel corresponding to the upgrade request discussed in the upgrade channel. The problem of upgrade channel timeout in the L0p mode can be solved.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a re-timer and a method and apparatus for implementing the up-channel of its low-latency mode. Background Technology

[0002] PCIe (peripheral component interconnect express) is a high-performance, general-purpose high-speed serial bus standard proposed in 2001. It is the I / O local bus standard of the existing computer architecture. By using high-speed serial transmission, PCIe can support external devices with higher signal transmission rates and bandwidth requirements.

[0003] PCIe 6.0 introduces the L0p (Low-Power Active State) mode compared to previous versions. Earlier versions of PCIe allowed disabling unused channels, but re-enabling them required reconfiguration. PCIe 6.0's L0p mode, however, supports dynamic channel switching, enabling users to more flexibly manage system power consumption and adjust the performance-power balance in real time according to application scenarios. For example, all channels can be enabled during high-throughput periods, while unnecessary channels can be disabled to save power when high throughput is not required. Furthermore, this adjustment does not require physical layer (PHY) training or similar operations.

[0004] In high-speed data transmission scenarios, signal quality degrades with increasing transmission distance and complexity. A retimer, a hybrid digital-analog signal device, possesses sensing capabilities and can fully recover the data signal for retransmission. Using a retimer to enhance the transmitted signal in a PCIe link effectively solves the signal attenuation problem while ensuring signal integrity and accuracy.

[0005] Furthermore, the L0p mode also opens a low-latency channel. When the low-latency function is enabled in the PCIe link, how to ensure the smooth implementation of up-through in the L0p mode has become a concern for those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method and device for implementing a re-timer and its low-latency mode up-channel, so as to improve the above-mentioned problems.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a re-timer, the re-timer comprising: a first physical layer, a second physical layer, a conventional signal processing path, a low-latency signal processing path, and a first path selection module; Both the conventional signal processing path and the low-latency signal processing path are provided with N channels. The nth input terminal of the conventional signal processing path and the nth input terminal of the low-latency signal processing path are both connected to the nth output terminal of the first physical layer. The nth output terminal of the low-latency signal processing path is connected to the nth input terminal of the first path selection module. The nth output terminal of the conventional signal processing path is connected to the N+n input terminal of the first path selection module. The nth output terminal of the first path selection module is connected to the nth input terminal of the second physical layer. The conventional signal processing path is used to control the N+i input terminal of the first path selection module to conduct with its i-th output terminal when the corresponding part of the i-th channel in the first physical layer is detected to be out of electrical idle, generate an activation code stream, and transmit the activation code stream backward through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, the activation code stream is transmitted to the downstream device so that the corresponding part of the i-th channel in the physical layer of the downstream device is out of electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

[0008] After detecting that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, it is not necessary to wait for the re-timer to lock and forward the data. Instead, the i-th channel is directly controlled to exit low-latency mode, and an activation code stream is constructed and transmitted to the downstream device. This ensures that the corresponding part of the i-th channel in the physical layer of the downstream device exits electrical idle before the downstream device deletes the upgrade request, thus completing the channel upgrade. This can solve the channel upgrade timeout problem in L0p mode.

[0009] Optionally, the conventional signal processing path includes a pre-processing module, a deskipation module, a second path selection module, and a post-processing module connected in sequence. The conventional signal processing path also includes a code stream generation module externally connected to the bypass input terminal of the second path selection module. The control terminal of the bitstream generation module and the control terminal of the second path selection module are connected to the deskew module, and the deskew module is also connected to the first physical layer; The deskew module is used to start the stream generation module when it detects that the corresponding part of the i-th channel in the first physical layer has exited the electrical idle state, and to control the bypass input terminal of the second path selection module to be connected to the output terminal corresponding to the i-th channel, and to control the N+i-th input terminal of the first path selection module to be connected to its i-th output terminal. The code stream generation module is used to generate an activation code stream after startup and transmit the activation code stream to the path selection module; The second path selection module is used to transmit the activation code stream to the next stage through its i-th output terminal. After being processed by the subsequent processing module, the code stream is transmitted to the N+i-th input terminal of the first path selection module.

[0010] The deskip module switches the internal conduction relationship of the path selection module in the conventional signal processing path, controls the code stream generation module to generate an activation code stream, and transmits the activation code stream to the subsequent modules through the path selection module, ensuring that the subsequent modules can quickly receive the activation code stream, thereby ensuring the realization of the upscaling channel.

[0011] Optionally, when the downstream device of the re-timer is an EP device, the re-timer further includes a low-delay control module; The nth input terminal of the low-latency control module is connected to the nth output terminal of the deskew module, and the output terminal of the low-latency control module is connected to the trigger terminal of the low-latency signal processing path. The low-latency control module is used to send a trigger signal corresponding to the i-th channel to the low-latency signal processing path when it detects that the number of target bit streams output by the i-th output terminal of the deskip module is greater than a preset number threshold. The target code stream refers to the code stream whose target flag bit is consistent with the target flag bit of the code stream sent by the RC device; The low-latency signal processing path is used to start de-skew processing on the i-th channel after obtaining the trigger signal corresponding to the i-th channel. After the de-skew processing of the i-th channel is started, it controls the i-th input terminal of the first path selection module to be connected to its i-th output terminal.

[0012] This ensures the feasibility of entering low-latency mode after the upgrade channel is completed, and avoids entering low-latency mode prematurely before the upgrade channel is completed.

[0013] Optionally, after the deskewing process of the i-th channel is initiated, the low-latency signal processing path is further used to feed back a completion signal to the deskewing module; the deskewing module, upon receiving the completion signal, controls the bitstream generation module to stop generating the active bitstream. This reduces operating power consumption.

[0014] Secondly, embodiments of the present invention provide a method for implementing a low-latency mode of a re-timer, applied to the aforementioned re-timer, the method comprising: When the conventional signal processing path detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, it controls the N+i-th input terminal of the first path selection module to be turned on and its i-th output terminal to generate an activation code stream. The activation code stream is then transmitted to the next stage device through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, the activation code stream is transmitted to the next stage device so that the corresponding part of the i-th channel in the physical layer of the next stage device exits electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

[0015] Thirdly, embodiments of the present invention provide an electronic device including the aforementioned retimer.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of the re-timer provided in an embodiment of the present invention.

[0019] Figure 2 The second schematic diagram of the re-timer provided in this embodiment of the invention.

[0020] Figure 3 A flowchart illustrating the method for implementing the re-timer low-delay mode up-channel according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Please refer to Figure 1 , Figure 1 This is one of the structural schematic diagrams of a re-timer provided in an embodiment of the present invention. The re-timer includes: a first physical layer, a second physical layer, a conventional signal processing path, a low-latency signal processing path, and a first path selection module.

[0026] Both the conventional signal processing path and the low-latency signal processing path have N channels. The nth input terminal of both the conventional signal processing path and the low-latency signal processing path are connected to the nth output terminal of the first physical layer. The nth output terminal of the low-latency signal processing path is connected to the nth input terminal of the first path selection module. The nth output terminal of the conventional signal processing path is connected to the (N+n)th input terminal of the first path selection module. The nth output terminal of the first path selection module is connected to the nth input terminal of the second physical layer. The nth input terminal of the first physical layer is connected to the nth output terminal of the front-end device, and the nth output terminal of the second physical layer is connected to the nth input terminal of the back-end device. For ease of viewing, only the nth channel is shown as an example in the diagram. It should be noted that 1≤n≤N, 2≤N, and the value of N can be, but is not limited to, 8 or 16.

[0027] The conventional signal processing path is used to control the N+i input terminal of the first path selection module (connected to the i-th output terminal of the conventional signal processing path) to conduct with its i-th output terminal when the corresponding part of the i-th channel in the first physical layer is detected to be out of electrical idle (equivalent to controlling the i-th channel to exit the low-latency mode), generate an activation code stream, and transmit the activation code stream backward through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, it is transmitted to the downstream device so that the corresponding part of the i-th channel in the physical layer of the downstream device is out of electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion, where 2≤i≤N.

[0028] Since the N+i input terminal of the first path selection module is connected to the i-th output terminal of the conventional signal processing path, controlling the N+i input terminal of the first path selection module to conduct with its i-th output terminal is equivalent to controlling the i-th channel to exit the low-latency mode.

[0029] RC devices and EP devices can discuss upgrading channels through an open channel (e.g., channel lane1). The EP device will cache the discussed upgrade request. Since the EP device has a fixed caching time for upgrade requests, if the i-th channel that the EP device needs to upgrade has not exited the idle state and has not been activated within the fixed caching time, the EP device will delete the upgrade request, causing the upgrade to fail.

[0030] Even if the RC device immediately sends activation data through the i-th channel after the channel upgrade is discussed, and even if the i-th channel is in low-latency mode (i.e., the i-th input and i-th output of the first path selection module are connected), the retimer still needs to perform data locking and forwarding processing. These processing steps will consume multiple skip ordered sets or clock compensation ordered sets (skp for short). The interval of skp is about 6us. The total duration of the interval of multiple skp will exceed the buffer duration of the EP device, which will cause the channel upgrade to fail.

[0031] In the re-timer provided in this embodiment of the invention, after detecting that the corresponding part of the i-th channel in the first physical layer has exited the electrical idle state, it is not necessary to wait for the re-timer to lock and forward the data. Instead, the i-th channel is directly controlled to exit the low-latency mode, and an activation code stream is constructed and transmitted to the downstream device. This ensures that the corresponding part of the i-th channel in the physical layer of the downstream device exits the electrical idle state before the downstream device deletes the upgrade request, thereby completing the channel upgrade and solving the problem of channel upgrade timeout in L0p mode.

[0032] Building upon the preceding text, this invention also provides an optional implementation method for the specific structure of conventional signal processing pathways. Please refer to the following documentation for further details. Figure 1 .

[0033] The conventional signal processing path includes a pre-processing module, a de-skew module, a second path selection module, and a post-processing module connected in sequence. The conventional signal processing path also includes a stream generation module connected to the bypass input of the second path selection module, that is, the output of the stream generation module is connected to the bypass input of the second path selection module.

[0034] The control terminal of the bitstream generation module and the control terminal of the second path selection module are connected to the deskew module, which is also connected to the first physical layer.

[0035] The deskip module is used to start the bit stream generation module when it detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, and to control the bypass input terminal of the second path selection module to be connected to the output terminal corresponding to the i-th channel, and to control the N+i input terminal of the first path selection module (connected to the i-th output terminal of the conventional signal processing path) to be connected to its i-th output terminal.

[0036] Optionally, the deskipation module can directly control the first path selection module to switch its internal conduction relationship, or the deskipation module can send a command to the low-delay path module in the low-delay signal processing path to make the low-delay path module drive the first path selection module to switch its internal conduction relationship.

[0037] The stream generation module is used to generate an activation stream after startup and transmit the activation stream to the path selection module; The second path selection module transmits the activation code stream through its i-th output terminal. After processing by the subsequent processing module, it is transmitted to the N+i-th input terminal of the first path selection module. After passing through the first path selection module and the second physical layer, it is transmitted to the subsequent device so that the portion corresponding to the i-th channel in the physical layer of the subsequent device is out of electrical idle, thereby completing the channel upscaling.

[0038] It should be understood that the i-th output of the second path selection module becomes the i-th output of the conventional signal processing path after passing through the subsequent processing module.

[0039] In one alternative implementation, the deskipation module is provided with an input interface cur_is_ll to indicate whether each channel in the device is currently in low-latency mode.

[0040] The deskip module switches the internal conduction relationship of the path selection module in the conventional signal processing path, controls the code stream generation module to generate an activation code stream, and transmits the activation code stream to the subsequent modules through the path selection module, ensuring that the subsequent modules can quickly receive the activation code stream, thereby ensuring the realization of the upscaling channel.

[0041] Building upon the foregoing, this invention also provides an optional implementation method to ensure subsequent entry into low-latency mode. Please refer to [link / reference needed]. Figure 2 , Figure 2 This is the second schematic diagram of the re-timer provided in an embodiment of the present invention.

[0042] When the downstream device of the retimer is an EP device, the retimer also includes a low-delay control module. The nth input terminal of the low-delay control module is connected to the nth output terminal of the deskipation module, and the output terminal of the low-delay control module is connected to the trigger terminal of the low-delay signal processing path, specifically, it can be connected to the trigger terminal of the low-delay path module.

[0043] In this embodiment of the invention, the RC device is a root complex device, representing the root node of the PCIe bus tree; the EP device is an endpoint device, representing the leaf node of the PCIe bus tree.

[0044] The low-latency control module is used to send the trigger signal corresponding to the i-th channel to the low-latency signal processing path (specifically, to the low-latency path module) when it detects that the number of target bit streams output by the i-th output terminal of the deskip module is greater than a preset number threshold.

[0045] The target stream refers to the stream whose target flag is the same as the target flag of the stream sent by the RC device. The preset number threshold can be, but is not limited to, 2.

[0046] The low-latency signal processing path is used to start de-skew processing on the i-th channel after acquiring the trigger signal corresponding to the i-th channel. After the de-skew processing of the i-th channel is started, it controls the i-th input terminal of the first path selection module (connected to the i-th output terminal of the low-latency signal processing path) to be connected to its i-th output terminal.

[0047] At this point, the low-latency function of the i-th channel is enabled, and the data of the i-th channel in the conventional signal processing path is no longer sent backward.

[0048] The current-level device is also a re-timer. When the number of target bitstreams detected is greater than the preset threshold, it indicates that the front-level device has completed the path switch to the low-latency path, and the L0p lane upgrade function has also been completed.

[0049] When the first-level retimer, acting as the front-end device, has not completed the path switching, the bitstream received by the second-level retimer is the bitstream constructed by the first-level retimer. At this time, if the second-level retimer directly switches to the low-latency channel, it will be de-skewed according to the bitstream constructed by the first level. When the bitstream after the first-level retimer actually enters the low-latency channel, there may still be skew deviation, which will eventually lead to the failure of L0p lane upgrade.

[0050] Please continue to refer to this. Figure 2 The low-latency signal processing path includes a first data locking module and a low-latency path module connected in sequence. The low-latency path module is also connected to a de-skew module and a control terminal of the first path selection module.

[0051] The low-delay path module is used to control the N+i input terminal of the first path selection module to be connected to its i-th output terminal when it receives the i-th channel exit electrical idle indication transmitted by the deskip module.

[0052] The first data locking module is used to identify the physical layer output bitstream (a bunch of parallel irregular data) corresponding to the physical layer, in order to determine the fixed position information of the effective bitstream, and to pass the physical layer output bitstream to the low latency path module.

[0053] Optionally, after the deskipation processing of the i-th channel is started, the low-latency signal processing path is also used to feed back a completion signal to the deskipation module (specifically, it can be a completion signal fed back by the low-latency path module).

[0054] The deskew module, upon receiving a completion signal, controls the bitstream generation module to stop generating the active bitstream. Simultaneously, it can switch the i-th input of the second path selection module back to be connected to the i-th output, and control the low-latency control module to stop monitoring the output bitstream from the i-th output of the deskew module. This reduces operating power consumption.

[0055] Optionally, the control terminal of the low-latency control module is connected to the deskip module.

[0056] The deskip module is used to send a monitoring command for the i-th channel to the low-latency control module when it detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, so that the low-latency control module can monitor the output bit stream of the i-th output terminal of the deskip module.

[0057] Please continue to refer to this. Figure 1 When the downstream device of the retimer is another retimer, the stream generation module modifies the target flag bit in the active stream to be different from the target flag bit of the stream sent by the RC device.

[0058] It should be noted that when the downstream device of the re-timer is another re-timer, the low-latency signal processing path in the re-timer does not need to perform de-skew processing on the data in the i-th channel. Therefore, when the de-skew module identifies the target bitstream, it can send a start signal to the low-latency signal processing path (low-latency path module) to enable the low-latency signal processing path (low-latency path module) to control the i-th input and i-th output of the first path selection module to conduct. Furthermore, the de-skew module controls the bitstream generation module to stop generating the active bitstream, and can also switch the i-th input of the second path selection module back to conduct with the i-th output.

[0059] Optionally, the front-end processing module includes a second data locking module, a data decoding module, and a data descrambling module connected in sequence; the back-end processing module includes a data scrambling module and a data encoding module connected in sequence.

[0060] In this embodiment of the invention, the physical layer is a subsystem in the retimer. It can adjust the quality of the received bit signals to the optimal state that it is adapted to, and at the same time perform serial-to-parallel conversion to convert serial data transmitted by external devices (such as CPU or GPU) into parallel data and transmit the parallel data to the branch in the retimer. It also converts the parallel data transmitted by the branch in the retimer into serial data and transmits the serial data to the external devices (such as CPU or GPU).

[0061] The second data locking module is used to identify the physical layer output bitstream (a bunch of parallel irregular data) corresponding to the physical layer, in order to determine the fixed position information of the valid bitstream, and to pass the physical layer output bitstream to the data decoding module in the branch.

[0062] The data decoding module is used to decode the received physical layer output bitstream based on the fixed position information determined by the data locking module, and then transmit the decoded bitstream data to the data descrambling module in the branch.

[0063] The data descrambling module is used to descramble the received bitstream data and pass the descrambled bitstream data to the data alignment module in the branch. The bitstream data is descrambled according to the corresponding protocol to parse it into training sequence 1 bitstream (TS1 bitstream), training sequence 2 bitstream (TS2 bitstream), and data bitstream that can be recognized normally.

[0064] The data alignment module is used to deskew the received bitstream data and then pass the deskewed bitstream data to the data scrambling module in the branch.

[0065] The data scrambling module is used to scramble the received bitstream data and then pass the scrambled bitstream data to the data encoding module in the branch.

[0066] The data encoding module is used to encode the received bitstream data according to the corresponding protocol and then transmit the encoded bitstream data to the backend physical layer.

[0067] Please continue to refer to this. Figure 2 The nth input terminal of the first physical layer is connected to the nth output terminal of the preceding device.

[0068] The nth input of the first data locking module is connected to the nth output of the first physical layer. The nth output of the first data locking module is connected to the nth input of the low-latency path module. The nth output of the low-latency path module is connected to the nth input of the first path selection module. The nth output of the first path selection module is connected to the nth input of the second physical layer. The nth output of the second physical layer is connected to the nth input of the subsequent device.

[0069] The nth input of the pre-processing module is connected to the nth output of the first physical layer. The nth output of the pre-processing module is connected to the nth input of the de-skew module. The nth output of the de-skew module is connected to the nth input of the second path selection module and the nth input of the low-latency control module. The nth output of the second path selection module is connected to the nth input of the post-processing module. The nth output of the post-processing module is connected to the N+nth input of the first path selection module.

[0070] This invention also provides a method for implementing the up-channel mode of the re-timer in low-latency mode, which is applied to the re-timer mentioned above. Please refer to [link / reference]. Figure 3 The methods for implementing the up-channel in low-latency mode of the retimer include: S101, when the conventional signal processing path detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, it controls the N+i-th input terminal of the first path selection module to be turned on and its i-th output terminal.

[0071] S102, the conventional signal processing path generates an activation code stream and transmits the activation code stream backward through the i-th output terminal of the conventional signal processing path.

[0072] After passing through the first path selection module and the second physical layer, the data is transmitted to the downstream device so that the portion corresponding to the i-th channel in the physical layer of the downstream device is out of electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

[0073] This invention also provides an electronic device including the aforementioned retimer.

[0074] In summary, the present invention provides a re-timer and a method and device for implementing channel upgrade in low-latency mode. A conventional signal processing path is used to control the N+i input terminal and the i-th output terminal of the first path selection module to conduct when the corresponding part of the i-th channel in the first physical layer is detected to be out of electrical idle. This directly controls the i-th channel to exit low-latency mode and generates an activation code stream. The activation code stream is then transmitted backward through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, it is transmitted to the subsequent device. This ensures that the corresponding part of the i-th channel in the physical layer of the subsequent device exits electrical idle before the subsequent device deletes the upgrade request, thus completing the channel upgrade. This solves the problem of channel upgrade timeout in L0p mode. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0076] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A re-timer, comprising: The retimer includes: a first physical layer, a second physical layer, a conventional signal processing path, a low-latency signal processing path, and a first path selection module; Both the conventional signal processing path and the low-latency signal processing path are provided with N channels. The nth input terminal of the conventional signal processing path and the nth input terminal of the low-latency signal processing path are both connected to the nth output terminal of the first physical layer. The nth output terminal of the low-latency signal processing path is connected to the nth input terminal of the first path selection module. The nth output terminal of the conventional signal processing path is connected to the N+n input terminal of the first path selection module. The nth output terminal of the first path selection module is connected to the nth input terminal of the second physical layer. The conventional signal processing path is used to control the N+i input terminal of the first path selection module to conduct with its i-th output terminal when the corresponding part of the i-th channel in the first physical layer is detected to be out of electrical idle, generate an activation code stream, and transmit the activation code stream backward through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, the activation code stream is transmitted to the downstream device so that the corresponding part of the i-th channel in the physical layer of the downstream device is out of electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

2. The re-timer as described in claim 1, characterized in that, The conventional signal processing path includes a pre-processing module, a deskipation module, a second path selection module, and a post-processing module connected in sequence. The conventional signal processing path also includes a code stream generation module externally connected to the bypass input terminal of the second path selection module. The control terminal of the bitstream generation module and the control terminal of the second path selection module are connected to the deskew module, and the deskew module is also connected to the first physical layer; The deskew module is used to start the stream generation module when it detects that the corresponding part of the i-th channel in the first physical layer has exited the electrical idle state, and to control the bypass input terminal of the second path selection module to be connected to the output terminal corresponding to the i-th channel, and to control the N+i-th input terminal of the first path selection module to be connected to its i-th output terminal. The code stream generation module is used to generate an activation code stream after startup and transmit the activation code stream to the path selection module; The second path selection module is used to transmit the activation code stream to the next stage through its i-th output terminal. After being processed by the subsequent processing module, the code stream is transmitted to the N+i-th input terminal of the first path selection module.

3. The re-timer as described in claim 2, characterized in that, When the downstream device of the re-timer is an EP device, the re-timer further includes a low-delay control module; The nth input terminal of the low-latency control module is connected to the nth output terminal of the deskew module, and the output terminal of the low-latency control module is connected to the trigger terminal of the low-latency signal processing path. The low-latency control module is used to send a trigger signal corresponding to the i-th channel to the low-latency signal processing path when it detects that the number of target bit streams output by the i-th output terminal of the deskip module is greater than a preset number threshold. The target code stream refers to the code stream whose target flag bit is consistent with the target flag bit of the code stream sent by the RC device; The low-latency signal processing path is used to start de-skew processing on the i-th channel after obtaining the trigger signal corresponding to the i-th channel. After the de-skew processing of the i-th channel is started, it controls the i-th input terminal of the first path selection module to be connected to its i-th output terminal.

4. The re-timer as described in claim 3, characterized in that, The low-latency signal processing path includes a first data locking module and a low-latency path module connected in sequence. The low-latency path module is also connected to the de-skew module and the control terminal of the first path selection module. The low-latency path module is used to control the N+i input terminal of the first path selection module to be connected to its i-th output terminal when it receives the i-th channel exit electrical idle indication transmitted by the deskipation module.

5. The re-timer as described in claim 3, characterized in that, After the deskip processing of the i-th channel is started, the low-delay signal processing path is also used to feed back a completion signal to the deskip module; The deskew module is used to control the bitstream generation module to stop generating the activation bitstream after the completion signal is obtained.

6. The re-timer as described in claim 3, characterized in that, The control terminal of the low-latency control module is connected to the deskip module; The deskip module is used to send a monitoring command for the i-th channel to the low-latency control module when it detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, so that the low-latency control module can monitor the output bit stream of the i-th output terminal of the deskip module.

7. The re-timer as described in claim 2, characterized in that, When the downstream device of the re-timer is another re-timer, the bitstream generation module is used to modify the target flag bit in the active bitstream to be different from the target flag bit of the bitstream sent by the RC device.

8. The re-timer as described in claim 2, characterized in that, The front-end processing module includes a second data locking module, a data decoding module, and a data descrambling module connected in sequence. The subsequent processing module includes a data scrambling module and a data encoding module connected in sequence.

9. A method for implementing a re-timer low-delay mode up-channel, characterized in that, The method, applied to the retimer according to any one of claims 1-8, comprises: When the conventional signal processing path detects that the corresponding part of the i-th channel in the first physical layer has exited electrical idle, it controls the N+i-th input terminal of the first path selection module to be turned on and its i-th output terminal to generate an activation code stream. The activation code stream is then transmitted to the next stage device through the i-th output terminal of the conventional signal processing path. After passing through the first path selection module and the second physical layer, the activation code stream is transmitted to the next stage device so that the corresponding part of the i-th channel in the physical layer of the next stage device exits electrical idle, thereby completing the channel upgrade. The i-th channel is the channel corresponding to the upgrade request discussed in the channel upgrade discussion.

10. An electronic device, characterized in that, The re-timer includes any one of claims 1-8.

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