A method for constructing an IC-level electromagnetic compatibility data asset

Abstract

The application relates to a method for constructing an IC-grade EMC data asset. The method adopts a hierarchical test rule: a first test data of an intrinsic EMC characteristic of an IC and a calibration simulation model are obtained through a benchmark layer; second test data and simulation data corresponding to different design variables are obtained by changing the design variables one by one through an extension layer; IC basic information, PCB design information, test data, simulation data and calibration parameters are organized into hierarchical data assets, and multi-dimensional searchable tags containing product codes, EMI performance grades and measure sensitivities are given. The application converts unstructured EMC data into structured and machine-readable data assets, and provides quantitative basis for IC selection, localization substitution and electromagnetic protection design.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic compatibility (EMC) design and testing technology, specifically relating to a method for constructing integrated circuit (IC) level electromagnetic compatibility data assets. Background Technology

[0002] EMC testing is a key indicator for evaluating the ability of electronic devices to operate normally in electromagnetic environments. Current EMC design generally adopts an iterative model of component-level testing, rectification, and retesting: after product development, it is sent to a third-party laboratory for testing; rectification is carried out based on the test report; this process is repeated multiple times until the standard is met. The final result is a test report in an unstructured format, such as a PDF, Word document, or image, deeply tied to the specific product status and test setup.

[0003] The existing technology has the following drawbacks: First, EMC test data is tied to specific products. When the same IC appears in different products, the test reports are unstructured and the test conditions are inconsistent, making the test data unusable and unable to provide reference for the design and development of other products. This makes it difficult to shorten the development cycle and reduce R&D costs. Second, component-level EMC test results are the coupled result of factors such as IC-level EMC characteristics, PCB layout, port filtering, and structural shielding. It is impossible to quantitatively distinguish between the IC's own EMC contribution and the contribution of external measures. Third, the test conditions, test methods, and data formats of EMC data in the technical manuals provided by different IC manufacturers are different. Moreover, the specific PCB size, stack-up structure, and layout topology used in the test are not disclosed, making it impossible to make horizontal comparisons between manufacturers' data. This creates incomparable "information silos," making it impossible to make horizontal comparisons between different ICs or to quantitatively apply them directly to product design and development. Fourth, when domestic ICs replace imported ICs, it is difficult to prove the feasibility of IC replacement through component-level system EMC testing alone, because system EMC test results are affected by many factors and cannot be used to assess whether the IC-level EMC performance meets the requirements.

[0004] In the prior art, CN118428291A discloses a method for predicting conducted emission behavior of SiP chips based on multivariate fitting. This method tests the conducted emission of SiP chips under different operating voltages, frequencies, and load resistances, and uses a neural network to train a mapping relationship to establish an electromagnetic interference (EMI) current source model. While this method involves conducted emission testing, its purpose is to establish a predictive model rather than to build reusable data assets. It does not employ a layered testing rule of a baseline + extended layer, does not quantitatively analyze the EMC impact of design variables, and does not establish a multi-dimensional searchable tagging system for IC-level EMC, making it difficult to achieve cross-project reuse of test data and horizontal comparison between different ICs. Summary of the Invention

[0005] The purpose of this invention is to provide a method for constructing IC-level electromagnetic compatibility data assets, so as to realize cross-project reuse and quantitative analysis of test data. In particular, it solves the problem of incomparability between data from different manufacturers due to inconsistent test conditions, the problem that traditional test reports are presented in unstructured format and are difficult to be directly called and intelligently processed by design tools, and the problem that existing IC data assets lack comprehensive records of IC multi-dimensional attributes (such as physical, electrical, environmental, reliability, etc.), which leads to limited application scenarios.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for constructing IC-level electromagnetic compatibility data assets includes the following:

[0008] Baseline data acquisition: For the target IC, design and manufacture the minimum system test PCB that enables it to work properly according to the first rule set, perform EMC testing, and obtain the first test data that reflects the intrinsic electromagnetic characteristics of the IC;

[0009] Extended data acquisition: Based on the minimum system, an extended test PCB is designed and fabricated by changing a single design variable according to the second rule set, and EMC testing is performed to obtain second test data reflecting the impact of the design variable on EMC performance; wherein, each extended test changes only one design variable, and all other relevant conditions remain unchanged, including the benchmark test state or the state of the previous extended test;

[0010] Asset Construction: The identification information, physical parameters, electrical parameters, environmental adaptability parameters, reliability parameters, PCB design information used for the benchmark and extended tests, the first test data, the second test data, and the first and second simulation data of the target IC are organized into data assets according to a preset data structure. The data assets are then assigned multi-dimensional searchable tags, which include at least one or more of the following: IC function classification, manufacturer information, product code, package type, operating frequency range, EMI performance level, and sensitivity to mitigation measures.

[0011] The identification information of the target IC includes at least one of the following: manufacturer information, product code, model, batch, and datasheet version; the physical parameters include at least one of the following: package type, number of pins, pin pitch, chip size, and thermal resistance; the electrical parameters include at least one of the following: operating voltage range, operating frequency range, output drive capability, power consumption, input / output impedance, and switching characteristics; the environmental adaptability parameters include at least one of the following: temperature characteristics, voltage sensitivity, load sensitivity, and frequency sensitivity; and the reliability parameters include at least one of the following: lifespan rating, certification rating, ESD tolerance rating, EFT tolerance rating, and surge tolerance rating.

[0012] Furthermore, the first rule set includes at least one of the following rules:

[0013] • Circuit integrity rules are used to ensure the proper configuration of peripheral circuits for IC operation;

[0014] • Physical dimension baseline rules are used to define baseline PCB dimensions;

[0015] • Layered structure baseline rules are used to define baseline layered structures;

[0016] • Port layout baseline rules are used to define the baseline parameters for port routing;

[0017] • Decoupling scheme baseline rules are used to define standard decoupling configurations to ensure the normal operation of ICs;

[0018] • Grounding method reference rules, used to define standard grounding methods.

[0019] Furthermore, the design variables in the second rule set include at least one of the following types:

[0020] • Physical dimension variables, including the planar dimensions of the PCB;

[0021] • Layer stack-up variables, including the number of PCB layers, stack-up order, and dielectric thickness;

[0022] • Filtering measures variables, including the presence, type, and parameters of the filter circuit;

[0023] • Variables of shielding measures, including the presence, material, size, and grounding method of the shielding cover;

[0024] • Grounding optimization variables, including the number, location, and connection method of grounding vias;

[0025] • Layout adjustment variables, including the position of the IC on the PCB and the layout of peripheral components;

[0026] • Software configuration variables, including configurable spread spectrum function, drive strength, slew rate, and operating mode parameters within the IC;

[0027] • Environmental variables, including ambient temperature, load conditions, and input voltage.

[0028] Furthermore, the method also includes quantitative analysis: comparing the second test data obtained from different extended tests with the first test data, and / or comparing the second test data obtained from different extended tests with each other, to calculate the quantitative contribution value of each design variable change to EMC performance and the relative effect between different variables.

[0029] The quantified contribution value includes at least one of the following forms:

[0030] • Measured values, extended test data expressed in EMC test standard units (including dBμV, dBμV / m, dBμA, dBμA / m);

[0031] • The change relative to the baseline, expressed in dB, is the difference between the extended test data and the baseline test data;

[0032] • The amount of change between extensions, expressed in dB, is the difference between test data of different extensions;

[0033] • Continuous variable influence coefficient: The change in EMC index caused by the change of a unit continuous design variable, expressed in dB per variable unit (e.g., dB / mm, dB / Ω, dB / ℃).

[0034] • The comprehensive effect value of the measures is the combined impact of a single discrete design variable change on multiple EMC indicators (including EMI, EMS, etc.), expressed as the set of changes in each indicator or a comprehensive evaluation index;

[0035] • Sensitivity level: The level of response of the IC to different hardware or software measures;

[0036] • Ranking of effectiveness: the relative order or hierarchy of the impact of different design variables on EMC performance.

[0037] Furthermore, the method also includes simulation calibration: establishing a first simulation model corresponding to the minimum system test PCB, performing EMC simulation to obtain first simulation data; correlating and calibrating the first simulation data with the first test data to make the deviation between the two less than a preset threshold; recording calibration parameters, and including the first simulation model and the calibration parameters as part of the data asset.

[0038] Furthermore, the data assets have a hierarchical structure, including at least:

[0039] • IC basic information layer, which stores at least one of the following: identification information, physical parameters, electrical parameters, environmental adaptability parameters, and reliability parameters of the target IC;

[0040] • The benchmark layer stores the first test data, the corresponding first simulation model, and the PCB design information used for the benchmark test;

[0041] • An extension layer stores the second test data, the corresponding second simulation model, and the PCB design information used for the extension test in at least one extension dimension;

[0042] • Quantization layer, which stores the quantified contribution of the design variable changes to EMC performance;

[0043] • Tag layer, storing the multidimensional searchable tags.

[0044] Furthermore, the multidimensional searchable tags include at least one of the following categories:

[0045] • IC function classification label indicates the IC's function type: power supply, clock, communication, radio frequency, or logic.

[0046] • Package label, indicating the IC's SOP, QFP, BGA, DFN, or QFN package type;

[0047] • Frequency label indicates the low-frequency, medium-frequency, or high-frequency operating frequency range of the IC;

[0048] • Performance label indicates the EMI strength rating or immunity rating of the IC;

[0049] • Sensitivity label indicates the IC's sensitivity level to hardware measures such as filtering, shielding, and grounding, as well as software measures such as spread spectrum and drive strength.

[0050] • Temperature rating label indicates the operating temperature range or rating of the IC;

[0051] • Reliability rating label indicates the IC's lifespan rating or certification level.

[0052] The data assets constructed by this invention adopt a structured storage format. Each set of test data is associated with the corresponding physical size, stack-up structure, and test conditions, forming a searchable and callable data record.

[0053] This invention also provides an IC-level EMC data asset, constructed using the above method, wherein the data asset includes at least:

[0054] • IC basic information layer, which stores at least one of the following: identification information, physical parameters, electrical parameters, environmental adaptability parameters, and reliability parameters of the target IC;

[0055] • The benchmark layer stores the first test data, the corresponding first simulation model, and the PCB design information used for the benchmark test;

[0056] • An extension layer stores the second test data under at least one extension dimension, the corresponding second simulation model, and the PCB design information used for the extension test;

[0057] • Quantization layer, which stores the quantified contribution of the design variable changes to EMC performance;

[0058] • Tag layer, storing multi-dimensional searchable tags.

[0059] This invention also provides a system for constructing IC-level EMC data assets, comprising:

[0060] • The rule management module is used to store and manage the first rule set and the second rule set;

[0061] • The benchmark module is used to test the IC in a minimum system according to the first rule set and obtain the first test data;

[0062] • The extended test module is used to test the IC after changing a single design variable according to the second rule set and obtain the second test data;

[0063] • The quantitative analysis module is used to compare the second test data with the first test data and calculate the quantitative contribution value of the design variable changes to EMC performance.

[0064] • The asset building module is used to organize the basic information, test data, simulation data and PCB design information of the target IC into data assets and assign them multi-dimensional searchable tags;

[0065] • Storage module, used to store the data assets.

[0066] The beneficial effects of this invention are:

[0067] First, the reference layer data of this invention reflects the electromagnetic behavior of IC in its intrinsic operating state, is not affected by external measures, and can be used for horizontal comparison of EMC performance between different ICs.

[0068] Second, the extended layer data of this invention quantifies the contributions of factors such as physical size, stacked structure, protective measures, software configuration, and environmental conditions, transforming engineering design experience into quantifiable data.

[0069] Third, by constructing a multi-dimensional searchable tag system, this invention enables rapid retrieval, horizontal comparison, and intelligent access to data assets, allowing data obtained from a single test to be reused in multiple projects.

[0070] Fourth, this invention transforms traditional unstructured EMC data into structured, comparable, and machine-readable EMC data assets through a unified data format and tagging system, enabling the data to be directly called upon in subsequent design processes.

[0071] Fifth, when replacing domestically produced ICs, the feasibility of replacement can be quantified by comparing intrinsic data and the sensitivity of measures, providing data support for the replacement demonstration.

[0072] Sixth, this invention can locate ICs that contribute significantly to EMI in a system, and take targeted hardware or software protection measures based on their sensitivity labels to achieve precise protection.

[0073] Seventh, by incorporating the PCB design information (including PCB size, layer stack-up, port layout, filter circuit topology, shielding structure, grounding optimization method, etc.) used in benchmark and extended tests into data assets, each set of test data has a complete test condition definition, ensuring the reproducibility, comparability and reusability of test data, and solving the problem of traditional PDF test reports becoming "information silos" due to the lack of test condition information.

[0074] Eighth, by providing diverse forms of quantitative contribution values, including measured values, changes relative to a baseline, changes between extensions, continuous variable influence coefficients, comprehensive effect values ​​of measures, sensitivity levels, and ranking of effectiveness, it provides multi-dimensional quantitative basis for IC selection, design optimization, and domestic substitution. For example, continuous variable influence coefficients (such as dB / mm, dB / ℃) can be directly used to assess the impact trend of continuous variables such as physical size and temperature on EMC performance; comprehensive effect values ​​of measures (such as a 18dB reduction in radiated emission, a 15dB reduction in conducted emission, and a 2kV increase in ESD immunity after adding a shield) can comprehensively evaluate the combined contribution of a single discrete measure to multiple EMC indicators; the combination of sensitivity levels and measure sensitivity labels can guide designers to take the most effective protection measures for IC characteristics, achieving precise protection; and the ranking of effectiveness can provide an intuitive basis for comparing different design schemes, assisting design decisions. Attached Figure Description

[0075] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0076] Figure 1 This is the overall flowchart of the present invention, where S1-S5 respectively represent the establishment of a hierarchical standardized test rule set, benchmark layer testing, simulation modeling and calibration, extension layer construction, and data asset construction and tagging.

[0077] Figure 2 This is a schematic diagram of the PCB for the reference layer test of this invention.

[0078] Figure 3 This is a schematic diagram showing the physical dimensions of the present invention.

[0079] Figure 4 This is a schematic diagram illustrating the extended filtering measures of the present invention.

[0080] Figure 5 This is a schematic diagram illustrating the extended shielding measures of the present invention.

[0081] Figure 6 This is a flowchart illustrating the calibration process for linking test data and simulation data in this invention.

[0082] Figure 7 This is a schematic diagram of the hierarchical data asset structure of the present invention. Detailed Implementation

[0083] The overall process of this invention includes: S1 establishing a hierarchical standardized test rule set, including a first rule set (minimum system rules) and a second rule set (single variable change rules); S2 benchmark layer testing, obtaining the first test data of IC intrinsic data; S3 simulation modeling and calibration, obtaining the benchmark simulation model and calibration parameters; S4 extension layer construction, with testing and simulation performed in parallel, obtaining the second test data and the second simulation data, and comparing them with the benchmark to calculate the quantitative contribution value; S5 data asset construction and tagging, organizing the above data into hierarchical data assets and assigning multi-dimensional searchable tags.

[0084]

Example 1

[0085] This embodiment uses a certain type of step-down DC-DC converter as an example. The IC operates at a frequency of 1.2MHz and uses an SOP-8 package. First, benchmark data acquisition is performed. A benchmark test PCB is designed according to the first rule set. The PCB size is 30mm × 30mm, and it adopts a four-layer board structure, containing only the input / output capacitors, feedback resistors, and inductors necessary for the normal operation of the IC, forming the minimum working circuit. Radiated emission testing is performed using an IC-level EMC test system according to the IEC 61967 standard, with a test frequency range of 30MHz to 1GHz. The test results show that the peak radiation measured at a frequency of 150MHz is 45dBμV / m, which corresponds to the harmonic component of the IC switching frequency. This test data is recorded as the first test data.

[0086] Next, simulation calibration was performed. A three-dimensional electromagnetic simulation model was established based on the benchmark PCB, with an equivalent circuit model used for the IC section. Electromagnetic simulation was conducted under the same conditions as the test, and the first simulation data was obtained. The first simulation data was compared with the first test data, and the initial simulation result deviated from the measured result by 3.5 dB. By adjusting the PCB material parameters in the simulation model, the deviation between the simulation result and the measured result was reduced to 1.2 dB, completing the calibration, and the calibration parameters were recorded.

[0087] Next, extended data acquisition is performed. Following the second set of rules, single design variables are changed sequentially based on the minimum system, and extended testing is conducted.

[0088] Physical size expansion testing: Test PCBs of 40mm×40mm and 50mm×50mm were designed respectively, with other conditions consistent with the benchmark test. Test results showed that the 40mm×40mm test board had a peak radiation of 43dBμV / m at 150MHz, while the 50mm×50mm test board had a peak radiation of 42dBμV / m at the same frequency. Quantitative calculations showed that for every 10mm increase in PCB size, radiated emission decreased by approximately 1.5dB (continuous variable influence coefficient).

[0089] Extended Filtering Test: A π-type filter was added to the power input of the benchmark test board. This filter consisted of a 2.2μH inductor, a 10μF capacitor, and a 2.2μH inductor. Test results showed that adding the π-type filter reduced the radiated peak at 150MHz to 33dBμV / m. Quantitative calculations showed that this filtering measure reduced radiated emissions by 12dB (the change relative to the reference).

[0090] Extended Shielding Test: Based on the benchmark test board, three shielding schemes were tested: (1) partial shielding, with a shielding cover added above the IC; (2) overall shielding, with a shielding cover added above the entire PCB. Test results showed that after partial shielding, the radiation at 150MHz decreased to 27dBμV / m, and after overall shielding, it decreased to 25dBμV / m. Quantitative calculations showed that this shielding measure reduced radiated emissions by 18dB (partial) and 20dB (overall).

[0091] Grounding optimization extended testing: Based on the benchmark test board, the number of ground vias under the IC was increased from 4 to 9. Test results showed that after grounding optimization, the radiated peak at 150MHz decreased to 39dBμV / m. Quantitative calculations showed that this grounding optimization measure reduced radiated emissions by 6dB.

[0092] Software configuration extension test: Based on the benchmark board, the spread spectrum function was enabled and disabled respectively through the IC's internal register configuration. Test results showed that after enabling the spread spectrum function, the radiated peak at 150MHz decreased from 45dBμV / m to 38dBμV / m, reducing radiated emission by 7dB. Further drive strength configuration tests were conducted, reducing the output drive current from 100% to 50%. Test results showed that the radiated peak at 150MHz decreased to 42dBμV / m, reducing radiated emission by 3dB.

[0093] Extended environmental variable testing: Based on the benchmark board, the load conditions were changed, and the radiated emission was tested at 10%, 50%, and 100% of the rated load. The results showed that the heavier the load, the greater the radiated emission, with a peak radiation value of 47 dBμV / m at 100% load.

[0094] Finally, asset construction is carried out. All the above data is organized into a hierarchical data asset structure.

[0095] The IC basic information layer stores identification information (manufacturer information such as XXX company, product code such as XXX), physical parameters (package type SOP-8, number of pins 8, pin pitch 1.27mm, chip size 3mm×5mm, thermal resistance 50°C / W), electrical parameters (operating voltage range 3.0V-3.6V, typical value 3.3V; operating frequency 1.2MHz; output drive capability 500mA; power consumption 200mW; input impedance 50Ω; switching characteristic rise time 2ns), environmental adaptability parameters (temperature characteristic test shows radiated emission increases by 3dB from 25°C to 85°C; voltage sensitivity test shows radiated emission changes by ±2dB with voltage ±10%; load sensitivity test shows radiated emission increases by 5dB with load 10%→100%), and reliability parameters (ESD tolerance level HBM ±2kV, compliant with AEC-Q100 Grade 1 automotive-grade certification), etc.

[0096] • The reference layer stores the first test data (45dBμV / m), the calibrated first simulation model, and the PCB design information used for the benchmark test (including 30mm×30mm size, four-layer board structure, port layout, etc.).

[0097] • The extension layer stores test data for each extension dimension, corresponding second simulation data, and PCB design information used for each extension test:

[0098] Physical size extensions: PCB design information for 40mm×40mm and 50mm×50mm;

[0099] Extended Filtering Measures: Circuit Topology and Parameters of π-Type Filters;

[0100] Shielding measures expanded to include shielding cover structures for partial and overall shielding;

[0101] Grounding optimization extension: via layout and quantity;

[0102] Software configuration extensions: configuration parameters for spread spectrum function and drive strength;

[0103] Environment variable expansion: test conditions for the load.

[0104] • The quantization layer stores the quantized contribution values ​​of changes in each design variable, including:

[0105] Measured values ​​(e.g., 45dBμV / m, 43dBμV / m, 42dBμV / m, etc.);

[0106] Changes relative to a reference (e.g., -12dB, -18dB, -20dB, -6dB, -7dB, -3dB, etc.);

[0107] Influence coefficient of continuous variables (e.g., -1.5dB / 10mm);

[0108] The overall effect of the measures (such as the combined impact of the shielding on radiation, conduction, and ESD).

[0109] • The tag layer stores multidimensional searchable tags, including:

[0110] Manufacturer information: XXX Company;

[0111] Product code: XXX;

[0112] Functional category tag: Power supplies;

[0113] Package label: SOP-8;

[0114] Frequency label: Intermediate frequency;

[0115] Performance label: EMI rating Class A;

[0116] Sensitivity rating labels: Filter sensitive, Shield sensitive, Medium grounding sensitivity, Spread spectrum sensitive, Drive strength sensitive;

[0117] Temperature rating label: Automotive grade (-40℃~125℃);

[0118] Reliability rating label: AEC-Q100 Grade 1.

[0119]

Example 2

[0120] This embodiment takes a certain type of CAN transceiver as an example. This IC is a communication chip, which adopts SOIC-8 package and operates in the intermediate frequency range.

[0121] First, baseline data was acquired. A benchmark PCB was designed according to the first rule set, containing a CAN transceiver, terminating resistors, and decoupling capacitors, forming the minimum operating circuit. The benchmark PCB measures 30mm × 30mm, employs a two-layer structure, and its port layout conforms to the CAN bus standard. Conducted emission testing was performed according to the IEC 62228 standard, with a test frequency range of 150kHz to 30MHz. The test results showed a common-mode conducted emission peak of 65dBμV at 5MHz. This test data was recorded as the first set of test data.

[0122] Next, simulation calibration is performed. A three-dimensional electromagnetic simulation model is established based on the benchmark PCB, with a behavioral-level model used for the IC portion. Electromagnetic simulation is performed under the same conditions as the test to obtain the first simulation data. The first simulation data is compared with the first test data, and the PCB material parameters and parasitic parameters in the simulation model are adjusted to ensure that the deviation between the two is less than a preset threshold. The calibration is then completed, and the calibration parameters are recorded.

[0123] Next, extended data acquisition is performed. Following the second rule set, single design variables are successively changed based on the minimum system, and extended tests are conducted. For each extended test, a corresponding simulation model is built, and second simulation data is obtained and cross-validated with the test data. For simplicity, the test results are described below.

[0124] Extended Filtering Test: A common-mode choke was added to the CAN bus on the benchmark board. The choke model was XXX, and the common-mode inductance was XXXμH. Test results showed that after adding the common-mode choke, the peak conducted emission at 5MHz decreased to 48dBμV. Quantization calculations showed that this filtering measure reduced conducted emissions by 17dB (the change relative to the benchmark).

[0125] Layout optimization extended testing: Based on the benchmark test board, the CAN bus routing was changed from long, loose traces to tightly coupled differential pair traces, and the differential pair spacing was adjusted to X mm. Test results show that after layout optimization, the conducted emission peak at 5 MHz decreased to 55 dBμV. Quantitative calculations show that layout optimization reduced conducted emissions by 10 dB (the change relative to the benchmark).

[0126] Finally, asset construction is carried out. All the above data is organized into a hierarchical data asset structure.

[0127] • The IC basic information layer stores identification information (manufacturer information such as YYY company, product code such as XXX), physical parameters (package type SOIC-8, number of pins 8, pin pitch 1.27mm), electrical parameters (operating voltage range, etc.), environmental adaptability parameters (temperature characteristics, etc.), reliability parameters (ESD level, etc.), and other information.

[0128] • The reference layer stores the first test data (65dBμV at 5MHz), the calibrated first simulation model, and the PCB design information used for the benchmark test (including 30mm×30mm size, two-layer board structure, port layout, etc.).

[0129] • The extension layer stores test data for each extension dimension, corresponding second simulation data, and PCB design information used for each extension test:

[0130] Extended filtering measures: Circuit parameters and layout information of common-mode chokes;

[0131] Layout optimization extension: Design parameters for differential pair traces (trace width, spacing, length, etc.).

[0132] • The quantization layer stores the quantized contribution values ​​of changes in each design variable, including:

[0133] Measured values ​​(e.g., 65dBμV, 48dBμV, 55dBμV);

[0134] Changes relative to a reference (e.g., -17dB, -10dB).

[0135] • The tag layer stores multidimensional searchable tags, including:

[0136] Manufacturer information: YYY Company;

[0137] Product code: XXX;

[0138] Functional category tag: Communication;

[0139] Package label: SOIC-8;

[0140] Frequency label: Intermediate frequency;

[0141] Performance label: EMI rating: Class D;

[0142] Sensitivity rating for measures: Common mode choke highly sensitive, layout moderately sensitive;

[0143] Temperature rating label: Industrial grade (-40℃~85℃);

[0144] Reliability rating label: Meets industrial-grade requirements.

[0145]

Example 3

[0146] This embodiment takes a certain model of 50MHz crystal oscillator as an example. This IC is a clock chip, which adopts SMD packaging and operates at a high frequency (50MHz).

[0147] First, baseline data was acquired. A benchmark PCB was designed according to the first rule set. The PCB measures 30mm × 30mm and uses a two-layer structure. A complete ground plane was laid beneath the crystal oscillator, and necessary load capacitors were arranged around the crystal oscillator. Radiated emission testing was performed according to the IEC 61967 standard, with a test frequency range of 30MHz to 200MHz. The test results showed a peak radiation value of 52dBμV / m at the fundamental frequency of 50MHz and a peak radiation value of 48dBμV / m at the second harmonic at 100MHz. This test data was recorded as the first set of test data.

[0148] Next, simulation calibration is performed. A three-dimensional electromagnetic simulation model is established based on the benchmark PCB, with a behavioral-level model used for the IC portion. Electromagnetic simulation is performed under the same conditions as the test to obtain the first simulation data. The first simulation data is compared with the first test data. By adjusting the PCB material parameters and crystal oscillator parasitic parameters in the simulation model, the deviation between the two is made less than a preset threshold, thus completing the calibration. The calibration parameters are then recorded.

[0149] Next, extended data acquisition is performed. Following the second rule set, single design variables are successively changed based on the minimum system, and extended tests are conducted. For each extended test, a corresponding simulation model is built, and second simulation data is obtained and cross-validated with the test data. For simplicity, the test results are described below.

[0150] Grounding optimization extended testing: Based on the benchmark test board, the integrity of the ground plane below the crystal oscillator was optimized, the number of grounding vias was increased from 3 to 8, and the via layout was optimized. Test results show that after grounding optimization, the radiated peak at the fundamental frequency of 50MHz decreased to 46dBμV / m. Quantitative calculations show that grounding optimization reduced radiated emissions by 6dB (the change relative to the benchmark).

[0151] Layout Adjustment Extended Testing: Based on the benchmark test board, the crystal oscillator was moved from the edge of the PCB to the center, while other layout conditions remained unchanged. Test results showed that after the layout adjustment, the peak radiated emission at the fundamental frequency of 50MHz decreased to 47dBμV / m. Quantitative calculations showed that the layout adjustment reduced radiated emissions by 5dB (the change relative to the benchmark).

[0152] Finally, asset construction is carried out. All the above data is organized into a hierarchical data asset structure.

[0153] • The IC basic information layer stores identification information (manufacturer information such as ZZZ company, product code such as XXX), physical parameters (package type SMD, number of pins 4, pin pitch, etc.), electrical parameters (operating frequency 50MHz, drive capability, etc.), functional classification (clock type), environmental adaptability parameters, reliability parameters, and other information.

[0154] • The reference layer stores the first test data (52dBμV / m at 50MHz, 48dBμV / m at 100MHz), the calibrated first simulation model, and the PCB design information used for the benchmark test (including 30mm×30mm size, two-layer board structure, ground plane layout under the crystal oscillator, etc.).

[0155] • The extension layer stores test data for each extension dimension, corresponding second simulation data, and PCB design information used for each extension test:

[0156] Grounding optimization extension: Number (8) and layout information of grounding vias;

[0157] Layout adjustment and expansion: the position (center position) of the crystal oscillator on the PCB and the routing layout.

[0158] • The quantization layer stores the quantized contribution values ​​of changes in each design variable, including:

[0159] Measured values ​​(e.g., 52dBμV / m, 46dBμV / m, 47dBμV / m);

[0160] The amount of change relative to a reference (e.g., -6dB, -5dB).

[0161] • The tag layer stores multidimensional searchable tags, including:

[0162] Manufacturer information: ZZZ Company;

[0163] Product code: XXX;

[0164] Functional category tag: Clocks;

[0165] Package label: SMD;

[0166] Frequency label: High frequency;

[0167] Performance label: EMI rating B;

[0168] Temperature rating label: Consumer grade (0℃~70℃);

[0169] Reliability rating label: Meets consumer-grade reliability requirements.

[0170] Application Examples

[0171] The data assets constructed by this invention can be applied to the following scenarios:

[0172] 1. IC selection scenarios

[0173] Designers can quickly locate ICs with the required functional types and operating frequency ranges by searching the multi-dimensional tags of data assets. For example, for a power management application, the following three candidate ICs can be retrieved from the data assets:

[0174] IC Model Reference radiation (150MHz) Filtering effect Shielding measures effectiveness Functional Classification Packaging IC-A 45dBμV / m 12dB 18dB Power supply SOP-8 IC-B 52dBμV / m 15dB 20dB Power supply SOP-8 IC-C 48dBμV / m 8dB 12dB Power supply SOP-8

[0175] By comparing the intrinsic data of the baseline layer, IC-A exhibits the lowest electromagnetic radiation. Further investigation of its sensitivity label reveals that this IC is highly sensitive to both filtering and shielding, allowing for targeted protection through appropriate design measures. Therefore, designers can select IC-A and add a π-type filter (expected to reduce radiation by 12dB) or a local shielding cover (expected to reduce radiation by 18dB) at the power input to ensure the final product meets EMC requirements.

[0176] 2. Scenario for Demonstrating Domestic IC Substitution

[0177] In domestic substitution projects, the feasibility of substitution can be quantitatively assessed by comparing the baseline intrinsic data and sensitivity labels of imported and domestically produced ICs. For example, the comparative data for a certain communication interface IC is as follows:

[0178] index Imported ICs Domestic IC Difference Reference conducted emission (5MHz) 65dBμV 68dBμV +3dB Electrostatic discharge immunity ±8kV ±6kV -2kV Common mode choke sensitivity Highly sensitive Highly sensitive same Layout optimization sensitivity Moderate sensitivity Moderate sensitivity same

[0179] Analysis shows that although the intrinsic conducted emissions of the domestically produced IC are slightly higher by 3dB, it is highly sensitive to common-mode chokes. The overall conducted emissions can be reduced to 51dBμV by adding a common-mode choke (expected to reduce by 17dB), which is superior to imported ICs. Furthermore, the immunity level and sensitivity labels are consistent. Based on these factors, this domestically produced IC is a feasible alternative.

[0180] 3. Electromagnetic protection design scenarios

[0181] In system-level electromagnetic interference (EMI) protection design, the main interference sources can be located and targeted protection measures can be implemented by analyzing the EMI contribution and sensitivity labels of each IC in the system. For example, the EMI contribution analysis results of a certain control system are as follows:

[0182] IC type EMI contribution (dBμV / m) Sensitivity label of measures Power IC 58 Shielding sensitive (high) Clock IC 52 Grounding sensitivity (moderate) Communication IC 45 Layout sensitive (moderate) Logic IC 38 Filter sensitivity (low) RF IC 42 Shielding sensitivity (moderate)

[0183] Analysis revealed that the power supply IC was the primary source of interference (58dB) and highly sensitive to shielding measures; therefore, a separate shielding cover was added to it (expected to reduce EMI by 18dB). The clock IC was a secondary source of interference and sensitive to grounding optimization; therefore, its underlying ground plane was optimized and a grounding via was added (expected to reduce EMI by 6dB). Simultaneously, local shielding and grounding optimization measures were implemented for the entire PCB. Through precise protection, the system EMI can be reduced to below 45dB, meeting design requirements.

[0184] The embodiments and application examples described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for constructing IC-level electromagnetic compatibility (EMC) data assets, characterized in that, Including the following: Baseline data acquisition: For the target IC, design and manufacture the minimum system test PCB that enables it to work properly according to the first rule set, perform EMC testing, and obtain the first test data that reflects the intrinsic EMC characteristics of the IC; Extended data acquisition: Based on the minimum system, an extended test PCB is designed and fabricated by changing a single design variable according to the second rule set, and EMC testing is performed to obtain second test data reflecting the impact of the design variable on EMC performance; wherein, each extended test changes only one design variable, and all other relevant conditions remain unchanged, including the benchmark test state or the state of the previous extended test; Asset Construction: The identification information, physical parameters, electrical parameters, environmental adaptability parameters, reliability parameters, PCB design information used for the benchmark and extended tests, the first test data, the second test data, and the first and second simulation data of the target IC are organized into data assets according to a preset data structure. The data assets are then assigned multi-dimensional searchable tags, which include at least one or more of the following: manufacturer information, product code, IC function classification, package type, operating frequency range, EMI performance level, sensitivity to measures, temperature level, and reliability level.

2. The method according to claim 1, characterized in that, The first rule set includes at least one of the following rules: Circuit integrity rules are used to ensure the proper configuration of peripheral circuits for IC operation. Physical dimension baseline rules are used to define baseline PCB dimensions; The basic rules for stacked structures are used to define the basic stacked structure. Port layout baseline rules are used to define the baseline parameters for port routing; Decoupling scheme baseline rules are used to define standard decoupling configurations; Grounding method reference rules are used to define standard grounding methods.

3. The method according to claim 1, characterized in that, The design variables in the second rule set include at least one of the following types: Physical dimension variables, including the planar dimensions of the PCB; Layer stack-up variables include the number of PCB layers, layer stack-up order, and dielectric thickness; Filtering measures variables include the presence, type, and parameters of the filter circuit; Variables of shielding measures include the presence, material, size, and grounding method of the shielding cover; Grounding optimization variables include the number, location, and connection method of grounding vias; Layout adjustment variables include the position of the IC on the PCB and the layout of peripheral components; Software configuration variables include configurable spread spectrum function, drive strength, slew rate, and operating mode parameters within the IC; Environmental variables include ambient temperature, load conditions, and input voltage.

4. The method according to claim 1, characterized in that, It also includes quantitative analysis: The second test data obtained from different extended tests are compared with the first test data, and / or the second test data obtained from different extended tests are compared with each other to calculate the quantitative contribution value of each design variable change to EMC performance and the relative effect between different variables.

5. The method according to claim 4, characterized in that, The quantified contribution value includes at least one of the following forms: Measured values, extended test data expressed in EMC test standard units (including dBμV, dBμV / m, dBμA, dBμA / m); The difference between the extended test data and the benchmark test data, expressed in dB, relative to the change from the benchmark. The amount of change between extensions, expressed in dB, is the difference between test data of different extensions. The influence coefficient of a continuous variable is the change in EMC index caused by a change in a unit continuous design variable, expressed in dB per variable unit (e.g., dB / mm, dB / Ω, dB / ℃). The comprehensive effect value of the measures is the combined impact of a single discrete design variable change on multiple EMC indicators (including EMI, EMS, etc.), expressed as the set of changes in each indicator or a comprehensive evaluation index. Sensitivity level refers to the degree of responsiveness of an IC to different hardware or software measures. The ranking of effectiveness, and the relative order or classification of the degree of influence of different design variables on EMC performance.

6. The method according to claim 1, characterized in that, It also includes simulation calibration: Establish a first simulation model corresponding to the minimum system test PCB, and perform simulation to obtain first simulation data; The first simulation data and the first test data are correlated and calibrated to make the deviation between them less than a preset threshold. Record the calibration parameters and include the first simulation model and the calibration parameters as part of the data asset.

7. The method according to claim 1, characterized in that, The data assets have a hierarchical structure and include at least: The IC basic information layer stores at least one of the following: the target IC's identification information, physical parameters, electrical parameters, environmental adaptability parameters, and reliability parameters. The baseline layer stores the first test data, the corresponding first simulation model, and the PCB design information used for the benchmark test. An extension layer stores the second test data, the corresponding second simulation model, and the corresponding PCB design information in at least one extended dimension. The quantification layer stores the quantified contribution values ​​of the design variable changes to EMC performance; The tag layer stores the multidimensional searchable tags.

8. The method according to claim 1, characterized in that, The multidimensional searchable tags include at least one of the following categories: IC function classification labels indicate the IC's function type, such as power supply, clock, communication, radio frequency, or logic. The package label indicates the IC's SOP, QFP, BGA, DFN, or QFN package type; The frequency label indicates the low-frequency, medium-frequency, or high-frequency operating frequency range of the IC; The performance label indicates the EMI strength rating or immunity rating of the IC; The sensitivity label indicates the IC's sensitivity level to hardware measures such as filtering, shielding, and grounding, as well as software measures such as spread spectrum and drive strength. Temperature rating label indicates the operating temperature range or rating of the IC; The reliability rating label indicates the IC's lifespan rating or certification level.

9. An IC-grade EMC data asset, characterized in that, The data asset is constructed using the method described in any one of claims 1-8, and includes at least: The IC basic information layer stores at least one of the following: the target IC's identification information, physical parameters, electrical parameters, environmental adaptability parameters, and reliability parameters. The baseline layer stores the first test data, the corresponding first simulation model, and the PCB design information used for the benchmark test. An extension layer stores the second test data under at least one extension dimension, the corresponding second simulation model, and the PCB design information used for the extension test. The quantification layer stores the quantified contribution values ​​of the design variable changes to EMC performance; The tag layer stores multidimensional searchable tags.

10. A system for constructing IC-level EMC data assets, characterized in that, include: The rule management module is used to store and manage the first rule set and the second rule set; The benchmark module is used to test the IC in a minimum system according to the first rule set and obtain the first test data. An extended test module is used to test the IC after a single design variable is changed according to the second rule set and to obtain second test data. The quantitative analysis module is used to compare the second test data with the first test data and calculate the quantitative contribution value of the design variable change to EMC performance. The asset construction module is used to organize the target IC's identification information, physical parameters, electrical parameters, environmental adaptability parameters, reliability parameters, test data, simulation data, and PCB design information into data assets and assign them multi-dimensional searchable tags; A storage module is used to store the data assets.

Images