A method and device for optimizing leakage power consumption of a chip

Abstract

The present application relates to a leakage power consumption optimization method and device of a chip. The method comprises: finding a timing logic device whose threshold voltage is lower than a predetermined threshold voltage in a circuit to form an initial device set; determining a first feature and a second feature of the timing logic device, the first feature comprising a timing margin of the timing logic device, and the second feature comprising a judgment result of whether there exists a replaceable target timing logic device corresponding to the timing logic device in a device library, the target timing logic device having a same function type as the timing logic device and a threshold voltage higher than that of the timing logic device; selecting a replaceable timing logic device from the initial device set according to the first feature, the second feature and a leakage power consumption optimization strategy parameter; and replacing the replaceable timing logic device in the target circuit with the target timing logic device. The method effectively reduces the leakage power consumption of the chip and improves the energy efficiency ratio of the chip under the premise of ensuring the timing performance of the circuit.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of chip design and implementation, and in particular to a method and apparatus for optimizing the leakage power consumption of a chip. Background Technology

[0002] With the improvement of chip manufacturing technology, leakage power consumption accounts for an increasing proportion of the total power consumption of chip products. Optimizing leakage power consumption is a technical problem that urgently needs to be solved. Summary of the Invention

[0003] To address the problems existing in the prior art, this specification provides a method and apparatus for optimizing the leakage power consumption of a chip. The method involves screening out low-threshold voltage type sequential logic devices in the circuit, extracting the timing margin values ​​of these devices on multiple timing paths, performing annealing optimization based on the timing margin values ​​on each timing path to obtain target sequential logic devices that meet the replacement conditions, replacing the target sequential logic devices, and determining whether the leakage power consumption of the circuit meets the standard. If it does not meet the standard, the above steps are repeated for the replaced circuit until the final leakage power consumption meets the standard.

[0004] The specific technical solutions of the embodiments in this specification are as follows: On one hand, embodiments of this specification provide a method for optimizing the leakage power consumption of a chip, the method comprising: Locate sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage, and form an initial device set; A first feature and a second feature of the sequential logic device are determined. The first feature includes the timing margin of the sequential logic device. The second feature includes a judgment result on whether there is a replaceable target sequential logic device corresponding to the sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. Based on the first feature, the second feature, and the leakage power consumption optimization strategy parameters, optimizeable sequential logic devices are selected from the initial device set. Replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

[0005] Furthermore, the leakage power consumption optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference; The selection of optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and the leakage current power consumption optimization strategy parameters further includes: Based on the condition that the timing margin is less than the predetermined margin threshold, sequential logic devices are selected from the initial device set to form a first subset; Based on the condition that no replaceable target sequential logic device corresponding to the sequential logic device exists in the device library, sequential logic devices are filtered from the initial device set to form a second subset. The condition that no replaceable target sequential logic device corresponding to the sequential logic device exists in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is greater than or equal to the threshold voltage level of the sequential logic device. Determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

[0006] Furthermore, selecting a first subset from the initial device set based on the condition that the timing margin is less than a predetermined margin threshold further includes: Based on the timing margin of the sequential logic device on multiple timing paths in the target circuit and the conditions of the predetermined margin threshold corresponding to each timing path, a subset corresponding to each timing path is selected from the initial device set. The first subset is obtained by determining the union of the subsets corresponding to all time-series paths.

[0007] Furthermore, the method also includes: If the set of optimized devices is empty, the leakage power consumption optimization of the target circuit ends.

[0008] Furthermore, the method also includes: Determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the step of finding and replacing sequential logic devices in the target circuit whose threshold voltage is lower than the predetermined threshold voltage will be performed again. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

[0009] Furthermore, after completing the leakage current and power consumption optimization of the target circuit, the method further includes: Calculate the key performance indicators of the optimized target circuit; The parameters of the leakage current power consumption optimization strategy are adjusted based on the key indicators.

[0010] Furthermore, the key indicators include the decrease in area / proportion of sequential logic devices with threshold voltages lower than a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

[0011] Furthermore, adjusting the leakage current power consumption optimization strategy parameters based on the key indicators includes: If the key indicators do not meet the predetermined requirements, the parameters of the leakage power consumption optimization strategy will be adjusted.

[0012] On the other hand, embodiments of this specification also provide a chip leakage power optimization device, the device comprising: The low threshold voltage device lookup unit is used to find sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage, and form an initial device set. The feature analysis unit is used to determine a first feature and a second feature of the sequential logic device. The first feature includes the timing margin of the sequential logic device. The second feature includes a judgment result on whether there is a replaceable target sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. An optimizable device screening unit is used to screen optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and leakage power consumption optimization strategy parameters. The replacement optimization unit is used to replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

[0013] Furthermore, the leakage power consumption optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference; The optimizable device screening unit includes a first subset screening module, a second subset screening module, and a union inversion module; The first subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that the timing margin is less than the predetermined margin threshold, to form a first subset; The second subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library, forming a second subset. The condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is greater than or equal to the threshold voltage level of the sequential logic device. The union inversion module is used to determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

[0014] Furthermore, selecting a first subset from the initial device set based on the condition that the timing margin is less than a predetermined margin threshold further includes: Based on the timing margin of the sequential logic device on multiple timing paths in the target circuit and the conditions of the predetermined margin threshold corresponding to each timing path, a subset corresponding to each timing path is selected from the initial device set. The first subset is obtained by determining the union of the subsets corresponding to all time-series paths.

[0015] Furthermore, the optimizable device screening unit is further configured to: terminate the leakage power consumption optimization of the target circuit when the set of optimized devices is empty.

[0016] Furthermore, the device also includes an optimization compliance judgment unit, used to determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the low threshold voltage device search unit, feature analysis unit, optimizable device screening unit and replacement optimization unit are triggered to optimize the leakage power consumption of the target circuit after replacement. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

[0017] Furthermore, the device also includes a leakage power optimization strategy parameter adjustment unit, used to calculate the key indicators of the optimized target circuit after the leakage power optimization of the target circuit is completed; and to adjust the leakage power optimization strategy parameters according to the key indicators.

[0018] Furthermore, the key indicators include the decrease in area / proportion of sequential logic devices with threshold voltages lower than a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

[0019] Furthermore, the leakage power consumption optimization strategy parameter adjustment unit adjusts the leakage power consumption optimization strategy parameters according to the key indicators, including: If the key indicators do not meet the predetermined requirements, the parameters of the leakage power consumption optimization strategy will be adjusted.

[0020] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0021] On the other hand, embodiments of this specification also provide a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0022] The method described in this specification optimizes leakage power consumption during the physical layout stage. It introduces physical awareness into the engineering environment by identifying sequential logic devices in the circuit whose threshold voltage is lower than a predetermined threshold voltage, forming an initial device set. This initial device set represents the range within which sequential logic devices can be replaced in the circuit. Then, from this range, sequential logic devices are filtered based on their first and second characteristics to select optimizable sequential logic devices. This avoids an excessively large replacement range, ensures a controllable data model, and improves the efficiency of leakage power consumption optimization. The first characteristic of this specification's embodiments includes the timing margin of the sequential logic devices, thereby optimizing the leakage power consumption of the circuit from the perspective of physical layout and the specificity of the sequential logic devices. It considers the timing margin of the timing paths between sequential logic devices, maintaining timing and area to a certain extent, reducing leakage power consumption, and thus maintaining the quality requirements of chip implementation in terms of timing, area, and power consumption to a certain extent. The second feature includes the determination result of whether there is a replaceable target sequential logic device in the device library. This ensures that the original relevant attributes are maintained during the response phase after the sequential logic device replacement is completed. Then, incremental optimization of the circuit's physical layout is performed. This process does not require the introduction of third-party tools, thereby improving process efficiency and consistency. The method in this specification's embodiments constructs an operating space for optimizing leakage power consumption based on physical layout and engineering environment. Compared to existing methods, the method in this specification's embodiments is not limited to a purely logic engineering environment. After optimization, it can also provide various parameter information of the sequential logic device, solving the problem of data extraction accuracy in engineering for reducing leakage power consumption. If the remaining path after optimization has engineering optimization problems related to timing, power consumption, and area, it can provide technical guidance for subsequent design stages.

[0023] The method described in this specification can perform multiple iterations to optimize leakage power consumption, thereby improving the optimization effect of leakage power consumption. Furthermore, the number of iterations can be set to make the number of iterations for replacing low-threshold voltage type sequential logic devices in the circuit controllable and reduce invalid iterations. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The diagram shows the physical layout in the prior art from the initial indeterminate state to the optimized stable state; Figure 2 The diagram shown is a flowchart illustrating a method for optimizing leakage power consumption of a chip in an embodiment of this specification. Figure 3 The diagram shown is a flowchart illustrating how, in an embodiment of this specification, optimizable sequential logic devices are selected from the initial device set based on the first feature, the second feature, and leakage power consumption optimization strategy parameters. Figure 4 The diagram shown is a flowchart illustrating the adjustment of the leakage power consumption optimization strategy parameters in an embodiment of this specification. Figure 5 The diagram shown is a schematic diagram of the structure of a chip leakage power consumption optimization device in an embodiment of this specification. Figure 6 The diagram shown is a structural schematic of the computer device in an embodiment of this specification.

[0026] [Explanation of Figure Markers]: 501. Low threshold voltage device lookup unit; 502. Feature Analysis Unit; 503. Optimizable device screening unit; 504. Replace and optimize the unit; 602. Computer equipment; 604, Processor; 606. Memory; 608. Drive mechanism; 610. Input / output module; 612. Input devices; 614. Output devices; 616. Presentation equipment; 618. Graphical User Interface; 620. Network interface; 622. Communication link; 624. Communication bus. Detailed Implementation

[0027] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.

[0028] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0029] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.

[0030] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0031] The inventors discovered in their research that existing leakage power optimization schemes lack consideration for the physical layout of the circuit. However, physical factors do have a certain impact on the optimization of leakage power, and engineering data based on physical layout is more accurate and reliable. Furthermore, existing solutions lack specific analysis of sequential logic devices in the circuit. They are basically based on optimizing and replacing all sequential logic devices in the circuit, and the main focus is on the paths between sequential logic devices. This results in an excessively large range of replacement targets and limitations in the types of paths analyzed. Moreover, existing solutions lack consideration or optimization for the efficiency of engineering practice, as they analyze global timing paths, resulting in massive data volumes, but not all targets need to be analyzed and extracted in engineering practice. Additionally, in terms of process arrangement, existing solutions often use third-party tools, introducing additional consistency and new efficiency issues. Finally, after implementation, existing solutions cannot guarantee that the convergence of quality requirements will not be compromised.

[0032] The inventors believe that placement is a crucial step in chip implementation, where chip implementation progresses from the RTL level to the gate level, and the circuit begins to be influenced by more physical factors in its pure logic state. These factors include inter-cell physical distance, placement density, and wiring congestion. Entering the physical placement stage with its multiple influencing factors, numerous placement optimization problems arise in chip physical implementation. However, these remain engineering optimization problems (i.e., PPA optimization problems) with three objectives: timing (Performance), power (Power), and area (Area).

[0033] The PPA optimization problem is a non-deterministic, polynomial-time hard problem involving multiple factors, making it difficult to find the optimal solution in all cases using known efficient algorithms. Therefore, while there is no unique solution for the engineering results of chip implementation, better solutions may exist. Chip implementation begins with mapping Verilog code to a standard cell library, undergoing various logic optimizations, placement, clock tree construction, and routing, culminating in the final physical layout. This series of processes represents an annealing process from the initial uncertain state of the PPA to its stable state.

[0034] Due to the complexity of chip design, timing objectives are often the top priority for annealing optimization to convergence. This necessity and priority mean that optimization resources invested in power consumption and area targets may be less than those invested in timing objectives. In the final stage of placement implementation using EDA tools, timing convergence is usually observed, but there is still an engineering result of timing margins in the global timing path. The existence of timing margins indicates at least one engineering conclusion: there exists a device cell that can be replaced, i.e., there is room for leakage power optimization.

[0035] In engineering, it is difficult to simultaneously and fully achieve the three objectives of PPA optimization during the layout process. When the timing optimization of the layout process achieves global optimal optimization, the leakage power consumption is often not in a globally optimal state, leaving room for annealing.

[0036] Specifically, such as Figure 1 As shown in (a), in an engineering environment based on pure logic synthesis, the cells do not consider the physical space of timing, area, and power consumption. The PPA results are, in fact, in an undefined state. Based on this, timing path margin analysis and the replacement of low-threshold voltage devices lead to distortion of the intrinsic characteristics of the engineering environment. Figure 1 In (b) of this specification, under a comprehensive physical engineering environment, the three major factors of timing, area, and power consumption exhibit a certain steady state. However, in engineering practice, this is usually the result of a coarse layout, and leakage power consumption under this engineering environment still exhibits distortion. No solution to this problem has been proposed in the existing technology. In the methods of the embodiments of this specification, such as... Figure 1In section (c), based on optimization during the physical layout stage, the implementation tool fully considers factors such as timing between circuit units, physical location and orientation of units (between units), regional unit density, winding blockage, and winding allocation. Timing will achieve a layout stable state after physical layout optimization, and area will also enter a stable state due to the steady state of timing. Based on engineering conclusions, when there is timing margin in the physical layout, there is room for optimization of leakage power consumption; that is, at this time, while timing and area are in a steady state, power consumption has not yet fully entered the layout steady state. This technical solution focuses on this state, and based on the physical layout engineering environment, performs efficient, accurate, and timing- and area-preserving leakage power consumption optimization when timing margin exists.

[0037] Based on the above analysis, this specification proposes a method for optimizing the leakage power consumption of a chip. Figure 2 The diagram shows a flowchart illustrating a method for optimizing leakage power consumption in a chip according to an embodiment of this specification. The optimization process for leakage power consumption is described in this diagram. The order of steps listed in the embodiment is merely one possible execution order among many steps and does not represent the only possible execution order. In actual system or device products, the method can be executed sequentially or in parallel according to the embodiment or the accompanying drawings. Specifically, as shown... Figure 2 As shown, the method may include: Step 201: Locate sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage to form an initial device set; Step 202: Determine the first feature and the second feature of the sequential logic device. The first feature includes the timing margin of the sequential logic device. The second feature includes the judgment result of whether there is a replaceable target sequential logic device corresponding to the sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. Step 203: Select optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and the leakage power consumption optimization strategy parameters; Step 204: Replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

[0038] The method described in this specification optimizes leakage power consumption during the physical layout stage. It introduces physical awareness into the engineering environment by identifying sequential logic devices in the circuit whose threshold voltage is lower than a predetermined threshold voltage, forming an initial device set. This initial device set represents the range within which sequential logic devices can be replaced in the circuit. Then, from this range, sequential logic devices are filtered based on their first and second characteristics to select optimizable sequential logic devices. This avoids an excessively large replacement range, ensures a controllable data model, and improves the efficiency of leakage power consumption optimization. The first characteristic of this specification's embodiments includes the timing margin of the sequential logic devices, thereby optimizing the leakage power consumption of the circuit from the perspective of physical layout and the specificity of the sequential logic devices. It considers the timing margin of the timing paths between sequential logic devices, maintaining timing and area to a certain extent, reducing leakage power consumption, and thus maintaining the quality requirements of chip implementation in terms of timing, area, and power consumption to a certain extent. The second feature includes the determination result of whether there is a replaceable target sequential logic device in the device library. This ensures that the original relevant attributes are maintained during the response phase after the sequential logic device replacement is completed. Then, incremental optimization of the circuit's physical layout is performed. This process does not require the introduction of third-party tools, thereby improving process efficiency and consistency. The method in this specification's embodiments constructs an operating space for optimizing leakage power consumption based on physical layout and engineering environment. Compared to existing methods, the method in this specification's embodiments is not limited to a purely logic engineering environment. After optimization, it can also provide various parameter information of the sequential logic device, solving the problem of data extraction accuracy in engineering for reducing leakage power consumption. If the remaining path after optimization has engineering optimization problems related to timing, power consumption, and area, it can provide technical guidance for subsequent design stages.

[0039] In the embodiments of this specification, sequential logic devices can be registers, etc. These embodiments can use circuit analysis tools to scan the entire target circuit and identify the threshold voltage parameters of all sequential logic devices. Sequential logic devices with threshold voltages lower than a preset threshold are selected to form an initial set of devices to be optimized. While these low-threshold-voltage devices have faster switching speeds, they also generate larger leakage currents, which is the main reason for the high static power consumption of the chip.

[0040] In some other embodiments of this specification, the library cells implemented by the chip can be pre-labeled, and the library cells can be classified according to various threshold voltages to obtain library cells with multiple threshold voltage levels. Therefore, the sequential logic devices in the target circuit that belong to the library cells corresponding to the low threshold voltage level can be found to form an initial device set.

[0041] Then, the first and second characteristics of the sequential logic devices in the initial device set are determined. The first characteristic includes the timing margin of the sequential logic device. For example, the timing margin of each device on the critical path can be calculated using static timing analysis tools; that is, the difference between the actual delay of the sequential logic device and the timing requirement. Sequential logic devices with larger timing margins indicate that their speed requirements are relatively relaxed and they have the potential to be replaced by sequential logic devices with higher threshold voltage levels.

[0042] The second feature includes determining whether a replaceable target sequential logic device exists in the device library. The device library is searched for a target sequential logic device with the same functional type as the current device but a higher threshold voltage. The target sequential logic device has the same functional type as the current sequential logic device, and its threshold voltage is higher than that of the current sequential logic device (i.e., a higher threshold voltage level). Such a target device has lower leakage current.

[0043] Then, based on the first and second characteristics and the leakage power optimization strategy parameters, optimizable sequential logic devices are selected from the initial device set. The leakage power optimization strategy parameters specify the compliance conditions corresponding to the first and second characteristics, thereby selecting optimizable sequential logic devices based on the compliance conditions. For example, for each device in the initial device set, it is first determined whether there is a corresponding replaceable target sequential logic device in the device library. If not, the device is skipped. If it exists, it is further checked whether the timing margin of the sequential logic device meets the compliance conditions to ensure that the replacement will not violate the timing constraints. Optimizable sequential logic devices that meet the timing requirements and effectively reduce power consumption are selected from the initial device set.

[0044] Finally, the optimizable sequential logic devices in the target circuit are replaced with the target sequential logic devices. In the circuit netlist, the selected optimizable devices are replaced one by one with the corresponding target sequential logic devices with high threshold voltages. Then, global placement optimization is performed again to complete incremental optimization, such as the incremental action in the final stage of place opt. In engineering practice, the placement stage is roughly divided into initial coarse placement, initial DRC solution, initial placement optimization, final legal placement, and final placement optimization. Through this replacement, while ensuring circuit functionality and timing performance, the static leakage power consumption of the chip is significantly reduced, improving the chip's energy efficiency.

[0045] According to one embodiment of this specification, the leakage current optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference. For example... Figure 3 As shown, selecting optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and leakage power consumption optimization strategy parameters further includes: Step 301: Select sequential logic devices from the initial device set based on the condition that the timing margin is less than the predetermined margin threshold to form a first subset; Step 302: Select sequential logic devices from the initial device set based on the condition that no replaceable target sequential logic device exists in the device library, forming a second subset; In this step, the condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is different from the threshold voltage level of the sequential logic device by a value equal to the threshold voltage level difference. Step 303: Determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

[0046] In the embodiments of this specification, when the timing margin of a sequential logic device is less than a predetermined margin threshold, it indicates that the sequential logic device cannot be replaced. Therefore, in the embodiments of this specification, sequential logic devices with timing margins less than the predetermined margin threshold are first selected from the initial device set to form a first subset. The sequential logic devices included in the first subset are all non-replaceable sequential logic devices.

[0047] When the threshold voltage level of a sequential logic device with the same functional type as the sequential logic device is not higher than the threshold voltage level difference, it indicates that the sequential logic device cannot be replaced. It should be noted that if there is no sequential logic device with the same functional type but a higher threshold voltage level, then the sequential logic device also cannot be replaced. Furthermore, if there is no sequential logic device with the same functional type, then the sequential logic device also cannot be replaced. Therefore, in this embodiment, the absence of a sequential logic device with the same functional type as the sequential logic device in the device library, or the absence of a sequential logic device whose threshold voltage level differs from the threshold voltage level of the sequential logic device by a value equal to the threshold voltage level difference, serves as the filtering condition to select irreplaceable sequential logic devices from the initial device set, forming a second subset.

[0048] Therefore, it can be seen that both the first and second subsets include irreplaceable sequential logic devices. Since some sequential logic devices do not fall into all of the above categories, this embodiment determines the union of the first and second subsets. The sequential logic devices in the union are all irreplaceable sequential logic devices in the initial device set. Then, by inverting this union, an optimized device set including optimizable sequential logic devices can be obtained.

[0049] The optimization method described above allows for the replacement of low-threshold voltage devices with high-threshold voltage devices while maintaining circuit timing performance, significantly reducing leakage current power consumption. The leakage current of high-threshold voltage devices is typically more than an order of magnitude lower than that of low-threshold voltage devices, thus effectively optimizing the overall chip power consumption. This method, through a systematic device selection and replacement strategy, ensures the reliability and effectiveness of the optimization process.

[0050] Preferably, this embodiment of the specification obtains the timing margin of sequential logic devices on a predetermined plurality of timing paths. These plurality of timing paths may include reg2reg, reg2out, and in2reg. The timing margins on these three timing paths are obtained respectively. Then, based on the timing margins of the sequential logic devices on the reg2reg, reg2out, and in2reg timing paths and the predetermined margin thresholds corresponding to each timing path, subsets corresponding to each timing path are selected from the initial device set. Because some sequential logic devices may not all exist on the reg2reg, reg2out, and in2reg timing paths, this embodiment of the specification determines the union of the subsets corresponding to all timing paths to obtain the first subset.

[0051] The above method can accurately identify sequential logic devices in the target circuit that can be optimized for leakage current consumption, while ensuring that the optimization process does not violate the timing constraints of each timing path. This method considers both device substitutability and timing margin constraints, improving the accuracy and reliability of power consumption optimization.

[0052] According to one embodiment of this specification, a special case where the optimized device set is empty also needs to be handled. If the optimized device set is empty, the leakage power optimization of the target circuit is terminated. This situation indicates that there are no sequential logic devices in the current circuit that meet the optimization conditions, and continuing the optimization operation will not yield effective results. Therefore, terminating the optimization process in a timely manner can avoid unnecessary computational overhead.

[0053] In a specific embodiment of the circuit leakage power optimization method, after the replacement of optimizable sequential logic devices is completed, the optimized target circuit needs to undergo leakage power compliance evaluation and iterative optimization. Specifically, according to one embodiment of this specification, the method further includes: Determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the step of finding and replacing sequential logic devices in the target circuit whose threshold voltage is lower than the predetermined threshold voltage will be performed again. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

[0054] In the embodiments of this specification, firstly, leakage power consumption is measured and analyzed on the target circuit after replacing the optimized sequential logic devices. The system performs static power consumption analysis on the optimized target circuit using circuit simulation tools, calculates the sum of leakage currents of each device in the circuit, and compares the leakage power consumption value with a preset power consumption threshold. The preset power consumption threshold is usually determined according to the application scenario and power consumption requirements of the circuit, and this embodiment of the specification does not impose any limitations.

[0055] The system compares and analyzes data to determine whether the leakage power consumption of the replaced target circuit meets the design requirements. If the measured leakage power consumption value is lower than or equal to the preset power consumption threshold, it indicates that the leakage power consumption of the circuit has met the standard, and the system will end the leakage power consumption optimization process of the target circuit and output the final optimized circuit design scheme.

[0056] If the measured leakage power consumption value is still higher than the preset power consumption threshold, it indicates that the current optimization level is insufficient to meet the power consumption requirements, and further iterative optimization is needed. In this case, the following optimization steps are performed again: find and replace sequential logic devices in the target circuit whose threshold voltage is lower than the predetermined threshold voltage; form an initial device set; determine the first and second characteristics of the sequential logic devices; select optimizable sequential logic devices from the initial device set based on the first and second characteristics and leakage power consumption optimization strategy parameters; and replace the optimizable sequential logic devices in the target circuit with the target sequential logic devices.

[0057] During iterative optimization, the current target circuit after replacement can be fully rescanned to identify sequential logic devices with threshold voltages lower than a predetermined threshold voltage. These devices may have been excluded from the previous optimization round due to meeting the screening criteria of the first and second features, or they may be newly emerging optimization candidate devices due to changes in circuit topology. The method in the embodiments of this specification re-evaluates the replaceability of these devices and then selects the corresponding sequential logic devices with higher threshold voltages for replacement.

[0058] This iterative optimization mechanism gradually reduces the leakage power consumption of the target circuit until the preset power consumption requirement is met. Each iteration further reduces the number of low-threshold voltage sequential logic devices in the circuit, thereby continuously improving the leakage power consumption performance. This method ensures that the power consumption characteristics of the circuit are optimized to the maximum extent while meeting the timing and functional requirements, providing an effective solution for low-power circuit design.

[0059] In some other embodiments of this specification, a maximum number of iterations can be set, and the actual number of iterations cannot exceed the set maximum number of iterations. If the leakage power consumption of the circuit still does not meet the standard when the actual number of iterations exceeds the maximum number of iterations, the optimization ends. This makes the number of iterations for replacing low threshold voltage type sequential logic devices in the circuit controllable and reduces invalid iterations.

[0060] In the embodiments of this specification, the leakage power optimization strategy parameters are empirical or experimental values. The selection of these parameters will affect the selection of optimizable sequential logic devices and the timing and area of ​​the replaced circuit. Therefore, the embodiments of this specification propose adjusting the leakage power optimization strategy parameters based on whether the leakage power of the replaced circuit meets the standard, thereby improving the leakage power optimization effect while ensuring circuit quality.

[0061] Specifically, such as Figure 4 As shown, after optimizing the leakage power consumption of the target circuit, the method further includes: Step 401: Calculate the key performance indicators of the optimized target circuit; Step 402: Adjust the leakage current power consumption optimization strategy parameters according to the key indicators.

[0062] In the embodiments of this specification, the key indicators include, but are not limited to, the decrease in area / percentage of sequential logic devices with threshold voltages lower than a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

[0063] If the aforementioned key indicators do not meet the predetermined requirements, the leakage power optimization strategy parameters will be adjusted accordingly, such as increasing or decreasing the predetermined margin threshold and the threshold voltage level difference. Optionally, a model for adjusting the leakage power optimization strategy parameters can be trained, taking the difference between the key indicators of the replaced target circuit and the predetermined requirements, as well as the current values ​​of the leakage power optimization strategy parameters, as input to the model, and outputting the adjusted leakage power optimization strategy parameters.

[0064] Through this iterative process of calculating key indicators and adjusting parameters, the optimal reduction in leakage power consumption can be achieved while ensuring the correctness of circuit function and timing requirements. This ensures that the optimized target circuit meets both performance indicators and power consumption optimization goals.

[0065] Based on the same inventive concept, embodiments of this specification also provide a chip leakage power consumption optimization device, such as... Figure 5 As shown, the device includes: The low threshold voltage device lookup unit 501 is used to find sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage, and form an initial device set. The feature analysis unit 502 is used to determine a first feature and a second feature of the sequential logic device. The first feature includes the timing margin of the sequential logic device. The second feature includes a judgment result of whether there is a replaceable target sequential logic device corresponding to the sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. The optimizable device screening unit 503 is used to screen out optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and the leakage power consumption optimization strategy parameters. The replacement optimization unit 504 is used to replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

[0066] Furthermore, the leakage power consumption optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference; The optimizable device screening unit 503 includes a first subset screening module, a second subset screening module, and a union inversion module; The first subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that the timing margin is less than the predetermined margin threshold, to form a first subset; The second subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library, forming a second subset. The condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is greater than or equal to the threshold voltage level of the sequential logic device. The union inversion module is used to determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

[0067] Furthermore, selecting a first subset from the initial device set based on the condition that the timing margin is less than a predetermined margin threshold further includes: Based on the timing margin of the sequential logic device on multiple timing paths in the target circuit and the conditions of the predetermined margin threshold corresponding to each timing path, a subset corresponding to each timing path is selected from the initial device set. The first subset is obtained by determining the union of the subsets corresponding to all time-series paths.

[0068] Furthermore, the optimizable device screening unit 503 is further configured to: terminate the leakage power consumption optimization of the target circuit when the set of optimized devices is empty.

[0069] Furthermore, the device also includes an optimization compliance judgment unit, used to determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the low threshold voltage device search unit 501, feature analysis unit 502, optimizable device screening unit 503 and replacement optimization unit 504 are triggered to optimize the leakage power consumption of the target circuit after replacement. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

[0070] Furthermore, the device also includes a leakage power optimization strategy parameter adjustment unit, used to calculate the key indicators of the optimized target circuit after the leakage power optimization of the target circuit is completed; and to adjust the leakage power optimization strategy parameters according to the key indicators.

[0071] Furthermore, the key indicators include the decrease in area / proportion of sequential logic devices with threshold voltages lower than a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

[0072] Furthermore, the leakage power consumption optimization strategy parameter adjustment unit adjusts the leakage power consumption optimization strategy parameters according to the key indicators, including: If the key indicators do not meet the predetermined requirements, the parameters of the leakage power consumption optimization strategy will be adjusted.

[0073] The beneficial effects obtained by the above-described device are the same as those obtained by the above-described method, and will not be described in detail in the embodiments of this specification.

[0074] like Figure 6 The diagram shown is a structural schematic of a computer device according to an embodiment of this specification. The methods described in this specification can be applied to the computer device of this embodiment.

[0075] Computer device 602 may include one or more processors 604, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. Computer device 602 may also include any memory 606 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, memory 606 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any storage resource can be used to store information using any technology.

[0076] Furthermore, any storage resource can provide volatile or non-volatile retention of information.

[0077] Furthermore, any storage resource can represent a fixed or removable component of the computer device 602. In one case, when the processor 604 executes associated instructions stored in any storage resource or combination of storage resources, the computer device 602 can perform any operation of the associated instructions. The computer device 602 also includes one or more drive mechanisms 608 for interacting with any storage resource, such as a hard disk drive system, an optical disk drive system, etc.

[0078] Computer device 602 may also include an input / output module 610 (I / O) for receiving various inputs (via input device 612) and providing various outputs (via output device 614). A specific output mechanism may include a presentation device 616 and an associated graphical user interface (GUI) 618. In other embodiments, the input / output module 610 (I / O), input device 612, and output device 614 may be omitted, and the device may function solely as a computer device within a network. Computer device 602 may also include one or more network interfaces 620 for exchanging data with other devices via one or more communication links 622. One or more communication buses 624 couple the components described above together.

[0079] Communication link 622 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 622 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0080] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0081] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.

[0082] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0083] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0084] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.

[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0086] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0088] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0089] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.

Claims

1. A method for optimizing leakage current and power consumption of a chip, characterized in that, The method includes: Locate sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage, and form an initial device set; A first feature and a second feature of the sequential logic device are determined. The first feature includes the timing margin of the sequential logic device. The second feature includes a judgment result on whether there is a replaceable target sequential logic device corresponding to the sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. Based on the first feature, the second feature, and the leakage power consumption optimization strategy parameters, optimizeable sequential logic devices are selected from the initial device set. Replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

2. The method according to claim 1, characterized in that, The leakage current power consumption optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference; The selection of optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and the leakage current power consumption optimization strategy parameters further includes: Based on the condition that the timing margin is less than the predetermined margin threshold, sequential logic devices are selected from the initial device set to form a first subset; Based on the condition that no replaceable target sequential logic device corresponding to the sequential logic device exists in the device library, sequential logic devices are filtered from the initial device set to form a second subset. The condition that no replaceable target sequential logic device corresponding to the sequential logic device exists in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is greater than or equal to the threshold voltage level of the sequential logic device. Determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

3. The method according to claim 2, characterized in that, Selecting a first subset from the initial device set based on the condition that the timing margin is less than a predetermined margin threshold further includes: Based on the timing margin of the sequential logic device on multiple timing paths in the target circuit and the conditions of the predetermined margin threshold corresponding to each timing path, a subset corresponding to each timing path is selected from the initial device set. The first subset is obtained by determining the union of the subsets corresponding to all time-series paths.

4. The method according to claim 2, characterized in that, The method further includes: If the set of optimized devices is empty, the leakage power consumption optimization of the target circuit ends.

5. The method according to claim 1, characterized in that, The method further includes: Determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the step of finding and replacing sequential logic devices in the target circuit whose threshold voltage is lower than the predetermined threshold voltage will be performed again. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

6. The method according to claim 5, characterized in that, After optimizing the leakage power consumption of the target circuit, the method further includes: Calculate the key performance indicators of the optimized target circuit; The parameters of the leakage current power consumption optimization strategy are adjusted based on the key indicators.

7. The method according to claim 6, characterized in that, The key indicators include the decrease in area / proportion of sequential logic devices with threshold voltages below a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

8. The method according to claim 6, characterized in that, Adjusting the leakage current power consumption optimization strategy parameters based on the aforementioned key indicators includes: If the key indicators do not meet the predetermined requirements, the parameters of the leakage power consumption optimization strategy will be adjusted.

9. A device for optimizing leakage current and power consumption of a chip, characterized in that, The device includes: The low threshold voltage device lookup unit is used to find sequential logic devices in the target circuit whose threshold voltage is lower than a predetermined threshold voltage, and form an initial device set. The feature analysis unit is used to determine a first feature and a second feature of the sequential logic device. The first feature includes the timing margin of the sequential logic device. The second feature includes a judgment result on whether there is a replaceable target sequential logic device in the device library. The function type of the target sequential logic device is the same as that of the sequential logic device and the threshold voltage of the target sequential logic device is higher than that of the sequential logic device. An optimizable device screening unit is used to screen optimizable sequential logic devices from the initial device set based on the first feature, the second feature, and leakage power consumption optimization strategy parameters. The replacement optimization unit is used to replace the optimizable sequential logic device in the target circuit with the target sequential logic device.

10. The apparatus according to claim 9, characterized in that, The leakage current power consumption optimization strategy parameters include a predetermined margin threshold and a threshold voltage level difference; The optimizable device screening unit includes a first subset screening module, a second subset screening module, and a union inversion module; The first subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that the timing margin is less than the predetermined margin threshold, to form a first subset; The second subset filtering module is used to filter sequential logic devices from the initial device set based on the condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library, forming a second subset. The condition that there is no replaceable target sequential logic device corresponding to the sequential logic device in the device library means: there is no sequential logic device in the device library with the same functional type as the sequential logic device, or there is no sequential logic device whose threshold voltage level is greater than or equal to the threshold voltage level of the sequential logic device. The union inversion module is used to determine the union of the first subset and the second subset, and invert the union to obtain an optimized device set including the optimizable sequential logic device.

11. The apparatus according to claim 10, characterized in that, Selecting a first subset from the initial device set based on the condition that the timing margin is less than a predetermined margin threshold further includes: Based on the timing margin of the sequential logic device on multiple timing paths in the target circuit and the conditions of the predetermined margin threshold corresponding to each timing path, a subset corresponding to each timing path is selected from the initial device set. The first subset is obtained by determining the union of the subsets corresponding to all time-series paths.

12. The apparatus according to claim 10, characterized in that, The optimizable device screening unit is further configured to: terminate the leakage power consumption optimization of the target circuit when the set of optimizable devices is empty.

13. The apparatus according to claim 9, characterized in that, The device further includes an optimization compliance judgment unit, used to determine whether the leakage power consumption of the target circuit after replacing the optimizable sequential logic unit meets the standard; If the target is not met, the low threshold voltage device search unit, feature analysis unit, optimizable device screening unit and replacement optimization unit are triggered to optimize the leakage power consumption of the target circuit after replacement. If the target is met, the leakage power consumption optimization of the target circuit is terminated.

14. The apparatus according to claim 13, characterized in that, The device further includes a leakage power optimization strategy parameter adjustment unit, which is used to calculate the key indicators of the optimized target circuit after the leakage power optimization of the target circuit is completed; and adjust the leakage power optimization strategy parameters according to the key indicators.

15. The apparatus according to claim 14, characterized in that, The key indicators include the decrease in area / proportion of sequential logic devices with threshold voltages below a predetermined threshold voltage, timing changes, changes in the total chip implementation area, and changes in the wiring allocation of the physical layout.

16. The apparatus according to claim 14, characterized in that, The leakage power consumption optimization strategy parameter adjustment unit adjusts the leakage power consumption optimization strategy parameters according to the key indicators, including: If the key indicators do not meet the predetermined requirements, the parameters of the leakage power consumption optimization strategy will be adjusted.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 8.

18. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 8.

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