In-memory computing method and device based on in-memory index and multi-layer perceptron

Abstract

The application provides in-memory index-based multilayer perceptron high-energy-efficiency in-memory calculation, and relates to the technical field of neural network hardware acceleration. The method comprises the following steps: extracting weight parameters of each layer in a multilayer perceptron model, generating a lookup table, and storing the lookup table in on-chip memory; according to the network layer type, dynamically loading a weight sub-table from the lookup table into a multiple address concurrent cache to form a local lookup table for single-cycle multi-address parallel access; according to the network layer type and a block strategy, batch reading of input feature vectors is performed and the input feature vectors are divided into multiple data blocks; using an activation function, feature values in each data block are transformed into index addresses, the local lookup table is accessed in parallel, and multiple weight data are obtained as lookup table results in a single cycle; through a hierarchical reduction circuit, the lookup table results are accumulated and fused to generate an activation output value; the activation output value is format-converted and written back to a feature data storage as input features of the next layer network or a model inference result. In this way, the requirements of low power consumption and high throughput are effectively balanced.

Description

Technical Field

[0001] This invention relates to the field of neural network hardware acceleration technology, and in particular to a high-energy-efficiency in-memory computing method and apparatus for multilayer perceptrons based on in-memory indexing. Background Technology

[0002] With the widespread application of artificial intelligence technology, the model size and complexity of deep neural networks have grown exponentially. Modern neural networks typically contain hundreds of millions of parameters and massive multiply-accumulate operations. In the traditional von Neumann architecture, the computation unit and storage unit are separated, and frequent data transfer leads to huge latency and power consumption, namely the "memory wall" and "power wall" bottlenecks. Among many network operators, the Multilayer Perceptron (MLP), especially the Feed-Forward Network (FFN) in the Transformer architecture, accounts for about 2 / 3 of the total number of parameters and the vast majority of the computation. For example, in large models such as the Generative Pre-trained Transformer-3 (GPT-3), the floating-point operation cost of the MLP layer is much higher than that of the attention mechanism; even at typical sequence lengths, the computational load of the MLP layer still accounts for more than 90%. Therefore, the acceleration efficiency of the MLP layer directly determines the feasibility of deploying the entire model at the edge.

[0003] Existing model acceleration techniques largely focus on optimizing Multi-Head Attention (MHA) operations, such as sparse attention and low-rank approximation, while paying insufficient attention to optimizing the computational complexity of MLP layers. Taking a hardware acceleration scheme for MLP based on a multiply-accumulate array as an example, this type of scheme uses parallel multiply-accumulate units to perform matrix multiplication operations. It completes the computation of the fully connected layer by reading weights from Block Random Access Memory (BRAM) and multiplying and accumulating them with the input features. However, this traditional approach has inherent contradictions: on the one hand, to achieve high throughput, it is necessary to increase computational parallelism and frequently access the weight memory, but the single-port characteristic of BRAM limits the number of weights that can be obtained in a single cycle, making memory access bandwidth a bottleneck restricting throughput improvement; on the other hand, to reduce power consumption, it is necessary to reduce data movement and computational overhead, but the multiplier itself has high power consumption, and the repeated movement of weight data between on-chip cache and computation units generates a large amount of dynamic power consumption, resulting in a significant increase in data movement energy consumption under the traditional von Neumann architecture. The aforementioned contradiction makes it difficult for existing solutions to simultaneously achieve low power consumption and high throughput. If high throughput is pursued, memory access bandwidth is limited and power consumption increases; if power consumption is limited, computational parallelism and throughput decrease significantly. Summary of the Invention

[0004] The purpose of this invention is to provide a high-energy-efficiency in-memory computing method and apparatus for multilayer perceptrons based on in-memory indexing, solving the problem that existing technologies cannot simultaneously meet the requirements of low power consumption and high throughput.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of this invention provides a high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing, the method comprising: Extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in on-chip memory. Based on the type of network layer to be processed, the corresponding weight sub-table is dynamically loaded from the lookup table in on-chip memory into the multi-access concurrent cache to form a local lookup table that supports single-cycle multi-address parallel access. Based on the network layer type to be processed and the preset block division strategy, the input feature vectors are read in batches from the feature data storage and divided into multiple data blocks; By using an activation function, the feature values ​​in each data block are transformed into index addresses, and the local lookup table is accessed in parallel according to the index addresses to obtain multiple weight data in a single period. The multiple weight data are used as the lookup results of the corresponding data blocks. After completing the lookup operation for all data blocks, the lookup results for each data block are accumulated and fused through a hierarchical reduction circuit to generate the activation output value of the current neuron. Based on the data exchange bus width, the activation output value is formatted and written back to the feature data memory. The written-back activation output value is then used as the input feature of the next layer network or as the output of the model inference result.

[0006] A second aspect of the present invention provides a high-energy-efficiency in-memory computing device for a multilayer perceptron based on in-memory indexing, the device comprising: The extraction and generation unit is used to extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in on-chip memory. The loading and forming unit is used to dynamically load the corresponding weight sub-table from the lookup table in the on-chip memory into the multi-access concurrent cache according to the type of network layer to be processed, so as to form a local lookup table that supports single-cycle multi-address parallel access. The partitioning unit is used to read the input feature vectors in batches from the feature data storage and divide them into multiple data blocks according to the network layer type to be processed and the preset partitioning strategy; The parallel access unit is used to transform the feature values ​​in each data block into index addresses using an activation function, and access the local lookup table in parallel according to the index addresses to obtain multiple weight data in a single period, and use the multiple weight data as the lookup results of the corresponding data block. The accumulator fusion unit is used to accumulate and fuse the lookup results of each data block after completing the lookup operation of all data blocks, and generate the activation output value of the current neuron through the hierarchical reduction circuit. The conversion and write-back unit is used to convert the format of the activation output value according to the data exchange bus width and write it back to the feature data memory. The written-back activation output value is used as the input feature of the next layer network or the output of the model inference result.

[0007] Compared to existing technologies, the present invention provides a high-energy-efficiency in-memory computation method and apparatus for multilayer perceptrons based on in-memory indexing. This method extracts the weight parameters of each layer in the multilayer perceptron model and generates a lookup table based on these parameters, storing the lookup table in on-chip memory. According to the type of network layer to be processed, the corresponding weight sub-table is dynamically loaded from the lookup table in on-chip memory into a multi-address concurrent cache, forming a local lookup table that supports single-cycle multi-address parallel access. Based on the type of network layer to be processed and a preset block partitioning strategy, the input feature vectors are read in batches from the feature data memory and divided into multiple data blocks. Using a trigger... The live function transforms the feature values ​​in each data block into index addresses and accesses the local lookup table in parallel based on these index addresses to obtain multiple weight data within a single cycle. These multiple weight data are then used as the lookup results for the corresponding data block. After completing the lookup operations for all data blocks, the lookup results for each data block are accumulated and fused through a hierarchical reduction circuit to generate the activation output value of the current neuron. Based on the data exchange bus width, the activation output value is formatted and written back to the feature data memory. The written-back activation output value is then used as the input feature of the next layer network or as the output of the model inference result. In this way, by replacing the traditional multiply-accumulate operation with a lookup operation, the dynamic power consumption of the multiplier is significantly reduced. At the same time, the use of multi-access concurrent caching enables parallel acquisition of multiple weights in a single cycle, and the pipelined accumulation mechanism in the hierarchical reduction circuit eliminates memory access pauses, thereby achieving high throughput with extremely low power consumption, effectively balancing the requirements of low power consumption and high throughput. Attached Figure Description

[0008] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1A schematic diagram of a high-energy-efficiency in-memory computing system based on in-memory indexing of a multilayer perceptron is shown. Figure 2 A flowchart illustrating a high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing is shown. Figure 3 A schematic diagram illustrating the processing of a high-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing is shown. Figure 4 A schematic diagram of a high-efficiency in-memory computing device based on in-memory indexing of a multilayer perceptron is shown. Detailed Implementation

[0009] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0010] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0011] The methods described in the embodiments of the present invention will be explained in detail below.

[0012] The present invention provides a high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing, which is applied to a high-energy-efficiency in-memory computing system for multilayer perceptrons based on in-memory indexing. Figure 1 A schematic diagram of a high-energy-efficiency in-memory computing system based on in-memory indexing of a multilayer perceptron is shown. See [link / reference]. Figure 1 As shown, the high-energy-efficiency in-memory computing system of multilayer perceptron based on in-memory indexing includes: feature data memory, lookup table memory, multi-address concurrent lookup table cache, data acquisition module, dynamic lookup table accumulation module, and data write-back module.

[0013] The feature data memory, as the core data cache unit of this invention, is hardware-implemented based on the BRAM resources within a Field Programmable Gate Array (FPGA). At the physical implementation level, each BRAM is configured with a 64-bit width, allowing a single memory access operation to acquire 16 4-bit quantized feature values ​​in parallel (64 bits / 4 bits = 16). This data packing strategy fully utilizes the storage bandwidth of the BRAM. The feature data memory employs a pipelined read / write mechanism. At computation startup, the system reads feature vectors from the BRAM according to a pipelined processing strategy, gradually acquiring data blocks at different addresses for subsequent processing through a preset address mapping logic. Simultaneously, the feature data memory adopts a bidirectional data path design, responsible for both caching the original input features and temporarily storing the computation results. The activated output value, after format conversion, is written back to the designated address space of the BRAM, serving as input features for the next layer of the network or directly as the inference result output, forming a complete data loop.

[0014] The lookup table memory stores lookup tables generated based on weight parameters. The table values ​​are generated from the neural network weight parameters obtained during algorithm training, after quantization, compression, and discretization. The lookup table memory uses BRAM as its primary storage medium, leveraging BRAM's dual-port feature to support parallel operations for weight reading and result writing. Combined with pipelined scheduling, it achieves deep overlap between computation and memory access. When a task queue is detected as ready, the system dynamically loads the corresponding layer's weight sub-table into a dedicated cache area. When the current stage's computation is complete and the next stage is about to start, the system dynamically loads the corresponding layer's weights into the lookup table memory again, improving resource utilization by overwriting previous layer data.

[0015] As a key component for improving hardware acceleration efficiency, the multi-address concurrent lookup table cache's core function is to overcome the limitation of traditional lookup table memories, which can only perform read and write operations on a single address per cycle. This multi-address concurrent lookup table cache is implemented based on flip-flops (FFs) within the FPGA, leveraging the independent addressing capability of flip-flops to construct a memory architecture that supports multiple concurrent accesses per cycle. Specifically, when performing a lookup operation, the multi-address concurrent lookup table cache, through a parallel address decoding mechanism, simultaneously responds to multiple lookup table value access requests within the same clock cycle, achieving batch retrieval of weighted data. This not only solves the memory access bottleneck problem caused by the single-port characteristic of traditional BRAM-based lookup table memories but also significantly improves the throughput of lookup operations through the low latency of flip-flops.

[0016] The data acquisition module, as the core control unit of the feature data access system of this invention, dynamically generates the physical access address sequence of the feature data storage device according to the current computing task requirements, and synchronously generates an enable signal matching the memory access timing. This data acquisition module converts the computational features between neural network layers into specific storage addresses through preset address mapping rules, and generates corresponding enable signals according to the pipeline scheduling timing to ensure that concurrent access requests to the feature data storage device are completed within a single clock cycle. When the enable signal is valid, the feature data storage device transmits the feature data (such as a 4-bit quantized data packet) corresponding to the target address through a parallel data bus.

[0017] The dynamic lookup table accumulation module is the core computing unit for achieving high-efficiency MLP hardware acceleration in this invention, playing a crucial role throughout the entire process from feature processing to final activation output generation. This module significantly improves the computational efficiency of the neural network by dynamically generating lookup indexes, executing multiple lookup operations in parallel, and efficiently fusing intermediate results. Specifically, after feature extraction and block processing of the input feature data block, the dynamic lookup table accumulation module dynamically generates index addresses pointing to the lookup table based on the current data features. The index values ​​are then transformed by activation functions (such as ReLU or Sigmoid) to accurately match the discretized weight parameter distribution. During the lookup stage, the system utilizes the multi-access concurrency characteristics of the lookup table cache and employs a parallel address decoding mechanism implemented with FF to simultaneously acquire multiple weight data and load them into temporary registers within a single clock cycle. This overcomes the limitations of traditional BRAM single-port access, improving weight acquisition efficiency by 3-5 times. For batch-processed feature data blocks, the dynamic lookup table accumulation module uses a hierarchical reduction circuit to accumulate and fuse the lookup results of each data block. Hardware pipeline technology achieves deep overlap between computation and memory access, ultimately generating the activation output value of the neuron.

[0018] The data write-back module, as a key control unit in the data path of this invention, has the core function of dynamically generating the physical write address sequence of the feature data store based on the current activation output value of the neuron, and simultaneously generating an enable signal matching the memory access timing. This data write-back module converts the inter-layer computation results of the neural network into specific storage addresses through preset address mapping rules, and generates corresponding enable signals according to the pipeline scheduling timing, ensuring that the write operation to the feature data store is completed within a single clock cycle. When the activation output value is generated, data is written to the specified address through a parallel data bus. Through the coordinated mechanism of address generation and enable control, accurate write-back of the computation results is achieved.

[0019] Figure 2 A flowchart illustrating a high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing, as shown in an embodiment of the present invention, is provided. Figure 2As shown, this energy-efficient in-memory computation method for multilayer perceptrons based on in-memory indexing may include: S201. Extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in the on-chip memory.

[0020] In the hardware acceleration implementation of a multilayer perceptron model, the first step is to extract the weight parameters of each layer of the neural network using tools such as Python. For example, the weight parameters can be the connection weights from the input layer to the hidden layer, or the connection weights from the hidden layer to the output layer.

[0021] Specifically, the weight parameters of each layer in the multilayer perceptron model are extracted, and a lookup table is generated based on the weight parameters. The lookup table is then stored in on-chip memory, including: Step A1: Extract the weight parameters of each layer in the multilayer perceptron model.

[0022] The extracted weight parameters must meet the requirements of subsequent quantization compression and discretization processing. For example, the format of the weight parameters needs to be adjusted to target low-bit quantization (e.g., 4-bit) to avoid the inability to perform low-bit quantization due to excessively large numerical ranges. The feature data memory is configured in a 64-bit width mode to acquire 16 4-bit quantized values ​​in parallel. Therefore, the weight parameters need to be divided into blocks to adapt to the hardware's parallel computing requirements.

[0023] Step A2: Divide the weight parameters into multiple weight sub-matrices along the input channel direction.

[0024] To adapt to the in-memory computing architecture of this invention, the dimensions of the weight matrix corresponding to the weight parameters are first reconstructed.

[0025] The weight matrix corresponding to the weight parameters Divided along the input channel direction into Each sub-block corresponds to a weight submatrix, and each weight submatrix corresponds to a portion of the weight parameters. The width of each sub-block is defined as... For the first The weight submatrix of each sub-block corresponds to a subspace. The decomposition formula is as follows: ; in, This is the weight matrix corresponding to the weight parameters. For the first The weight submatrix corresponding to each sub-block The number of input channels. The number of output channels. Number of output channels Number of input channels The set of real matrices, The width of each sub-block, This represents the number of sub-blocks divided along the input channel direction.

[0026] Step A3: Perform low-bit quantization on the weight parameters in each weight submatrix to obtain the quantized weights.

[0027] Low-bit quantization employs either a symmetric or asymmetric quantization strategy, with a quantization bit width of 4 bits.

[0028] The weight parameters within each weighted submatrix are original floating-point weight parameters. Through low-bit quantization, these original floating-point weight parameters are converted into low-bit integers, reducing storage bandwidth requirements. For example, the original floating-point weight parameters can be 32-bit floating-point numbers (FP32), and the low-bit integers can be 4-bit integers (INT4) or 8-bit integers (INT8).

[0029] For the weight submatrix A shared scaling factor is introduced for normalization, mapping the floating-point weights to the fixed-point domain. A quantization function is defined. : ; in, For the first The quantized weights corresponding to each sub-block For quantization bit width, quantization bit width You can choose 4 or 8. For the first The shared scaling factor corresponding to each sub-block This is a rounding operation. Step A3 provides a unified data foundation for subsequent discretization indexing.

[0030] Step A4: Cluster discretize the quantized weights to divide the quantized weights in each weight submatrix into multiple clusters, assign a corresponding cluster index to each quantized weight, and use the cluster center of each cluster as the weight cluster value.

[0031] Step A5: Generate a lookup table based on the weight cluster values ​​and store the lookup table in on-chip memory.

[0032] The lookup table is used to retrieve the corresponding weighted cluster value based on the cluster index.

[0033] Specifically, after low-bit quantization and cluster discretization of the weight parameters in each weight submatrix, the weight parameters in each weight submatrix are transformed into a finite set, which is suitable for the lookup table format of the hardware accelerator and stored in the cache or on-chip memory to reduce memory access latency during subsequent calculations.

[0034] The generated lookup table is an in-memory lookup table (LUT). This invention performs clustering discretization within the quantized subspace. Let the first... The codebook for the subspace corresponding to each sub-block is Each of them This represents a cluster center vector. For the , The weight submatrix corresponding to each sub-block any weight vector in (corresponding to the first) (n output neurons), by minimizing the reconstruction error objective function with sparse constraints. To determine its optimal cluster index : ; ; in, This is the quantized weight vector. These are the weighted cluster values. To measure the quantized weight vector With weight cluster values The objective function for the reconstruction error of the degree of matching between them. For the first The shared scaling factor corresponding to each sub-block weighted cluster values The L1 norm, For cluster index, For the first The weight submatrix corresponding to each sub-block The Middle The quantized weight vector corresponding to each output neuron. The quantized weight vector The corresponding optimal cluster index, For the first The codebook of the subspace corresponding to each sub-block contains Cluster center, The number of clusters within each subspace. To quantize bit width, For the first In the codebook of the subspace corresponding to the sub-block, the first... The weight cluster value corresponding to each cluster To measure the quantized weight vector With the In the codebook of the subspace corresponding to the sub-block, the first... The weight cluster value corresponding to each cluster The objective function for the reconstruction error of the degree of matching between them. The regularization coefficient is used to constrain the sparsity of the codebook centers to reduce hardware storage overhead. After steps A4 and A5, the original large weight matrix... It is transformed into two lightweight data structures: an index table. Sum Value Table .

[0035] The weight cluster values ​​from the lookup table are directly written to read-only memory (ROM) or a concurrent cache implemented with triggers. Leveraging the dual-port BRAM feature of the FPGA, dynamic loading of the weight sub-tables within the lookup table is achieved, supporting layer-by-layer weight configuration switching. Based on the memory access granularity of the hardware computing unit (e.g., 64-bit width), LUT entries are packaged into blocks; for example, a single memory access operation can acquire 16 4-bit quantized values ​​in parallel, significantly improving memory bandwidth utilization.

[0036] S202. Based on the type of network layer to be processed, dynamically load the corresponding weight sub-table from the lookup table in the on-chip memory into the multi-address concurrent cache to form a local lookup table that supports single-cycle multi-address parallel access.

[0037] Among them, the number of parallel accesses supported by the multi-address concurrent cache in a single cycle is at least 16.

[0038] Specifically, based on the type of network layer to be processed, the corresponding weight sub-table is dynamically loaded from the on-chip memory lookup table into the multi-access concurrent cache, forming a local lookup table that supports single-cycle multi-address parallel access, including: Step B1: Determine the storage address of the weight sub-table to be loaded in the lookup table based on the type of network layer to be processed.

[0039] Step B2: Using DMA technology, read the weight sub-table corresponding to the storage address from the dual-port block random access memory and load the weight sub-table into the multi-access concurrent cache.

[0040] The multi-address concurrent cache is built based on triggers.

[0041] Step B3: Based on the loaded weighted sub-table, configure the multi-address concurrent cache through the parallel address decoding mechanism to form a local lookup table that supports multi-address parallel access in a single cycle.

[0042] Specifically, when a task queue is detected to contain data to be processed, the computing module is triggered to start. At the same time, based on the task type, the corresponding weighted sub-table is loaded from the global lookup table memory into a dedicated lookup table cache area, namely the multi-address concurrent cache.

[0043] During implementation, the task queue status is monitored and task metadata, such as the MLP network layer type, is parsed to generate the storage address of the weight sub-table in the lookup table. Using Direct Memory Access (DMA) or pipelining techniques, the weight sub-table is dynamically loaded from the dual-port BRAM, overwriting old data to reuse storage space. A mechanism based on trigger-configured multi-address concurrent caching is used to support single-cycle multi-weight concurrent table lookups through parallel address decoding. After the weight sub-table loading is complete, a synchronization signal, such as an interrupt signal or a pulse signal, is sent to start the dynamic lookup accumulation module, lock hardware resources, and insert pipeline synchronization logic to avoid computation and memory access conflicts.

[0044] S203. Based on the network layer type to be processed and the preset block division strategy, read the input feature vectors in batches from the feature data storage and divide them into multiple data blocks.

[0045] Specifically, based on the type of network layer to be processed and the preset block partitioning strategy, the input feature vectors are read in batches from the feature data storage and divided into multiple data blocks, including: Step C1: Determine the block granularity corresponding to the current network layer based on the type of network layer to be processed.

[0046] Step C2: Generate the address sequence and the corresponding enable signal according to the block granularity.

[0047] Step C3: Read the input feature vectors in batches from the feature data memory according to the address sequence and the enable signal.

[0048] Step C4: Divide the read input feature vector into multiple data blocks according to the block granularity. Each data block contains the number of feature values ​​corresponding to the block granularity.

[0049] Specifically, regarding the preset block partitioning strategy, the block granularity is dynamically adjusted based on the throughput of the computing unit. Each block contains 8 feature values ​​during input layer computation and 16 feature values ​​during hidden layer computation to match the amount of data accessed by BRAM in a single memory access. At the same time, the preset block partitioning strategy is optimized based on the feature value distribution characteristics (such as sparsity), allocating independent cache regions to high-activity feature clusters to reduce the idle cycle of computing units.

[0050] The data acquisition module generates a physical access address sequence according to preset rules, transforms the inter-layer computation features of the neural network into the physical address mapping logic of BRAM, and synchronously generates an enable signal that matches the memory access timing to ensure that concurrent access requests are completed within a single clock cycle.

[0051] Utilizing the 64-bit width mode of BRAM configuration, 16 4-bit quantized feature values ​​are acquired in parallel during a single memory access operation. Combined with a pipelined read / write mechanism, efficient data transfer is achieved. When the enable signal is active, the feature data memory transmits the feature data corresponding to the target address via a parallel data bus.

[0052] A dedicated multi-address concurrent cache area is allocated for each data block, and a parallel address decoding mechanism implemented using triggers supports concurrent access to multiple data blocks in a single cycle.

[0053] S204. Using an activation function, the feature values ​​in each data block are transformed into index addresses, and the local lookup table is accessed in parallel according to the index addresses to obtain multiple weight data in a single period, and the multiple weight data are used as the lookup results of the corresponding data blocks.

[0054] The activation function can be ReLU, Sigmoid, or Sign.

[0055] Specifically, an activation function is used to transform the feature values ​​in each data block into index addresses. Local lookup tables are then accessed in parallel based on these index addresses to retrieve multiple weight data points within a single period. These multiple weight data points are then used as the lookup results for the corresponding data blocks, including: Step D1: Use the activation function to perform a nonlinear transformation on the feature values ​​in each data block to obtain the transformed feature values.

[0056] Choose a lightweight activation function based on the model requirements, such as the ReLU activation function or the Sign activation function. The ReLU activation function retains only positive values, while the Sign activation function achieves binarization and reduces computational complexity. If high precision is required, the piecewise linear approximation Sigmoid activation function can be used.

[0057] The transformed feature values ​​are quantized using 4 bits to match the subsequent lookup table index range (e.g., 0~15), avoiding floating-point operation overhead. The activation function is implemented on the FPGA using combinational logic circuits, executing in parallel with the lookup operation to reduce pipeline stalls.

[0058] Step D2: Perform low-bit quantization on the transformed feature values ​​to obtain quantized feature values, and map the quantized feature values ​​to index addresses.

[0059] In implementation, the discretization mapping discretizes the activation values ​​into a finite set of integers according to a preset interval. For example, the range [0,15] output of the ReLU activation function is directly mapped to a 4-bit index (0~15), ensuring alignment with the cluster center of the weight LUT. A parallel address decoding mechanism implemented through triggers maps multiple indices to different channels of the multi-access cache simultaneously, supporting concurrent access of multiple weights in a single cycle. The mapping rules are dynamically adjusted according to the task type (such as different MLP layers). For example, a linear mapping is used for the input layer, while a non-uniform distribution mapping is used for the output layer to adapt to the weight distribution characteristics.

[0060] In implementation, a dynamic shift-XOR address generation model maps the quantized feature values ​​to index addresses. Specifically, during the inference phase, the input feature vector... Divided into Subvectors Through in-memory index operators Obtain the calculation results. To quickly locate data in hardware memory, the first step is to generate... The first output neuron of the first output neuron The index address corresponding to each subvector Combining hardware code logic (base address and offset), the index address generation follows the dynamic shift XOR derivation model: First, define the input feature vector. hash mapping Used to determine the base address of the lookup table, which is then combined with the previously quantized weight vector. Corresponding optimal cluster index Calculate the index address: ; in, For the first The first moment The first output neuron of the first output neuron The index addresses corresponding to each subvector For the first The base address of the lookup table corresponding to each subvector. For the first Subvectors, For the first Subvectors The corresponding hash mapping, The quantized weight vector The corresponding optimal cluster index, For the first Subvectors, The number of sub-vectors into which the input feature vector is segmented. The number of bits to shift left. Indicates left shift Bitwise operations are used to align row addresses of memory storage entities; This represents address concatenation or XOR operation, achieving fast hardware coupling between the weight index and the input feature vector. Based on this index address... The in-memory computing unit directly outputs the pre-calculated product terms, eliminating the need for real-time multiplication. ; in, For the first one read from the lookup table The first output neuron of the first output neuron The output values ​​corresponding to each subvector. To look up the table, For the first The weight submatrix corresponding to each subvector The Middle The quantized weight vector corresponding to each output neuron.

[0061] Step D3: Assign the index address to multiple parallel channels.

[0062] Each parallel channel corresponds to an independent address space in the multi-address concurrent cache.

[0063] Step D3 includes: Step D31: Based on the number of parallel channels supported by the multi-address concurrent cache, determine the number of parallel channels to be 16.

[0064] Step D32: Based on the number of parallel channels being 16, allocate the index address to the 16 parallel channels, with each parallel channel corresponding to an independent address space in the multi-access concurrent cache.

[0065] Step D4: Within a single clock cycle, access the weight data corresponding to the index address in the local lookup table in parallel through multiple parallel channels to obtain the corresponding weight data.

[0066] The system uses 16 parallel channels to access 16 weight data points corresponding to the index addresses in the local lookup table, enabling concurrent acquisition of 16 weight data points within a single cycle.

[0067] When the index sequence is input into the cached lookup table, the lookup operation is performed in parallel, and the result value corresponding to each index is loaded into the temporary register of the computation unit.

[0068] Step D5: Use multiple weighted data as the lookup results for the corresponding data blocks.

[0069] S205. After completing the lookup operation for all data blocks, the lookup results for each data block are accumulated and fused through a hierarchical reduction circuit to generate the activation output value of the current neuron.

[0070] Hierarchical reduction circuits, also known as additive tree circuits, employ pipelined technology and significantly reduce the delay in neuron activation output generation by overlapping computation and memory access depths.

[0071] Specifically, after completing the lookup operations for all data blocks, the lookup results for each data block are accumulated and fused using a hierarchical reduction circuit to generate the activation output value of the current neuron, including: Step E1: After completing the lookup operation for all data blocks, input the lookup results corresponding to each data block into the hierarchical reduction circuit in sequence.

[0072] Step E2: The lookup results are accumulated level by level using a hierarchical reduction circuit and pipeline technology.

[0073] Each accumulation operation involves adding the intermediate result obtained from the previous accumulation to the lookup result of the current level to obtain the current level's intermediate accumulation result.

[0074] Step E3: After completing the last level of accumulation, obtain the intermediate result of the last level of accumulation, and use the intermediate result of the last level of accumulation as the activation output value of the current neuron.

[0075] During implementation, after obtaining the in-memory read result, accumulation and activation of the fully connected layer are required. To accurately describe the behavior in the hardware pipeline, the first... The output calculation of each output neuron is modeled as a recursive accumulation process.

[0076] Definition of the first The partial sum of the time and the register state are ,in The sequence of steps for processing a sub-block is as follows: ; ; in, For the first The output neuron in the first... The partial time step and register state, i.e., the accumulated intermediate results. For the first The output neuron in the first... Partial time and register state, For the first The output neuron, the first The lookup results for each sub-block For the first Initial bias of each output neuron For the first Bias of each output neuron This is the hardware shift truncation factor. This is a numerical representation of the hardware shift truncation factor, used to dynamically adjust the decimal point position of the fixed-point number during accumulation to prevent overflow.

[0077] When all After processing each sub-block, the final accumulated value is obtained. , For the first All output neurons The final accumulated value of each sub-block. At this point, global dequantization and an activation function are introduced to generate the first... The final output of each output neuron This refers to the accumulated intermediate result of the last stage. Considering the non-linear characteristics of the hardware implementation, the final output formula is derived as follows: ; in, For the first The final output of each output neuron, For quantitative operations, For activation function, For the first The shared scaling factor corresponding to each sub-block For the first The first output neuron of the first output neuron Each sub-block, after completing all The cumulative intermediate results of the last level after all time points corresponding to each sub-block. This is the inter-layer scaling factor. If the ReLU activation function is used, then the above-mentioned... The formula for the final output of each output neuron can be further transformed into hardware threshold comparison logic: ; in, For rounding operation, For the first Each output neuron completes all The cumulative intermediate result of the last level after all the time intervals corresponding to each sub-block.

[0078] Figure 3 A schematic diagram illustrating the processing of a high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing is shown below. Figure 3As shown, the data input consists of multiple 4-bit input feature vector blocks, namely, 4-bit first input feature vector (4-bit datain1), 4-bit second input feature vector (4-bit datain2), 4-bit third input feature vector (4-bit datain3), and 4-bit fourth input feature vector (4-bit datain4). First, the data blocks are divided. The divided data blocks are then transformed by an activation function to generate index addresses pointing to lookup tables. These index addresses access multiple lookup tables in parallel. The lookup tables include a first lookup table (LUT1), a second lookup table (LUT2), a third lookup table (LUT3), and a fourth lookup table (LUT4). Each lookup table outputs corresponding 16-bit weight data within a single cycle. The weight data output by each lookup table includes the 16-bit first weight data (16-bit dataout1) output by LUT1, the 16-bit second weight data (16-bit dataout2) output by LUT2, the 16-bit third weight data (16-bit dataout3) output by LUT3, and the 16-bit fourth weight data (16-bit dataout4) output by LUT4. (dataout4); The weight data output from each lookup table is used as the lookup result for the corresponding data block and input into the addition tree for accumulation and fusion, ultimately generating the activation output value (dataout) of the neuron. The entire process achieves deep overlap between computation and memory access through hardware pipeline technology.

[0079] S206. Based on the data exchange bus width, convert the format of the activation output value and write it back to the feature data memory. Use the written-back activation output value as the input feature of the next layer network or the output of the model inference result.

[0080] Specifically, based on the data exchange bus width, the activated output value is formatted and written back to the feature data memory, including: Step F1: Based on the bit width of the data exchange bus, concatenate or split the active output value to obtain the target output value.

[0081] The target output value is the output value that matches the width of the data exchange bus.

[0082] Step F2: Write the target output value back to the feature data memory.

[0083] The activation output value, after format conversion, is written back to the feature data memory. It can be used as input features for the next layer of the network or directly output as the model inference result. The entire process achieves deep overlap between computation and memory access through hardware pipeline technology, significantly improving the inference efficiency of the MLP model.

[0084] This invention relates to a high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing. This method is applied to FPGA smart cameras in industrial production lines. By running a visual Transformer model, it enables real-time detection of product surface defects with high frame rate and low power consumption.

[0085] The effectiveness of this invention can be further illustrated by the following experimental data.

[0086] Table 1. Energy Efficiency Comparison between the Invention and Existing Technologies

[0087] Table 1 is a comparison table of energy efficiency between the present invention and the prior art. Existing method 1 in Table 1 is from the paper "Xu Kunran. Design and research of high energy efficiency deep neural network acceleration chip [D]. Xi'an University of Electronic Science and Technology, 2022. DOI:10.27389 / d.cnki.gxadu.2022.000115.", and existing method 2 is from "Taka E, Gourounas D, Gerstlauer A, et al. Efficient approaches for gemm acceleration on leading ai-optimizedfpgas [C] / / 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2024: 54-65.".

[0088] As shown in Table 1, this experiment selected a representative 3-layer MLP as the benchmark, with a network configuration of 128 neurons (128×128×128) each in the input, hidden, and output layers. This configuration is widely used in the FFN sublayer of classic Transformer models. For example, the classic Transformer model can be a BERT-Tiny variant or a model with a single attention head processing unit in the standard Transformer, and it has high practical application reference value.

[0089] Under the same baseline network and parallelism (16×16 computing array), the MLP acceleration scheme based on lookup tables in this invention achieves a peak computing power of 102.4 GOPS on a Zynq Ultrascale+ ZCU102 FPGA. Compared to the traditional implementation based on the Artix7 XC7A100T multiplication array, and the 51.2 GOPS of the existing method 1, the computing power of this invention is improved by 2 times. This performance leap is mainly due to two aspects: first, this invention uses a higher operating frequency of 200MHz, while the existing method 1 uses 100MHz; second, it adopts an innovative multi-address concurrent lookup table cache design, and the parallel address decoding mechanism implemented by triggers effectively solves the weight access bottleneck of dense matrix operations in Transformer-type models, significantly improving the weight acquisition efficiency by 3-5 times.

[0090] In terms of energy efficiency and power consumption, this invention demonstrates a groundbreaking advantage. The power consumption of this invention is only 0.018W, a reduction of approximately 10.9 times compared to the 0.196W of the existing method 1. More notably, compared to the existing method 2, which employs a large-scale complete network computing architecture and achieves a peak computing power of 76720 GOPS through massive hardware stacking, its power consumption is as high as 82.7W, resulting in an energy efficiency ratio of only 932 GOPS / W. In contrast, this invention compresses data using 4-bit quantization technology to reduce bandwidth and dynamic power consumption, and utilizes a bidirectional data path based on BRAM and a trigger-based multiple access cache to avoid the energy consumption of frequent data movement. This enables this invention to ultimately achieve an astonishing energy efficiency ratio of 5688.9 GOPS / W, which is 21.8 times the energy efficiency ratio of the existing method 1 (261.2 GOPS / W) and 6.1 times the energy efficiency ratio of the existing method 2 (932 GOPS / W).

[0091] This significant energy efficiency optimization verifies that the invention does not simply rely on stacking hardware scale, but rather eliminates pipeline stalls through deep overlap of computation and memory access operations, truly achieving efficient computation with minimal complexity. Furthermore, combined with a dynamic weighted sub-table loading strategy and non-uniform discretization mapping technology, the invention successfully balances model accuracy and hardware overhead with an extremely low power budget, fully demonstrating its core competitiveness of combining high throughput and ultra-low power consumption in power-sensitive edge computing scenarios.

[0092] This invention proposes an implementation scheme for a high-energy-efficiency in-memory computation method for multilayer perceptrons (MLPs) based on in-memory indexing. It improves the inference efficiency of the MLP model by quantizing, compressing, and discretizing the neural network weight parameters and converting them into a lookup table format, combined with a hardware acceleration architecture. Specifically, the weight parameters of each layer of the MLP model are extracted using tools such as Python, then quantized, compressed, and discretized before being stored in a cache or on-chip memory, reducing memory access latency. At the FPGA implementation level, the feature data memory is based on BRAM resources, employing 4-bit quantization storage optimization technology and configured as a 64-bit wide mode. It acquires 16 quantized feature values ​​in parallel through a single memory access, and combines a pipelined read / write mechanism and a bidirectional data path design to achieve efficient caching and write-back of input features and computation results. The lookup table memory utilizes the dual-port characteristics of BRAM to support parallel operations of weight reading and result writing, and achieves resource reuse through a dynamic loading strategy of weight sub-tables. The key lies in the design of the multi-address concurrent lookup table cache, which is based on triggers to build a storage architecture that supports multiple concurrent accesses in a single cycle. It overcomes the memory access bottleneck of traditional single-port memory through a parallel address decoding mechanism, improving weight acquisition efficiency by 3-5 times. The data acquisition module dynamically generates storage address sequences and control timing signals according to task requirements, ensuring concurrent access to feature data. The dynamic lookup table accumulation module generates index addresses through activation functions, combining the parallel lookup capabilities of the multi-address cache to complete the loading of multi-weight data within a single cycle, and uses a hierarchical reduction circuit to fuse intermediate results to generate neuron activation values. The data write-back module achieves accurate write-back of calculation results through address mapping rules and enable signals, forming a complete data closed loop. The overall solution significantly improves the hardware acceleration efficiency of the MLP model by deeply overlapping computation and memory access operations using hardware pipeline technology.

[0093] Based on the above Figure 1As can be seen from the implementation method, the embodiments of the present invention extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in on-chip memory; according to the type of network layer to be processed, the corresponding weight sub-table is dynamically loaded from the lookup table in on-chip memory into the multi-address concurrent cache to form a local lookup table that supports multi-address parallel access in a single cycle; according to the type of network layer to be processed and the preset block strategy, the input feature vector is read in batches from the feature data memory and divided into multiple data blocks; using the activation function, the feature values ​​in each data block are transformed into index addresses, and the local lookup table is accessed in parallel according to the index addresses to obtain multiple weight data in a single cycle, and the multiple weight data are used as the lookup results of the corresponding data blocks; after completing the lookup operation of all data blocks, the lookup results corresponding to each data block are accumulated and fused through the hierarchical reduction circuit to generate the activation output value of the current neuron; according to the data exchange bus width, the activation output value is format converted and written back to the feature data memory, and the written-back activation output value is used as the input feature of the next layer network or the model inference result output. In this way, by replacing traditional multiplication and addition operations with table lookup operations, the dynamic power consumption of the multiplier is greatly reduced; at the same time, multi-address concurrent cache is used to achieve parallel acquisition of multiple weights in a single cycle, and the pipeline accumulation mechanism in the hierarchical reduction circuit is combined to eliminate memory access pauses, thereby achieving high throughput with extremely low power consumption, effectively balancing the requirements of low power consumption and high throughput.

[0094] Based on the same inventive concept, as an implementation of the above-mentioned high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing, this embodiment of the invention also provides a high-energy-efficiency in-memory computing device for multilayer perceptrons based on in-memory indexing. Figure 4 This is a structural diagram of a high-energy-efficiency in-memory computing device based on in-memory indexing of a multilayer perceptron in an embodiment of the present invention. See also... Figure 4 As shown, the device may include: The extraction and generation unit 401 is used to extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in the on-chip memory. The loading and forming unit 402 is used to dynamically load the corresponding weight sub-table from the lookup table in the on-chip memory into the multi-access concurrent cache according to the type of network layer to be processed, so as to form a local lookup table that supports single-cycle multi-address parallel access. The partitioning unit 403 is used to read the input feature vectors in batches from the feature data storage according to the network layer type to be processed and the preset partitioning strategy, and divide them into multiple data blocks; The parallel access unit 404 is used to transform the feature values ​​in each data block into index addresses using an activation function, and to access the local lookup table in parallel according to the index addresses, so as to obtain multiple weight data in a single period and use the multiple weight data as the lookup results of the corresponding data block. The accumulator fusion unit 405 is used to accumulate and fuse the lookup results of each data block through a hierarchical reduction circuit after completing the lookup operation of all data blocks to generate the activation output value of the current neuron. The conversion and write-back unit 406 is used to convert the format of the activation output value according to the data exchange bus width and write it back to the feature data memory, and use the written-back activation output value as the input feature of the next layer network or the output of the model inference result.

[0095] The extraction and generation unit 401 is specifically used to extract the weight parameters of each layer in the multilayer perceptron model; divide the weight parameters into multiple weight sub-matrices along the input channel direction; perform low-bit quantization on the weight parameters in each weight sub-matrices to obtain quantized weights; perform clustering and discretization on the quantized weights to divide the quantized weights in each weight sub-matrices into multiple clusters, and assign a corresponding cluster index to each quantized weight, using the cluster center of each cluster as the weight cluster value; generate a lookup table based on the weight cluster value, and store the lookup table in on-chip memory. The lookup table is used to obtain the corresponding weight cluster value based on the cluster index.

[0096] The loading and forming unit 402 is specifically used to determine the storage address of the weight sub-table to be loaded in the lookup table according to the type of network layer to be processed; to read the weight sub-table corresponding to the storage address from the dual-port block random access memory through DMA technology, and to load the weight sub-table into the multi-access concurrent cache, which is constructed based on triggers; and to configure the multi-access concurrent cache according to the loaded weight sub-table through a parallel address decoding mechanism to form a local lookup table that supports single-cycle multi-address parallel access.

[0097] The partitioning unit 403 is specifically used to determine the block granularity corresponding to the current network layer according to the type of network layer to be processed; generate an address sequence and a corresponding enable signal according to the block granularity; read the input feature vectors in batches from the feature data memory according to the address sequence and enable signal; and divide the read input feature vectors into multiple data blocks according to the block granularity, with each data block containing a number of feature values ​​corresponding to the block granularity.

[0098] The parallel access unit 404 is specifically used to perform nonlinear transformation on the feature values ​​in each data block using an activation function to obtain the transformed feature values; perform low-bit quantization on the transformed feature values ​​to obtain quantized feature values, and map the quantized feature values ​​to index addresses; allocate the index addresses to multiple parallel channels, where each parallel channel corresponds to an independent address space in the multiple access concurrent cache; within a single clock cycle, access the weight data corresponding to the index address in the local lookup table through multiple parallel channels to obtain the corresponding multiple weight data; and use the multiple weight data as the lookup result of the corresponding data block.

[0099] The accumulator fusion unit 405 is specifically used to input the lookup results corresponding to each data block into the hierarchical reduction circuit in sequence after completing the lookup operation of all data blocks. Through the hierarchical reduction circuit, the lookup results are accumulated level by level using pipeline technology. Each level of accumulation operation is to accumulate the intermediate result obtained from the previous level accumulation with the lookup result of the current level to obtain the current level accumulation intermediate result. After completing the last level accumulation operation, the last level accumulation intermediate result is obtained and used as the activation output value of the current neuron.

[0100] The conversion and write-back unit 406 is specifically used to concatenate or divide the active output value according to the bit width of the data exchange bus to obtain the target output value, which is the output value that matches the bit width of the data exchange bus; and to write the target output value back to the feature data memory.

[0101] It should be noted that the above description of the high-energy-efficiency in-memory computing device embodiment based on in-memory indexing of a multilayer perceptron is similar to the description of the high-energy-efficiency in-memory computing method embodiment based on in-memory indexing of a multilayer perceptron, and has similar beneficial effects. For any technical details not disclosed in the embodiments of the high-energy-efficiency in-memory computing device based on in-memory indexing of the multilayer perceptron of the present invention, please refer to the description of the high-energy-efficiency in-memory computing method embodiment based on in-memory indexing of the present invention for understanding.

[0102] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing, characterized in that, include: Extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in on-chip memory. Based on the type of network layer to be processed, the corresponding weight sub-table is dynamically loaded from the lookup table of the on-chip memory into the multi-address concurrent cache to form a local lookup table that supports single-cycle multi-address parallel access. Based on the network layer type to be processed and the preset block division strategy, the input feature vectors are read in batches from the feature data storage and divided into multiple data blocks; By using an activation function, the feature values ​​in each data block are transformed into index addresses, and the local lookup table is accessed in parallel according to the index addresses to obtain multiple weight data in a single period, and the multiple weight data are used as the lookup results of the corresponding data blocks. After completing the lookup operation for all data blocks, the lookup results corresponding to each data block are accumulated and fused through a hierarchical reduction circuit to generate the activation output value of the current neuron. Based on the data exchange bus width, the activation output value is formatted and written back to the feature data memory. The written-back activation output value is then used as the input feature of the next layer network or as the output of the model inference result.

2. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The step of extracting the weight parameters of each layer in the multilayer perceptron model, generating a lookup table based on the weight parameters, and storing the lookup table in on-chip memory includes: Extract the weight parameters of each layer in the multilayer perceptron model; The weight parameters are divided into multiple weight sub-matrices along the input channel direction; The weight parameters in each weight submatrix are quantized using low-bit quantization to obtain the quantized weights. The quantized weights are clustered and discretized to divide the quantized weights in each weight submatrix into multiple clusters, and a corresponding cluster index is assigned to each quantized weight. The cluster center of each cluster is used as the weight cluster value. The lookup table is generated based on the weight cluster value and stored in the on-chip memory. The lookup table is used to obtain the corresponding weight cluster value based on the cluster index.

3. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The step of dynamically loading the corresponding weight sub-table from the lookup table in the on-chip memory into the multi-access concurrent cache according to the network layer type to be processed, forming a local lookup table that supports single-cycle multi-address parallel access, includes: Based on the type of network layer to be processed, determine the storage address of the weight sub-table to be loaded in the lookup table; Using DMA technology, the weight sub-table corresponding to the storage address is read from the dual-port block random access memory, and the weight sub-table is loaded into the multi-access concurrent cache, which is constructed based on triggers; Based on the loaded weighted sub-table, the multi-address concurrent cache is configured through a parallel address decoding mechanism to form the local lookup table that supports single-cycle multi-address parallel access.

4. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The step involves reading input feature vectors in batches from the feature data storage according to the network layer type to be processed and a preset block partitioning strategy, and dividing them into multiple data blocks, including: Based on the type of network layer to be processed, determine the block granularity corresponding to the current network layer; Based on the block granularity, an address sequence and a corresponding enable signal are generated; The input feature vectors are read in batches from the feature data memory according to the address sequence and the enable signal; Based on the block granularity, the read input feature vector is divided into the multiple data blocks, and each data block contains the number of feature values ​​corresponding to the block granularity.

5. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The process involves using an activation function to transform the feature values ​​in each data block into index addresses, and then accessing the local lookup table in parallel based on these index addresses to obtain multiple weight data points within a single period. These multiple weight data points are then used as the lookup results for the corresponding data blocks. The activation function is used to perform a nonlinear transformation on the feature values ​​in each data block to obtain the transformed feature values. The transformed feature value is quantized using low-bit quantization to obtain the quantized feature value, and the quantized feature value is mapped to an index address. The index address is allocated to multiple parallel channels, wherein each parallel channel corresponds to an independent address space in the multiple access concurrency cache; Within a single clock cycle, the weight data corresponding to the index address in the local lookup table is accessed in parallel through the multiple parallel channels to obtain the corresponding multiple weight data. The multiple weight data are used as the lookup results for the corresponding data blocks.

6. The high-energy-efficiency in-memory computation method for multilayer perceptrons based on in-memory indexing according to claim 5, characterized in that, The step of allocating the index address to multiple parallel channels includes: Based on the number of parallel channels supported by the multi-address concurrent cache, the number of parallel channels is determined to be 16; Based on the fact that the number of parallel channels is 16, the index address is allocated to 16 parallel channels, and each parallel channel corresponds to an independent address space in the multi-access concurrent cache.

7. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, After completing the lookup operation for all data blocks, the lookup results for each data block are accumulated and fused using a hierarchical reduction circuit to generate the activation output value of the current neuron, including: After completing the lookup operation for all data blocks, the lookup results corresponding to each data block are sequentially input into the hierarchical reduction circuit. Through the hierarchical reduction circuit, the lookup results are accumulated level by level using pipeline technology. Each level of accumulation operation is to add the intermediate result obtained from the previous level accumulation to the lookup result of the current level to obtain the current level's accumulated intermediate result. After completing the final accumulation operation, the intermediate accumulation result of the final stage is obtained, and the intermediate accumulation result of the final stage is used as the activation output value of the current neuron.

8. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The step of format conversion of the activated output value and writing it back to the feature data memory according to the data exchange bus width includes: Based on the bit width of the data exchange bus, the active output value is spliced ​​or segmented to obtain the target output value, which is an output value that matches the bit width of the data exchange bus. The target output value is written back to the feature data storage.

9. The high-energy-efficiency in-memory computing method for multilayer perceptrons based on in-memory indexing according to claim 1, characterized in that, The number of parallel accesses supported per cycle by the multi-address concurrent cache is at least 16.

10. A high-energy-efficiency in-memory computing device based on in-memory indexing of a multilayer perceptron, characterized in that, include: The extraction and generation unit is used to extract the weight parameters of each layer in the multilayer perceptron model, generate a lookup table based on the weight parameters, and store the lookup table in on-chip memory. The loading and forming unit is used to dynamically load the corresponding weight sub-table from the lookup table of the on-chip memory into the multi-access concurrent cache according to the type of network layer to be processed, so as to form a local lookup table that supports single-cycle multi-address parallel access. The partitioning unit is used to read the input feature vectors in batches from the feature data storage and divide them into multiple data blocks according to the network layer type to be processed and the preset partitioning strategy. The parallel access unit is used to transform the feature values ​​in each data block into index addresses using an activation function, and to access the local lookup table in parallel according to the index addresses, so as to obtain multiple weight data in a single period and use the multiple weight data as the lookup results of the corresponding data block. The accumulation and fusion unit is used to accumulate and fuse the lookup results of each data block after completing the lookup operation of all data blocks, and generate the activation output value of the current neuron by means of the hierarchical reduction circuit. The conversion and write-back unit is used to convert the format of the activation output value according to the data exchange bus width and write it back to the feature data memory, and output the written-back activation output value as the input feature of the next layer network or the model inference result.

Images