Display screen driving integrated circuit control method, device, equipment and storage medium

Abstract

The application discloses a display screen driving integrated circuit control method, device and equipment and a storage medium, relates to the technical field of display screen control, and discloses a display screen driving integrated circuit control method, which comprises the following steps: obtaining a target register configuration, wherein the target register configuration is a register configuration for closing a field synchronization signal falling edge counter function; in response to a frame synchronization signal sent by a host, collecting the number of line synchronization signals according to the target register configuration; determining whether the display screen meets preset display timing requirements according to the number of line synchronization signals; and when the display screen meets the preset display timing requirements, turning off the field synchronization signal, so as to complete the display screen driving integrated circuit control. The application improves the mura problem caused by the loss of a data enable signal of the host after the display screen is woken up from hibernation, and improves the anti-interference performance and reliability of the display screen driving integrated circuit control.

Description

Technical Field

[0001] This application relates to the field of display screen control technology, and in particular to methods, apparatus, devices and storage media for controlling display screen driver integrated circuits. Background Technology

[0002] With the rapid development of automotive displays and portable smart terminals, LCD screens have become a core component of human-computer interaction, and their display stability directly affects the overall user experience and reliability. In automotive scenarios, to reduce overall vehicle power consumption and meet energy-saving requirements, the host and display module typically need to frequently perform sleep and wake-up operations. During this process, the video data output timing on the host side needs to be strictly matched with the scanning timing within the display driver integrated circuit.

[0003] In conventional techniques, to ensure stable output of the field synchronization signal, driver integrated circuits typically employ a shutdown mechanism based on counting the horizontal synchronization signal and superimposed with delay control. This means that after the field synchronization signal maintains a predetermined number of horizontal synchronization cycles, the shutdown operation is executed through internal delay counting logic, thereby achieving precise control of the field synchronization pulse width. However, in practical applications, when the host experiences an abnormal data enable signal within a specific time window, the driver integrated circuit may prematurely generate an abnormal horizontal synchronization signal. This interferes with the delay counting process and causes the field synchronization signal to be prematurely or abnormally shut down, ultimately resulting in scan state errors and persistent screen distortion.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, device, and storage medium for controlling a display screen's driver integrated circuit, aiming to solve the technical problem that the display screen cannot automatically recover from screen flickering faults after waking from sleep mode when the host data enable signal is occasionally abnormal or lost.

[0006] To achieve the above objectives, this application proposes a method for controlling a display screen's driving integrated circuit, the method comprising: Obtain the target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; In response to the frame synchronization signal sent by the host, the number of acquisition line synchronization signals is configured according to the target register; Determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; When the display screen meets the preset display timing requirements, the field synchronization signal is turned off to complete the control of the display screen's driving integrated circuit.

[0007] In one embodiment, the step of configuring the number of acquisition line synchronization signals according to the target register in response to a frame synchronization signal sent by the host includes: In response to the frame synchronization signal sent by the host, the field synchronization signal is pulled high to obtain the target field synchronization signal; The number of line synchronization signals is obtained by collecting and counting the target field synchronization signals.

[0008] In one embodiment, the step of determining whether the display screen meets the preset display timing requirements based on the number of line synchronization signals includes: Obtain the threshold for the number of line synchronization signals; When the number of line synchronization signals reaches the threshold of the number of line synchronization signals, it is determined that the display screen meets the preset display timing requirements.

[0009] In one embodiment, prior to the step of obtaining the target register configuration, the following steps are included: Obtain the initial register configuration of the driver integrated circuit; Modify the enabled state of the field synchronization signal falling edge counter function in the initial register configuration to disable it to obtain the target register configuration.

[0010] In one embodiment, prior to the step of obtaining the target register configuration, the method further includes: Obtain the duration of the initial field synchronization signal; The display timing is updated based on the initial field synchronization signal duration to obtain the target field synchronization signal duration. The threshold for the number of line synchronization signals is determined based on the duration of the target field synchronization signal.

[0011] In one embodiment, the step of determining the threshold number of line synchronization signals based on the duration of the target field synchronization signal includes: The number of line synchronization signals maintained is determined based on the duration of the target field synchronization signal. The threshold for the number of line synchronization signals is determined based on the number of line synchronization signals maintained.

[0012] In one embodiment, the step of updating the display timing based on the initial field synchronization signal duration to obtain the target field synchronization signal duration includes: Obtain the preset display timing requirements; The target display duration is determined according to the preset display timing requirements; The initial field synchronization signal duration is updated based on the target display duration to obtain the target field synchronization signal duration.

[0013] In addition, to achieve the above objectives, this application also proposes a display screen driver integrated circuit control device, the display screen driver integrated circuit control device comprising: a configuration acquisition module for acquiring a target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; The signal acquisition module is used to respond to the frame synchronization signal sent by the host and to acquire the number of line synchronization signals according to the target register. The requirement is to determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; The circuit control module is used to turn off the field synchronization signal when the display screen meets the preset display timing requirements, so as to complete the control of the display screen's driving integrated circuit.

[0014] Furthermore, to achieve the above objectives, this application also proposes a display screen driver integrated circuit control device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the display screen driver integrated circuit control method described above.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the display screen driving integrated circuit control method described above.

[0016] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the display screen driver integrated circuit control method described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: By employing a target register configuration to acquire the function of disabling the falling edge counter of the vertical sync signal, responding to the frame synchronization signal sent by the host and collecting the number of horizontal sync signals according to the target register configuration, and then determining whether the display screen meets the preset display timing requirements based on the number of horizontal sync signals, and disabling the vertical sync signal when it does, this technique solves the technical problem in existing technologies where the low probability of data loss of the host-side enable signal causes the counting process of the falling edge counter of the vertical sync signal to be interfered with by abnormally generated horizontal sync signals, resulting in abnormal premature shutdown of the vertical sync signal, disorder of the internal state machine of the driver integrated circuit, and screen distortion after the display screen wakes up from sleep mode that cannot recover on its own. Compared with existing technologies, this technique completely eliminates the interference path introduced by the falling edge counter of the vertical sync signal, making the shutdown of the vertical sync signal only related to the counting of the horizontal sync signal, no longer relying on the absolute stability of the host signal in a specific time period. This effectively improves the anti-interference capability and operational reliability of the display screen driver integrated circuit control. At the same time, optimization is achieved only through register configuration adjustment, without changing the hardware circuit, making implementation simple, low-cost, and having no impact on the host side, with good compatibility. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating an embodiment of the display screen driver integrated circuit control method of this application; Figure 2 A flowchart illustrating a second embodiment of the display screen driver integrated circuit control method of this application; Figure 3 A simplified flowchart illustrating the display screen driver integrated circuit control method provided in Embodiment 2 of this application; Figure 4 This is a schematic diagram of the module structure of the display screen driver integrated circuit control device according to an embodiment of this application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the display screen driver integrated circuit control method in the embodiments of this application.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is: to obtain the target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; in response to the frame synchronization signal sent by the host, to collect the number of line synchronization signals according to the target register configuration; to determine whether the display screen meets the preset display timing requirements according to the number of line synchronization signals; and when the display screen meets the preset display timing requirements, to turn off the field synchronization signal to complete the control of the display screen driver integrated circuit.

[0025] In this embodiment, for ease of description, the following description will focus on the driver integrated circuit control device for identifying the display screen.

[0026] Because existing technologies often fail to resolve screen flickering issues after waking from sleep mode due to occasional anomalies or loss of the host data enable signal, this application provides a solution. This solution employs a target register configuration to acquire and disable the falling edge counter of the field sync signal. It responds to the frame sync signal sent by the host and collects the number of line sync signals based on this target register configuration. Then, it determines whether the display meets the preset display timing requirements based on the number of line sync signals, and disables the field sync signal if it does. This addresses the problem in existing technologies where a low probability of data enable signal loss on the host side leads to abnormal generation of the falling edge counter. The technical problem of horizontal sync signal interference causing abnormal premature shutdown of the vertical sync signal and disorder of the internal state machine of the driver integrated circuit, resulting in screen distortion after the display wakes up from sleep and cannot recover on its own, is addressed by a new technology. Compared with existing technologies, this technology completely eliminates the interference path introduced by the counter of the falling edge of the vertical sync signal. The shutdown of the vertical sync signal is only related to the counting of the horizontal sync signal, no longer relying on the absolute stability of the host signal in a specific time period. This effectively improves the anti-interference capability and operational reliability of the display driver integrated circuit. At the same time, optimization is achieved only through register configuration adjustment, without changing the hardware circuit. It is simple to implement, low in cost, has no impact on the host, and has good compatibility.

[0027] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone; or an electronic device, a display screen driver integrated circuit control device, and a driver integrated circuit, etc., capable of realizing the above functions. The following description uses a driver integrated circuit as an example to illustrate this embodiment and the subsequent embodiments.

[0028] Based on this, embodiments of this application provide a method for controlling a display screen's driving integrated circuit, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the display screen driver integrated circuit control method of this application.

[0029] In this embodiment, the method for controlling the driving integrated circuit of the display screen includes steps S10 to S40: Step S10: Obtain the target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; It should be understood that in actual applications, when the display screen is used in conjunction with the host to conduct sleep and wake-up stress tests, there is a low probability of a screen displaying a distorted image after waking up and failing to recover on its own. After in-depth analysis of the cause, it can be found that the root cause of this failure is a defect on the host side that results in a low probability of losing the data enable signal. The data enable signal is one of the key control signals in the display driver process. Its function is to identify the area of ​​valid image data. The driver integrated circuit will generate horizontal synchronization signal and vertical synchronization signal based on the data enable signal.

[0030] Furthermore, to ensure the stability of the field synchronization signal, a delay shutdown mechanism based on the counting of the line synchronization signal is usually adopted. Specifically, the driver integrated circuit will set a falling edge counter for the field synchronization signal. Before preparing to shut down the field synchronization signal, the counter will start counting and delay for a certain number of line synchronization signal cycles before actually performing the operation to shut down the field synchronization signal.

[0031] Furthermore, under normal circumstances, no new horizontal sync signal should appear during the counting period of the falling edge counter of the vertical sync signal. However, if the host unexpectedly loses the data enable signal during the counting period of the falling edge counter of the vertical sync signal, it will cause the driver integrated circuit to generate an abnormal horizontal sync signal in advance. This prematurely appearing horizontal sync signal will interfere with the counting process of the falling edge counter of the vertical sync signal, which may cause the counter to be triggered before it has finished counting, thereby prematurely turning off the vertical sync signal. This abnormal shutdown will cause the state machine inside the driver integrated circuit to malfunction, making it impossible for the subsequent vertical sync signal to be pulled high again correctly, ultimately resulting in a complete error in the scanning timing, which manifests as a continuous screen distortion on the screen. Moreover, because the state of the driver integrated circuit is abnormal, this fault cannot be repaired by itself in subsequent display cycles.

[0032] It should be noted that the target register configuration is a combination of parameter settings inside the driver integrated circuit used to define the on or off states of various functions. It is the core configuration data for adapting the timing control of the display screen and can be flexibly adjusted through software modification.

[0033] It should be understood that the driver integrated circuit is the core device for display control. It is responsible for receiving control signals from the host and generating various synchronization signals required for display scanning, regulating the pixel scanning and image display process of the display, and is a key control unit connecting the host and the display.

[0034] Additionally, the falling edge counter function of the field synchronization signal is a delay counting control function in the driver integrated circuit used before the field synchronization signal is turned off. This function responds to changes in external signals during the counting period and is a key delay mechanism in the original display timing control.

[0035] Understandably, the driver integrated circuit pre-sets and stores the target register configuration. When performing display screen driver control, it actively retrieves the target register configuration from the internal storage area. This configuration is a dedicated configuration for disabling the falling edge counter function of the field synchronization signal, thus completing the loading and activation of the configuration.

[0036] Furthermore, by disabling the independent delay counter shutdown mechanism, which is susceptible to external signal interference, the interference path caused by abnormal signals interrupting the counting process of the field synchronization signal falling edge counter is eliminated at the source. This lays the foundation for subsequent stable display timing control and frees the functional configuration of the driver integrated circuit from dependence on the easily interfered delay counting function.

[0037] In one feasible implementation, steps A01-A02 may be included before step S10: Step A01: Obtain the initial register configuration of the driver integrated circuit; It should be noted that the initial register configuration is the default register parameter setting combination used by the driver integrated circuit in the original display control logic. It is the basic configuration data for realizing the original field synchronization signal turn-off timing control, and includes the startup and working status settings of various functions.

[0038] It is understandable that the driver integrated circuit retrieves the pre-stored initial register configuration from its own register configuration storage area, completes the acquisition and loading of the configuration, and provides the basic configuration basis for subsequent register configuration modification operations.

[0039] Step A02: Modify the enabled state of the field synchronization signal falling edge counter function in the initial register configuration to disabled state to obtain the target register configuration.

[0040] It should be noted that the active state is when the field synchronization signal falling edge counter function is set to be enabled in the register configuration and can perform delayed counting operations normally. In this state, the counter can respond to changes in external signals and start counting, which is the default function state in the original display control.

[0041] Additionally, the target register configuration is a dedicated configuration obtained after modifying the functional state of the initial register configuration. Its core feature is that the falling edge counter function of the field synchronization signal is in the off state, which is the core configuration data for adapting to the subsequent stable display timing control.

[0042] Understandably, the driver integrated circuit modifies the parameters of the acquired initial register configuration, adjusting the start-up valid state corresponding to the falling edge counter function of the field synchronization signal to the off state. Specifically, it sets the synchronization control register and delay configuration register that control the turn-off timing of the field synchronization signal from the valid state to the invalid state. After completing all the modification operations, the target register configuration is obtained.

[0043] Furthermore, precise functional state modifications are made starting from the original initial configuration of the driver integrated circuit. Only the falling edge counter function of the field synchronization signal, which is susceptible to interference, is disabled. No entirely new register configuration needs to be developed, making the modification method simple and highly targeted. This function is completely disabled by setting the corresponding control register to an invalid state, thus completely disabling the independent delay counter shutdown mechanism, which is susceptible to external signal interference, from the configuration source. This eliminates the possibility of the falling edge counter of the field synchronization signal being interfered with by abnormal signals. The entire modification process is achieved solely through software adjustment of register parameters, without changing hardware circuits or adding physical components. This results in low implementation cost, simple operation, and the modified target register configuration accurately adapts to subsequent display timing control requirements, laying a reliable configuration foundation for stable horizontal synchronization signal acquisition and field synchronization signal shutdown.

[0044] Step S20: In response to the frame synchronization signal sent by the host, configure the number of acquisition line synchronization signals according to the target register; It should be noted that the frame synchronization signal is a control signal sent by the host to the driver integrated circuit to identify the start of the transmission of a new frame of image data. It is the starting signal that triggers the scanning and display of the image on the display screen and dominates the timing of the display of a frame of image.

[0045] It should be understood that the host is the control terminal that sends various control signals and image data to the driver integrated circuit. It is the initiator of the display content and display timing of the display screen and is responsible for issuing relevant instructions for image display to the driver integrated circuit.

[0046] In addition, the number of horizontal sync signals is a value obtained by the driver integrated circuit in real time by statistically analyzing the horizontal sync signals. This value is a core quantitative indicator for measuring the horizontal scanning progress of the display screen and is directly related to the timing of the field sync signal being turned off.

[0047] Understandably, the driver integrated circuit continuously monitors the signals sent by the host, and responds immediately upon receiving the frame synchronization signal sent by the host. Based on the loaded and effective target register configuration, it starts the line synchronization signal acquisition module to capture and count the line synchronization signals in real time, and continuously collects and records the number of line synchronization signals.

[0048] Furthermore, by using the frame synchronization signal as a precise trigger starting point and combining it with the interference-free target register configuration to collect the number of line synchronization signals, the independence and stability of the acquisition process are ensured, the acquisition deviation caused by the original counting function is avoided, and the acquisition process of the line synchronization signal is only controlled by the core display timing.

[0049] In one feasible implementation, step S20 may include steps S21-S22: Step S21: In response to the frame synchronization signal sent by the host, the field synchronization signal is pulled high to obtain the target field synchronization signal; It should be noted that the target field synchronization signal is the field synchronization signal that is in an effective working state obtained after the driver integrated circuit performs a high operation on the field synchronization signal. It is a signal with frame scan triggering capability.

[0050] Furthermore, pulling up the field sync signal is a signal operation that switches the level of the field sync signal from low to high. It is the core action to activate the frame scan trigger function of the field sync signal. Only the field sync signal in a high-level state can send a valid command to the gate driver.

[0051] Understandably, after receiving the frame synchronization signal sent by the host, the driver integrated circuit responds by pulling the field synchronization signal high and generating the target field synchronization signal to trigger frame scanning preparation.

[0052] Step S22: Collect and count the line synchronization signals based on the target field synchronization signal to obtain the number of line synchronization signals.

[0053] It should be noted that the horizontal synchronization signal is a control signal generated by the driver integrated circuit based on the data enable signal. It is the core signal for regulating the horizontal scanning of the display screen and directly determines the timing of the scanning of horizontal pixels.

[0054] In addition, the number of horizontal synchronization signals is a value obtained by the driver integrated circuit counting the acquired horizontal synchronization signals in real time, and it is a core quantitative indicator for measuring the horizontal scanning progress of the display screen.

[0055] Understandably, the driver integrated circuit uses the target field synchronization signal as the starting point for scanning, collects the line synchronization signal in real time, and performs counting operations simultaneously to obtain the number of line synchronization signals.

[0056] Furthermore, by using the frame synchronization signal as a precise triggering starting point and raising the field synchronization signal to clarify the start time of frame scanning, the acquisition and counting of the line synchronization signal are precisely matched with the frame scanning rhythm, ensuring the timing accuracy and data validity of the acquisition of the number of line synchronization signals. At the same time, the target register configuration eliminates the interference of external signals on the acquisition process, making the line synchronization signal count only related to the display timing, providing a reliable quantitative basis for the precise shutdown of the subsequent field synchronization signal.

[0057] Step S30: Determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; It should be noted that the preset display timing requirements are a threshold standard for the number of horizontal synchronization signals pre-set according to the characteristics of the display panel and the overall needs of the display module. It is the core basis for judging whether the display screen has reached the condition of turning off the vertical synchronization signal and is fully adapted to the normal display pattern of the display screen.

[0058] It should be understood that the display panel is the core component of the display screen for realizing image display. It consists of a large number of pixel units and is the carrier for image light signal output. The display module is a complete display unit that includes the display panel, driving circuit, and various drivers. It is an independent functional module for realizing image display.

[0059] Understandably, the driver integrated circuit compares the number of horizontal synchronization signals obtained from real-time acquisition and statistics with the threshold of the preset display timing requirements one by one. Combining the scanning characteristics of the display panel and the working requirements of the display module, it comprehensively determines whether the current horizontal scanning progress of the display screen has reached the timing condition for the vertical synchronization signal to be turned off, thereby determining whether the display screen meets the preset display timing requirements.

[0060] Furthermore, by accurately comparing the quantified number of horizontal synchronization signals with a preset standard, an objective determination of the display timing status of the screen can be achieved, providing a reliable basis for the precise shutdown of the vertical synchronization signal and ensuring the accuracy and rationality of the display timing control.

[0061] In one feasible implementation, step S30 may include steps S31-S32: Step S31: Obtain the threshold number of line synchronization signals; It should be noted that the horizontal sync signal quantity threshold is a pre-set critical value for counting horizontal sync signals based on the characteristics of the display panel and the overall timing requirements of the display module. It is the core quantitative standard for determining whether the display screen has met the timing conditions for turning off the vertical sync signal, and its value is adapted to the horizontal scanning rhythm of the display screen during normal display.

[0062] It is understandable that the driver integrated circuit retrieves the pre-set threshold for the number of line synchronization signals stored internally, completes the acquisition and loading of this threshold, and provides a quantitative basis for subsequent timing determination.

[0063] Step S32: When the number of line synchronization signals reaches the threshold of the number of line synchronization signals, it is determined that the display screen meets the preset display timing requirements.

[0064] It should be noted that the preset display timing requirements are timing specifications adapted to the normal image display of the display screen. They are the core basis for determining the field synchronization signal to perform the shutdown operation and are jointly determined by the inherent characteristics of the display panel and the display module.

[0065] It is understandable that the driver integrated circuit compares the number of line synchronization signals obtained by real-time acquisition and statistics with the threshold number of acquired line synchronization signals. When the number of line synchronization signals reaches the threshold, it directly determines that the display screen meets the preset display timing requirements.

[0066] Furthermore, by using a pre-set threshold for the number of horizontal synchronization signals as a quantitative standard for timing determination, the process of determining whether the display meets the preset display timing requirements becomes more objective and accurate. The threshold setting aligns with the actual characteristics of the display panel and display module, ensuring a high degree of matching between the determination result and the actual scanning state of the display. At the same time, using the compliance status of the number of horizontal synchronization signals as the determination criterion eliminates the reliance on the interference-prone delay counting mechanism, making the timing determination process only related to the counting of horizontal synchronization signals. This eliminates the interference risk caused by abnormal host signals at the determination stage, providing a reliable determination result for the accurate shutdown of subsequent field synchronization signals, and improving the stability and reliability of the display drive control.

[0067] Step S40: When the display screen meets the preset display timing requirements, the field synchronization signal is turned off to complete the control of the display screen's driving integrated circuit.

[0068] It should be noted that the field synchronization signal is the core control signal sent by the driving integrated circuit to the gate driver. When it is pulled high, it triggers the opening of the scanning path of the new frame image, directly controlling the overall rhythm of the display frame scanning. It is the core control signal of the frame scanning timing.

[0069] It should be understood that the gate driver is a dedicated driving device that receives the field synchronization signal and the horizontal synchronization signal from the driving integrated circuit and controls the opening and closing of the horizontal scanning path of the pixel unit of the display screen. It is a key component for realizing the horizontal scanning of the display screen.

[0070] Understandably, after the driver integrated circuit completes the judgment and determines that the display screen meets the preset display timing requirements, it immediately triggers the field synchronization signal turn-off command, controls the field synchronization signal to switch from the high state to the off state, completes the full timing control of the display screen's line scanning and frame scanning, and thus completes the control of the display screen's driver integrated circuit.

[0071] This embodiment provides a method for controlling the driver integrated circuit of a display screen. By disabling the falling edge counter function of the vertical sync signal and adjusting the number of horizontal sync signals maintained by the vertical sync signal, and shutting down the vertical sync signal according to the counting result of the horizontal sync signal, the method solves the problem of screen distortion after the display screen wakes up from sleep mode due to the loss of the host data enable signal and cannot recover on its own. This effectively improves the anti-interference and reliability of the display screen driver integrated circuit control, and is implemented only through software configuration, which is low in cost and has good compatibility.

[0072] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 Before step S10, the method for controlling the display screen's driving integrated circuit further includes steps B01 to B03: Step B01: Obtain the duration of the initial field synchronization signal; It should be noted that the initial field synchronization signal duration is the duration from pull-up to turn-off set by the driver integrated circuit in the original display control logic for the field synchronization signal. This duration is measured in units of the period of the horizontal synchronization signal and is the basic time parameter for adapting to the original display timing.

[0073] In addition, the field synchronization signal duration is the total duration for which the field synchronization signal is in a high active state. It is a core time indicator that determines the frame scanning timing of the display screen and is directly related to the overall progress of the line scanning.

[0074] It is understandable that the driver integrated circuit retrieves the preset initial field synchronization signal duration from the internally stored display timing configuration.

[0075] Step B02: Update the display timing based on the initial field synchronization signal duration to obtain the target field synchronization signal duration; It should be noted that the display timing update is an optimization and adjustment operation for the frame scanning and line scanning timing parameters of the display screen. It is a core configuration action that adapts the new control logic based on the original timing parameters, and only quantitatively adjusts the duration of the field synchronization signal.

[0076] In addition, the target field synchronization signal duration is an optimized duration obtained after updating the display timing of the initial field synchronization signal duration. It is a new timing parameter adapted to the falling edge counter function without field synchronization signal.

[0077] Understandably, the driver integrated circuit makes quantitative adjustments based on the acquired initial field synchronization signal duration and the timing requirements of the display module to complete the display timing update and obtain the target field synchronization signal duration.

[0078] In one feasible implementation, step B02 may include steps B021 to S023: Step B021: Obtain the preset display timing requirements; It should be noted that the preset display timing requirements are display control specifications pre-defined based on the characteristics of the display panel and the overall working requirements of the display module. They are the core timing basis for the display screen to achieve normal image display and cover the limiting standards for key timing parameters such as the duration of field synchronization signal maintenance.

[0079] Understandably, the driver integrated circuit retrieves the preset display timing requirements from its internal timing configuration storage area to complete the acquisition and loading of these requirements.

[0080] Step B022: Determine the target display duration according to the preset display timing requirements; It should be noted that the target display duration is the optimal duration of the field synchronization signal determined based on the preset display timing requirements. It is the core time parameter for adapting the display screen to normal scanning display, and the period of the line synchronization signal is the only unit of measurement.

[0081] Additionally, the line synchronization signal period is the length of time it takes for the line synchronization signal to complete one effective trigger and achieve one line pixel scan. It is the basic unit for measuring the duration of the line synchronization signal and is compatible with all display timing parameter settings.

[0082] It is understandable that the driver integrated circuit determines the corresponding target display duration based on the acquired preset display timing requirements and the scanning characteristics of the display panel.

[0083] Step B023: Update the initial field synchronization signal duration according to the target display duration to obtain the target field synchronization signal duration.

[0084] It should be noted that the initial field synchronization signal duration is the duration from pull-up to turn-off set by the driver integrated circuit for the field synchronization signal in the original display control logic. It is the basic time parameter for adapting to the original display timing and was originally designed as a fixed number of line synchronization signal cycles.

[0085] In addition, the target field synchronization signal duration is an optimized duration obtained after updating the initial field synchronization signal duration. It is a new timing parameter adapted to the falling edge counter function without field synchronization signal and can completely offset the delay of the original delay counting mechanism.

[0086] Understandably, the driver integrated circuit quantitatively adjusts and updates the initial field synchronization signal duration based on the determined target display duration to obtain the target field synchronization signal duration. In this embodiment, the initial field synchronization signal duration is 10 line synchronization signal cycles, and the updated target field synchronization signal duration is 11 line synchronization signal cycles.

[0087] Step B03: Determine the threshold number of line synchronization signals based on the duration of the target field synchronization signal.

[0088] It should be noted that the threshold for the number of horizontal synchronization signals is a critical value for counting horizontal synchronization signals that corresponds one-to-one with the duration of the vertical synchronization signal. It is the core quantitative standard for determining whether the display screen meets the preset display timing requirements, and its value is completely matched with the unit of measurement of the duration of the vertical synchronization signal.

[0089] In addition, the line synchronization signal period is the length of time it takes for the line synchronization signal to complete one effective trigger. It is the basic unit of the duration of the metering field synchronization signal and the core basis for the conversion between the number of line synchronization signals and time parameters.

[0090] Understandably, the driver integrated circuit determines the corresponding threshold for the number of line synchronization signals based on the duration of the target field synchronization signal and the conversion between the period completion time and the number of line synchronization signals.

[0091] Furthermore, by retrieving, updating, and quantizing the initial field synchronization signal duration, precise adaptation of the display timing parameters to the falling edge counter function without the field synchronization signal is achieved. This ensures that the threshold number of horizontal synchronization signals perfectly matches the optimized field synchronization signal duration, guaranteeing the accuracy of subsequent timing determination and field synchronization signal shutdown. The timing update only quantitatively increases the horizontal synchronization signal period, perfectly matching the timing requirements of the display panel and display module, avoiding new display problems caused by parameter adjustments. At the same time, optimization is based on the original initial parameters, eliminating the need to redevelop entirely new timing configurations. This makes implementation simple and highly adaptable, providing precise quantitative basis for subsequent stable display timing control and eliminating the risk of abnormal signal interference at the parameter level.

[0092] In one feasible implementation, step B03 may include steps B031 to S032: Step B031: Determine the number of line synchronization signals to be maintained based on the duration of the target field synchronization signal; It should be noted that the target field synchronization signal duration is the duration obtained after optimizing and updating the initial field synchronization signal duration. It is the total duration of the field synchronization signal from being pulled up to being turned off, with the period of the line synchronization signal as the sole unit of measurement.

[0093] In addition, the number of line synchronization signals maintained is the specific number of line synchronization signals corresponding to the duration of the target field synchronization signal. It is a quantitative result of converting time parameters into quantity parameters and is a core quantity indicator for adapting display timing control.

[0094] Understandably, the driver integrated circuit determines the corresponding number of times the line synchronization signal is maintained based on the duration of the target field synchronization signal and the conversion of the period completion time of the line synchronization signal into a number.

[0095] Step B032: Determine the threshold for the number of line synchronization signals based on the number of line synchronization signals maintained.

[0096] It should be noted that the threshold for the number of horizontal synchronization signals is a critical number value for determining whether the display screen meets the preset display timing requirements. It is the core criterion for triggering the operation of turning off the vertical synchronization signal and has a one-to-one matching relationship with the number of horizontal synchronization signals maintained.

[0097] It is understandable that the driver integrated circuit directly sets the number of maintained line synchronization signals as the line synchronization signal number threshold, thus determining the line synchronization signal number threshold. In this embodiment, when the number of maintained line synchronization signals is 11, the corresponding line synchronization signal number threshold is 11.

[0098] This embodiment provides a method for controlling a display screen driver integrated circuit. By acquiring the initial field synchronization signal duration and updating the target field synchronization signal duration in combination with preset display timing requirements, and then converting it into a threshold for the number of horizontal synchronization signals for subsequent display timing determination, this method solves the problem of incompatibility between the original timing parameters and the new control logic after disabling the falling edge counter of the field synchronization signal. At the same time, it further avoids the display screen hibernation and wake-up screen distortion caused by the loss of the host data enable signal. It achieves accurate matching between display timing parameters and new control logic, ensuring the accuracy of subsequent field synchronization signal shutdown and timing determination. From the parameter level, it further improves the stability and anti-interference of the display screen driver integrated circuit control. Moreover, this adjustment is completed only through software configuration, which is simple to implement and low in cost.

[0099] For example, to help understand the implementation flow of the display screen driving integrated circuit control method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 3 , Figure 3 A simplified flowchart of a method for controlling a display screen's driver integrated circuit is provided, specifically: The host sends a frame synchronization signal, which drives the integrated circuit (IC) to raise the field synchronization signal, i.e., the vertical synchronization signal (Start Vertical, STV). Then, the falling edge counter is canceled, and the STV duration is adjusted to 11 horizontal synchronization (Hsync) cycles. Next, Hsync counting begins, with the goal of maintaining 11 Hsync cycles. At this point, it is checked whether the Hsync count has reached 11. If it has not reached 11, it returns to continue counting. If it has reached 11, the STV signal is directly turned off. Ultimately, the display timing is normal, and there is no screen distortion. The entire process avoids abnormal Hsync interference caused by the loss of the host data enable signal (DE) by canceling the original FallingCounter mechanism and replacing it with a fixed number of Hsync counts before directly turning off STV. This ensures that the display will not have screen distortion after waking up from sleep.

[0100] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the driving integrated circuit control method of the display screen of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0101] This application also provides a display screen driver integrated circuit control device, please refer to... Figure 4 The display screen driver integrated circuit control device includes: Configuration acquisition module 10 is used to acquire target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; Signal acquisition module 20 is used to respond to the frame synchronization signal sent by the host and to configure the number of line synchronization signals to be acquired according to the target register; Module 30 is required to determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals. The circuit control module 40 is used to turn off the field synchronization signal when the display screen meets the preset display timing requirements, so as to complete the control of the display screen's driving integrated circuit.

[0102] The display screen driver integrated circuit control device provided in this application, employing the display screen driver integrated circuit control method in the above embodiments, can solve the technical problem that the display screen cannot automatically recover from the screen flickering fault after waking from sleep mode when the host data enable signal is occasionally abnormal or lost. Compared with the prior art, the beneficial effects of the display screen driver integrated circuit control device provided in this application are the same as those of the display screen driver integrated circuit control method provided in the above embodiments, and other technical features in the display screen driver integrated circuit control device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0103] In one embodiment, the signal acquisition module 20 is further configured to, in response to a frame synchronization signal sent by the host, raise the field synchronization signal to obtain a target field synchronization signal; and acquire and count the line synchronization signals based on the target field synchronization signal to obtain the number of line synchronization signals.

[0104] In one embodiment, the requirement determination module 30 is further configured to obtain a threshold number of line synchronization signals; when the number of line synchronization signals reaches the threshold number of line synchronization signals, it is determined that the display screen meets the preset display timing requirements.

[0105] In one embodiment, the configuration acquisition module 10 is further configured to acquire the initial register configuration of the driver integrated circuit; and modify the enabled state of the field synchronization signal falling edge counter function of the initial register configuration to disabled state to obtain the target register configuration.

[0106] In one embodiment, the configuration acquisition module 10 is further configured to acquire the initial field synchronization signal duration; perform display timing updates based on the initial field synchronization signal duration to obtain the target field synchronization signal duration; and determine a threshold for the number of line synchronization signals based on the target field synchronization signal duration.

[0107] In one embodiment, the configuration acquisition module 10 is further configured to determine the number of line synchronization signals maintained based on the duration of the target field synchronization signal; and to determine a threshold for the number of line synchronization signals maintained based on the number of line synchronization signals maintained.

[0108] In one embodiment, the configuration acquisition module 10 is further configured to acquire a preset display timing requirement; determine a target display duration based on the preset display timing requirement; and update the initial field synchronization signal duration based on the target display duration to obtain the target field synchronization signal duration.

[0109] This application provides a display screen driver integrated circuit control device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the display screen driver integrated circuit control method in the first embodiment described above.

[0110] The following is for reference. Figure 5 This document illustrates a schematic diagram of a driver integrated circuit control device suitable for implementing the embodiments of this application. The driver integrated circuit control device for the display screen in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The illustrated display screen driver integrated circuit control device is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0111] like Figure 5As shown, the display screen driver integrated circuit control device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in ROM (Read Only Memory) 1002 or a program loaded from storage device 1003 into RAM (Random Access Memory) 1004. RAM 1004 also stores various programs and data required for the operation of the display screen driver integrated circuit control device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touch screens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. The communication device 1009 allows the display screen driver integrated circuit control device to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show display screen driver integrated circuit control devices with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0112] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0113] The display screen driver integrated circuit control device provided in this application, employing the display screen driver integrated circuit control method in the above embodiments, can solve the technical problem that the display screen cannot automatically recover from the screen flickering fault after waking from sleep mode when the host data enable signal is occasionally abnormal or lost. Compared with the prior art, the beneficial effects of the display screen driver integrated circuit control device provided in this application are the same as those of the display screen driver integrated circuit control method provided in the above embodiments, and other technical features in this display screen driver integrated circuit control device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0114] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0116] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the display screen driving integrated circuit control method in the above embodiments.

[0117] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, RAM (Random Access Memory), ROM (Read Only Memory), Erasable Programmable Read Only Memory (EPROM), optical fiber, CD-ROM (CD-Read Only Memory), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0118] The aforementioned computer-readable storage medium may be included in the display screen driver integrated circuit control device; or it may exist independently and not assembled into the display screen driver integrated circuit control device.

[0119] The aforementioned computer-readable storage medium carries one or more programs that, when executed by the display screen driver integrated circuit control device, cause the display screen driver integrated circuit control device to: acquire a target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field sync signal; in response to a frame synchronization signal sent by the host, acquire the number of line synchronization signals according to the target register configuration; determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; and, when the display screen meets the preset display timing requirements, turn off the field sync signal to complete the display screen driver integrated circuit control.

[0120] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including LAN (Local Area Network) or WAN (Wide Area Network)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0122] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0123] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described display screen driver integrated circuit control method. This solves the technical problem that the display screen cannot automatically recover from screen flickering after waking from sleep mode when the host data enable signal is occasionally abnormal or lost. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the display screen driver integrated circuit control method provided in the above embodiments, and will not be repeated here.

[0124] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the display screen driver integrated circuit control method described above.

[0125] The computer program product provided in this application can solve the technical problem that the display screen cannot automatically recover from the screen flickering fault after waking from sleep mode when the host data enable signal is occasionally abnormal or lost. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the display screen driver integrated circuit control method provided in the above embodiments, and will not be repeated here.

[0126] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for controlling a display screen's driving integrated circuit, characterized in that, The method includes: Obtain the target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; In response to the frame synchronization signal sent by the host, the number of acquisition line synchronization signals is configured according to the target register; Determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; When the display screen meets the preset display timing requirements, the field synchronization signal is turned off to complete the control of the display screen's driving integrated circuit.

2. The method as described in claim 1, characterized in that, The step of configuring the number of acquisition line synchronization signals according to the target register in response to the frame synchronization signal sent by the host includes: In response to the frame synchronization signal sent by the host, the field synchronization signal is pulled high to obtain the target field synchronization signal; The number of line synchronization signals is obtained by collecting and counting the target field synchronization signals.

3. The method as described in claim 1, characterized in that, The step of determining whether the display screen meets the preset display timing requirements based on the number of horizontal synchronization signals includes: Obtain the threshold for the number of line synchronization signals; When the number of line synchronization signals reaches the threshold of the number of line synchronization signals, it is determined that the display screen meets the preset display timing requirements.

4. The method as described in claim 1, characterized in that, Before the step of obtaining the target register configuration, the following steps are included: Obtain the initial register configuration of the driver integrated circuit; Modify the enabled state of the field synchronization signal falling edge counter function in the initial register configuration to disable it to obtain the target register configuration.

5. The method as described in claim 1, characterized in that, Before the step of obtaining the target register configuration, the following is also included: Acquire the initial field synchronization signal duration The display timing is updated based on the initial field synchronization signal duration to obtain the target field synchronization signal duration. The threshold for the number of line synchronization signals is determined based on the duration of the target field synchronization signal.

6. The method as described in claim 5, characterized in that, The step of determining the threshold for the number of line synchronization signals based on the duration of the target field synchronization signal includes: The number of line synchronization signals maintained is determined based on the duration of the target field synchronization signal. The threshold for the number of line synchronization signals is determined based on the number of line synchronization signals maintained.

7. The method as described in claim 5, characterized in that, The step of updating the display timing based on the initial field synchronization signal duration to obtain the target field synchronization signal duration includes: Obtain the preset display timing requirements; The target display duration is determined according to the preset display timing requirements; The initial field synchronization signal duration is updated based on the target display duration to obtain the target field synchronization signal duration.

8. A driver integrated circuit control device for a display screen, characterized in that, The device includes: A configuration acquisition module is used to acquire the target register configuration, wherein the target register configuration is a register configuration that disables the falling edge counter function of the field synchronization signal; The signal acquisition module is used to respond to the frame synchronization signal sent by the host and to acquire the number of line synchronization signals according to the target register. The requirement is to determine whether the display screen meets the preset display timing requirements based on the number of line synchronization signals; The circuit control module is used to turn off the field synchronization signal when the display screen meets the preset display timing requirements, so as to complete the control of the display screen's driving integrated circuit.

9. A display screen driver integrated circuit control device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for controlling the display screen using a driving integrated circuit as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the display screen driving integrated circuit control method as described in any one of claims 1 to 7.

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