Method of initializing a phase change memory array and phase change memory
By obtaining the initial threshold voltage of the phase-change memory array and configuring differentiated initialization operation parameters, partitioned control is performed for different regions, solving the problems of low efficiency and inconsistent threshold voltage in traditional initialization methods. This achieves a fast and efficient initialization process, improving the performance and reliability of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 新存科技(武汉)有限责任公司
- Filing Date
- 2026-01-07
- Publication Date
- 2026-06-05
AI Technical Summary
Traditional phase-change memory array initialization methods are inefficient, and differences in line resistance distribution lead to inconsistent threshold voltages, affecting chip yield and reliability.
By acquiring the initial threshold voltage of different regions of the phase-change memory array, and configuring differentiated initialization operation parameters such as operating frequency, voltage, current, number of operations and timing, zoned control is performed for different regions to compensate for differences in line resistance.
It significantly shortens initialization time, improves threshold voltage consistency, expands the memory window, and enhances chip yield and reliability.
Smart Images
Figure CN122157727A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to an initialization method for a phase-change memory array and a phase-change memory. Background Technology
[0002] Three-dimensional phase-change memory (3DPCM) arrays utilize the threshold voltage difference between the SET state (low threshold voltage state) and the RST state (high threshold voltage state) to store data, and the size of the storage window directly affects device performance. Traditional initialization methods require tens of thousands of alternating RST / SET write operations to stabilize the threshold voltage window. However, in actual arrays, due to differences in word line and bit line resistance distribution, memory cells in different regions exhibit threshold voltage dispersion after initialization. Furthermore, as the number of write operations increases, the voltage division effect of line resistance further exacerbates the difference in operating energy between different regions, resulting in different threshold voltage change rates for memory cells in each region, ultimately leading to storage window shrinkage and difficulty in selecting read voltage. Existing technologies mainly suffer from the following problems: 1) Low initialization efficiency, with conventional methods consuming a significant amount of testing time; 2) Deterioration in threshold voltage consistency caused by line resistance differences severely restricts chip yield and reliability. Summary of the Invention
[0003] This application provides an initialization method for a phase-change memory array and a phase-change memory, aiming to solve the problems of poor threshold voltage consistency of memory cells in different regions and the excessive time consumption of traditional initialization methods.
[0004] Firstly, a method for initializing a phase-change memory array includes: Obtain the initial threshold voltage of the memory cells in different regions of the phase change memory array, and calculate the difference between the maximum and minimum values of the initial threshold voltage; If the difference does not exceed a preset threshold, initialization operation parameters are configured for the phase-change memory array; wherein, the initialization operation parameters include at least one of operation frequency, operation conditions, number of operations, and operation timing; if the difference exceeds the preset threshold, the phase-change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions; wherein, the different initialization operation parameters include at least one of different write operation counts, word line voltage, bit line voltage, operation current, and operation time. The phase-change memory array is initialized according to the configured initialization operation parameters.
[0005] Secondly, a phase-change memory is also provided, comprising: At least one phase-change memory array and a processor; The at least one phase-change memory array is communicatively connected to the processor to receive initialization operation instructions and execute the initialization method of the phase-change memory array as described in any one of the first aspects.
[0006] Beneficial effects: This application obtains the initial threshold voltage of memory cells in different regions of a phase-change memory array and determines the uniformity of the threshold voltage distribution based on the difference between the maximum and minimum values, thereby dynamically deciding on the initialization strategy: if the difference does not exceed a preset threshold, initialization operation parameters are configured for the phase-change memory array; if the difference exceeds the preset threshold, the phase-change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions. For example, higher voltage / current or more operation counts can be used to compensate for high-resistance regions, while the operation intensity can be appropriately reduced for low-resistance regions, thereby effectively balancing the threshold voltage distribution of the entire array. By optimizing initialization operation parameters such as operating frequency, operating conditions, number of operations, and operating timing, redundant operations caused by device instability are reduced, significantly shortening the time consumption while ensuring initialization quality.
[0007] Therefore, this application achieves a significant improvement in the consistency of the threshold voltage of the phase change memory array and a substantial reduction in the initialization time by adaptively configuring the initialization operation parameters according to the differences in threshold voltage distribution. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This is a schematic diagram of different positions of the array provided in the embodiments of this application; Figure 2 This is a schematic diagram of the array threshold voltage provided in an embodiment of this application; Figure 3 This is a flowchart of the initialization method for a phase-change memory array provided in an embodiment of this application; Figure 4a This is an RST waveform diagram at a frequency of 600MHz provided in an embodiment of this application; Figure 4b This is an RST waveform diagram at a frequency of 200MHz provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating how extending the write operation delay can accelerate the initialization of the threshold voltage, as provided in an embodiment of this application. Figure 6aThis is a schematic diagram illustrating the setting of different word line voltages provided in an embodiment of this application; Figure 6b This is a schematic diagram illustrating the setting of different bit line voltages provided in the embodiments of this application; Figure 6c This is a schematic diagram illustrating the setting of different operation times provided in the embodiments of this application; Figure 6d This is a schematic diagram illustrating different operating current settings provided in the embodiments of this application; Figure 7 This is a schematic diagram of the distribution of threshold voltage considering the difference in device position provided in the embodiments of this application. Detailed Implementation
[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0011] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0012] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0013] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0014] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0015] The technical terms used in this application are explained.
[0016] Three-dimensional phase change memory (3DPCM): A type of phase change memory chip that is stacked in three dimensions. By integrating multiple layers of memory cells in a vertical direction, it achieves higher storage density in the same area.
[0017] Array: A matrix structure composed of storage units arranged in rows and columns. Each storage unit is addressed by word lines and bit lines, forming a basic network of data storage units.
[0018] Word line: A control line connecting the same row of memory cells. It is used to select the target row and apply operating voltage to achieve read and write operations.
[0019] Bit line: A data line that connects the same column of memory cells. It intersects with word lines to form memory nodes and is used to detect changes in current or voltage to read data status (such as high impedance / low impedance).
[0020] Threshold voltage: The minimum voltage required for a memory cell to switch from a high-resistivity state to a low-resistivity state. Its consistency directly affects read reliability, and process fluctuations can cause this parameter to be distributed discretely.
[0021] Initialization: After power-on, the phase-change memory array is pre-adjusted. By optimizing the write parameters, the threshold voltage of the entire array is made to be more consistent, thus solving the problem of uneven performance caused by process deviations.
[0022] like Figure 1 , Figure 2 As shown, Figure 1The memory array is surrounded by word line drivers and bit line drivers. The regions closer to the word line drivers and bit line drivers (labeled "near end") have lower line resistance, while the regions farther away from the word line drivers and bit line drivers (labeled "far end") have higher line resistance. Due to the difference in line resistance distribution caused by the word line / bit line layout (higher resistance at the far end, lower resistance at the near end), each memory cell exhibits significant threshold voltage dispersion in the initial stage, such as... Figure 2 As shown by the black curve, the threshold voltages of the SET state ("1") / RST state ("0") exhibit a wide distribution at the zeroth write operation, and their dispersion directly reflects the degree of influence of the line resistance voltage division effect. During device use, the material properties of the OTS (threshold switch) (such as element migration) cause the threshold voltage to decrease overall with the increase of write operations. At the same time, the difference in line resistance further causes uneven distribution of operating energy in different regions. That is, the far end has lower operating energy due to the influence of voltage division and current limiting, and the threshold voltage decreases slowly; while the near end has higher operating energy, and the threshold voltage decreases faster. This effect further differentiates the threshold voltages in different regions during the write operation, such as... Figure 2 As shown in the gray curve corresponding to cycles 100 to 20K, the overall distribution continues to widen, while the storage window narrows significantly, making it difficult to select a stable read voltage (e.g., Figure 2 (As shown by the blue vertical line) to reliably distinguish device status.
[0023] The stability and consistency of the array threshold voltage directly affect the initial yield and long-term reliability of the chip. Conventional initialization methods require tens of thousands of write operations to stabilize the threshold voltage, resulting in low efficiency. This application addresses this issue by using differentiated compensation for uneven energy distribution caused by line resistance, enabling the array threshold voltage to converge rapidly and achieve a high degree of consistency. Figure 2 As shown by the red curve in the middle. Based on this, the array can not only obtain a larger available storage window ( Figure 2 (As shown by the variation in the spacing of the green dashed lines), it can also stably maintain an effective read voltage window throughout the entire device lifecycle, thereby significantly improving the operational reliability and product yield of the memory.
[0024] As can be seen from the above, due to the differences in resistance distribution among word lines, bit lines, and vias in the phase-change memory array, the threshold voltage distribution of memory cells in different regions is wide and unstable in the initial state (e.g., Figure 2 (The black line). As the number of write operations increases, the OTS characteristic drift and the line resistance voltage divider effect will further exacerbate the dispersion of the threshold voltage (e.g., the black line). Figure 2 The gray line indicates that the memory window is narrowed, making it difficult to select a stable read voltage to distinguish between SET / RST states. Therefore, it is necessary to initialize the phase-change memory.
[0025] Based on this, this application compensates for resistance differences by configuring differentiated initialization operation parameters, including the number of write operations, write operation parameters, and frequency, so that the threshold voltage quickly converges to a stable and consistent distribution, thereby expanding the storage window, improving yield, and ensuring that the device has reliable data reading capability throughout its entire life cycle.
[0026] On the one hand, such as Figure 3 As shown, this embodiment provides an initialization method for a phase-change memory array, including the following steps: S301, obtain the initial threshold voltage of the storage cells in different regions of the phase change memory array, and calculate the difference between the maximum and minimum values of the initial threshold voltage.
[0027] Understandably, by measuring the initial threshold voltage of memory cells in different regions of the phase-change memory array (the initial threshold voltage characterizes the initial state uniformity of the phase-change memory array), and calculating the difference between the maximum and minimum values of these initial threshold voltages, the initial consistency of the memory cell threshold voltage is reflected. If the difference is too large (e.g., exceeding a preset threshold of 100mV), it indicates that the array state is unstable or there are significant process fluctuations, requiring targeted adjustments to subsequent initialization operation parameters (such as the number of operations, voltage conditions, etc.). Avoiding blind initialization and precisely optimizing operations through quantification of differences reduces ineffective operation time and prevents excessive operation from damaging the device.
[0028] S302, if the difference does not exceed a preset threshold, configure initialization operation parameters for the phase change memory array, wherein the initialization operation parameters include at least one of operation frequency, operation conditions, number of operations, and operation timing.
[0029] Understandably, based on the threshold voltage difference measured in step S301, differentiated initialization operation parameters are configured for the phase-change memory array when the difference does not exceed a preset threshold (e.g., 100mV). The initialization operation parameters include any one of the following (1) to (4): (1) Operating frequency. For example, adjusting the system clock frequency during initialization from 600MHz to 200MHz can extend the effective operating time (from 1.667ns to 5ns), reduce the invalid instruction interval, and improve operating energy efficiency. For example, at 200MHz, the effective RST operating time is longer and the threshold voltage converges faster within the same time.
[0030] (2) Operating conditions. For example, setting word line / bit line voltage / current / time, RST / SET ratio, and the number of power supplies at the far end and near end; for example, using a combination of higher word line voltage and lower bit line voltage can increase RST current and time; voltage / current can also be configured differently according to the line resistance zone (such as near end / far end). For example, the far end has a serious voltage drop due to high line resistance, so a higher voltage compensation is required; the near end reduces the voltage to avoid device damage.
[0031] (3) Number of operations. For example, the number of write operations increases at the far end due to the voltage division of the line resistance, while the number of write operations decreases at the near end to protect the device; different products are dynamically partitioned due to differences in resistance distribution, and the far end (high resistance area) requires more write operations (e.g., 20 times), while the near end (low resistance area) requires fewer (e.g., 10 times); for example, in a multilayer 3D array, the layer with high via resistance requires additional operation operations.
[0032] (4) Operation timing. A traversal write strategy is adopted, prioritizing the completion of the basic operations of the entire array before supplementing the partition counts; all addresses can be traversed first to complete the basic write cycle, and then the counts can be supplemented according to the region; for example, after the device write operation interval is extended, the temperature and state are more stable, and the threshold voltage drop efficiency is improved.
[0033] The purpose of step S302 is to: quickly stabilize the threshold voltage to the target range (e.g., offset <100mV) by configuring the initialization operation parameters, reduce invalid operation time, and improve overall initialization efficiency. Specifically, by configuring parameters in different regions (e.g., increasing the number of operations at the far end and decreasing the voltage at the near end), the influence of line resistance differences is offset, causing the threshold voltages in each region of the array to converge to similar levels; by strengthening the RST operation (e.g., a 10:1 ratio) and frequency adjustment, the phase change material state can be quickly stabilized, and the difference between high and low resistance states can be widened; by using a traversal write timing strategy, invalid operations are reduced, such as reducing to a low-frequency mode of 200MHz to increase the energy of a single operation, thus improving overall efficiency; and by automatically increasing the number of operations or strengthening the operation conditions for wafers with large resistance distribution fluctuations, repeated initialization failures are avoided.
[0034] S303, when the difference exceeds the preset threshold, the phase-change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions; wherein, the different initialization operation parameters include at least one of different write operation counts, word line voltages, bit line voltages, operating currents, and operating times.
[0035] Understandably, when the initial threshold voltage differences between different regions of a phase-change memory (PCM) array are significant (exceeding a preset threshold), it indicates that the threshold voltage distribution across the entire array is uneven. In this case, a zone-based differentiated control strategy is required. Specifically, the entire array is divided into multiple regions, and different initialization operation parameters are configured for the memory cell characteristics of different regions. These parameters include at least one of the following: write operation count, word line voltage, bit line voltage, operating current, and operating time. For example, for high-resistivity regions with high initial threshold voltages, higher operating voltage / current or more write operations can be configured to accelerate the crystallization process of the PCM material. Conversely, for low-resistivity regions with low initial threshold voltages, the operating intensity can be appropriately reduced to avoid performance degradation due to excessive operation. Through this zone-based differentiated control, the performance differences between regions can be compensated specifically, effectively balancing the threshold voltage distribution across the entire array. This significantly shortens the initialization time while ensuring initialization quality, thereby improving the overall performance and reliability of the PCM array.
[0036] In some embodiments, the configuration initialization operation parameters further include: increasing the number of write operations or enhancing the operation conditions for wafers with large resistance distribution fluctuations, based on wafer process variability.
[0037] Understandably, to address the differences in resistance distribution between wafers caused by process fluctuations, this application proposes a scheme for dynamically adjusting initialization parameters: when it is detected that some wafers have large fluctuations in resistance distribution due to process fluctuations, the number of initial write operations for that wafer is increased or the operating conditions (such as word line voltage / bit line voltage / operating current) are enhanced to compensate for the differences in energy transfer caused by uneven resistance distribution. This adaptive adjustment can ensure that high-resistance regions receive sufficient operating energy while avoiding over-operation in low-resistance regions (such as using fewer voltage sources near the edge), ultimately enabling wafers under different process fluctuations to achieve a stable and consistent threshold voltage.
[0038] S304, Perform initialization operation on the phase change memory array according to the configured initialization operation parameters.
[0039] Understandably, based on the configured initialization operation parameters (such as the number of partition operations, voltage / current conditions, and RST / SET ratio), an initialization operation is performed on the phase-change memory array, and the initialization effect is verified by sampling the threshold voltage offset of the memory cells. Specifically, after initialization is performed according to the partitioning strategy, memory cells at different locations in the array are sampled for threshold voltage measurement. If the offset is <100mV (assuming 100mV is a preset value, the preset value can also be set as needed in other embodiments), the initialization is considered complete. Its function is to: quantify the initialization consistency through the threshold voltage offset, solving the threshold dispersion problem caused by process fluctuations; repeat the initialization operation or adjust the parameters (such as near-end voltage reduction, far-end increase) for out-of-range areas (such as offset >100mV) to ensure that the threshold voltage of the entire array converges to a stable state; and combine frequency reduction (such as reducing to 200MHz) and traversal write timing (such as extending the inter-device delay) to increase the energy of a single operation while reducing the total test time, ultimately achieving a larger memory window and stable read voltage.
[0040] In some embodiments, the initialization method of the phase-change memory array further includes: after performing the initialization operation, calculating the offset of the threshold voltage of the memory cell; if the offset is less than a preset value, determining that the initialization is complete; if the offset is greater than or equal to the preset value, adjusting the initialization operation parameters and re-performing the initialization operation.
[0041] Understandably, after initialization, the system samples the threshold voltage of memory cells in different areas of the storage array and performs a preset number of write tests (e.g., 20K times). It then detects the offset of the threshold voltage (i.e., the maximum change in threshold voltage before and after the write operation). If the offset is less than a preset value (e.g., 100mV), it indicates that the threshold voltage of each memory cell has stabilized and converged, and initialization is considered complete. If the offset is not less than the preset value, it indicates that the consistency of the threshold voltage of each memory cell is not met (e.g., possibly due to uneven resistance distribution or process fluctuations). In this case, the initialization parameters need to be dynamically adjusted (e.g., increasing the number of writes to the remote area, optimizing the RST / SET ratio to 10:1, or reducing the frequency to 200MHz to extend the effective operation time, etc.), and the initialization operation needs to be re-executed. Its functions are as follows: to ensure the threshold voltage remains stable during long-term operation through write loop testing; to adjust parameters based on offset feedback to solve initialization failure problems caused by line resistance voltage division (e.g., higher voltage / more cycles required at the far end) or process fluctuations (e.g., additional operation cycles); to avoid blindly repeating operations and optimize only the non-compliant areas, thus shortening the total testing time; and to use a preset value (e.g., 100mV) as a target standard to ensure the consistency of the storage window of the storage array and provide a stable benchmark for subsequent read operations.
[0042] In some specific examples, calculating the offset of the threshold voltage of the storage cell includes: obtaining the detection threshold voltage of the storage cell after the initialization operation is performed; calculating the difference between the detection threshold and the initial threshold, and taking the difference with the largest absolute value as the offset.
[0043] Understandably, the process for determining whether initialization is complete includes: first, sampling the initial threshold voltage of memory cells from different regions of the phase-change memory array (such as near-end, far-end, etc.); after the memory cell performs the initialization operation, obtaining its detection threshold voltage; then, calculating the difference between the detection threshold voltage and the initial threshold voltage of each sampled memory cell, and taking the value with the largest absolute value among all differences as the threshold voltage offset. If the offset is less than a preset value (such as 100mV), initialization is considered complete; if the offset is not less than the preset value, the initialization operation parameters need to be adjusted and the initialization operation repeated, and the detection threshold voltage is sampled again until the target is met. By dynamically detecting the threshold voltage offset, the system evaluates and ensures that the memory cells in each region of the array reach a stable and reliable initialization state.
[0044] In some embodiments, the initialization operation includes an RST operation and a SET operation; the ratio of the RST operation to the SET operation is greater than 1.
[0045] Understandably, RST and SET operations can be used during initialization, with the number of RST operations exceeding the number of SET operations (i.e., the RST to SET ratio is greater than 1, for example, 10:1). The purpose is twofold: RST operations use higher voltage, current, and longer operation time, injecting more energy in a single operation, thus more efficiently reducing the threshold voltage of the phase-change memory cell and allowing it to stabilize quickly; while retaining a small number of SET operations allows for better initialization of the phase-change material through the cycle of RST and SET, ultimately resulting in a larger and more stable memory window for the entire memory array. This strategy significantly improves operational efficiency while ensuring effective initialization.
[0046] In some embodiments, the phase-change memory array includes a near-end region with low resistance to the driver and a far-end region with high resistance to the driver; the far-end region uses at least one different initialization operating parameter compared to the near-end region: more voltage sources, higher word line voltage, lower bit line voltage, and greater operating current.
[0047] Understandably, due to the varying line resistance distribution within a phase-change memory array, the operating energy in the far-end region is reduced during initialization due to voltage division and current limiting effects, resulting in longer paths and higher line resistance. Conversely, the operating energy in the near-end region is excessively high due to lower line resistance. Therefore, this application configures stronger operating conditions for the far-end region, such as using more voltage sources (e.g., three), higher word line voltages, lower bit line voltages, larger operating currents, or longer operating times, to compensate for the energy loss caused by line resistance, effectively reducing and stabilizing the threshold voltage of cells in this region. Meanwhile, milder conditions are used for the near-end region to prevent over-operation and ensure reliability. This differentiated regional control makes the threshold voltage distribution of cells in each region of the array more uniform, thereby improving product yield and memory window stability.
[0048] During the initialization of the 3DPCM array, different operating parameters are set for the near-end and far-end regions. Higher word line voltage and lower bit line voltage are used to enhance the electric field strength; a larger RST operating current is set to ensure sufficient phase transition; a longer RST operating time is configured to guarantee operation completion; and a preset ratio is used as the RST / SET operation ratio, with SET operations reserved to form a complete RST-SET cycle. This differentiated initialization parameter setting effectively compensates for the uneven energy distribution caused by differences in line resistance, and better initializes the phase change material through alternating RST and SET operations, resulting in a wider and more stable storage window.
[0049] Different initialization parameters are configured for different regions to ensure that the threshold voltages of different regions of the phase-change memory array are similar and stable, resulting in better product yield. Due to differences in line resistance, the operating energy varies across regions. Regions with higher line resistance exhibit weaker operating performance due to voltage division and current limiting, while regions with lower line resistance have stronger operating performance. Therefore, a weaker voltage source is used near the region with lower line resistance to ensure device reliability and prevent excessively low threshold voltages. Conversely, more write operations are used at the far end with higher line resistance to significantly reduce the threshold voltage. The number of write operations is adjusted based on the specific line resistance distribution to ensure that the threshold voltages of different regions of the phase-change memory array are similar and stable, leading to better product yield. Different initialization write operation counts are used for regions with different line resistances. In the far end region, due to higher line resistance, more write operations are performed; while in the near end region, with lower line resistance, relatively fewer write operations are performed. This differentiated write operation count setting based on line resistance distribution ensures that the threshold voltages of different regions of the 3DPCM array tend to be similar and stable during initialization, thereby improving product yield.
[0050] This application can also divide the phase-change memory array into multiple different initialization regions based on the physical size, resistance distribution characteristics, and control capabilities of the peripheral circuits. Each region can be independently configured with differentiated initialization parameter combinations, including but not limited to: word line voltage, bit line voltage, operating time, and operating current; these parameters are set to increase sequentially from the near-end region to the far-end region. This regional control scheme can more accurately compensate for the uneven energy transfer caused by process deviations and differences in wire resistance, thereby achieving optimal threshold voltage consistency initialization at the array level.
[0051] In some embodiments, the configuration initialization operation parameters further include: reducing the operation frequency from the normal operation frequency to a preset initialization frequency.
[0052] During initialization, if the write operation designed by the system already uses the maximum number of semaphore commands, the effective operation time can be extended within the same time frame by reducing the system frequency. For example, if the product's normal operating frequency is 600MHz (e.g., ...), ... Figure 4a As shown), each instruction cycle is 1.667ns; during initialization, the frequency is reduced to 200MHz (assuming the preset initialization frequency is 200MHz, such as...). Figure 4b As shown (indicated), the instruction cycle is increased to 5ns. Although the number of write operations is reduced to one-third in the same time, the instruction interval is reduced. For example, a single 200MHz RST operation has a longer effective operation time than three 600MHz RST operations, thus providing more efficient operation energy. Therefore, reducing the operation frequency from the normal test frequency to the preset initialization frequency can optimize the energy transfer efficiency of write operations. The frequency setting to be protected in this application is not limited to this and can be set according to actual needs.
[0053] like Figure 5 As shown, Figure 5 This study demonstrates that extending the write operation delay significantly accelerates the initialization process of the threshold voltage in phase-change memory (PCM) cells. Specifically, under the same operating conditions, a write operation with a 5-second delay (red line) exhibits a significantly faster rate of threshold voltage decrease with increasing cycle count compared to a write operation with a 1-microsecond delay (blue line). This difference remains stable across MM (far end), NN (near end), and different process deviation levels (3 ps, 3 sigma), indicating that appropriately increasing the operation delay can inject more effective energy into the PCM, thereby more efficiently inducing the cell to transition from a high-resistivity state to a stable state and significantly shortening the number of cycles required to achieve the target threshold voltage. Therefore, by optimizing the operation timing (e.g., increasing the delay from 1 microsecond to 5 seconds), initialization efficiency can be significantly improved while maintaining unchanged operating conditions, accelerating the uniformization process of the entire array's threshold voltage and providing crucial experimental evidence for reducing initialization time.
[0054] In some other embodiments, the initialization operation includes: The phase change memory array is traversed with the minimum number of write operations; additional write operations are added according to the needs of each region, and multiple memory cells are traversed in each operation to ensure that the temperature distribution of the phase change memory array is uniform.
[0055] In another specific example, the step of supplementing additional write operations according to the needs of each region, with each operation traversing multiple memory units, includes: successively reducing the range of the continued write loop operation in the direction away from the word line and away from the bit line, and finally supplementing the additional write loop count for the near-end region.
[0056] Understandably, in the initialization operation, if a system-side approach is adopted where the required number of write operations is completed for one address before moving to the next address—that is, operating address by address when the number of write operations differs across regions—although the delay between write operations for a single device is short, the device temperature and state become unstable after each write operation, leading to unstable write operation results and low threshold voltage drop efficiency. This application, during the initialization operation, first traverses all memory cells of the phase-change memory array with the minimum number of write operations, and then supplements the number of additional write operations according to the needs of each region, traversing multiple memory cells each time. This traversal write operation method has significant advantages. Figures 6a to 6d The traversal write operation method shown initially iterates through all addresses. Then, it progressively narrows the write operation range based on the current region, writing along word lines and bit lines, handling different regions specifically. Finally, it adds up the extra write operations near the end, summing them up to achieve the desired overall write cycle count. Figure 6d The proposed solution involves first initializing all memory cells, then supplementing operations based on regional needs, with each operation traversing multiple memory cells. This effectively increases the latency between two write operations on a single device, allowing sufficient time for the device to stabilize, a significant advantage compared to the unstable state resulting from rapid address-by-address operations. Furthermore, the overall time consumption remains unchanged because stabilization is achieved through a well-planned timing sequence of traversal and supplementary operations, rather than waiting slowly for each address operation. Simultaneously, since each operation traverses multiple memory cells, the temperature distribution of the phase-change memory array becomes more uniform, preventing localized overheating or uneven heat dissipation from negatively impacting device state and write operation performance. This ultimately results in higher threshold voltage reduction efficiency and effectively saves testing time.
[0057] like Figure 7 As shown, Figure 7This demonstrates whether the impact of device location differences on the uniformity of the threshold voltage (Vt_) distribution is considered during initialization. The effect is presented by comparing the closeness of the data distributions under the two strategies to the theoretical normal distribution: the red scatter line (NOED) represents the threshold voltage distribution after initializing all locations with the same number of cycles, which deviates significantly from the normal distribution curve, indicating poor parameter consistency; the blue scatter line (BYED) represents the threshold voltage distribution measured after differentiating the number of cycles based on the device location (e.g., near end, far end), and its scatter points closely follow the diagonal of the theoretical normal distribution. Therefore, Figure 7 It was verified that giving different number of loops according to position during initialization can significantly improve the uniformity and stability of the threshold voltage distribution of the entire array, making it closer to the ideal normal distribution, thereby improving the consistency of device parameters and product yield.
[0058] In other embodiments, under the same operating conditions, device power is affected by line resistance; locations with higher line resistance require more operations, and different array sizes, structures, or line resistance materials will have different resistance distributions. For different array situations, the required operating conditions or number of operations for initialization at different array locations can be determined by pre-estimating the line resistance distribution. This allows for achieving a more optimal threshold voltage after array initialization. For example, differentiated initialization operation parameters can be configured based on partitions, thereby solving the problem of poor threshold voltage consistency caused by uneven array resistance distribution. Simultaneously, initialization efficiency is optimized, avoiding the drawbacks of traditional initialization methods that may result in excessively long processing times due to not considering resistance distribution differences.
[0059] In other specific examples, for 3DPCM arrays, the word line and bit line routing in each layer of the multilayer structure will also differ. Simultaneously, the via resistance of the vertical conductive channels in the multilayer structure will also vary, and its impact must be considered. Because the multilayer stacked structure leads to differences in word line / bit line lengths across different layers (shorter traces on upper layers, longer traces on lower layers), and the resistance distribution of vertical vias (TSVs) increases significantly with process errors and interlayer spacing, these factors further exacerbate the resistance non-uniformity in different regions of the array. If uniform initialization parameters are applied, it will result in overstressing of upper-layer cells and insufficient energy in lower-layer cells. Therefore, it is necessary to compensate for the resistance gradient differences through layered and zoned control.
[0060] On the other hand, this embodiment provides a phase-change memory, including: at least one phase-change memory array and a processor; the at least one phase-change memory array is communicatively connected to the processor to receive initialization operation instructions and execute the initialization method described in any of the above embodiments; the memory stores a computer program, which, when executed by the processor, implements the initialization method of the phase-change memory array as described in any of the above embodiments.
[0061] This embodiment also provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to perform the steps of any of the methods in the above embodiments.
[0062] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.
[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0064] The foregoing has provided a detailed description of the initialization method for a phase-change memory array and the phase-change memory provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. An initialization method for a phase-change memory array, characterized in that, include: Obtain the initial threshold voltage of the memory cells in different regions of the phase change memory array, and calculate the difference between the maximum and minimum values of the initial threshold voltage; If the difference does not exceed a preset threshold, initialization operation parameters are configured for the phase-change memory array; wherein, the initialization operation parameters include at least one of operation frequency, operation conditions, number of operations, and operation timing; if the difference exceeds the preset threshold, the phase-change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions; wherein, the different initialization operation parameters include at least one of different write operation counts, word line voltage, bit line voltage, operation current, and operation time. The phase-change memory array is initialized according to the configured initialization operation parameters.
2. The initialization method for a phase-change memory array according to claim 1, characterized in that, If the difference exceeds the preset threshold, the phase-change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions, including: Obtain the actual test values of the resistance of the word lines, bit lines and vias of the phase-change memory array in order to calculate the resistance distribution parameters; Based on the resistance distribution parameters, the resistance differences in different regions of the phase change memory array are determined; Based on the resistance difference, the phase change memory array is divided into multiple regions, and different initialization operation parameters are configured for different regions.
3. The initialization method for a phase-change memory array according to claim 2, characterized in that, The phase-change memory array includes a near-end region with low resistance to the driver and a far-end region with high resistance to the driver; the far-end region uses at least one different initialization operation parameter compared to the near-end region: more voltage sources, higher word line voltage, lower bit line voltage, greater operating current, or longer operating time.
4. The initialization method for a phase-change memory array according to any one of claims 1 to 3, characterized in that, The initialization operation includes: Traverse all memory cells of the phase-change memory array with the minimum number of write operations; Additional write operations are performed based on the needs of each region, with each operation traversing multiple storage cells to ensure a uniform temperature distribution in the phase-change memory array.
5. The initialization method for a phase-change memory array according to claim 4, characterized in that, The step of supplementing additional write operations according to the needs of each region, with each operation traversing multiple storage units, includes: The write loop operation range is reduced sequentially in the directions away from the word line and away from the bit line, and finally the extra write loop count in the near-end region is added.
6. The initialization method for a phase-change memory array according to any one of claims 1 to 3, characterized in that, The initialization operation includes an RST operation and a SET operation; the ratio of the RST operation to the SET operation is greater than 1.
7. The initialization method for a phase-change memory array according to any one of claims 1 to 3, characterized in that, The configuration initialization operation parameters also include: Based on the variability of wafer process, the number of write operations or the operating conditions are increased for wafers with large resistance distribution variability.
8. The initialization method for a phase-change memory array according to claim 1, characterized in that, Also includes: After the initialization operation is performed, the offset of the threshold voltage of the memory cell is calculated; If the offset is less than a preset value, the initialization is considered complete. If the offset is greater than or equal to the preset value, the initialization operation is re-executed after adjusting the initialization operation parameters.
9. The initialization method for a phase-change memory array according to claim 8, characterized in that, The calculation of the threshold voltage offset of the memory cell includes: Obtain the detection threshold voltage after the storage unit performs the initialization operation; Calculate the difference between the detection threshold and the initial threshold, and take the difference with the largest absolute value as the offset.
10. A phase-change memory, characterized in that, include: At least one phase-change memory array and a processor; The at least one phase-change memory array is communicatively connected to the processor to receive initialization operation instructions and execute the initialization method of the phase-change memory array as described in any one of claims 1-8.