D-t hybrid multi-port dc fault current limiter topology structure and control method thereof
By using a hybrid topology of thyristors and diodes and the application of IGBTs, the problems of high cost and poor stability of existing DC fault current limiters are solved, achieving economical and efficient fault current limiting and rapid recovery.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TIANJIN UNIV
- Filing Date
- 2026-04-24
- Publication Date
- 2026-06-05
AI Technical Summary
Existing DC fault current limiters are expensive to manufacture due to the use of a large number of fully controlled power electronic devices, and the long-term investment or malfunction of the current-limiting reactor affects the stability of the system.
It adopts a multi-port topology that combines thyristors and diodes, combined with insulated gate bipolar transistors (IGBTs), to reduce the number of expensive components, and achieves rapid fault isolation and recovery through intelligent discrimination methods.
While ensuring current limiting capabilities, it reduces manufacturing costs, improves system stability and economy, and avoids interference with normal operation.
Smart Images
Figure CN122159153A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of DC transmission / distribution / microgrids, and in particular relates to a DC fault current limiter with multi-terminal current limiting capability suitable for multi-terminal DC grids. Background Technology
[0002] Flexible DC systems possess significant technological advantages in large-scale renewable energy base transmission and grid connection, as well as flexible interconnection of asynchronous power grids, representing a typical form of new power system development. Against this backdrop, multi-terminal flexible DC grids, with DC lines interconnected via DC buses, offer high power supply reliability and have thus become a major development direction in DC transmission and distribution. While flexible DC systems boast substantial technological advantages, they also suffer from large fault current surges and weak overcurrent tolerance in core equipment. With the continuous increase in system scale and transmission capacity, effective fault current limiting measures are urgently needed to ensure safe equipment operation and reliable fault ride-through of the system.
[0003] Currently, the typical fault current limiting method in flexible DC systems is to directly install current-limiting reactors at the converter station outlet or both ends of the line. However, the extensive installation of current-limiting reactors in DC transmission systems will significantly reduce the system's transient response speed and deteriorate the system's operational stability. At the same time, the presence of current-limiting reactors will also significantly increase the energy consumption demand of MOVs, leading to a significant extension of the fault current clearing time, and thus placing higher demands on the capacity of MOVs.
[0004] To address the aforementioned issues, scholars both domestically and internationally have proposed various multi-port DC fault current limiters, aiming to effectively switch the current-limiting inductor during different stages of system operation and fault conditions, thereby eliminating its adverse effects. However, existing topologies employ a large number of IGBT thyristors, resulting in high device costs and making it difficult to balance current-limiting performance with cost-effectiveness. Therefore, while ensuring sufficient current-limiting capability, improvements to the topology can reduce the number of thyristors and energy-consuming resistors, thereby lowering investment costs. Summary of the Invention
[0005] This invention aims to solve the problems of high manufacturing costs caused by the use of a large number of fully controlled power electronic devices in existing DC fault current limiters, and the impact on system stability caused by long-term operation of current-limiting reactors or device malfunctions. By implementing a multi-port topology with hybrid thyristors and diodes and a matching control design, the invention significantly reduces the number of expensive devices while ensuring current limiting and reliable shutdown capabilities, and avoids interference with normal operation, thereby achieving a balance between economy and reliability.
[0006] To achieve the aforementioned objectives, the present invention provides the following technical solution: In a first aspect, the present invention proposes a DT hybrid multi-port DC fault current limiter, including a current limiting branch, an energy dissipation branch and a control branch; The current-limiting branch includes n A current-limiting inductor L 1, L 2, ..., L n The n One end of each current-limiting inductor is connected to the DC bus, and the other ends are connected to... n One DC line; The energy-consuming branch includes a first energy-consuming branch and a second energy-consuming branch; The first energy-consuming branch is the first thyristor valve group. T 1 and the first energy-consuming resistor R 1. It is connected in series, and its forward conduction direction is from the DC bus to the line side; The second energy-consuming branch is the second thyristor valve group. T 2 and the second energy-consuming resistor R The two are connected in series, with their forward conduction direction pointing from the line side to the DC bus; In this circuit, an insulated gate bipolar transistor (IGBT) is connected in series in the first energy-consuming branch and / or the second energy-consuming branch to actively interrupt the circuit current during the fault clearing phase. The control branch includes a first control branch and a second control branch; The first control branch is an upper diode valve assembly, which includes n A first diode sub-valve group connected in parallel D 11 , D 12 , ..., D 1n Each of the first diode sub-valve groups is composed of multiple unidirectional diodes connected in series; the common anode of the upper diode valve group is connected to the first energy-consuming branch and the first energy-consuming resistor. R 1. One end connected, its n Each negative terminal is connected to the corresponding n One DC line; The second control branch is a lower diode valve assembly, which includes n A second diode sub-valve group connected in parallel D 21 , D 22 , ..., D 2n Each second diode sub-valve group is composed of multiple unidirectional diodes connected in series; the n anodes of the lower diode valve group are respectively connected to the corresponding... n A DC line, the common cathode of which is connected to one end of the second energy-consuming branch that is connected to the second energy-consuming resistor R2.
[0007] Furthermore, it is applicable to flexible DC transmission systems with a DC bus and multiple DC lines; when a fault occurs on the DC bus or any DC line, at least two of the current-limiting inductors are connected to the fault current path to jointly suppress the fault current.
[0008] Furthermore, the insulated gate bipolar transistor (IGBT) connected in series in the power dissipation branch is configured to perform a turn-off operation during the fault clearing phase when the current flowing through its power dissipation branch decays to a preset level, thereby forcibly cutting off the sustaining current of the first thyristor valve group T1 and / or the second thyristor valve group T2 to ensure reliable turn-off.
[0009] Furthermore, when a DC line fault occurs and its corresponding DC circuit breaker (DCCB) trips: The current-limiting inductor corresponding to the faulty line forms a first freewheeling energy dissipation circuit with the second energy dissipation branch via the corresponding second diode sub-valve group in the second control branch. The current-limiting inductor corresponding to the non-faulty line forms a second freewheeling energy dissipation circuit with the first energy dissipation branch via the first diode sub-valve group in the first control branch.
[0010] Secondly, the present invention provides a method for controlling the DT hybrid multi-port DC fault current limiter described in any one of the claims, comprising the following steps: Monitoring steps: Monitor the current of each DC line in real time; Start-up judgment step: When the absolute value of any monitored current change exceeds a preset current change threshold, a timer is started; Fault determination and triggering steps: If a DC circuit breaker (DCCB) trip signal is received before the timer reaches the first preset duration, a DC fault is determined, and a first trigger signal is generated to control the IGBT and the thyristor valve group corresponding to the fault current direction to conduct; if no DC circuit breaker trip signal is received after the first preset duration, a system disturbance is determined, and a second trigger signal is generated to control the IGBT and the first thyristor valve group to conduct. T 1 and the second thyristor valve group T 2. Conduction; Recovery step: After the thyristor valve group is turned on, after a second preset time, the connection to the first thyristor valve group is removed. T 1 and the second thyristor valve group T The trigger signal 2 is activated, and the insulated gate bipolar transistor (IGBT) is turned off, restoring the fault current limiter to its initial state.
[0011] Thirdly, the present invention proposes an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the control method of the DT hybrid multi-port DC fault current limiter.
[0012] Fourthly, the present invention proposes a non-transitory computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the control method of the DT hybrid multi-port DC fault current limiter.
[0013] As can be seen from the technical solution provided by the present invention above, compared with the existing multi-port DC fault current limiters, the DT hybrid multi-port DC fault current limiter proposed in this invention has the following main advantages: 1) Compared to existing multi-port DC fault current limiters, the DT hybrid multi-port DC fault current limiter of this invention uses a hybrid configuration of thyristors and diodes to replace a large number of pure thyristors, and optimizes multiple energy-consuming resistors into two energy-consuming resistors. While maintaining the overall current-limiting capability, it can effectively reduce the manufacturing cost of the current limiter.
[0014] 2) Compared with existing multi-port DC fault current limiters, the invented DT hybrid multi-port DC fault current limiter uses an IGBT to replace the thyristor, which can ensure that the current in the circuit formed by the current limiting inductor and the energy dissipation resistor is completely cleared during the fault clearing stage, thereby ensuring that the current limiter can be restored to the initial current limiting state in a timely and reliable manner, and prepare for dealing with subsequent faults.
[0015] 3) An intelligent discrimination method based on local current surges and DC circuit breaker tripping signals for timing interlocking is proposed. This method can quickly and accurately distinguish between real short-circuit faults and normal system power flow fluctuations. It can achieve rapid coordination with fault isolation, maximizing the current-limiting effect, while avoiding unnecessary impact on normal system operation. This essentially transforms the "long-term series-connected current-limiting inductor" into an "energy absorption device that is instantaneously supplied on demand," fundamentally reducing the negative impact on system transient stability and dynamic performance, and improving the overall operational stability of the power grid. Attached Figure Description
[0016] Figure 1 This invention relates to a topology of a DT hybrid multi-port DC fault current limiter.
[0017] Figure 2 The diagram shows the working principle of a DT hybrid multi-port DC fault current limiter of the present invention when a fault occurs on the line: (a) fault current limiting stage, (b) fault current clearing stage, (c) fault recovery stage, and (d) non-faulty line returning to normal operation stage.
[0018] Figure 3 This is a flowchart of a control method for a DT hybrid multi-port DC fault current limiter according to the present invention. Detailed Implementation
[0019] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0020] like Figure 1 As shown, the fault current limiter includes a current limiting branch, an energy dissipation branch, and a control branch. The current limiting branch is connected to the DC bus side (converter station port side or line port side), the energy dissipation branch includes a first energy dissipation branch and a second energy dissipation branch, and the control branch includes a first control branch and a second control branch.
[0021] for n For the end system, the fault current limiter is equipped with... n Each port has a rate-limiting branch. L 1, L 2, ..., L n Diode valve groups are connected to their respective control branches. D 1n , D 2n Connected.
[0022] The energy-consuming branch consists of a unidirectional thyristor group. T 1 and energy-consuming resistor R The first branch consists of a series connection, with the current direction set from the DC bus to the line side; the second branch consists of a unidirectional thyristor group. T 2 and energy-consuming resistor R The circuit consists of two series connections, with the current direction set from the line side to the DC bus side. Furthermore, in one of the power-consuming branches, an Insulated Gate Bipolar Transistor (IGBT) replaces the original thyristor to ensure that the loop current formed by this branch and the current-limiting inductor can be completely cut off during the fault clearing phase.
[0023] The first control branch is the upper diode valve group, by n’ The upper diode valve group consists of several diode valves connected in parallel, each formed by multiple unidirectional diodes connected in series. The common anode of the upper diode valve group is connected to the first power consumption branch, and each cathode is connected to its corresponding circuit. The second control branch is the lower diode valve group, whose structure is symmetrical to the upper diode valve group, and also consists of... n’ The system consists of several parallel diode valve groups, each composed of multiple unidirectional diodes connected in series. The anodes of each diode valve group are connected to their respective circuits, and their common cathode is connected to the second power-dissipating branch.
[0024] like Figure 2 The diagram illustrates the working principle of the fault current limiter of this invention when a fault occurs on the line.
[0025] Figure 2 (a) illustrates the fault current limiting process of the current limiter. During normal system operation, the power consumption branch and control branch are not engaged; at this time, each current-limiting inductor... L 1, L 2, ..., L n By connecting it directly in series in the corresponding DC line, the current limiter can limit the fault current without delay after a DC fault occurs.
[0026] Figure 2 (b) is the fault current clearing stage for the current limiter. The faulty line (e.g.) line 2) After the DC circuit breaker (DCCB) completes its commutation interruption, the fault current is transferred to its metal oxide voltage limiter (MOV) for energy dissipation, at which point the fault current reaches its peak value. Simultaneously, energy is supplied to the corresponding thyristor valve group in the current limiter. T 1 / T 2. The IGBT sends a trigger signal, causing the freewheeling current of each current-limiting inductor (as shown by the blue and purple dashed lines in the figure) to form a loop inside the current limiter, and to form a circuit with the first energy-consuming branch or the second energy-consuming branch respectively.
[0027] Figure 2 (c) is the fault recovery phase of the current limiter. At this time, the current-limiting inductor of the faulty line (such as...) L 2) Current-limiting inductors for non-faulty lines (such as...) L 1. L 3) Passing through the corresponding control branch and energy-consuming resistor R1 respectively, R 2. A freewheeling energy dissipation loop is formed, gradually dissipating the energy stored in the inductor. This process can be completed within the time required for system insulation recovery (e.g., 200~300ms). As the energy dissipates, the loop current gradually decreases to a lower level (tens to hundreds of milliamps).
[0028] To ensure reliable turn-off after current decay, this invention incorporates an IGBT connected in series in the energy-consuming branch. When the current drops below a level insufficient to maintain thyristor conduction, the IGBT can actively turn off the remaining freewheeling current, ensuring reliable device reset.
[0029] Figure 2 (d) illustrates the rapid recovery process of a normal line. For non-faulty lines, the converter station can continue to transmit power to the DC line through the already conducting thyristor valve group, allowing the current to quickly recover to a steady state, thereby ensuring the rapid recovery of the intact network after the faulty line is isolated.
[0030] like Figure 3The control method of the DT hybrid multi-port DC fault current limiter is shown, which specifically includes the following steps: S1. When the system is running normally and stably, IGBT1 and IGBT2 are not conducting, and the thyristor group... T 1 and T Both are in the off state, and the current flows through each current-limiting inductor; S2, The control process begins with real-time monitoring of each DC line. line 1~ linen Current; S3. If the change in current of any DC line satisfies | i dc_n |> i set Start the timer; S4. After the timer starts, if the current limiter reaches the preset time... t If a trip signal is received from the corresponding line DCCB within 1 hour, it is determined to be a DC fault. The faulty line DCCB trips and sends a conduction signal to the IGBT of the current limiter and the corresponding thyristor group. S5, if in t If no trip signal is received within 1 hour, it is determined to be a power flow fluctuation, and the timer expires. t At time 1, a conduction signal is also issued.
[0031] S6. Delay after the thyristor group is turned on. t 2. Remove T 1. The trigger signal is sent to the IGBT and a turn-off signal is sent to the current limiter to restore it to its initial state.
[0032] The present invention proposes an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the control method of the DT hybrid multi-port DC fault current limiter.
[0033] This invention proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the control method of the DT hybrid multi-port DC fault current limiter.
[0034] In summary, this invention employs a hybrid configuration of diode valve groups and thyristors, supplemented by key IGBTs. While ensuring multi-port collaborative current limiting and reliable turn-off capabilities, it significantly reduces the number of required control devices, offering advantages such as low cost, high reliability, and prevention of malfunctions.
Claims
1. A DT hybrid multi-port DC fault current limiter, characterized in that, This includes current-limiting branches, energy-consuming branches, and control branches; The current-limiting branch includes n A current-limiting inductor L 1, L 2, ..., L n The n One end of each current-limiting inductor is connected to the DC bus, and the other ends are connected to... n One DC line; The energy-consuming branch includes a first energy-consuming branch and a second energy-consuming branch; The first energy-consuming branch is the first thyristor valve group. T 1 and the first energy-consuming resistor R 1. It is connected in series, and its forward conduction direction is from the DC bus to the line side; The second energy-consuming branch is the second thyristor valve group. T 2 and the second energy-consuming resistor R The two are connected in series, with their forward conduction direction pointing from the line side to the DC bus; In this circuit, an insulated gate bipolar transistor (IGBT) is connected in series in the first energy-consuming branch and / or the second energy-consuming branch to actively interrupt the circuit current during the fault clearing phase. The control branch includes a first control branch and a second control branch; The first control branch is an upper diode valve assembly, which includes n A first diode sub-valve group connected in parallel D 11 , D 12 ,..., D 1n Each of the first diode sub-valve groups is composed of multiple unidirectional diodes connected in series; the common anode of the upper diode valve group is connected to the first energy-consuming branch and the first energy-consuming resistor. R 1. One end connected, its n Each negative terminal is connected to the corresponding n One DC line; The second control branch is a lower diode valve assembly, which includes n A second diode sub-valve group connected in parallel D 21 , D 22 ,..., D 2n Each second diode sub-valve group is composed of multiple unidirectional diodes connected in series; the n anodes of the lower diode valve group are respectively connected to the corresponding... n A DC line, the common cathode of which is connected to one end of the second energy-consuming branch that is connected to the second energy-consuming resistor R2.
2. The DT hybrid multi-port DC fault current limiter according to claim 1, characterized in that, It is applicable to flexible DC transmission systems with DC bus and multiple DC lines; when a fault occurs on the DC bus or any DC line, at least two of the current-limiting inductors are connected to the fault current path to jointly suppress the fault current.
3. The DT hybrid multi-port DC fault current limiter according to claim 1, characterized in that, The insulated gate bipolar transistor (IGBT) connected in series in the power dissipation branch is configured to perform a turn-off operation during the fault clearing phase when the current flowing through its power dissipation branch decays to a preset level, thereby forcibly cutting off the sustaining current of the first thyristor valve group T1 and / or the second thyristor valve group T2 to ensure reliable turn-off.
4. The DT hybrid multi-port DC fault current limiter according to any one of claims 1 to 3, characterized in that, When a fault occurs in a DC line and its corresponding DC circuit breaker (DCCB) trips: The current-limiting inductor corresponding to the faulty line forms a first freewheeling energy dissipation circuit with the second energy dissipation branch via the corresponding second diode sub-valve group in the second control branch. The current-limiting inductor corresponding to the non-faulty line forms a second freewheeling energy dissipation circuit with the first energy dissipation branch via the first diode sub-valve group in the first control branch.
5. A control method for a DT hybrid multi-port DC fault current limiter according to any one of claims 1 to 4, characterized in that, Includes the following steps: Monitoring steps: Monitor the current of each DC line in real time; Start-up judgment step: When the absolute value of any monitored current change exceeds a preset current change threshold, a timer is started; Fault determination and triggering steps: If a DC circuit breaker (DCCB) trip signal is received before the timer reaches the first preset duration, a DC fault is determined, and a first trigger signal is generated to control the IGBT and the thyristor valve group corresponding to the fault current direction to conduct; if no DC circuit breaker trip signal is received after the first preset duration, a system disturbance is determined, and a second trigger signal is generated to control the IGBT and the first thyristor valve group to conduct. T 1 and the second thyristor valve group T 2. Conduction; Recovery step: After the thyristor valve group is turned on, after a second preset time, the connection to the first thyristor valve group is removed. T 1 and the second thyristor valve group T The trigger signal 2 is activated, and the insulated gate bipolar transistor (IGBT) is turned off, restoring the fault current limiter to its initial state.
6. An electronic device, comprising: The device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the control method for the DT hybrid multi-port DC fault current limiter according to claim 5.
7. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements a control method for controlling the DT hybrid multi-port DC fault current limiter according to claim 5.