A processing system and method based on a high-speed adaptive digital filter

Abstract

The application discloses a processing system and method based on a high-speed adaptive digital filter, relates to the technical field of filter control, and receives a phase error signal of a front-stage phase discriminator, accumulatively calculates the phase error signal, and generates a frequency deviation accumulation value; proportionally amplifies the phase error signal to obtain an instantaneous phase adjustment value; combines the frequency deviation accumulation value and the instantaneous phase adjustment value to obtain a combined signal; secondarily accumulatively operates the combined signal to obtain an initial phase control code; judges the confidence degree according to the phase error signal, filters instantaneous noise, dynamically adjusts the total system gain by slidingly intercepting the effective bit width of the initial phase control code according to the judgment result, and finally outputs an optimized phase control code, so that the jitter of recovered data and clock is improved.

Description

Technical Field

[0001] This invention relates to the field of filter control technology, and in particular to a processing system and method based on a high-speed adaptive digital filter. Background Technology

[0002] In serial communication systems, high-speed signals are attenuated and affected by signal integrity issues such as interference after being transmitted through the channel. The receiving end needs to correctly sample and decode the input signal and recover the clock signal with the same frequency as the signal base frequency. This function is implemented by the clock data recovery circuit (CDR). In the phase interpolation type CDR structure, the digital filter (DLF) determines the frequency offset tracking range of the receiving system and is related to the jitter performance of the recovered data clock and the stability of the system.

[0003] Existing digital filters have the following drawbacks: when ambient temperature, power supply voltage (PVT), and input signal rate change, a fixed gain cannot maintain its optimal state, resulting in reduced system jitter tolerance and increased bit error rate; frequency offset tracking capability is limited. The frequency offset tracking capability of a CDR system depends on the number of bits of the accumulator in the DLF integration path. Once the frequency offset is too large, causing the accumulator to exceed its saturation value, the output will be incorrect, which will lead to the CDR system losing lock. In order to increase the tracking capability, the traditional approach can only passively increase the number of bits of the accumulator, resulting in a sharp increase in hardware resource consumption. Summary of the Invention

[0004] The technical problem solved by this invention is that a fixed gain cannot be maintained in the optimal state, and the frequency offset tracking capability is limited.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] Firstly, a processing system based on a high-speed adaptive digital filter includes an integration path module, a proportional path module, a combination module, an output accumulator module, and a total gain control module.

[0007] The integration path module is used to receive the phase error signal from the front-end phase detector, accumulate and calculate the phase error signal, and generate a cumulative frequency deviation value.

[0008] The proportional path module is used to proportionally amplify the phase error signal to obtain the instantaneous phase adjustment value;

[0009] The combination module is used to perform a combination operation on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal;

[0010] The output accumulator module is used to perform a second accumulation operation on the combined signal to obtain an N-bit initial phase control code;

[0011] The total gain control module is used to determine the confidence level and filter instantaneous noise based on the phase error signal, and dynamically adjust the total gain of the system by sliding and truncating the effective bit width of the N-bit initial phase control code according to the determination result, and finally output the optimized phase control code.

[0012] Preferably, the integration path module includes a first gain unit and a mode control unit;

[0013] The first gain unit is used to receive the phase error signal in real time. By performing high-bit extension processing of left shift, an amplified phase error signal is generated. The amplified phase error signal at the current moment is superimposed with the accumulated value saved at the previous moment using the first accumulator to obtain the accumulated result value. The first accumulator also includes a set terminal for presetting a non-zero initial frequency value during the startup phase.

[0014] The phase error signal is a discrete Bang-Bang type code, including phase-leading code, phase-lag code and no effective transition code. The phase error signal does not contain phase error amplitude information.

[0015] The accumulated result value output by the first accumulator is truncated by bit width, discarding the low-order data and retaining the high-order data, and the obtained high-order data is used as the frequency deviation accumulated value.

[0016] Preferably, the mode control unit is used to monitor the accumulated result value in real time and switch the mode state according to the accumulated result value:

[0017] When the absolute value of the accumulated result is less than the preset saturation threshold, it is in frequency tracking mode; when the absolute value of the accumulated result is greater than or equal to the preset saturation threshold, it switches to frequency holding mode and forcibly locks the output clamp at the extreme point.

[0018] When the output clamp is forcibly locked at the extreme point, it continuously responds to the reverse error signal dynamically. When the reverse error signal is received and the accumulated result value is corrected so that the absolute value of the accumulated result value is less than the preset saturation threshold, it exits the frequency holding mode and returns to the frequency tracking mode.

[0019] Preferably, the proportional path module includes a second gain unit, which is used to perform left shift and low-bit zero-padding operation on the phase error signal to obtain an instantaneous phase adjustment value;

[0020] By using left-shifted high-bit sign extension, the phase error signal is mapped into multi-bit wide data, and the multi-bit wide data is output as an instantaneous phase adjustment value, which does not contain the accumulated information of historical errors.

[0021] Preferably, the mode states include frequency tracking mode, frequency hold mode, and no frequency offset mode;

[0022] The frequency tracking mode is used to maintain non-interference with the accumulated result value, allowing the first accumulator to perform addition and subtraction operations normally according to the phase error signal of each clock cycle, and pass the result through to the subsequent stage;

[0023] The frequency hold mode is used to activate the internal clamping logic, cut off the normal accumulation feedback path, and force the output to be locked at the corresponding positive or negative extreme value.

[0024] The no-frequency-offset mode is used to lock the ENS signal to be valid, and then detect frequent changes in the sign bit within a preset monitoring window. It determines that there is no systematic frequency offset in the current environment and forcibly clears the cumulative result value output by the integration path to zero.

[0025] Preferably, the combination module is used to perform a combined operation on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal;

[0026] Receive the cumulative frequency deviation value of the integral path module and the instantaneous phase adjustment value of the proportional path module;

[0027] The frequency deviation accumulation value and instantaneous phase adjustment value are aligned by low bit and sign extension by hardware connection logic to obtain an aligned signal group. The signal group is then subjected to binary two's complement addition by the first adder to obtain the intermediate operation result.

[0028] Based on the rising edge of the master clock, the intermediate calculation results are sampled and latched using the second flip-flop group to obtain the combined signal.

[0029] Preferably, the output accumulator module includes:

[0030] The system receives a combined signal and uses it as the reference input for secondary accumulation. It constructs an accumulation feedback loop using a second adder and a third flip-flop group. The combined signal is input into the accumulation feedback loop to perform the operation. In each clock cycle, the second adder adds the current combined signal to the value of the previous clock cycle stored in the third flip-flop group using binary two's complement to obtain the output result of the second adder. The output result is then latched by the third flip-flop group to generate an N-bit initial phase control code.

[0031] Preferably, the total gain control module includes a confidence judgment unit and an adaptive control unit;

[0032] The confidence judgment unit is used to monitor the phase error signal in real time and counts the number of consecutively occurring same-direction error symbols in the phase error signal within a preset time using two counters.

[0033] When the phase error signal has no valid transition code, it is not included in the number of valid code elements;

[0034] When the phase error signal is a phase lead code, increment the phase lead code count and increment the number of valid symbols.

[0035] When the phase error signal is a phase hysteresis code, increment the phase hysteresis code count and the number of valid code elements by one;

[0036] Record the polarity of the previous valid symbol. If the polarity of the current valid symbol is different from that of the previous valid symbol, increment the number of flips F by one.

[0037] The current monitoring window ends when the number of valid symbols reaches a preset symbol threshold, based on | - | Update the trend criterion with the value of the number of flips and clear the number of valid symbols, the phase lead code count, the phase lag code count and the number of flips, enter the next monitoring window, and keep the output gain state control code unchanged until the end of the next monitoring window.

[0038] Preferably, the adaptive control unit is connected to the confidence judgment unit and the output accumulator module, and is used to receive N-bit initial phase control codes;

[0039] Based on the gain control code, a multiplexer is used to dynamically slide and extract M consecutive bits of data from the N-bit initial phase control code as the optimized phase control code, where N>M;

[0040] By changing the high and low positions of the truncation bits in the initial phase control code, the adaptive adjustment of the control weights is achieved, and the optimized phase control code is output to the subsequent circuit.

[0041] Secondly, a processing method based on a high-speed adaptive digital filter includes the following steps:

[0042] Step S1: Receive the phase error signal and perform long-range accumulation to generate a frequency deviation accumulation value;

[0043] Step S2: Amplify the phase error signal proportionally to generate an instantaneous phase adjustment value;

[0044] Step S3: Combine the cumulative frequency deviation value with the instantaneous phase adjustment value to generate a combined signal;

[0045] Step S4: The combined signal is accumulated twice to generate an N-bit initial phase control code;

[0046] Step S5: Confidence judgment and instantaneous noise filtering are performed based on the phase error signal. Based on the judgment result, the total gain of the system is dynamically adjusted by sliding the effective bit width of the N-bit initial phase control code, and finally the optimized phase control code is output.

[0047] The beneficial effects of this invention are as follows: Based on the traditional digital loop filter, this invention adds an automatic gain adjustment mechanism, which enables it to better cope with changes in PVT, improves the jitter tolerance of the RX system, reduces the jitter of the recovery data clock, and speeds up the system's locking speed.

[0048] An anti-overflow mode control function has been added to the integration path, which causes the accumulator in the first path to enter the extreme value mode and stay at the saturation value after reaching the positive or negative saturation value, until it encounters a reverse adjustment and leaves the extreme value mode saturation value. This prevents the DLF from immediately malfunctioning and the system from losing lock after the accumulator reaches saturation. Through the clamping and holding mechanism, the instantaneous reverse adjustment and loss of lock of CDR caused by the numerical overflow and flip at the extreme point of the traditional accumulator are avoided. The effective stable tracking range of the system is extended to the edge by about 1500ppm without increasing the hardware bit width, which greatly improves the robustness against extreme frequency offset impacts.

[0049] Furthermore, under Bang-Bang tri-state inputs with a large number of 0s and 0s, relying solely on a single count or continuous length can easily lead to misjudgments due to insufficient information or jitter, causing gain hunting. This invention uses a combination of difference strength and flip characteristics as trend criteria, and introduces a freeze / release mechanism to keep gain scheduling stable under noise boundaries. Further, when the integrator enters saturation hold due to limited bit width, the total gain control module will naturally select high gain upon detecting continuous unidirectional errors, allowing the loop to escape the saturation region with minimal delay. This expands the frequency offset tracking range without increasing the accumulator bit width, while avoiding direction flipping loss due to saturation. It effectively extracts hidden trend information from discrete Bang-Bang symbols, avoiding gain misjudgments due to insufficient information in harsh channel environments with numerous invalid transition codes. In the locked steady state, the system will enter a no-frequency-offset mode upon detecting frequent symbol bit transitions, forcibly clearing the integrated accumulation value to zero. Simultaneously, the total gain control module will select low gain based on the high number of flips. The synergistic effect of both significantly reduces clock jitter during recovery. Attached Figure Description

[0050] Figure 1 A basic flowchart of a processing system based on a high-speed adaptive digital filter is provided for one embodiment of the present invention;

[0051] Figure 2 A flowchart illustrating the steps of a processing method based on a high-speed adaptive digital filter, as provided in one embodiment of the present invention;

[0052] Figure 3 This is a structural diagram of the high-speed adaptive digital filter implementation of the present invention;

[0053] Figure 4 This is a schematic diagram of the first gain unit structure of the present invention;

[0054] Figure 5 This is a logic diagram of the mode control module of the present invention;

[0055] Figure 6 This is a logic diagram of the total gain control module of the present invention;

[0056] Figure 7 The principle and truth table diagram of the first trigger of the present invention are shown below;

[0057] Figure 8 This is a schematic diagram of the DLF principle of the present invention. Detailed Implementation

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0059] Example 1, refer to Figure 1-8 This paper presents a processing system based on a high-speed adaptive digital filter, including an integration path module, a proportional path module, a combination module, an output accumulator module, and a total gain control module.

[0060] The integration path module is used to receive the phase error signal from the previous phase detector, accumulate and calculate the phase error signal, and generate a cumulative value of frequency deviation.

[0061] The proportional path module is used to proportionally amplify the phase error signal to obtain the instantaneous phase adjustment value;

[0062] The combination module is used to perform combined calculations on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal;

[0063] The output accumulator module is used to perform a second accumulation operation on the combined signal to obtain an N-bit initial phase control code;

[0064] The total gain control module is used to determine the confidence level and filter instantaneous noise based on the phase error signal. Based on the determination result, it dynamically adjusts the total gain of the system by sliding and truncating the effective bit width of the N-bit initial phase control code, and finally outputs the optimized phase control code.

[0065] This invention adds an automatic gain adjustment mechanism to the traditional DLF, enabling it to better cope with PVT changes, improve the jitter tolerance of the RX system, reduce the jitter of the recovery data clock, and speed up the system's locking speed. An anti-overflow mode control function is added to the integration path, so that the accumulator in the first path enters an extreme value mode after reaching the positive or negative saturation value and stays at the saturation value until it encounters a reverse adjustment and leaves the extreme value mode saturation value. This prevents the DLF from immediately malfunctioning and losing lock after the accumulator reaches saturation, and improves the frequency offset tracking capability by about 1500ppm without increasing the number of bits of the accumulator.

[0066] In addition, the present invention adopts a fully custom digital circuit design, which greatly improves the operating speed of the filter, reduces the number of data deserialization stages, thereby reducing the total loop delay and improving the jitter of data recovery and clock.

[0067] The integration path module includes a first gain unit and a mode control unit;

[0068] The first gain unit is used to receive the phase error signal in real time. By performing high-bit extension processing of left shift, an amplified phase error signal is generated. The amplified phase error signal at the current moment is superimposed with the accumulated value saved at the previous moment using the first accumulator to obtain the accumulated result value. The first accumulator also includes a set terminal, which is used to preset a non-zero initial frequency value during the startup phase.

[0069] The phase error signal is a discrete Bang-Bang type code, including phase-leading code, phase-lag code and code without effective transition. The phase error signal does not contain phase error amplitude information.

[0070] The accumulated result value output by the first accumulator is truncated by bit width, discarding the low-order data and retaining the high-order data. The obtained high-order data is used as the frequency deviation accumulated value.

[0071] This embodiment refers to Figure 3The specific implementation of the integration path module (first path) is as follows: After receiving the phase error signal, the first gain unit amplifies the phase error signal by a factor of two through a left shift operation in the digital circuit, and performs sign bit expansion in the high bits to maintain the positive and negative polarities. The amplified phase error signal is then sent to the first accumulator (DFF1). During the system power-on or reset startup phase, the external control logic can write a non-zero preset initial value (such as the center frequency offset commonly used in this application scenario) through the set terminal of the first accumulator. This design avoids the accumulator slowly ramping up from zero, significantly shortening the lock-in time of the CDR system. In addition, in order to filter out the interference of high-frequency random noise, the 16-bit full-precision accumulated result value is not directly output. Instead, a fixed bit width truncation operation is performed, such as discarding the lower 7 bits and sending only the higher 9 bits as the frequency deviation accumulated value to the subsequent stage, which is equivalent to implementing a low-pass filter.

[0072] The mode control unit is used to monitor the cumulative result value in real time and switch the mode state according to the cumulative result value:

[0073] When the absolute value of the accumulated result is less than the preset saturation threshold, it is in frequency tracking mode; when the absolute value of the accumulated result is greater than or equal to the preset saturation threshold, it switches to frequency hold mode and forces the output clamp to lock at the extreme point.

[0074] When the output clamp is forcibly locked at the extreme point, it continuously responds to the reverse error signal dynamically. When the reverse error signal is received and the accumulated result value is corrected so that the absolute value of the accumulated result value is less than the preset saturation threshold, it exits the frequency holding mode and returns to the frequency tracking mode.

[0075] The mode control unit (overflow prevention unit) monitors the uncrunted cumulative result value in real time. When the cumulative result value has not yet reached the saturation threshold set by the system (0x7FFF in 16-bit two's complement in this embodiment), it sets the current tracking mode, and each error input will be normally superimposed. When encountering a large frequency deviation environment, when the accumulated value touches the extreme point of the saturation threshold, it automatically switches to frequency holding mode, stops the continued accumulation in the same direction, prevents the value from overflowing and becoming an error value with opposite polarity, and clamps the output at the extreme point of the saturation threshold. In the clamped state, the system does not completely stop, but continues to monitor the reverse error signal. Once the channel condition improves and the phase detector outputs a reverse correction signal (for example, it originally required acceleration, but now it requires deceleration), the accumulator immediately performs subtraction. As long as the accumulated result value falls back to within the saturation threshold, it immediately leaves the holding mode and seamlessly switches back to frequency tracking mode.

[0076] The proportional path module includes a second gain unit, which performs left shift and low-bit zero-padding on the phase error signal to obtain the instantaneous phase adjustment value.

[0077] By using left-shifted high-bit sign extension, the phase error signal is mapped to multi-bit wide data, and the multi-bit wide data is output as the instantaneous phase adjustment value. The instantaneous phase adjustment value does not contain the accumulated information of historical errors.

[0078] The proportional path module (second path) in this embodiment adopts a pure combinational logic circuit design, without any storage elements such as flip-flops or registers. The receiving unit does not have the function of remembering historical errors. When the input terminal jumps, for example, from "01" representing phase lead to "11" representing phase lag, the output terminal of the receiving unit will change accordingly immediately due to the logic gate. There is no need to wait for the clock edge to trigger, which ensures that the system can react to high-frequency phase jitter at the fastest speed, minimizes the loop feedback delay, and effectively suppresses the high-frequency jitter of the system.

[0079] In this embodiment, in order to effectively synthesize the small adjustment amount of the proportional path with the large-scale cumulative value of the integral path, the second gain unit performs complex bit width mapping and shifting operations: Left shift operation processing: The second gain unit receives the original phase error signal from the receiving unit, and performs a left shift operation on the original signal through the built-in multiplexer circuit according to the preset proportional gain coefficient (8 times in this embodiment).

[0080] High-order sign extension mechanism: During the left shift, because the data bit width is expanded from the original 2 bits to the 12 bits required for subsequent operations, a crucial high-order sign extension is performed:

[0081] Positive value extension: If the current phase is ahead and the input signal is positive, then after shifting N bits to the left, the vacated high bits are all filled with logic 0;

[0082] Negative value extension: If the current phase is lagging and the input signal is negative, and the negative value is represented in two's complement form, then after left shift, all the empty high bits must be filled with logic 1;

[0083] The logic for handling instantaneous jump amplitude is as follows:

[0084] After the sign extension of the high-order bits, the generated instantaneous phase adjustment value is a two's complement binary data with a width of multiple bits. The instantaneous phase adjustment value only represents the direction and magnitude of the phase error jump at the current moment.

[0085] This embodiment ensures that the signal output by the proportional path does not contain any accumulated information of historical errors, thereby avoiding erroneous interference from the proportional path to low-frequency deviation. It achieves decoupled control of instantaneous correction and long-term tracking by aligning and adding the output of the integral path with the output in the combination module.

[0086] The modes include frequency tracking mode, frequency hold mode, and no frequency offset mode;

[0087] Frequency tracking mode is used to maintain non-interference with the accumulated result value, allowing the first accumulator to perform addition and subtraction operations normally according to the phase error signal of each clock cycle, and pass the result through to the next stage;

[0088] Frequency hold mode is used to activate internal clamping logic, cut off the normal accumulation feedback path, and force the output to be locked at the corresponding positive or negative extreme value; to prevent arithmetic overflow of the accumulator. If not clamped, the value will flip from the positive maximum value to the negative minimum value, causing the CDR system to adjust in reverse momentarily, thereby causing a loss of lock.

[0089] The no-frequency-offset mode is used to lock the ENS signal to be valid. If frequent changes in the sign bit are detected within the preset monitoring window, it is determined that there is no systematic frequency offset in the current environment, and the cumulative result value output by the integration path is forcibly cleared to zero.

[0090] This embodiment refers to Figure 5 By introducing a frequency hold mode and internal clamping logic, the critical state of the accumulator can be monitored in real time. Under extreme frequency offset conditions, when the accumulated result reaches the extreme value, the system actively cuts off the accumulation feedback path and locks the output at the extreme point, effectively avoiding the phase reversal error caused by the two's complement arithmetic overflow of the traditional accumulator, that is, the value flips from the positive maximum value to the negative minimum value instantly. This ensures that the CDR system can still maintain directional adjustment under the impact of excessive frequency offset, and completely solves the system lockout problem caused by overflow flip.

[0091] By setting a no-frequency-offset mode, the system can intelligently identify the statistical characteristics of the input signal within the monitoring window after the lockout signal (ENS) is valid. When frequent sign bit transitions indicate that the current environment only has non-trend transient noise, the system forcibly clears the output of the integration path, eliminating the invalid oscillation of the integration path near the equilibrium point, reducing the static jitter of the recovery clock, and making the phase of the output clock purer. This embodiment replaces the traditional approach of blindly increasing the accumulator bit width with mode switching logic, reducing the size of the logic gate array while ensuring performance. At the same time, the mode judgment logic is easy to implement using a fully custom analog approach, further shortening the processing delay of the digital filter in the high-speed loop, which is conducive to increasing the upper limit of the operating frequency of the entire serial interface.

[0092] The combination module is used to perform combined calculations on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal;

[0093] Receive the cumulative frequency deviation value of the integral path module and the instantaneous phase adjustment value of the proportional path module;

[0094] The frequency deviation accumulation value and instantaneous phase adjustment value are aligned by low bit and sign extension by hardware connection logic to obtain an aligned signal group. The signal group is then subjected to binary two's complement addition by the first adder to obtain the intermediate operation result.

[0095] Based on the rising edge of the master clock, the intermediate calculation results are sampled and latched using the second flip-flop group to obtain the combined signal.

[0096] The combined module in this embodiment (such as...) Figure 3 The input terminals of the first 12-bit adder and DFF2 (where the first 12-bit adder is the first adder) are connected to the integration path module and the proportional path module, respectively. The cumulative frequency deviation output of the integration path is connected to the input port A of the first adder; the instantaneous phase adjustment value output of the proportional path is connected to the input port B of the first adder. The hard-wired logic performs bit width matching: since the data bit width (9 bits) of the input port A is smaller than the bit width (12 bits) of the first adder, the circuit automatically maps the cumulative frequency deviation value to the lower 9 bits of the first adder and copies the highest bit (sign bit) of the cumulative frequency deviation value to fill the upper 3 bits of the first adder to complete the sign extension, ensuring that the integral component and the proportional component are aligned in the same binary two's complement domain, so that they have mathematical additivity.

[0097] Addition process:

[0098] The first adder employs a 12-bit carry-lookahead adder structure, performing binary two's complement addition on the aligned signal group. The first adder linearly superimposes the integral component, representing the long-term frequency trend, with the proportional component, representing instantaneous phase fluctuations. For example, when the integral path indicates a slow frequency (positive value) and the proportional path detects instantaneous phase lag (positive value), the adder outputs a larger positive value to accelerate adjustment; when the two values ​​are opposite in sign, the adder outputs the difference to smooth the adjustment. After the operation is complete, the adder outputs an intermediate result. To eliminate the interference of combinational logic circuits (i.e., the first adder) during signal transitions... To mitigate potential race conditions and logic glitches, the output of the first adder is connected to the data input (D terminal) of the second flip-flop group (DFF2). The second flip-flop group consists of 12 parallel D flip-flops, and its clock terminal (CLK) is connected to the system master clock. Driven by the rising edge of the clock signal, DFF2 synchronously samples and latches the intermediate operation results output by the adder, which is used to convert the asynchronous combinational logic level into a synchronous timing signal that is strictly aligned with the system clock. This filters out unstable states during the signal establishment process and finally generates a pure combinational signal that is transmitted to the subsequent output accumulator module.

[0099] The output accumulator module includes:

[0100] The system receives a combined signal and uses it as the reference input for the second accumulation. It constructs an accumulation feedback loop using the second adder and the third flip-flop group. The combined signal is input into the accumulation feedback loop to perform the operation. In each clock cycle, the second adder adds the current combined signal to the value of the previous clock cycle stored in the third flip-flop group using binary two's complement to obtain the output result of the second adder. The output result is then latched by the third flip-flop group to generate the initial phase control code.

[0101] In this embodiment, the output accumulator module plays a core processing role in the second-order integral and is used to generate the basic digital code for controlling the phase interpolator (PI).

[0102] The input of the output accumulator module is directly connected to the output of the second flip-flop group (DFF2) in the combinational module. The combinational signal received by the output accumulator module is a 12-bit digital signal that has been aligned by the previous stage, performed by addition, and synchronously sampled by DFF2. Figure 3 As shown, the core architecture of this module consists of an accumulation feedback loop composed of a second adder (Adder2) and a third flip-flop group (DFF3). In the specific operation process, the second adder performs a two's complement accumulation operation, arithmetically adding the current combined signal with the accumulated value stored in DFF3 from the previous moment. If the previous integration path is regarded as a first-order integral (reflecting frequency), then the superposition process here realizes a second-order integral, which transforms the combined signal representing the frequency deviation trend into a specific phase displacement, thereby generating a control vector that can drive the phase interpolator to rotate. The third flip-flop group (DFF3) captures the real-time summation result of the second adder at the rising edge of the system master clock and latches the real-time summation result as an initial phase control code. The initial phase control code represents the absolute offset of the current clock relative to the ideal locking position of the data edge. It is divided into two paths: one path is sent to the output selection module (MUX) of the next stage for final gain truncation; the other path returns to the input of the second adder through the feedback path to prepare for the accumulation of the next clock cycle.

[0103] To meet the timing requirements of high-speed serial transmission above 10Gbps, the second adder and the third flip-flop group in this embodiment adopt an analog full-custom circuit design. By optimizing the transistor size and layout, the physical path delay from the combined signal input to the output of the initial phase control code (S2 signal line) is shortened to the maximum extent, thereby significantly improving the phase margin and lock-in response speed of the CDR system.

[0104] The total gain control module includes a confidence level determination unit and an adaptive control unit;

[0105] The confidence judgment unit is used to monitor the phase error signal in real time and counts the number of consecutive in-direction error symbols in the phase error signal within a preset time using two counters.

[0106] When the phase error signal has no valid transition code, it is not included in the number of valid code elements. ;

[0107] When the phase error signal is a phase lead code, the phase lead code is counted. Increment by one and increment the number of valid symbols by one;

[0108] When the phase error signal is a phase hysteresis code, the phase hysteresis code is counted. Increment by one and increment the number of valid symbols by one;

[0109] Record the polarity of the previous valid symbol. If the polarity of the current valid symbol is different from that of the previous valid symbol, increment the number of flips F by one.

[0110] The current monitoring window ends when the number of valid symbols reaches a preset symbol threshold, based on | - | Update the trend criterion with the value of the number of flips and clear the number of valid symbols, the phase lead code count, the phase lag code count and the number of flips, enter the next monitoring window, and keep the output gain state control code unchanged until the end of the next monitoring window.

[0111] In phase interpolation type CDR, the phase error signal output by the Bang-Bang phase detector is a discrete three-state code, including phase lead code, phase lag code, and no effective transition code. Among them, the input data corresponding to the no effective transition code lacks edge information in the sampling period and cannot provide a basis for phase trend judgment. Therefore, this invention ignores it as invalid code in the trend criterion calculation and only counts the valid code (phase lead code and phase lag code).

[0112] This invention employs a monitoring window mechanism based on the number of valid symbols: a valid symbol counter is set. When a phase-leading code or a phase-lag code is detected Add one, when Reaching the preset threshold The current monitoring window ends and the trend criteria are updated, then the data is cleared. Then proceed to the next monitoring window. Compared with closing the window according to a fixed clock cycle, this mechanism can ensure that each decision is based on a sufficient number of valid observation samples in random data scenarios with a high proportion of no effective transition codes, thereby improving the stability of trend determination.

[0113] Within each monitoring window, the present invention counts the number of times the phase lead code occurs. Number of occurrences of phase hysteresis codes And calculate the difference intensity D=| - The difference in magnitude represents the degree of imbalance in the direction of the phase error. A larger difference indicates a larger equivalent phase error amplitude and a higher confidence level, while a smaller difference indicates that the system is close to the equilibrium point. Since the Bang-Bang phase detector does not output the error amplitude, this invention reconstructs the equivalent confidence level through the above pulse density statistics, thereby providing a continuous criterion for bandwidth scheduling for the subsequent gain state machine. At the same time, in order to utilize the statistical characteristics of alternating directions in the Bang-Bang locked state, this invention further counts the number of polarity flips F of the effective symbols: the polarity of the previous effective symbol is recorded. When the polarity of the current effective symbol is different from that of the previous effective symbol, the number of flips F is incremented by one. Generally, during the acquisition stage or when there is a systematic frequency offset, there is a clear trend of the same direction (larger D and smaller F), while during the locked steady state, there is a clear alternating characteristic (smaller D and larger F). Therefore, this invention uses the combined trend criterion composed of (D,F) to provide a decision basis for the subsequent gain state machine.

[0114] The reliability judgment unit has built-in gain mapping logic. By comparing the difference intensity D and the number of flips F obtained in the current monitoring window with the system's preset threshold, it generates the corresponding gain control code. The specific two-dimensional trend criterion mapping rules are as follows:

[0115] Set high-frequency off-threshold With low flip threshold When satisfied and When the current phase error is in the same direction for most of the time, the system is in the high frequency offset tracking or lock-out capture stage (high confidence). At this time, the confidence judgment unit outputs a high gain control code.

[0116] Set low-frequency offset threshold With high flip threshold ,in When satisfied and When the positive and negative phase error polarities alternate frequently, the system has entered the equilibrium state of the locked region or the current channel is mainly dominated by random transient noise (low confidence). At this time, the confidence judgment unit outputs a low gain control code.

[0117] When the combined trend criterion (D, F) does not meet any of the above conditions, i.e., it falls into the decision transition zone, the confidence judgment unit outputs a hold control code (i.e., the gain control code output when the previous monitoring window is closed remains unchanged). This hysteresis anti-shake mechanism effectively avoids frequent gain switching caused by local signal-to-noise ratio fluctuations, ensuring the smoothness of loop adjustment.

[0118] The adaptive control unit (MUX5 area) is connected to the confidence judgment unit and the output accumulator module to receive N-bit initial phase control codes;

[0119] Based on the gain control code, a multiplexer is used to dynamically slide and extract M consecutive bits of data from the N-bit initial phase control code as the optimized phase control code, where N>M;

[0120] By changing the high and low positions of the truncation bits in the initial phase control code, the adaptive adjustment of the control weights is achieved, and the optimized phase control code is output to the subsequent circuit.

[0121] The output accumulator module outputs a 12-bit full-precision initial phase control code, while the sampling clock control terminal only requires a 6-bit control word. The adaptive control unit uses a multiplexer (MUX5) as a sliding window. When the confidence level is low, the window is locked in the high-order interval of S2 (e.g., truncating S2[11:6]). At this time, since the low-order subdivision is discarded, the output change step size is extremely small, corresponding to a narrow bandwidth, which is beneficial to the stability after locking. High gain mode (CODE is high-order): When it is determined to be a large frequency offset (high confidence level), the gain control code drives the window to slide to the low-order (e.g., truncating S2[7:2]). At this time, the same numerical change is amplified by a power of 2 in terms of physical weight. In order to ensure that no additional loop delay is introduced in the 10Gbps+ environment, MUX5 adopts an analog full-custom transistor-level design to ensure that the propagation delay from the gain code to the output is less than 1 clock cycle. In this embodiment, the expensive gain multiplier is replaced by a simple bit truncation operation, which realizes the adaptive dynamic range of bandwidth under extremely low power consumption and balances the acquisition speed and static performance of the CDR system.

[0122] Example 2, refer to Figure 2 This paper provides a processing method based on a high-speed adaptive digital filter, which includes the following steps:

[0123] Step S1: Receive the phase error signal and perform long-range accumulation to generate a frequency deviation accumulation value;

[0124] Step S2: Amplify the phase error signal proportionally to generate an instantaneous phase adjustment value;

[0125] Step S3: Combine the cumulative frequency deviation value with the instantaneous phase adjustment value to generate a combined signal;

[0126] Step S4: The combined signal is accumulated twice to generate the initial phase control code;

[0127] Step S5: Confidence level is determined based on the phase error signal, instantaneous noise is filtered, and the total system gain is dynamically adjusted by sliding the effective bit width of the initial phase control code according to the determination result, and finally the optimized phase control code is output.

[0128] This invention adds an automatic gain adjustment mechanism to the traditional DLF, enabling it to better cope with PVT variations, improving the jitter tolerance of the RX system, reducing jitter in the recovered data clock, and accelerating the system's locking speed. An anti-overflow mode control function is added to the integration path, causing the accumulator in the first path to enter an extreme value mode and remain at the saturation value after reaching a positive or negative saturation value until encountering a reverse adjustment, thus preventing the DLF from immediately malfunctioning and the system from losing lock after the accumulator reaches saturation. This improves the frequency offset tracking capability by approximately 1500ppm without increasing the accumulator bit depth. Furthermore, this invention uses a fully custom digital circuit to design the digital filter, significantly improving the filter's operating speed, reducing the number of data deserialization stages, thereby reducing the total loop delay and improving the jitter of the recovered data and clock.

[0129] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the protection scope of the present invention.

Claims

1. A processing system based on a high-speed adaptive digital filter, characterized in that, It includes an integral path module, a proportional path module, a combination module, an output accumulator module, and a total gain control module: The integration path module is used to receive the phase error signal from the front-end phase detector, accumulate and calculate the phase error signal, and generate a cumulative frequency deviation value. The proportional path module is used to proportionally amplify the phase error signal to obtain the instantaneous phase adjustment value; The combination module is used to perform a combination operation on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal; The output accumulator module is used to perform a second accumulation operation on the combined signal to obtain an N-bit initial phase control code; The total gain control module is used to determine the confidence level and filter instantaneous noise based on the phase error signal, and dynamically adjust the total gain of the system by sliding and truncating the effective bit width of the N-bit initial phase control code according to the determination result, and finally output the optimized phase control code.

2. The processing system based on a high-speed adaptive digital filter as described in claim 1, characterized in that, The integration path module includes a first gain unit and a mode control unit; The first gain unit is used to receive the phase error signal in real time. By performing high-bit extension processing of left shift, an amplified phase error signal is generated. The amplified phase error signal at the current moment is superimposed with the accumulated value saved at the previous moment using the first accumulator to obtain the accumulated result value. The first accumulator also includes a set terminal for presetting a non-zero initial frequency value during the startup phase. The phase error signal is a discrete Bang-Bang type code, including phase-leading code, phase-lag code and no effective transition code. The phase error signal does not contain phase error amplitude information. The accumulated result value output by the first accumulator is truncated by bit width, discarding the low-order data and retaining the high-order data, and the obtained high-order data is used as the frequency deviation accumulated value.

3. The processing system based on a high-speed adaptive digital filter as described in claim 2, characterized in that, The mode control unit is used to monitor the accumulated result value in real time and switch the mode state according to the accumulated result value: When the absolute value of the accumulated result is less than the preset saturation threshold, it is in frequency tracking mode; when the absolute value of the accumulated result is greater than or equal to the preset saturation threshold, it switches to frequency holding mode and forcibly locks the output clamp at the extreme point. When the output clamp is forcibly locked at the extreme point, it continuously responds to the reverse error signal dynamically. When the reverse error signal is received and the accumulated result value is corrected so that the absolute value of the accumulated result value is less than the preset saturation threshold, it exits the frequency holding mode and returns to the frequency tracking mode.

4. The processing system based on a high-speed adaptive digital filter as described in claim 1, characterized in that, The proportional path module includes a second gain unit, which is used to perform left shift and low-bit zero-filling operation on the phase error signal to obtain the instantaneous phase adjustment value; By using left-shifted high-bit sign extension, the phase error signal is mapped into multi-bit wide data, and the multi-bit wide data is output as an instantaneous phase adjustment value, which does not contain the accumulated information of historical errors.

5. The processing system based on a high-speed adaptive digital filter as described in claim 3, characterized in that, The mode states include frequency tracking mode, frequency hold mode, and no frequency offset mode; The frequency tracking mode is used to maintain non-interference with the accumulated result value, allowing the first accumulator to perform addition and subtraction operations normally according to the phase error signal of each clock cycle, and pass the result through to the subsequent stage; The frequency hold mode is used to activate the internal clamping logic, cut off the normal accumulation feedback path, and force the output to be locked at the corresponding positive or negative extreme value. The no-frequency-offset mode is used to lock the ENS signal to be valid, and then detect frequent changes in the sign bit within a preset monitoring window. It determines that there is no systematic frequency offset in the current environment and forcibly clears the cumulative result value output by the integration path to zero.

6. The processing system based on a high-speed adaptive digital filter as described in claim 1, characterized in that, The combination module is used to perform combined calculations on the cumulative frequency deviation value and the instantaneous phase adjustment value to obtain a combined signal; Receive the cumulative frequency deviation value of the integral path module and the instantaneous phase adjustment value of the proportional path module; The frequency deviation accumulation value and instantaneous phase adjustment value are aligned by low bit and sign extension by hardware connection logic to obtain an aligned signal group. The signal group is then subjected to binary two's complement addition by the first adder to obtain the intermediate operation result. Based on the rising edge of the master clock, the intermediate calculation results are sampled and latched using the second flip-flop group to obtain the combined signal.

7. The processing system based on a high-speed adaptive digital filter as described in claim 1, characterized in that, The output accumulator module includes: The system receives a combined signal and uses it as the reference input for secondary accumulation. It constructs an accumulation feedback loop using a second adder and a third flip-flop group. The combined signal is input into the accumulation feedback loop to perform the operation. In each clock cycle, the second adder adds the current combined signal to the value of the previous clock cycle stored in the third flip-flop group using binary two's complement to obtain the output result of the second adder. The output result is then latched by the third flip-flop group to generate an N-bit initial phase control code.

8. The processing system based on a high-speed adaptive digital filter as described in claim 1, characterized in that, The total gain control module includes a confidence judgment unit and an adaptive control unit; The confidence judgment unit is used to monitor the phase error signal in real time and counts the number of consecutively occurring same-direction error symbols in the phase error signal within a preset time using two counters. When the phase error signal has no valid transition code, it is not included in the number of valid code elements. ; When the phase error signal is a phase lead code, the phase lead code is counted. Increment by one and also increment the number of valid symbols by one; When the phase error signal is a phase hysteresis code, the phase hysteresis code is counted. Increment by one and also increment the number of valid symbols by one; Record the polarity of the previous valid symbol. If the polarity of the current valid symbol is different from that of the previous valid symbol, increment the number of flips F by one. The current monitoring window ends when the number of valid symbols reaches a preset symbol threshold, based on | - | Update the trend criterion with the value of the number of flips and clear the number of valid symbols, the phase lead code count, the phase lag code count and the number of flips, enter the next monitoring window, and keep the output gain state control code unchanged until the end of the next monitoring window.

9. The processing system based on a high-speed adaptive digital filter as described in claim 8, characterized in that, The adaptive control unit is connected to the confidence judgment unit and the output accumulator module, and is used to receive N-bit initial phase control codes; Based on the gain control code, a multiplexer is used to dynamically slide and extract M consecutive bits of data from the N-bit initial phase control code as the optimized phase control code, where N>M; By changing the high and low positions of the truncation bits in the initial phase control code, the adaptive adjustment of the control weights is achieved, and the optimized phase control code is output to the subsequent circuit.

10. A processing method based on a high-speed adaptive digital filter, applied to a processing system based on a high-speed adaptive digital filter as described in any one of claims 1-9, characterized in that, Includes the following steps: Step S1: Receive the phase error signal and perform long-range accumulation to generate a frequency deviation accumulation value; Step S2: Amplify the phase error signal proportionally to generate an instantaneous phase adjustment value; Step S3: Combine the cumulative frequency deviation value with the instantaneous phase adjustment value to generate a combined signal; Step S4: The combined signal is accumulated twice to generate an N-bit initial phase control code; Step S5: Confidence judgment and instantaneous noise filtering are performed based on the phase error signal. Based on the judgment result, the total gain of the system is dynamically adjusted by sliding the effective bit width of the N-bit initial phase control code, and finally the optimized phase control code is output.

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