A burst mode clock data recovery circuit based on phase rotator dynamic scanning

Abstract

A burst mode clock data recovery circuit based on phase rotator dynamic scanning, comprising a decision maker, a binary phase discriminator (BBPD), a signal selector and a phase rotator (PR), the application can quickly search the phase space through the phase rotator and introduce a phase scanning mechanism based on dynamic step in the burst data arrival stage, and adaptively adjust the phase step resolution in the locking process, thereby significantly shorten the locking time while ensuring the phase accuracy, combined with the phase error decision mode of multi-phase sampling and majority voting, improve the decision reliability of the burst mode stage under the conditions of noise, jitter and frequency deviation. After locking, the circuit switches to continuous mode by multiplexing the same phase rotator, forms a closed-loop phase tracking, realizes low-jitter clock recovery, and balances fast burst locking and high-quality continuous recovery without increasing high-speed sampling circuit and disturbing the oscillator.

Description

Technical Field

[0001] This invention relates to a technology in the field of digital signal processing, specifically a burst-mode clock data recovery circuit based on dynamic scanning of a phase rotator. Background Technology

[0002] In high-speed wired communication applications, clock data recovery circuits need to quickly complete phase alignment and maintain stable output when data bursts arrive. Some existing clock data recovery technologies are based on closed-loop integral phase convergence mechanisms. Phase alignment in burst mode mainly relies on the dynamic response of the loop, making it difficult to actively search the phase space. As a result, it is difficult to achieve nanosecond-level fast and accurate positioning, and it is also impossible to achieve locking based on phase rotator scanning and dynamic step size adjustment. Summary of the Invention

[0003] This invention addresses the problems of long locking times, insufficient phase decision robustness, and the difficulty in balancing locking speed and steady-state performance in existing burst-mode clock data recovery circuits when high-speed data arrives. It proposes a burst-mode clock data recovery circuit based on dynamic scanning of a phase rotator. During the burst data arrival phase, the phase rotator performs a rapid search of the phase space and introduces a phase scanning mechanism based on dynamic step size. During locking, the phase step resolution is adaptively adjusted, thereby significantly shortening the locking time while maintaining phase accuracy. Furthermore, by combining multi-phase sampling and majority voting for phase error decision-making, the reliability of decision-making under noise, jitter, and frequency deviation conditions during the burst-mode phase is improved. After locking, the circuit reuses the same phase rotator to switch to continuous mode, forming a closed-loop phase tracking, achieving low-jitter clock recovery. This achieves both fast burst locking and high-quality continuous recovery without adding high-speed sampling circuitry or disturbing the oscillator.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a burst mode clock data recovery circuit based on dynamic scanning of a phase rotator, comprising: a decision unit, a binary phase detector (BBPD), a signal selector, and a phase rotator (PR), wherein: the decision unit performs multi-phase sampling and decision based on the input data, and outputs a data signal for phase decision and corresponding edge information for subsequent phase detection and control unit use; the binary phase detector performs phase error decision on the input data based on the multi-phase sampling results and detects the arrival of burst data to trigger burst mode locking; the signal selector selects the phase control word input source according to the mode switching control information output by the binary phase detector, obtains the phase control word corresponding to the burst mode or continuous mode, and outputs it to the phase rotator, realizing the multiplexing of the same phase execution unit in different working modes; the phase rotator adjusts the phase of the input multi-phase clock with different polarities and different timings according to the phase control word from the signal selector, obtains the recovery clock signal corresponding to the current working mode, and outputs it to the clock network.

[0006] The decision-maker is implemented by a comparator configured with a sample-and-hold unit. This comparator simultaneously receives differential data signals and differential reference signals and operates in the reset phase and the comparison phase. In the comparison phase, the voltage difference is generated by the front-stage differential pair and amplified and latched by the rear-stage cross-coupled regeneration unit to achieve high-speed decision-making.

[0007] The comparator adopts a two-stage four-input dynamic comparator structure. The subsequent stage uses a sampler based on TSPC D flip-flops to latch the comparison result, driven by the comparator reset clock, to ensure that the comparison result is stably maintained.

[0008] The method of connecting a compensation capacitor to the output node of the comparator and scanning for calibration reduces input offset and avoids configuring an additional DAC and separate compensation logic for each comparator, making it more suitable for multi-comparator parallel application scenarios.

[0009] The phase rotator described herein is a current injection type phase rotator, comprising: a clock phase selector, a pulse generator, and an injection counter. The clock phase selector selects a trigger clock from the VCO multiphase output for phase lead or lag adjustment. The pulse generator generates a narrow pulse injection signal. The injection counter controls the number of injections according to the phase control word and stops injection after reaching the target value. This allows for multi-step phase rotation to be completed within a single update cycle, improving the phase adjustment speed and making it more suitable for rapid locking in burst mode.

[0010] Technical effect

[0011] In the burst mode phase, this invention obtains a phase error decision result by multi-phase sampling of the input data and combining it with majority voting. The logic control unit then dynamically controls the phase rotator to perform phase scanning based on the phase error decision result, achieving rapid search and convergence of the recovered clock phase. This allows for initial phase alignment between the recovered clock and the input data in a very short time. After completing burst mode locking, the system switches to continuous mode, reusing the same phase rotator and phase adjustment path to form a closed-loop phase tracking structure. This enables continuous adjustment of the phase error, resulting in a stable, low-jitter recovered clock output. Compared to existing technologies, this invention achieves both rapid locking in burst mode and low-jitter, high-stability clock recovery in continuous mode without introducing additional high-speed sampling circuitry or directly disturbing the oscillator itself. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of the present invention;

[0013] Figure 2 This is a schematic diagram of the decision level in burst mode;

[0014] Figure 3 This is a schematic diagram of the BBPD architecture for burst mode;

[0015] Figure 4 and Figure 5 This is a schematic diagram illustrating the effect of the example;

[0016] Figure 6 This is a circuit diagram of a two-stage comparator in a decision circuit.

[0017] Figure 7 This is the circuit diagram of the sampler in the decision circuit;

[0018] Figure 8 This is a diagram of a current-injection type phase rotator architecture. Detailed Implementation

[0019] like Figure 1 As shown, this embodiment relates to a burst-mode clock data recovery method based on the above circuit, including:

[0020] Step 1, burst data detection and phase error determination, such as Figure 2 , Figure 6 and Figure 7 As shown, it specifically includes:

[0021] 1.1 The multiplexer, acting as the decision-maker, performs multi-phase sampling and decision-making on the input PAM-4 modulated signal, and outputs the data signal for phase decision-making and the corresponding edge information;

[0022] The multi-channel comparator includes a data comparison branch and an edge comparison branch. The data comparison branch corresponds to the main decision level and the reference comparison levels Vrefp and Vrefm, and is used to compare the sampled signals and output a thermometer code. In burst mode, when the edge sampled value is between Vrefp and Vrefm, a thermometer code representing a small phase error range is output; when the edge sampled value is outside of Vrefp and Vrefm, a thermometer code representing a large phase error range is output.

[0023] The multi-phase sampling refers to the following: two sets of edge sampling clocks and data sampling clocks sample two adjacent symbols respectively, and each sampling clock drives the corresponding decision unit to output a three-digit thermometer code.

[0024] 1.2 The binary phase detector (BBPD) performs phase error direction determination on the input data based on the multi-phase sampling results and outputs phase error polarity information after validating the input data. Specifically, the middle bit of each thermometer code is used as the phase error polarity criterion and sent to the corresponding BBPD XOR unit for phase detection. The multiple phase detection results are then processed by majority voting logic to output the final phase error signal.

[0025] Step 2: When a burst data arrival indicator is detected, the BBPD triggers the logic control unit to enter burst mode lockout state, such as... Figure 3 As shown, it specifically includes:

[0026] 2.1 The logic control unit in the BBPD generates a burst mode control signal START based on the phase error decision result output by the BBPD and controls the signal selector to switch the input source of the phase control word (PCW) to the logic control unit.

[0027] 2.2 Under the control of the logic control unit, the phase rotator (PR) adjusts the phase of the recovery clock using a dynamic step-size phase scanning method. Specifically, as shown in Table 1, the most significant bit and least significant bit of the sampler output corresponding to the first set of data sampling clock are used for logical operations, and the phase adjustment step size of the PR is controlled according to the pre-established mapping relationship. This achieves dynamic step-size adjustment based on the phase error range, enabling rapid convergence when the phase error is large and fine adjustment when approaching the lock position, thus simultaneously taking into account both the sudden lock-up speed and the phase adjustment accuracy.

[0028] Table 1

[0029] 2.3 When the phase error is large, a larger phase rotation step size is used to accelerate phase convergence; when the phase error is close to the locked position, a smaller step size is used for fine adjustment, thereby achieving fast search and accurate alignment of the recovered clock phase.

[0030] Step 3: Sudden lockout completion determination and mode switching, specifically including:

[0031] 3.1 When the logic control unit determines that the recovery clock has completed the initial phase alignment, it generates the burst mode end control signal DONE;

[0032] 3.2 Under the control of the DONE signal, the signal selector switches the input source of the phase control word (PCW) from the logic control unit to the digital control module, so that the system switches from burst mode to continuous mode operation.

[0033] 3.3 The DONE signal is also used to reset the logic control unit, restoring its internal state to the initial state, so as to ensure the repeatability and consistency of subsequent burst processes.

[0034] Step 4, Closed-loop phase tracking in continuous mode, specifically includes:

[0035] 4.1 In continuous mode, the digital control module continuously adjusts the phase error based on a closed-loop phase tracking mechanism and outputs a phase control word;

[0036] 4.2 The phase rotator adjusts the phase of the input multi-phase clock according to the phase control word to maintain phase alignment between the recovery clock and the input data;

[0037] 4.3 Through the above closed-loop phase tracking process, a stable, low-jitter recovery clock output is obtained, enabling reliable reception of high-speed data.

[0038] Through practical application experiments, the burst mode clock data recovery circuit based on dynamic scanning of a phase rotator, as described in this invention, was verified by system-level post-simulation under 40 nm CMOS process conditions. In the simulation environment, the data rate was set to 64 Gb / s, the recovery clock center frequency was 8 GHz, and the input signal was a PAM-4 burst data sequence with random jitter and a certain amplitude of deterministic jitter superimposed at the input to simulate actual link conditions. In burst mode, the circuit first uses a dynamic step-size scanning method controlled by the logic control unit to perform phase search by the phase rotator. After initial phase alignment is completed, it switches to continuous mode and enters closed-loop phase tracking state.

[0039] Simulation results show that the circuit of this invention can complete the initial phase locking in burst mode within approximately 8 ns, which is significantly faster than the traditional structure using only closed-loop integral regulation. After entering continuous mode, the recovered clock can maintain stable tracking, the output clock eye diagram has good opening, and the jitter level meets the requirements of high-speed links. Post-simulation statistics show that under the above operating conditions, the energy efficiency of the circuit of this invention is 1.4 pJ / bit. The transient simulation results of the burst locking circuit are as follows: Figure 4 As shown, the simulation results after continuous mode are as follows: Figure 5 As shown above, the simulation results demonstrate that the present invention can simultaneously achieve fast locking in burst mode and low-jitter, high-stability clock recovery in continuous mode without introducing additional high-speed sampling circuits or directly disturbing the oscillator itself, thus verifying the effectiveness of the technical solution.

[0040] Compared with existing technologies, this invention employs a burst mode locking mechanism based on PR scanning and directly triggers PR with an oscillator clock, freeing its operating frequency from the maximum operating frequency of the digital logic. This significantly shortens the burst locking time and reduces the residual phase error after locking without adding additional high-speed sampling circuitry. Furthermore, this invention introduces a dynamic step-size adjustment strategy based on phase error range determination. When the phase error is large, a larger phase rotation step size is used to accelerate the locking process; when approaching the locking position, a smaller step size is used for fine adjustment. This achieves both nanosecond-level fast phase convergence and high phase accuracy during the burst mode phase.

[0041] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A burst-mode clock data recovery circuit based on dynamic scanning of a phase rotator, characterized in that, include: The system comprises a decision unit, a binary phase detector (BBPD), a signal selector, and a phase rotator (PR). Specifically: the decision unit performs multi-phase sampling and decision-making based on the input data, outputting a data signal for phase decision-making and corresponding edge information for subsequent phase detection and control unit use; the binary phase detector performs phase error decision-making on the input data based on the multi-phase sampling results and detects the arrival of burst data to trigger burst mode locking; the signal selector selects the phase control word input source based on the mode switching control information output by the binary phase detector, obtaining the phase control word corresponding to burst mode or continuous mode and outputting it to the phase rotator, enabling the multiplexing of the same phase execution unit in different operating modes; and the phase rotator adjusts the phase of the input multi-phase clock with different polarities and different phase lengths based on the phase control word from the signal selector, obtaining the recovery clock signal corresponding to the current operating mode and outputting it to the clock network.

2. The burst-mode clock data recovery circuit based on dynamic scanning of a phase rotator according to claim 1, characterized in that, The decision-maker is implemented by a comparator configured with a sample-and-hold unit. This comparator simultaneously receives differential data signals and differential reference signals and operates in the reset phase and the comparison phase. In the comparison phase, the voltage difference is generated by the front-stage differential pair and amplified and latched by the rear-stage cross-coupled regeneration unit to achieve high-speed decision-making.

3. The burst mode clock data recovery circuit based on dynamic scanning of a phase rotator according to claim 1, characterized in that, The comparator adopts a two-stage four-input dynamic comparator structure. The subsequent stage uses a sampler based on TSPC D flip-flops to latch the comparison result, driven by the comparator reset clock, to ensure that the comparison result is stably maintained.

4. The burst mode clock data recovery circuit based on dynamic scanning of a phase rotator according to claim 1, characterized in that, The method of connecting a compensation capacitor to the output node of the comparator and scanning for calibration reduces input offset and avoids configuring an additional DAC and separate compensation logic for each comparator, making it more suitable for multi-comparator parallel application scenarios.

5. The burst mode clock data recovery circuit based on dynamic scanning of a phase rotator according to claim 1, characterized in that, The phase rotator described herein is a current injection type phase rotator, comprising: a clock phase selector, a pulse generator, and an injection counter. The clock phase selector selects a trigger clock from the VCO multiphase output for phase lead or lag adjustment. The pulse generator generates a narrow pulse injection signal. The injection counter controls the number of injections according to the phase control word and stops injection after reaching the target value. This allows for multi-step phase rotation to be completed within a single update cycle, improving the phase adjustment speed and making it more suitable for rapid locking in burst mode.

6. A method for burst-mode clock data recovery based on the circuit described in any one of claims 1-5, characterized in that, include: Step 1, burst data detection and phase error determination, specifically includes: 1.1 The multiplexer, acting as the decision-maker, performs multi-phase sampling and decision-making on the input PAM-4 modulated signal, and outputs the data signal for phase decision-making and the corresponding edge information; 1.2 The binary phase detector (BBPD) performs phase error direction determination on the input data based on the multi-phase sampling results and outputs phase error polarity information after validating the input data. Specifically, the middle bit of each thermometer code is used as the phase error polarity criterion and sent to the corresponding BBPD XOR unit for phase detection. The multiple phase detection results are then processed by majority voting logic to output the final phase error signal. Step 2: When a burst data arrival indicator is detected, the BBPD triggers the logic control unit to enter burst mode lockout state, specifically including: 2.1 The logic control unit in the BBPD generates a burst mode control signal START based on the phase error decision result output by the BBPD and controls the signal selector to switch the input source of the phase control word (PCW) to the logic control unit. 2.2 The phase rotator (PR), under the control of the logic control unit, adjusts the phase of the recovered clock using a dynamic step-size phase scanning method; 2.3 When the phase error is large, a larger phase rotation step size is used to accelerate phase convergence; when the phase error is close to the locked position, a smaller step size is used for fine adjustment, thereby achieving fast search and accurate alignment of the recovered clock phase. Step 3: Sudden lockout completion determination and mode switching, specifically including: 3.1 When the logic control unit determines that the recovery clock has completed the initial phase alignment, it generates the burst mode end control signal DONE; 3.2 Under the control of the DONE signal, the signal selector switches the input source of the phase control word (PCW) from the logic control unit to the digital control module, so that the system switches from burst mode to continuous mode operation. 3.3 The DONE signal is also used to reset the logic control unit, restoring its internal state to the initial state, so as to ensure the repeatability and consistency of subsequent burst processes; Step 4, Closed-loop phase tracking in continuous mode, specifically includes: 4.1 In continuous mode, the digital control module continuously adjusts the phase error based on a closed-loop phase tracking mechanism and outputs a phase control word; 4.2 The phase rotator adjusts the phase of the input multi-phase clock according to the phase control word to maintain phase alignment between the recovery clock and the input data; 4.3 Through the above closed-loop phase tracking process, a stable, low-jitter recovery clock output is obtained, enabling reliable reception of high-speed data.

7. The burst mode clock data recovery method according to claim 6, characterized in that, Step 2.2 is as follows: As shown in Table 1, the most significant bit and least significant bit of the sampler output corresponding to the first set of data sampling clocks are used to perform logical operations and the phase adjustment step size of PR is controlled according to the pre-established mapping relationship to realize dynamic step size adjustment based on phase error interval determination, so that it can converge quickly when the phase error is large and achieve fine adjustment when approaching the lock position, thereby taking into account both the sudden lock speed and the phase adjustment accuracy. Table 1 。 8. The burst mode clock data recovery method according to claim 6, characterized in that, The multi-channel comparator includes a data comparison branch and an edge comparison branch. The data comparison branch corresponds to the main decision level and the reference comparison level Vrefp and Vrefm, and is used to compare the sampled signals and output a thermometer code. In burst mode, when the edge sampled value is between Vrefp and Vrefm, a thermometer code representing a small phase error range is output; when the edge sampled value is outside Vrefp and Vrefm, a thermometer code representing a large phase error range is output.

9. The burst mode clock data recovery method according to claim 6, characterized in that, The multi-phase sampling refers to the following: two sets of edge sampling clocks and data sampling clocks sample two adjacent symbols respectively, and each sampling clock drives the corresponding decision unit to output a three-digit thermometer code.

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