Control circuit of a cascade structure
By combining power conversion and drive signal control modules, the cascaded structure can switch between direct drive and common source/common gate modes, solving the problem of balancing switching performance and reliability in existing technologies and improving the overall reliability and switching performance of the cascaded structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG ZHINENG TECH CO LTD
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-05
AI Technical Summary
Existing cascaded drive methods struggle to balance switching performance and reliability, especially given the significant process variations in the threshold voltage of high-voltage depletion-mode gallium nitride transistors under static operating conditions, which leads to reduced reliability.
The power conversion module converts the external DC power supply into the internal operating voltage, and the drive signal control module and drive module control the conduction or cutoff of the high voltage depletion type and low voltage enhancement type transistors. Combined with logic circuits and level holding circuits, the cascaded structure can switch between direct drive and common source common gate modes, reducing gate voltage stress.
While ensuring good switching performance, the reliability of the cascaded structure is significantly improved, switching losses and static differences are reduced, and the overall reliability of the device is enhanced.
Smart Images
Figure CN122159842A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, and more specifically, to a cascaded control circuit. Background Technology
[0002] Gallium nitride (GaN) high electron mobility transistors (HEMs) have become core switching devices in high-frequency, high-efficiency power electronic converters due to their advantages such as high breakdown electric field, high saturation electron velocity, and low on-resistance. Cascading structures, a common implementation of GaN power devices, typically consist of a low-voltage enhancement-mode silicon transistor connected in series with a high-voltage depletion-mode GaN transistor. Depending on the driving method, cascaded structures can be divided into direct-drive structures and cascode structures.
[0003] In a direct-drive structure, the low-voltage enhancement-mode silicon transistor is continuously on, directly controlling the gate drive voltage of the high-voltage depletion-mode gallium nitride (GaN) transistor, thereby controlling the on / off state of the entire cascaded structure. This gives the cascaded structure advantages such as fast switching response and low switching losses. However, due to the significant process variability in the threshold voltage of the high-voltage GaN transistor in the cascaded structure, adapting the drive voltage of the high-voltage GaN transistor presents certain difficulties. Especially under static operating conditions, the static difference between the gate-source voltage and the threshold voltage of the high-voltage GaN transistor is large, which will significantly reduce the reliability of the entire cascaded structure.
[0004] In a cascode structure, the switching on and off of the entire cascaded structure is controlled by adjusting the gate voltage of the low-voltage enhancement-mode silicon transistor (EDS), allowing the high-voltage depletion-mode gallium nitride (GaN) transistor to exhibit enhancement-mode characteristics, thereby improving the reliability of the cascaded structure. However, this cascaded structure cannot directly control the switching speed of the entire structure, resulting in poor adjustment flexibility. Furthermore, the body diode of the low-voltage EDS introduces a reverse recovery process, which further increases the switching losses of the cascaded structure.
[0005] In summary, existing cascaded drive methods have the problem of balancing switching performance and reliability. Summary of the Invention
[0006] The purpose of this application is to provide a control circuit for a cascaded structure that can improve the reliability of the cascaded structure while ensuring good switching performance.
[0007] The embodiments of this application are implemented as follows: A first aspect of this application provides a cascaded control circuit, which includes a power conversion module, a drive signal control module, and a drive module. The cascaded structure includes a high-voltage depletion-type transistor and a low-voltage enhancement-type transistor, wherein the source of the high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The first input terminal of the power conversion module is connected to the positive DC power supply, the second input terminal of the power conversion module and the first input terminal of the drive module are both connected to the negative DC power supply, the first output terminal of the power conversion module is connected to the power supply terminal of the chip, and the power conversion module is also connected to an external switching node. The input terminal of the drive signal control module is used to receive external input signals. The sampling terminal of the drive signal control module is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module, respectively. The first output terminal of the drive signal control module is connected to the gate of the low-voltage enhancement-mode transistor. The second output terminal of the drive signal control module is connected to the second input terminal of the drive module. The first output terminal of the drive module is connected to the gate of the high-voltage depletion-mode transistor. The second output terminal of the drive module is connected to the source of the low-voltage enhancement-mode transistor. The drive signal control module controls the low-voltage enhancement-mode transistor to turn on or off based on the external input signal and the voltage detection result obtained from the electrical signal collected by the sampling terminal of the drive signal control module, and sends the corresponding logic level to the drive module through the second output terminal of the drive signal control module. The drive module controls the high-voltage depletion-type transistor to turn on or off based on logic levels and the negative drive signal from the negative DC power supply input.
[0008] As one possible implementation, the power conversion module includes: a switching unit, a buck-boost converter, and a linear regulator; The first terminal of the switching unit and the input terminal of the linear regulator are connected to the positive DC power supply, and the output terminal of the linear regulator is connected to the power supply terminal of the chip. The control terminal of the switching conversion unit is connected to the buck-boost converter, the second terminal of the switching conversion unit is connected to an external switching node, and the third terminal of the switching conversion unit is connected to the negative DC power supply.
[0009] As one possible implementation, the aforementioned switching unit includes: a P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor; The source of the P-type metal-oxide-semiconductor transistor is connected to the positive DC power supply, the drain of the P-type metal-oxide-semiconductor transistor is connected to the drain of the first N-type metal-oxide-semiconductor transistor, and the gates of both the P-type metal-oxide-semiconductor transistor and the first N-type metal-oxide-semiconductor transistor are connected to the buck-boost converter. The source of the first N-type metal-oxide-semiconductor transistor is connected to the negative DC power supply, and the drain of both the P-type metal-oxide-semiconductor transistor and the drain of the first N-type metal-oxide-semiconductor transistor are connected to an external switching node.
[0010] As one possible implementation, the above-mentioned driving module includes: a level shifter, a first buffer, a first inverter, a first capacitor, and a driving unit; The input terminal of the level shifter is connected to the second output terminal of the drive signal control module. The output terminal of the level shifter is connected to the input terminal of the first buffer and the input terminal of the first inverter respectively. The output terminal of the first buffer is connected to the first control terminal of the drive unit. The output terminal of the first inverter is connected to the second control terminal of the drive unit. The first buffer is connected to the first inverter via the first capacitor. The input terminals of the first inverter and the driving unit are both connected to the negative DC power supply. The first output terminal of the driving unit is connected to the gate of the high-voltage depletion-type transistor. The second output terminal of the driving unit and the first buffer are both connected to the source of the low-voltage enhancement-type transistor.
[0011] As one possible implementation, the driving unit includes: a second N-type metal-oxide-semiconductor transistor and a third N-type metal-oxide-semiconductor transistor; The gate of the second N-type metal-oxide-semiconductor transistor is connected to the output terminal of the first buffer. The drain of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the low-voltage enhancement-mode transistor. The source of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the third N-type metal-oxide-semiconductor transistor. The source of the third N-type metal-oxide-semiconductor transistor is connected to the negative DC power supply. The source and drain of the second and third N-type metal-oxide-semiconductor transistors are also connected to the gate of the high-voltage depletion-mode transistor.
[0012] As one possible implementation, the above-mentioned drive signal control module includes: an input unit, a first logic processing unit, and a second logic processing unit; The input terminal of the input unit is used to receive external input signals. The first output terminal of the input unit is connected to the first input terminal of the first logic processing unit and the first input terminal of the second logic processing unit, respectively. The second output terminal of the input unit is connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit, respectively. The third input terminal of the second logic processing unit is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module, respectively. The first output terminal of the second logic processing unit is connected to the third input terminal of the first logic processing unit. The second output terminal of the second logic processing unit is connected to the gate of the low-voltage enhancement-mode transistor. The output terminal of the first logic processing unit is connected to the second input terminal of the drive module.
[0013] As one possible implementation, the above input unit includes: a second buffer and a level holder; The input terminal of the second buffer is used to receive external input signals. The output terminal of the second buffer is connected to the first input terminal of the first logic processing unit, the first input terminal of the second logic processing unit, and the input terminal of the level holder, respectively. The output terminal of the level holder is connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit, respectively.
[0014] As one possible implementation, the aforementioned level holder includes: a diode, a resistor, and a second capacitor; The input terminal of the diode and one end of the resistor are both connected to the output terminal of the second buffer. The output terminal of the diode, one end of the second capacitor, and the other end of the resistor are all connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit.
[0015] As one possible implementation, the first logic processing unit includes: a first AND gate, a second inverter, and a first OR gate; The first input terminal of the first AND gate is connected to the output terminal of the second buffer, the second input terminal of the first AND gate is connected to the first output terminal of the second logic processing unit, and the output terminal of the first AND gate is connected to the first input terminal of the first OR gate. The input of the second inverter is connected to the output of the level holder, the output of the second inverter is connected to the second input of the first OR gate, and the output of the first OR gate is connected to the second input of the driver module.
[0016] As one possible implementation, the second logic processing unit includes: a second OR gate, a second AND gate, a third buffer, and a voltage detector; The first input of the second OR gate is connected to the output of the second buffer, the second input of the second OR gate is connected to the output of the level hold, and the output of the second OR gate is connected to the first input of the second AND gate. The input terminal of the voltage detector is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module, respectively. The output terminal of the voltage detector is connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is connected to the second input terminal of the first AND gate and the input terminal of the third buffer, respectively. The output terminal of the third buffer is connected to the gate of the low-voltage enhancement-mode transistor.
[0017] A second aspect of this application provides an integrated power switching device, which includes: a control circuit and a cascaded structure as described in the first aspect above, wherein a first output terminal of the control circuit is connected to the gate of a high-voltage depletion-type transistor in the cascaded structure, and a second output terminal of the control circuit is connected to the gate of a low-voltage enhancement-type transistor in the cascaded structure.
[0018] A third aspect of this application provides a power system in which the integrated power switching device described in the second aspect is deployed.
[0019] The beneficial effects of the embodiments of this application include: This application provides a cascaded control circuit that converts the power supply voltage provided by an external positive DC power supply into the operating voltage required by the electronic devices inside the chip containing the cascaded structure and control circuit through a power conversion module. The power conversion module converts the power supply voltage provided by a negative DC power supply into the negative turn-off voltage required by the high-voltage depletion-type transistor through an internally integrated logic circuit, and transmits it to the gate of the high-voltage depletion-type transistor via a drive module. The drive signal control module samples the real-time voltage of each key voltage point of the control circuit through a sampling terminal and determines the over- or under-voltage state of each key voltage point. Based on the externally input pulse width modulation signal and the voltage detection results of each key voltage point of the control circuit, the drive signal control module controls the switching on and off of the low-voltage enhancement-type transistor and sends the corresponding logic level to the drive module. The drive module controls the switching on and off of the high-voltage depletion-type transistor based on the received logic level and the negative voltage drive signal. In this design, the drive signal control module maintains direct drive control for a period of time via a level-holding circuit, then automatically switches the control logic, turning off the low-voltage enhancement-mode transistor. Simultaneously, the drive module ensures that the gate voltage of the high-voltage depletion-mode transistor follows its threshold voltage, switching the cascaded structure to a common-source, common-gate operating mode. This significantly reduces gate voltage stress and improves device reliability. Thus, it achieves the effect of improving the reliability of the cascaded structure while ensuring good switching performance. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram illustrating the working principle of an existing cascaded structure in direct drive mode. Figure 2 This is a schematic diagram illustrating the working principle of an existing cascaded structure in common source, common gate mode. Figure 3 A schematic diagram of the control circuit for the first cascaded structure provided in this application embodiment; Figure 4 This is a schematic diagram of the control circuit for the second cascaded structure provided in the embodiments of this application; Figure 5 A schematic diagram of the control circuit for the third cascaded structure provided in this application embodiment; Figure 6 This is a schematic diagram of the structure of an integrated power device provided in an embodiment of this application; Figure 7 A schematic diagram of the power system provided in the embodiments of this application.
[0022] Reference numerals: 10: Control circuit; 101: Power conversion module; 1011: Switching unit; 111: P-type metal-oxide-semiconductor transistor; 112: First N-type metal-oxide-semiconductor transistor; 1012: Buck-boost converter; 1013: Linear regulator; 102: Drive signal control module; 1021: Input unit; 211: Second buffer; 212: Level holder; 2121: Diode; 2122: Resistor; 2123: Second capacitor; 1022: First logic processing unit; 221: First AND gate; 222: Second inverter; 223: First OR gate. Gate; 1023: Second logic processing unit; 231: Second OR gate; 232: Second AND gate; 233: Third buffer; 234: Voltage detector; 103: Driver module; 1031: Level shifter; 1032: First buffer; 1033: First inverter; 1034: First capacitor; 1035: Driver unit; 351: Second N-type metal-oxide-semiconductor transistor; 352: Third N-type metal-oxide-semiconductor transistor; 20: Cascaded structure; 201: High-voltage depletion-mode transistor; 202: Low-voltage enhancement-mode transistor; 30: Power switching device; 40: Power system. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0024] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0026] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0027] Cascading structures, a common implementation of gallium nitride (GaN) power devices, typically consist of a low-voltage enhancement-mode silicon transistor connected in series with a high-voltage depletion-mode GaN transistor. However, due to different driving methods, cascaded structures are often classified into direct-drive structures and cascode structures.
[0028] direct drive structure such as Figure 1 As shown, the low-voltage enhancement-mode silicon transistor Q2 is continuously turned on under the drive of the gate voltage Vcc, and a pulse width modulation signal is directly applied to the gate of the high-voltage depletion-mode gallium nitride transistor Q1 to directly control the gate drive of the high-voltage depletion-mode gallium nitride transistor Q1, thereby realizing the turn-on or turn-off control of the entire cascaded structure. The externally input pulse width modulation signal can directly control the drive of the high-voltage depletion-mode gallium nitride transistor Q1 in the cascaded structure, which can better adjust the switching speed of the entire cascaded structure and greatly reduce the switching losses of the cascaded structure. However, due to the large threshold voltage range of the high-voltage depletion-mode gallium nitride transistor Q1 in the direct-drive structure, it is difficult to adapt the drive voltage of the high-voltage depletion-mode gallium nitride transistor Q1. In particular, when the direct-drive structure is in static operation, the static difference between the gate-source voltage and the threshold voltage of the high-voltage depletion-mode gallium nitride transistor Q1 will increase, which will greatly reduce the gate reliability of the high-voltage depletion-mode gallium nitride transistor Q1, thus leading to a significant decrease in the reliability of the entire cascaded structure.
[0029] Common source and common gate structure, such as Figure 2As shown, the front-end drive circuit directly applies the pulse width modulation signal to the gate of the low-voltage enhancement-mode silicon transistor Q2, controlling the on / off state of the entire cascaded structure by controlling the on / off state of Q2. While this operating mode allows the high-voltage depletion-mode gallium nitride transistor Q1 to exhibit enhancement-mode characteristics, it cannot directly control the switching speed of Q1, making it difficult to adjust the switching speed of the entire cascaded structure and resulting in poor switching flexibility. Furthermore, the cascode structure allows the gate voltage of Q1 to automatically follow its threshold voltage when it is statically off, significantly reducing the static difference and improving its gate reliability. However, the body diode of the low-voltage enhancement-mode silicon transistor Q2 introduces a reverse recovery process, which increases the switching losses of the entire cascaded structure.
[0030] In summary, existing driving methods for cascaded structures struggle to balance the switching performance and reliability of these structures.
[0031] Currently, to obtain cascaded structures with better switching performance, the reliability of the entire cascaded structure is typically improved by reducing the static voltage drop of the high-voltage depletion-mode gallium nitride (GaN) transistor in the direct-drive structure. However, the threshold voltage of the high-voltage GaN transistor has a wide voltage range distribution, making it difficult to control the threshold voltage of the high-voltage GaN transistor within a specific small voltage range. The only solution is to select suitable components to match the drive voltage of the high-voltage GaN transistor, but this component selection method significantly reduces the production yield of the cascaded structure.
[0032] To address this, this application provides a control circuit for a cascaded structure. A power conversion module and an external negative DC power supply provide a negative drive signal to the gate drive module of the high-voltage depletion-type transistor (HMT). Simultaneously, a drive signal control module provides a logic level to the HMT gate drive module based on voltage detection results at key voltage points and an externally input pulse-width modulation (PWM) signal. Under the combined action of the logic level and the negative drive signal, the drive module controls the on / off state of the HMT. Furthermore, under the combined action of the external PWM signal and the voltage detection results at key voltage points, the drive signal control module sends corresponding drive signals to the low-voltage enhancement-type transistor (EDT) to control its on / off state. This achieves the goal of improving the reliability of the cascaded structure while ensuring good switching performance.
[0033] The control circuit, integrated power device, and power system of the cascaded structure provided in the embodiments of this application will be explained in detail below with reference to the accompanying drawings.
[0034] Figure 3 A schematic diagram of a cascaded control circuit provided in this application is shown below. Figure 3 This application provides a cascaded control circuit 10 including a power conversion module 101, a drive signal control module 102, and a drive module 103. The cascaded structure 20 includes a high-voltage depletion-type transistor 201 and a low-voltage enhancement-type transistor 202, with the source of the high-voltage depletion-type transistor 201 connected to the drain of the low-voltage enhancement-type transistor 202.
[0035] The first input terminal of the power conversion module 101 is connected to the positive DC power supply, the second input terminal of the power conversion module 101 and the first input terminal of the drive module 103 are both connected to the negative DC power supply, the first output terminal of the power conversion module 101 is connected to the power supply terminal of the chip, and the power conversion module 101 is also connected to an external switch node.
[0036] Optionally, the first input terminal of the power conversion module 101 is connected to the positive DC power supply, the second input terminal of the power conversion module 101 and the first input terminal of the drive module 103 are both connected to the negative DC power supply, and the first output terminal of the power conversion module 101 is connected to the power supply terminal of the chip. The power conversion module 101 is used to convert the DC voltage provided by the positive DC power supply into the working voltage, and input the working voltage through the power supply terminal of the chip integrated by the cascade structure 20 and the control circuit 10, so as to provide a stable and suitable working voltage for each electronic device in the entire cascade structure 20 and each electronic device in the control circuit 10 of the cascade structure.
[0037] The positive DC power supply connected to the first input terminal of the power conversion module 101 can be +12V, and the negative DC power supply connected to the second input terminal of the power conversion module 101 can be -14V. This application does not make specific limitations on this.
[0038] Optionally, the power conversion module 101 is also connected to an external switching node (SW). The power conversion module 101 controls the switching of the switching transistor connected between the positive DC power supply and the negative DC power supply through an internal buck-boost controller, thereby regulating and stabilizing the negative drive voltage provided by the negative DC power supply, and thus providing an adjustable negative drive signal for the high voltage depletion transistor 201.
[0039] The input terminal of the drive signal control module 102 is used to receive external input signals. The sampling terminal of the drive signal control module 102 is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module 101 respectively. The first output terminal of the drive signal control module 102 is connected to the gate of the low-voltage enhancement-mode transistor 202. The second output terminal of the drive signal control module 102 is connected to the second input terminal of the drive module 103. The first output terminal of the drive module 103 is connected to the gate of the high-voltage depletion-mode transistor 201. The second output terminal of the drive module 103 is connected to the source of the low-voltage enhancement-mode transistor 202.
[0040] Optionally, the input terminal of the drive signal control module 102 is used to receive external input signals, and the sampling terminal of the drive signal control module 102 samples the positive DC voltage provided by the positive DC power supply, the negative drive signal provided by the negative DC power supply, and the operating voltage provided by the power conversion module 101 to the chip, so as to monitor the voltage status of each key voltage point of the control circuit 10 in real time.
[0041] Optionally, the drive signal control module 102 integrates an undervoltage lockout circuit (such as a UVLO circuit) and a logic control circuit (such as an AND gate, an OR gate, an inverter, a level holder, and other electronic devices). The drive signal control module 102 determines the voltage detection results of each key voltage point of the control circuit 10, i.e., the overvoltage and undervoltage detection status, based on the real-time voltage of each key voltage point sampled by the sampling terminal.
[0042] Furthermore, the drive signal control module 102 determines whether the control circuit 10 is within the normal operating voltage range at the current moment based on the external input signal and the voltage detection results corresponding to each key voltage point sampled by the sampling terminal, and generates the corresponding control logic level accordingly.
[0043] The drive signal control module 102 controls the low-voltage enhancement transistor 202 to turn on or off based on the external input signal and the voltage detection result obtained from the electrical signal collected by the sampling terminal of the drive signal control module 102, and sends the corresponding logic level to the drive module 103 through the second output terminal of the drive signal control module 102.
[0044] Optionally, the drive signal control module 102 directly sends a gate drive signal to the low-voltage enhancement-mode transistor 202 through its first output terminal to control the turn-on or turn-off of the low-voltage enhancement-mode transistor 202. Simultaneously, the drive signal control module 102 sends a corresponding logic level to the drive module 103 through its second output terminal.
[0045] The drive module 103 controls the high-voltage depletion transistor 201 to turn on or off based on the logic level and the negative drive signal of the negative DC power input.
[0046] Optionally, the first input terminal of the drive module 103 is used to receive the negative drive signal provided by the negative DC power supply, and the second input terminal of the drive module 103 is used to receive the logic level provided by the drive signal control module 102. The drive module 103 sends a gate drive signal to the high voltage depletion transistor 201 based on the received negative drive signal and logic level to control the high voltage depletion transistor 201 to turn on or off.
[0047] It should be noted that, under normal switching conditions, the external input signal is a pulse width modulation signal.
[0048] Specifically, when the pulse width modulation signal of the input control circuit 10 is high, the drive signal control module 102 applies a high level to the gate of the low-voltage enhancement-mode transistor 202 through its first output terminal to drive the low-voltage enhancement-mode transistor 202 to conduct. Simultaneously, the drive signal control module 102 sends a high logic level to the drive module 103 through its second output terminal. Under the influence of this high level, the drive module 103 controls the high-voltage depletion-mode transistor 201 to conduct, and the gate of the high-voltage depletion-mode transistor 201 is coupled to the source of the low-voltage enhancement-mode transistor 202, so that the entire cascaded structure 20 operates in direct-drive mode.
[0049] Furthermore, when the pulse width modulation signal of the input control circuit 10 is low, the drive signal control module 102 applies a high level to the gate of the low-voltage enhancement-mode transistor 202 through its first output terminal to drive the low-voltage enhancement-mode transistor 202 to conduct. Simultaneously, the drive signal control module 102 sends a low logic level to the drive module 103 through its second output terminal. Under the influence of this low level, the drive module 103 controls the high-voltage depletion-mode transistor 201 to couple to the negative DC power supply, turning off the high-voltage depletion-mode transistor 201. The entire cascaded structure 20 still operates in direct-drive mode.
[0050] Furthermore, when the pulse width modulation signal of the input control circuit 10 remains low, it indicates that the entire cascaded structure 20 is in standby or long-term static off state. The drive signal control module 102 applies a low level to the gate of the low-voltage enhancement-mode transistor 202 through the first output terminal to drive the low-voltage enhancement-mode transistor 202 to turn off. At the same time, the drive signal control module 102 sends a high level logic level to the drive module 103 through the second output terminal. Under the action of the high level, the drive module 103 controls the gate of the high-voltage depletion-mode transistor 201 to couple to the source of the low-voltage enhancement-mode transistor 202, so that the high-voltage depletion-mode transistor 201 turns off along with the low-voltage enhancement-mode transistor 202, and the entire cascaded structure 20 operates in common-source common-gate mode.
[0051] In this embodiment, a power conversion module converts the power supply voltage provided by an external positive DC power supply into the operating voltage required by the electronic devices inside the chip containing the cascaded structure and control circuit. The power conversion module converts the power supply voltage provided by a negative DC power supply into the negative turn-off voltage required by the high-voltage depletion-type transistor through an internally integrated logic circuit, and transmits it to the gate of the high-voltage depletion-type transistor via a drive module. The drive signal control module samples the real-time voltage of each key voltage point of the control circuit through a sampling terminal and determines the over- or under-voltage state of each key voltage point. Based on the externally input pulse width modulation signal and the voltage detection results of each key voltage point of the control circuit, the drive signal control module controls the switching on and off of the low-voltage enhancement-type transistor, and simultaneously sends the corresponding logic level to the drive module. The drive module controls the switching on and off of the high-voltage depletion-type transistor based on the received logic level and the negative voltage drive signal. In this design, the drive signal control module maintains direct drive control for a period of time via a level-holding circuit, then automatically switches the control logic, turning off the low-voltage enhancement-mode transistor. Simultaneously, the drive module ensures that the gate voltage of the high-voltage depletion-mode transistor follows its threshold voltage, switching the cascaded structure to a common-source, common-gate operating mode. This significantly reduces gate voltage stress and improves device reliability. Thus, it achieves the effect of improving the reliability of the cascaded structure while ensuring good switching performance.
[0052] In one alternative implementation, see [link to implementation details]. Figure 4 The power conversion module 101 in the cascaded control circuit 10 provided in this application embodiment includes: a switching conversion unit 1011, a buck-boost converter 1012, and a linear regulator 1013.
[0053] The first terminal of the switching unit 1011 and the input terminal of the linear regulator 1013 are connected to the positive DC power supply, and the output terminal of the linear regulator 1013 is connected to the power supply terminal of the chip.
[0054] Optionally, the linear regulator 1013 is used to step down and regulate the positive DC voltage provided by the positive DC power supply, providing a stable power supply voltage (such as +5V) for the logic control circuits, level conversion circuits, etc. inside the chip, thereby reducing the internal power consumption of the chip and improving the overall efficiency.
[0055] The control terminal of the switching unit 1011 is connected to the buck-boost converter 1012, the second terminal of the switching unit 1011 is connected to an external switching node, and the third terminal of the switching unit 1011 is connected to the negative DC power supply.
[0056] Optionally, the switching conversion unit 1011 is used in conjunction with the buck-boost converter 1012 to generate an adjustable negative voltage drive signal. The first terminal of the switching conversion unit 1011 is a high-voltage input terminal, used to receive the positive DC voltage provided by the positive DC power supply; the second terminal of the switching conversion unit 1011 serves as a switching node terminal, connected to an external switching node (SW), which is a key node for power conversion in the power conversion module 101; the third terminal of the switching conversion unit 1011 is a low-voltage reference terminal, connected to the negative DC power supply.
[0057] Optionally, the buck-boost converter 1012 is connected to the control terminal of the switching unit 1011. By outputting a pulse width modulation (PWM) or pulse frequency modulation (PFM) signal, it controls the turn-on and turn-off timing of the switching devices in the switching unit 1011, thereby adjusting the voltage at the external switching node (SW). Finally, a stable and adjustable negative voltage drive signal is formed on the negative DC power supply line to provide a reliable turn-off voltage for the gate of the high-voltage depletion transistor 201.
[0058] In one alternative implementation, see [link to implementation details]. Figure 5 The switching unit 1011 in the cascaded control circuit 10 provided in this application embodiment includes: a P-type metal-oxide-semiconductor transistor 111 and a first N-type metal-oxide-semiconductor transistor 112.
[0059] The source of the P-type metal oxide semiconductor transistor 111 is connected to the positive DC power supply, the drain of the P-type metal oxide semiconductor transistor 111 is connected to the drain of the first N-type metal oxide semiconductor transistor 112, and the gates of both the P-type metal oxide semiconductor transistor 111 and the first N-type metal oxide semiconductor transistor 112 are connected to the buck-boost converter 1012. The source of the first N-type metal-oxide-semiconductor transistor 112 is connected to the negative DC power supply, and the drain of both the P-type metal-oxide-semiconductor transistor 111 and the drain of the first N-type metal-oxide-semiconductor transistor 112 are connected to an external switching node.
[0060] Optionally, the buck-boost converter 1012 generates an AC voltage waveform at the switching node (SW) by controlling two complementary switching transistors, the P-type metal-oxide-semiconductor transistor 111 and the first N-type metal-oxide-semiconductor transistor 112 (i.e., alternately turning on and off). The waveform is then filtered and level-shifted by an external filter network, and finally generates a stable negative voltage on the power line of the negative DC power supply that is required for the normal turn-off of the high-voltage depletion transistor 201.
[0061] In one alternative implementation, see [link to implementation details]. Figure 4The drive module 103 in the cascaded control circuit 10 provided in this application embodiment includes: a level shifter 1031, a first buffer 1032, a first inverter 1033, a first capacitor 1034, and a drive unit 1035.
[0062] The input terminal of the level shifter 1031 is connected to the second output terminal of the drive signal control module 102. The output terminal of the level shifter 1031 is connected to the input terminal of the first buffer 1032 and the input terminal of the first inverter 1033. The output terminal of the first buffer 1032 is connected to the first control terminal of the drive unit 1035. The output terminal of the first inverter 1033 is connected to the second control terminal of the drive unit 1035. The first buffer 1032 is connected to the first inverter 1033 via the first capacitor 1034.
[0063] Optionally, the level shifter 1031 receives the logic level output from the second output terminal of the drive signal control module 102 through its input terminal. The function of the level shifter 1031 is to shift the voltage reference point of the logic level so that its level range is adapted to the drive module 103 which uses negative voltage as a reference.
[0064] Optionally, the output of the level shifter 1031 is connected to the input of the first buffer 1032 and the input of the first inverter 1033, respectively. The first buffer 1032 is used to enhance the driving capability and isolate the preceding and following stages, and the first inverter 1033 is used to generate a control signal that is inverted from the input signal.
[0065] Optionally, the first capacitor 1034 is connected between the first buffer 1032 and the first inverter 1033, mainly for signal conditioning, such as filtering noise, improving signal edges, or providing delay, to optimize the timing relationship between the two control signals and prevent the risk of simultaneous conduction of the upper and lower power transistors in the drive unit 1035.
[0066] The input terminals of the first inverter 1033 and the driving unit 1035 are both connected to the negative DC power supply. The first output terminal of the driving unit 1035 is connected to the gate of the high-voltage depletion-type transistor 201. The second output terminal of the driving unit 1035 and the first buffer 1032 are both connected to the source of the low-voltage enhancement-type transistor 202.
[0067] Optionally, the input terminals of the first inverter 1033 and the drive unit 1035 are both connected to the negative DC power supply to obtain the voltage reference ground for their operation.
[0068] Optionally, the first output terminal of the driving unit 1035 is directly connected to the gate of the high-voltage depletion transistor 201 to provide the gate driving voltage required for the high-voltage depletion transistor 201 to turn on or off; the second output terminal of the driving unit 1035 and the output reference terminal of the first buffer 1032 are both connected to the source of the low-voltage enhancement transistor 202 to form a return path for the driving signal and ensure the establishment of the gate-source voltage of the high-voltage depletion transistor 201 in direct drive mode.
[0069] In one alternative implementation, see [link to implementation details]. Figure 5 The drive unit 1035 in the cascaded control circuit 10 provided in this application embodiment includes: a second N-type metal oxide semiconductor transistor 351 and a third N-type metal oxide semiconductor transistor 352.
[0070] The gate of the second N-type metal-oxide-semiconductor transistor 351 is connected to the output terminal of the first buffer 1032. The drain of the second N-type metal-oxide-semiconductor transistor 351 is connected to the drain of the low-voltage enhancement-mode transistor 202. The source of the second N-type metal-oxide-semiconductor transistor 351 is connected to the drain of the third N-type metal-oxide-semiconductor transistor 352. The source of the third N-type metal-oxide-semiconductor transistor 352 is connected to the negative DC power supply. The source of the second N-type metal-oxide-semiconductor transistor 351 and the drain of the third N-type metal-oxide-semiconductor transistor 352 are also connected to the gate of the high-voltage depletion-mode transistor 201.
[0071] Optionally, the gate of the second N-type metal-oxide-semiconductor transistor 351 is the first control terminal of the driving unit 1035 and is connected to the output terminal of the first buffer 1032; its source is connected to the drain of the third N-type metal-oxide-semiconductor transistor 352, together serving as the first output terminal of the driving unit 1035, directly driving the gate of the high-voltage depletion transistor 201.
[0072] Optionally, the gate of the third N-type metal-oxide-semiconductor transistor 352 is the second control terminal of the driving unit 1035 and is connected to the output terminal of the first inverter 1033; its source is directly connected to the negative DC power supply to obtain the negative driving signal provided by the negative DC power supply.
[0073] Optionally, the drive module 103 can control the second N-type metal-oxide-semiconductor transistor 351 and the third N-type metal-oxide-semiconductor transistor 352 to alternately conduct by outputting complementary control signals (i.e., when one is high level, the other is low level) through the first buffer 1032 and the first inverter 1033.
[0074] Specifically, when it is necessary to turn on the high-voltage depletion transistor 201 (i.e., the cascaded structure 20 enters direct drive mode), the second N-type metal-oxide-semiconductor transistor 351 is turned on and the third N-type metal-oxide-semiconductor transistor 352 is turned off, thereby pulling the gate potential of the high-voltage depletion transistor 201 up to a potential close to the source potential; when it is necessary to reliably turn off the high-voltage depletion transistor 201, the second N-type metal-oxide-semiconductor transistor 351 is turned off and the third N-type metal-oxide-semiconductor transistor 352 is turned on, thereby pulling the gate potential of the high-voltage depletion transistor 201 down to the negative drive voltage provided by the negative DC power supply, providing sufficient negative voltage turn-off capability.
[0075] In one alternative implementation, see [link to implementation details]. Figure 4 The drive signal control module 102 in the cascaded control circuit 10 provided in this application embodiment includes: an input unit 1021, a first logic processing unit 1022, and a second logic processing unit 1023.
[0076] The input terminal of the input unit 1021 is used to receive external input signals. The first output terminal of the input unit 1021 is connected to the first input terminal of the first logic processing unit 1022 and the first input terminal of the second logic processing unit 1023, respectively. The second output terminal of the input unit 1021 is connected to the second input terminal of the first logic processing unit 1022 and the second input terminal of the second logic processing unit 1023, respectively.
[0077] Optionally, the input unit 1021 receives external input signals via its input terminal, and sends the processed logic signals to the first logic processing unit 1022 and the second logic processing unit 1023 respectively via its first output terminal and second output terminal.
[0078] Optionally, the first input terminal and the second input terminal of the first logic processing unit 1022 are respectively used to receive logic signals output from the first output terminal and the second output terminal of the input unit 1021, and the third input terminal of the first logic processing unit 1022 is used to receive feedback signals from the second logic processing unit 1023. The first logic processing unit 1022 sends corresponding logic signals to the drive module 103 based on the received logic signals and feedback signals to control the working mode of the drive module 103.
[0079] The third input terminal of the second logic processing unit 1023 is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module 101 respectively. The first output terminal of the second logic processing unit 1023 is connected to the third input terminal of the first logic processing unit 1022. The second output terminal of the second logic processing unit 1023 is connected to the gate of the low-voltage enhancement-mode transistor 202. The output terminal of the first logic processing unit 1022 is connected to the second input terminal of the drive module 103.
[0080] Optionally, the first input terminal and the second input terminal of the second logic processing unit 1023 are used to receive the logic signals output from the first output terminal and the second output terminal of the input unit 1021, respectively. The third input terminal of the second logic processing unit 1023 serves as the sampling terminal of the driving module 103 and is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module 101, respectively, to monitor the real-time voltage of each key voltage point of the control circuit 10.
[0081] In addition, the first output terminal of the second logic processing unit 1023 is connected to the third input terminal of the first logic processing unit 1022 to provide enable or status feedback for the second logic processing unit 1023; the second output terminal of the second logic processing unit 1023 is directly connected to the gate of the low-voltage enhancement-mode transistor 202 to control its turn-on and turn-off.
[0082] In one alternative implementation, see [link to implementation details]. Figure 4 The input unit 1021 in the cascaded control circuit 10 provided in this application embodiment includes: a second buffer 211 and a level holder 212.
[0083] The input terminal of the second buffer 211 is used to receive external input signals. The output terminal of the second buffer 211 is connected to the first input terminal of the first logic processing unit 1022, the first input terminal of the second logic processing unit 1023, and the input terminal of the level holder 212. The output terminal of the level holder 212 is connected to the second input terminal of the first logic processing unit 1022 and the second input terminal of the second logic processing unit 1023.
[0084] Optionally, the input terminal of the second buffer 211 is used to receive external input signals to perform signal shaping, enhance driving force and provide electrical isolation for the external input signals. One output signal of the second buffer 211 is directly used as the first output of the input unit 1021 and sent to the subsequent first logic processing unit 1022 and second logic processing unit 1023; the other output signal of the second buffer 211 is directly sent to the input terminal of the level holder 212.
[0085] Optionally, the input of the level hold 212 is connected to the output of the second buffer 211, and the output of the level hold 212 serves as the second output of the input unit 1021. The level hold 212 maintains the level of the previous state for a period of time when the input signal undergoes a brief change or enters a static state, providing a delay window for safe switching of operating modes.
[0086] In one alternative implementation, see [link to implementation details]. Figure 5 The level holder 212 in the cascaded control circuit 10 provided in this application embodiment includes: a diode 2121, a resistor 2122, and a second capacitor 2123.
[0087] The input terminal of diode 2121 and one end of resistor 2122 are both connected to the output terminal of second buffer 211. The output terminal of diode 2121, one end of second capacitor 2123 and the other end of resistor 2122 are both connected to the second input terminal of first logic processing unit 1022 and the second input terminal of second logic processing unit 1023.
[0088] Optionally, the input terminal of diode 2121 and one end of resistor 2122 are connected together to the output terminal of second buffer 211 for unidirectional conduction processing of external input signals; the output terminal of diode 2121, the other end of resistor 2122 and one end of second capacitor 2123 are connected together to form the output terminal of level holder 212.
[0089] Optionally, when the input signal is high, the second capacitor 2123 is charged through the diode 2121 to maintain it at a high level; when the input signal becomes low, the second capacitor 2123 is slowly discharged through the resistor 2122, thereby achieving the function of maintaining the level.
[0090] In one alternative implementation, see [link to implementation details]. Figure 5 The first logic processing unit 1022 in the cascaded control circuit 10 provided in this application embodiment includes: a first AND gate 221, a second inverter 222, and a first OR gate 223.
[0091] The first input terminal of the first AND gate 221 is connected to the output terminal of the second buffer 211, the second input terminal of the first AND gate 221 is connected to the first output terminal of the second logic processing unit 1023, and the output terminal of the first AND gate 221 is connected to the first input terminal of the first OR gate 223. The input terminal of the second inverter 222 is connected to the output terminal of the level holder 212, the output terminal of the second inverter 222 is connected to the second input terminal of the first OR gate 223, and the output terminal of the first OR gate 223 is connected to the second input terminal of the driver module 103.
[0092] Optionally, the first input terminal of the first AND gate 221 is connected to the first output terminal of the input unit 1021 (i.e., the output terminal of the second buffer 211), and the second input terminal is connected to the first output terminal of the second logic processing unit 1023 (i.e., the voltage detection enable signal). The first AND gate 221 is used to perform a logical AND operation on the logic signal output by the input unit 1021 and the feedback signal of the second logic processing unit 1023, and input the logical operation result into the first input terminal of the first OR gate 223.
[0093] Optionally, the input terminal of the second inverter 222 is connected to the second output terminal of the input unit 1021 (i.e., the output terminal of the level holder 212) to logically invert the level held by the level holder 212.
[0094] Optionally, the first input terminal of the first OR gate 223 is connected to the output terminal of the first AND gate 221, and the second input terminal of the first OR gate 223 is connected to the output terminal of the second inverter 222. The output terminal of the first OR gate 223 is the output terminal of the first logic processing unit 1022. The OR logic operation result of the first OR gate 223 is directly sent to the driver module 103 to determine its working mode.
[0095] In one alternative implementation, see [link to implementation details]. Figure 5 The second logic processing unit 1023 in the cascaded control circuit 10 provided in this application embodiment includes: a second OR gate 231, a second AND gate 232, a third buffer 233, and a voltage detector 234.
[0096] The first input terminal of the second OR gate 231 is connected to the output terminal of the second buffer 211, the second input terminal of the second OR gate 231 is connected to the output terminal of the level holder 212, and the output terminal of the second OR gate 231 is connected to the first input terminal of the second AND gate 232. The input terminal of voltage detector 234 is connected to the positive DC power supply, the negative DC power supply and the first output terminal of power conversion module 101 respectively. The output terminal of voltage detector 234 is connected to the second input terminal of second AND gate 232. The output terminal of second AND gate 232 is connected to the second input terminal of first AND gate 221 and the input terminal of third buffer 233 respectively. The output terminal of third buffer 233 is connected to the gate of low voltage enhancement transistor 202.
[0097] Optionally, the first input terminal of the second OR gate 231 is connected to the first output terminal of the input unit 1021, the second input terminal of the second OR gate 231 is connected to the second output terminal of the input unit 1021, and the output terminal of the second OR gate 231 is connected to the first input terminal of the second AND gate 232, for integrating the state of the instantaneous input signal and the held signal.
[0098] Optionally, the input terminal of the voltage detector 234 is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module 101, respectively, to monitor whether the real-time voltage of these key voltage nodes is within the normal operating voltage range. The output terminal of the voltage detector 234 is connected to the second input terminal of the second AND gate 232, and outputs a valid high-level "enable" signal when all monitored voltage points are normal.
[0099] Optionally, the first input of the second AND gate 232 receives the output signal of the second OR gate 231, and the second input receives the enable signal of the voltage detector 234. Its output is high only when both inputs are high (i.e., there is a valid input signal logic and the system power supply is normal). One path of this output signal serves as the first output of the second logic processing unit 1023, feeding back to the second input of the first AND gate 221 as a prerequisite enable condition for the entire logic path; the other path is sent to the third buffer 233.
[0100] Optionally, the input of the third buffer 233 is connected to the output of the second AND gate 232 to enhance the driving capability, and its output serves as the second output of the second logic processing unit 1023 to directly drive the gate of the low-voltage enhancement transistor 202.
[0101] Specifically, when the external input signal is a normal pulse width signal, the circuit operates in direct drive mode. If the external input signal is high, the output signal of the second buffer 211 is also high, and the output response of the second OR gate 231 is high. At this time, the control circuit is powered normally, the voltage detector 234 outputs a high level, the second AND gate 232 outputs a high level, and after passing through the third buffer 233, it outputs a high level, driving the low-voltage enhancement transistor 202 to conduct. At the same time, the first input and the second input of the first AND gate 221 are both high, and the output response of the first AND gate 221 is high. The first input of the first OR gate 223 is high, and the output response of the first OR gate 223 is high. After passing through the level shifter 1031 for level conversion, the output logic high level is given to the first inverter 1033. After passing through the first inverter 1033, the output low level is given to the third N-type metal-oxide-semiconductor transistor 352, and the third N-type metal-oxide-semiconductor transistor 352 is not conducting at this time. The level shifter 1031 outputs a high level to the first buffer 1032, and the high level output from the first buffer 1032 is then sent to the second N-type metal-oxide-semiconductor transistor 351, which is now turned on. The gate of the high-voltage depletion-type transistor 201 is coupled to the source of the low-voltage enhancement-type transistor 202 through the second N-type metal-oxide-semiconductor transistor 351. At this time, the gate-source voltage of the high-voltage depletion-type transistor 201 is approximately equal to the drain-source voltage of the low-voltage enhancement-type transistor 202, and the high-voltage depletion-type transistor 201 is turned on, and the circuit operates in direct-drive mode.
[0102] Furthermore, when the external input signal is a normal pulse width signal, the circuit operates in direct drive mode. If the external input signal is low, the output of the second buffer 211 is also low. The level holder 212 maintains the high level of the previous state, so the first input of the second OR gate 231 is high, the second output is low, and the output response of the second OR gate 231 is high. At this time, the circuit is powered normally, the voltage detector 234 outputs a high level, the second AND gate 232 outputs a high level, and after passing through the third buffer 233, it outputs a high level, driving the low-voltage enhancement-type transistor 202 to conduct. At the same time, the first input of the first AND gate 221 is low, and the second input of the first AND gate 221 is high, so the output response of the first AND gate 221 is low, serving as the first input of the first OR gate 223. The level holder 212 simultaneously outputs a high level to the second inverter 222, and after passing through the second inverter 222, it outputs a low level, serving as the second input of the first OR gate 223. Both the first and second inputs of the first OR gate 223 are low, so the output of the first OR gate 223 is low. This output is then level-shifted by the level shifter 1031, resulting in a low-level output that is sent to the first buffer 1032. The low-level output of the first buffer 1032 is then sent to the second N-type metal-oxide-semiconductor transistor 351, which is now off. The low-level output is sent to the first inverter 1033, which then sends a high-level output to the third N-type metal-oxide-semiconductor transistor 352, turning it on. The gate of the low-voltage enhancement-mode transistor 202 is coupled to the negative voltage drive signal through the third N-type metal-oxide-semiconductor transistor 352. At this time, the gate voltage of the high-voltage depletion-mode transistor 201 is -14V, turning it off, and the circuit operates in direct-drive mode.
[0103] Optionally, when in standby mode, the input signal remains low, and the output of the second buffer 211 is also low. The output of the level holder 212 is low, so both the first input and second output of the second OR gate 231 are low, resulting in a low-level output response from the second OR gate 231. At this time, the circuit is powered normally, the output of the voltage detector 234 is high, and the output of the second AND gate 232 is low. After passing through the third buffer 233, the output is low, driving the low-voltage enhancement-mode transistor 202 to turn off. Simultaneously, both the first and second inputs of the first AND gate 221 are low, so the output of the first AND gate 221 is low, serving as the first input of the first OR gate 223. The output of level holder 212 is low and fed to the second inverter 222. The second inverter 222 outputs a high level, which serves as the second input to the first OR gate 223. Therefore, the output of the first OR gate 223 is high. This high level is then shifted by level shifter 1031 and fed to the first inverter 1033. The low level output from the first inverter 1033 is then fed to the third N-type metal-oxide-semiconductor transistor 352, which is currently not conducting. The high level output is then fed to the first buffer 1032, which in turn feeds the second N-type metal-oxide-semiconductor transistor 351. The gate of the high-voltage depletion-type transistor 201 is coupled to the source of the low-voltage enhancement-type transistor 202 through the second N-type metal-oxide-semiconductor transistor 351. At this time, the low-voltage enhancement-type transistor 202 is turned off, and the high-voltage depletion-type transistor 201 is turned off along with the low-voltage enhancement-type transistor 202, and the circuit operates in cascade mode. Thus, in standby mode, the circuit operates in common-source common-gate cascade mode, which greatly improves the reliability of the direct-drive structure device.
[0104] In one alternative implementation, see [link to implementation details]. Figure 6 This application provides an integrated power switching device 30, which includes a cascaded control circuit 10 and a cascaded structure 20. The first output terminal of the control circuit 10 is connected to the gate of the high-voltage depletion-type transistor 201 in the cascaded structure 20, and the second output terminal of the control circuit 10 is connected to the gate of the low-voltage enhancement-type transistor 202 in the cascaded structure 20. The working principle of this integrated power switching device 30 is the same as that of the above embodiments, and will not be described in detail here.
[0105] In one alternative implementation, see [link to implementation details]. Figure 7 This application provides an electric power system 40 in which an electric power system 40 is deployed with Figure 6 The integrated power switching device 30 shown is not described in detail here.
[0106] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0107] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A cascaded control circuit, characterized in that, The control circuit includes a power conversion module, a drive signal control module, and a drive module. The cascaded structure includes a high-voltage depletion-type transistor and a low-voltage enhancement-type transistor, wherein the source of the high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The first input terminal of the power conversion module is connected to the positive DC power supply, the second input terminal of the power conversion module and the first input terminal of the drive module are both connected to the negative DC power supply, the first output terminal of the power conversion module is connected to the power supply terminal of the chip, and the power conversion module is also connected to an external switching node. The input terminal of the drive signal control module is used to receive external input signals. The sampling terminal of the drive signal control module is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module. The first output terminal of the drive signal control module is connected to the gate of the low-voltage enhancement-mode transistor. The second output terminal of the drive signal control module is connected to the second input terminal of the drive module. The first output terminal of the drive module is connected to the gate of the high-voltage depletion-mode transistor. The second output terminal of the drive module is connected to the source of the low-voltage enhancement-mode transistor. The drive signal control module controls the low-voltage enhancement-mode transistor to turn on or off based on the external input signal and the voltage detection result obtained from the electrical signal collected by the sampling terminal of the drive signal control module, and sends the corresponding logic level to the drive module through the second output terminal of the drive signal control module. The driving module controls the high-voltage depletion transistor to turn on or off based on the logic level and the negative drive signal input from the negative DC power supply.
2. The control circuit of the cascaded structure according to claim 1, characterized in that, The power conversion module includes: a switching unit, a buck-boost converter, and a linear regulator; The first terminal of the switching unit and the input terminal of the linear regulator are connected to the positive DC power supply, and the output terminal of the linear regulator is connected to the power supply terminal of the chip. The control terminal of the switching conversion unit is connected to the buck-boost converter, the second terminal of the switching conversion unit is connected to an external switching node, and the third terminal of the switching conversion unit is connected to the negative DC power supply.
3. The control circuit of the cascaded structure according to claim 2, characterized in that, The switching unit includes: a P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor; The source of the P-type metal-oxide-semiconductor transistor is connected to the positive DC power supply, the drain of the P-type metal-oxide-semiconductor transistor is connected to the drain of the first N-type metal-oxide-semiconductor transistor, and the gates of the P-type metal-oxide-semiconductor transistor and the first N-type metal-oxide-semiconductor transistor are both connected to the buck-boost converter. The source of the first N-type metal-oxide-semiconductor transistor is connected to the negative DC power supply, and the drain of both the P-type metal-oxide-semiconductor transistor and the drain of the first N-type metal-oxide-semiconductor transistor are connected to an external switching node.
4. The control circuit of the cascaded structure according to claim 1, characterized in that, The driving module includes: a level shifter, a first buffer, a first inverter, a first capacitor, and a driving unit; The input terminal of the level shifter is connected to the second output terminal of the drive signal control module. The output terminal of the level shifter is connected to the input terminal of the first buffer and the input terminal of the first inverter, respectively. The output terminal of the first buffer is connected to the first control terminal of the drive unit. The output terminal of the first inverter is connected to the second control terminal of the drive unit. The first buffer is connected to the first inverter via the first capacitor. The first inverter and the input terminal of the driving unit are both connected to the negative DC power supply. The first output terminal of the driving unit is connected to the gate of the high-voltage depletion-type transistor. The second output terminal of the driving unit and the first buffer are both connected to the source of the low-voltage enhancement-type transistor.
5. The control circuit of the cascaded structure according to claim 4, characterized in that, The driving unit includes: a second N-type metal-oxide-semiconductor transistor and a third N-type metal-oxide-semiconductor transistor; The gate of the second N-type metal-oxide-semiconductor transistor is connected to the output terminal of the first buffer, the drain of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the low-voltage enhancement-mode transistor, the source of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the third N-type metal-oxide-semiconductor transistor, the source of the third N-type metal-oxide-semiconductor transistor is connected to the negative DC power supply, and the source and drain of the second N-type metal-oxide-semiconductor transistor are also connected to the gate of the high-voltage depletion-mode transistor.
6. The control circuit of the cascaded structure according to claim 1, characterized in that, The drive signal control module includes: an input unit, a first logic processing unit, and a second logic processing unit; The input terminal of the input unit is used to receive external input signals. The first output terminal of the input unit is connected to the first input terminal of the first logic processing unit and the first input terminal of the second logic processing unit, respectively. The second output terminal of the input unit is connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit, respectively. The third input terminal of the second logic processing unit is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module, respectively. The first output terminal of the second logic processing unit is connected to the third input terminal of the first logic processing unit. The second output terminal of the second logic processing unit is connected to the gate of the low-voltage enhancement-mode transistor. The output terminal of the first logic processing unit is connected to the second input terminal of the driving module.
7. The control circuit of the cascaded structure according to claim 6, characterized in that, The input unit includes: a second buffer and a level hold; The input terminal of the second buffer is used to receive external input signals. The output terminal of the second buffer is connected to the first input terminal of the first logic processing unit, the first input terminal of the second logic processing unit, and the input terminal of the level holder, respectively. The output terminal of the level holder is connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit, respectively.
8. The control circuit of the cascaded structure according to claim 7, characterized in that, The level holder includes: a diode, a resistor, and a second capacitor; The input terminal of the diode and one end of the resistor are both connected to the output terminal of the second buffer. The output terminal of the diode, one end of the second capacitor, and the other end of the resistor are all connected to the second input terminal of the first logic processing unit and the second input terminal of the second logic processing unit.
9. The control circuit of the cascaded structure according to claim 7, characterized in that, The first logic processing unit includes: a first AND gate, a second inverter, and a first OR gate; The first input terminal of the first AND gate is connected to the output terminal of the second buffer, the second input terminal of the first AND gate is connected to the first output terminal of the second logic processing unit, and the output terminal of the first AND gate is connected to the first input terminal of the first OR gate. The input terminal of the second inverter is connected to the output terminal of the level holder, the output terminal of the second inverter is connected to the second input terminal of the first OR gate, and the output terminal of the first OR gate is connected to the second input terminal of the drive module.
10. The control circuit of the cascaded structure according to claim 7, characterized in that, The second logic processing unit includes: a second OR gate, a second AND gate, a third buffer, and a voltage detector; The first input terminal of the second OR gate is connected to the output terminal of the second buffer, the second input terminal of the second OR gate is connected to the output terminal of the level holder, and the output terminal of the second OR gate is connected to the first input terminal of the second AND gate. The input terminal of the voltage detector is connected to the positive DC power supply, the negative DC power supply and the first output terminal of the power conversion module, respectively. The output terminal of the voltage detector is connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is connected to the second input terminal of the first AND gate and the input terminal of the third buffer, respectively. The output terminal of the third buffer is connected to the gate of the low-voltage enhancement-mode transistor.