Delta-sigma modulator with feedback current controlled by output

Abstract

A delta-sigma modulator includes a comparator circuit having an output that provides a digital signal indicative of a voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to an input of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output and a second second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node connected to the input of the comparator and to a capacitor.

Description

Technical Field

[0001] The present invention relates to a Δ-Σ modulator having an output-controlled feedback current leading to an integrator node. Background Technology

[0002] Δ-Σ modulators can be used to convert analog signals into digital signals. Summary of the Invention

[0003] In some embodiments, a Δ-Σ modulator circuit includes: a circuit input configured to receive a first input signal; and a comparator circuit including a comparator. The comparator includes a first input coupled to the circuit input via a continuous time path, and the comparator circuit includes an output providing a digital signal indicating a voltage of the first input signal. The Δ-Σ modulator circuit includes: a first integrator node in the continuous time path; a first feedback loop connected to the first integrator node and configured to provide a first feedback current to the first integrator node, the first feedback current being controlled by the output of the comparator circuit; a second integrator node in the continuous time path and connected to the first input of the comparator; a capacitor including a first electrode connected to the second integrator node; and a second feedback loop connected to the second integrator node, the second feedback loop being configured to provide a second feedback current to the second integrator node. The second feedback current is characterized by being controlled by the output of the comparator circuit.

[0004] In other embodiments, the continuous-time path is configured to provide a continuous-time voltage to the first input of the comparator, wherein the comparator is configured to compare the continuous-time voltage in response to a sampling clock signal.

[0005] In other embodiments, the second feedback loop includes a current generation circuit responsive to the output of the comparator circuit, the current generation circuit being configured to draw current from the second integrator node in response to the output of the comparator circuit being in a first output state, and configured to supply current to the second integrator node in response to the output of the comparator being in a second output state.

[0006] In other embodiments, the output of the comparator circuit includes a first output terminal and a second output terminal, and the current generation circuit includes a first transistor that turns on in response to the first output terminal to supply current to the second integration node, and the current generation circuit includes a second transistor that turns on in response to the second output terminal to draw current from the second integration node.

[0007] In other embodiments, the first transistor turns on in response to a negative comparison result of the comparator at its first input indicated by the first output terminal to supply current to the second integrating node, and the second transistor turns on in response to a positive comparison result of the comparator at its first input terminal indicated by the second output terminal to draw current from the second integrating node.

[0008] In other embodiments, the current generating circuit includes a third transistor of the same conductivity type as the first transistor and a fourth transistor of the same conductivity type as the second transistor. The first and second transistors are connected in series in a first circuit path, and the third and fourth transistors are connected in series in a second circuit path. The first and second circuit paths are connected in parallel. The current generating circuit provides the second feedback current at a node in the first circuit path located between the first and second transistors. The current generating circuit is characterized by a current guiding circuit. The second feedback loop further includes a non-overlapping circuit comprising: a first input coupled to the first output; a second input coupled to the second output; a first output coupled to the control terminal of the first transistor and responsive to the first output of the comparator circuit; a second output coupled to the control terminal of the second transistor and responsive to the second output of the comparator circuit; a third output coupled to the control terminal of the third transistor and responsive to the first output of the comparator circuit; and a fourth output coupled to the control terminal of the fourth transistor and responsive to the second output of the comparator circuit. The non-overlapping circuit drives its first and third output terminals with a margin to prevent the first and third transistors from conducting simultaneously. The non-overlapping circuit also drives its second and fourth output terminals with a margin to prevent the second and fourth transistors from conducting simultaneously.

[0009] In other embodiments, the first feedback loop includes a second current generation circuit responsive to the output of the comparator circuit, the second current generation circuit being configured to draw current from the first integrator node in response to the output of the comparator circuit being in the first output state, and configured to supply current to the first integrator node in response to the output of the comparator being in the second output state.

[0010] In other embodiments, the second current generating circuit is configured to absorb a larger current from the first integrator than the current absorbing from the second integrator, and is configured to supply a larger current to the first integrator than the current absorbing to the second integrator.

[0011] In other embodiments, the second feedback loop includes a resistor circuit having a first terminal coupled to the output of the comparator circuit and a second terminal connected to the second integrator node.

[0012] In other embodiments, the Δ-Σ modulator circuit is characterized by a passive Δ signal modulator circuit.

[0013] In other embodiments, the Δ-Σ modulator circuit further includes: a second circuit input configured to receive a second input signal, wherein the first input signal and the second input signal are differentially coupled, wherein the second circuit input is coupled to a second input of the comparator via a second continuous time path; a third integrator node in the second continuous time path; a third feedback loop connected to the third integrator node and configured to provide a third feedback current to the third integrator node, the third feedback current being controlled by the output of the comparator circuit; a fourth integrator node in the second continuous time path and connected to the second input of the comparator; and a fourth feedback loop connected to the fourth integrator node, the fourth feedback loop being configured to provide a fourth feedback current to the fourth integrator node, the fourth feedback current being controlled by the output of the comparator circuit.

[0014] In other embodiments, the fourth feedback loop includes a current generation circuit responsive to the output of the comparator circuit, the current generation circuit being configured to draw current from the fourth integrator node in response to the output of the comparator circuit being in a first output state, and configured to supply current to the fourth integrator node in response to the output of the comparator circuit being in a second output state.

[0015] In other embodiments, the second feedback loop includes the current generation circuit, which is configured to supply current to the second integrator node in response to the output of the comparator circuit being in the first output state, and to draw current from the second integrator node in response to the output of the comparator circuit being in the second output state.

[0016] In other embodiments, the Δ-Σ modulator circuit further includes the capacitor having a second electrode connected to the fourth integrator node.

[0017] In other embodiments, the Δ-Σ modulator circuit further includes a second capacitor, which includes a first electrode connected to the second integrating node.

[0018] In other embodiments, the comparator circuit includes a zero-reset circuit system that implements the zero-reset characteristic of the output of the comparator circuit.

[0019] In other embodiments, the output of the comparator circuit is characterized by not having a non-return-to-zero characteristic.

[0020] In other embodiments, a method of operating a passive Δ-Σ modulator includes: providing an input signal to a circuit input of a passive Δ-Σ modulator circuit, the circuit input being coupled in a continuous time path to the input of a comparator of a comparator circuit of the passive Δ-Σ modulator circuit. The method includes providing a first feedback current to a first integrator node of the continuous time path via a first feedback loop, the first feedback current being controlled by the output of the comparator circuit. The method includes providing a second feedback current to a second integrator node of the continuous time path via a second feedback loop, the second feedback current being controlled by the output of the comparator circuit, the second integrator node being connected to the input of the comparator and an electrode of a capacitor. The method includes providing a digital signal indicating a voltage of the input signal at the output of the comparator circuit.

[0021] In other embodiments, providing the second feedback current includes: drawing current from the second integrator node through a current generation circuit in response to the output of the comparator circuit being in a first output state; and supplying current to the second integrator node through the current generation circuit in response to the output of the comparator being in a second output state.

[0022] In other embodiments, the output of the comparator circuit includes a first output terminal and a second output terminal, and the current generation circuit includes a first transistor and a second transistor, the first transistor being turned on in response to the first output terminal to supply current to the second integration node, and the second transistor being turned on in response to the second output terminal to draw current from the second integration node. Attached Figure Description

[0023] The invention can be better understood by referring to the accompanying drawings, which will make its many objectives, features and advantages clear to those skilled in the art.

[0024] Figure 1 This is a block diagram of a prior art Δ-Σ modulator.

[0025] Figure 2 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0026] Figure 3 This is a circuit diagram of a non-overlapping circuit used in a Δ-Σ modulator according to an embodiment of the present invention.

[0027] Figure 4 This is according to an embodiment of the present invention. Figure 2 Timing diagram of the Δ-Σ modulator.

[0028] Figure 5 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0029] Figure 6 This is according to an embodiment of the present invention. Figure 5 Timing diagram of the Δ-Σ modulator.

[0030] Figure 7 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0031] Figure 8 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0032] Figure 9 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0033] Figure 10 This is a circuit diagram of a Δ-Σ modulator according to an embodiment of the present invention.

[0034] Unless otherwise specified, the same reference symbols are used in different figures to indicate the same items. The figures are not necessarily drawn to scale. Detailed Implementation

[0035] The following provides a detailed description of the modes used to carry out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0036] As disclosed herein, a Δ-Σ modulator includes a comparator circuit with an output that provides a digital signal indicating the voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to the input of a comparator in the comparator circuit. The modulator includes: a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output; and a second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node being connected to the input of the comparator and to a capacitor.

[0037] In some embodiments, this configuration can provide a Δ-Σ modulator that reduces the voltage swing at the comparator input caused by thermal noise. This feature can increase the comparator gain, thereby improving the noise shaping of the Δ-Σ modulator.

[0038] Passive Δ-Σ modulators may be more energy-efficient than active Δ-Σ modulators because their loop filters do not include active components for providing gain. However, the lack of gain in the loop filter can result in a lower voltage swing in the internal states of the loop filter, which can negatively impact the noise shaping of the modulator.

[0039] Figure 1 This is a circuit diagram of a prior art Δ-Σ modulator 101. Modulator 101 includes an input for receiving an analog signal (VIN) and an output for providing a serial digital bit stream OUT provided by comparator 103. Comparator 103 includes an inverting input coupled to the input via resistors 107 and 104, and connected to an integrating node 115 coupled to an integrating node 115 via a zero-resistance resistor 108 and a capacitor 109. The non-inverting input of comparator 103 is connected to a common voltage source. The output of comparator 103 is coupled to node 112 via a feedback resistor 105 to provide a feedback loop. Capacitor 106 is connected to the integrating node 112 and grounded. During operation, resistor 108 provides a zero point for the loop filter frequency response, stabilizing the loop.

[0040] Because modulator 101 is a passive modulator, it does not use active components (such as amplifiers) in the loop filter to provide gain, making it more energy-efficient than an active Δ-Σ modulator. However, the lack of gain in the loop filter results in a lower voltage swing at the internal nodes of the loop filter, including the inverting input of comparator 103. Because of this lower voltage swing at the comparator input, the comparator's noise contributes significantly to the modulator's total noise. Furthermore, the comparator's noise is not integrated because it is generated internally. This can cause the comparator to make incorrect decisions dynamically, effectively reducing the comparator gain and thus affecting the modulator's noise shaping.

[0041] Furthermore, resistors 107 and 108 introduce noise at the comparator input, where high-frequency components are not integrated, significantly impacting the comparator gain. Removing the zero-resistor 108 limits the bandwidth of resistor 107, significantly reducing the noise swing at the comparator input. However, simply removing resistor 108 may lead to loop instability, degrading the performance of the Δ-Σ modulator. Additionally, since the input of comparator 103 is connected to the integrating capacitor 109, removing resistor 108 reduces the ripple at the input of comparator 103 caused by its backlash.

[0042] Figure 2This is a circuit diagram of a Δ-Σ modulator 201 according to an embodiment of the present invention. The modulator 201 includes a single-ended input that includes an input terminal for receiving an analog signal (VIN), and generates serial output signals (OUTP, OUTN) at its output indicating a voltage of VIN using Δ-Σ modulation. In some embodiments, the output signals generate a 1-bit serial digital signal. The output of the modulator 201 is provided by a comparator circuit 205 including a comparator 207 and a return-to-zero (RTZ) block 209. The comparator 207 acts as a quantizer for the modulator 201. The block 209 receives differential output signals COP and CON from the non-inverting and inverting output terminals of the comparator 207, respectively, and implements a return-to-zero function to provide signals OUTP and OUTN at its non-inverting and inverting output terminals, respectively. The comparator 207 and the RTZ block 209 receive a clock signal FS, which defines the sampling frequency of the comparator circuit and the data period of the OUTP and OUTN signals. The pattern of the high-voltage state data period and low-voltage state data period on OUTP, and the opposite pattern on OUTN, indicate the analog voltage at VIN. In some embodiments, the ratio of the high-voltage state data period to the total data period in the OUTP signal (or the ratio of the low-voltage data state period to the total data period in the OUTN signal) indicates the analog voltage at VIN. In some embodiments, providing a zero-return characteristic to the output signal can reduce inter-symbol interference.

[0043] The non-inverting input of comparator 207 is connected to integrator node 210, and the inverting input of comparator 207 is connected to a common voltage (CV) source with a voltage higher than ground but lower than VDD. In some embodiments, CV is equal to VDD / 2, but in other embodiments, it may have other values. Modulator 201 includes a continuous-time path from the modulator input receiving the VIN signal to the non-inverting input of comparator 207. The continuous-time path includes resistor 211, integrator node 220, resistor 217, and integrator node 210, with integrator node 210 connected to the non-inverting input of comparator 207.

[0044] Integrating capacitor 219 includes one electrode connected to node 210 and the other electrode grounded. Resistor 217 includes one end connected to node 210 and the other end connected to integrating node 220. Resistor 211 includes one end connected to node 220 and the other end connected to the modulator input terminal receiving the VIN signal. Capacitor 215 includes one electrode connected to node 220 and the other electrode grounded. Feedback resistor 213 includes one end connected to node 220. The other end of feedback resistor 213 is connected to the inverting output of block 209 to implement a feedback loop for receiving the current generated by the OUTN signal on resistor 213. Therefore, the integrator implemented with resistor 211 and capacitor 215 integrates the feedback current generated by the OUTN signal with the input signal VIN at node 220.

[0045] Modulator 201 includes another integrator (implemented with resistor 217 and capacitor 215) for integrating the integrated signal generated at node 220 with the comparator-controlled feedback current (IFB) at node 210 to generate an integrated voltage at the non-inverting input of comparator 207. Figure 2 As shown, capacitor 219 includes one electrode connected to node 210 and another electrode grounded.

[0046] The voltages at nodes 220 and 210 are described as continuous-time voltages because they are based on the continuous variation of the modulator input and the feedback loop output. This differs from the discrete-time implementation, in which the voltages at nodes 220 and 210 remain constant over a defined time period (like the sampled signal).

[0047] The feedback loop generating the feedback current IFB includes a non-overlapping circuit 221 that receives OUTP and OUTN signals from comparator circuit 205 and generates P, PN, N, and NN signals, which are provided to the gates of PFET 225, PFET 229, NFET 227, and NFET 231 in current pilot circuit 223, respectively. Current pilot circuit 223 also includes a current source 233, which includes one terminal connected to the voltage supply rail VDD and the other terminal connected to the sources of PFETs 225 and 229. Circuit 223 includes a current source 235, which includes one terminal grounded and the other terminal connected to the sources of NFETs 227 and 231. The drains of NFET 227 and PFET 225 are connected to a common voltage source, and the drains of NFET 231 and PFET 229 are connected to integration node 210 to provide the feedback current IFB. In one embodiment, VDD is 1.8 volts, CV is 0.9 volts, VIN ranges from 0 to 1.8 volts, and signals N, P, PN, NN, OUTN, and OUTP range from 0 to 1.8 volts; however, in other embodiments, these voltages may have other values. In some embodiments, current source 235 may be connected to a negative voltage supply, and the inverting input of comparator 207 and the drains of NFET 227 and PFET 225 may be grounded. Current sources 233 and 235 may be implemented in various ways, for example, using transistors with bias voltages at their control terminals or using current mirrors. In one embodiment, the current generated by current sources 233 and 235 is in the range of 100-200 nA; however, in other embodiments, other values ​​may be present. In some embodiments, the Δ-Σ modulator is characterized by being a passive Δ-Σ modulator because no gain is applied at the integration nodes (210, 220) within the modulator's loop filter. Figure 2 As shown, the loop filter of modulator 201 is implemented using resistors 211 and 217 and capacitors 215 and 219. For example, the loop filter of modulator 201 does not include an amplifier.

[0048] When NFET 231 is turned on by a high-voltage NN signal and PFET 229 is turned on by a high-voltage PN signal but not on, current source 235 draws current from node 210 (IFB is negative) to lower the voltage of node 210. This occurs in response to a positive comparison of the voltage of node 210 indicated by comparator circuit 205 with the voltage CV of the sampling time (determined by clock signal FS) to generate a quantized value. When NFET 231 is turned on by a low-voltage NN signal but not on, and PFET 229 is turned on by a low-voltage PN signal, current source 233 supplies current to node 210 (IFB is positive) to raise the voltage of node 210. This occurs in response to a negative comparison of the voltage of node 210 indicated by comparator circuit 205 with the voltage CV of the sampling time.

[0049] Because the current IFB supplied to node 210 is controlled by the output of comparator circuit 205 to be either absorbed or supplied, the current IFB is characterized by being controlled by the comparator circuit output. Similarly, because resistor 213 is connected to the output of comparator circuit 205, the feedback current supplied to node 220 is also characterized by being controlled by the comparator circuit output.

[0050] Figure 3 This is a circuit diagram of a non-overlapping circuit 221 according to an embodiment of the present invention. Circuit 221 includes a signal generation circuit 301 that generates P and PN signals from an OUTN signal. Circuit 301 includes a NAND gate 305, which includes one input terminal receiving the OUTN signal and another input terminal receiving a delayed PN signal from a delay element 313. NAND gate 305 provides the P signal. NAND gate 307 receives the inverted OUTN signal from an inverter 303 at one input terminal and receives the delayed P signal from a delay element 311 at its other input terminal. NAND gate 307 generates the PN signal.

[0051] Circuit 221 includes signal generation circuit 321 that generates N and NN signals from the OUTP signal. Circuit 321 includes a NOR gate 325, which includes one input that receives the OUTP signal and another input that receives the delayed NN signal from the delay element 333. NOR gate 325 provides the N signal. NOR gate 327 receives the inverted OUTP signal from the inverter 323 at one input and the delayed N signal from the delay element 331 at its other input. NOR gate 327 generates the NN signal. In other embodiments, the non-overlapping circuit may have other configurations.

[0052] Figure 4A timing diagram illustrating the operation of a Δ-Σ modulator 201 according to an embodiment of the present invention is shown. The OUTN and OUTP signals indicate the result of the comparison between the voltage of the integrator node 210 and CV by the comparator circuit 205 at each rising edge of the sampling clock signal FS. During the high clock state of FS, when the OUTN signal is high and the OUTP signal is low, a negative comparison result is indicated. During the high clock state of FS, when the OUTP signal is high and the OUTN signal is low, a positive comparison result is indicated. Figure 4 As shown, the OUTN and OUTP signals have a return-to-zero characteristic, as provided in block 209, where both signals return to a low voltage state when the FS clock signal is low. Figure 4 Four consecutive data cycles (with four rising clock edges of FS) are shown, where the comparison results successively indicate negative comparison result, positive comparison result, negative comparison result, and positive comparison result. However, it should be understood that the voltage VIN changes continuously over time ( Figure 4 (not shown in the image), the comparison results can be any combination.

[0053] Because signal NN responds to the OUTP signal, it is in a high-voltage state in response to the OUTP signal, indicating a positive comparison result. NFET 231 is then turned on to draw current to node 210. The non-overlapping circuit 221 provides a 403-fold delay margin in the rise of the NN signal relative to the rise of the OUTP signal. Because signal PN responds to the OUTN signal, it is in a low-voltage state in response to the OUTN signal, indicating a negative comparison result. PFET 229 is then turned on to supply current to node 210. The non-overlapping circuit 221 provides a 405-fold delay margin in the fall of the PN signal relative to the rise of the OUTN signal.

[0054] Return to reference Figure 2 The current guiding circuit 223 includes a PFET 225 and an NFET 227, allowing current from current sources 233 and 235 to flow to the CV source when they are not supplying or absorbing current to node 210. (Reference) Figure 4 and Figure 2When NFET 231 is not conducting (when the NN signal is low), NFET 227 is conducting (when the N signal is high) to allow current to flow from current source 235 when NFET 231 is not conducting. However, the non-overlapping circuit 231 provides a "guard band" margin 403 so that the N signal and NN signal cannot be in a high conduction voltage state simultaneously. When PFET 229 is not conducting (when the PN signal is high), PFET 225 is conducting (when the P signal is low) to allow current to flow from current source 233 when PFET 229 is not conducting. However, the non-overlapping circuit 221 provides a guard band margin 405 so that the P signal and PN signal cannot be in a low conduction voltage state simultaneously.

[0055] In other embodiments, the current guiding circuit 223 may have other configurations. Furthermore, in other embodiments, the current guiding circuit 223 may be replaced with other types of current generating circuitry that absorbs and supplies feedback current to node 210 in response to the output of comparator circuit 205. Such other embodiments may include other types of non-overlapping circuitry or other circuitry systems for controlling the current generating circuitry based on the comparator circuit output signal.

[0056] Figure 5 This is a circuit diagram of a Δ-Σ modulator 501 according to another embodiment. Figure 5 In, it has the same Figure 2 Items with the same reference numerals perform similar functions. Figure 5 In this embodiment, the comparator circuit 503 does not include a... Figure 2 Block 209 is a similar zero-return block. Therefore, the outputs of comparator circuit 503 (CON and COP signals) do not have a zero-return characteristic.

[0057] Figure 6 This is a timing diagram showing the operation of the Δ-Σ modulator 501 over two data cycles. (Example:) Figure 6 As shown, the CON and COP signals do not have a zero-return characteristic because they only change the data state at the rising edge of the FS signal. Figure 6Two data cycles are shown, in which current IFB is supplied to node 210 in response to a negative comparison result in one cycle, and current IFB is drawn from node 210 in response to a positive comparison result in the next cycle. When the CON signal is high, indicating a negative comparison result, the PN signal supplies current in response to the CON signal. The overlay circuit delays the assertion (pull-down to low voltage state) of the PN signal by a margin 603 in response to the rising edge of the CON signal. When the COP signal is high, indicating a positive comparison result, the NN signal draws current in response to the COP signal. The overlay circuit 221 delays the assertion of the NN signal by a margin 603 in response to the rising edge of the COP signal. The guard band margin 603 implemented by the overlay circuit 221 prevents the P signal and PN signal from being low simultaneously, and prevents the N signal and NN signal from being high simultaneously.

[0058] Figure 7 This is a circuit diagram of a Δ-Σ modulator 701 according to another embodiment. Figure 7 In, it has the same Figure 2 Items with the same reference numerals perform similar functions. Modulator 701 and... Figure 2 The modulator 201 differs in that it does not use a current-guiding circuit (such as current-guiding circuit 223) or other types of current-generating circuits to provide feedback current to the integrator node 210 controlled by the comparator circuit output. Instead, the feedback current IFB, controlled by the comparator circuit output, is provided by connecting the output of comparator circuit 705 to one end of resistor 703, the other end of which is connected to node 210. Figure 7 In one embodiment, comparator circuit 705 does not include a zero-return block, so that the output signal (OUT) does not have a zero-return characteristic. However, in other embodiments, circuit 705 may include a zero-return block. Furthermore, integrator node 210 is connected to the inverting input of comparator 707, and the non-inverting input of comparator 707 is grounded.

[0059] In one embodiment, resistor 211 is 100K ohms, resistor 213 is 50K ohms, resistor 217 is 100K ohms, resistor 703 is 6M ohms, capacitor 215 is 50 pF, capacitor 219 is 10 pF, and the switching frequency is 50MHz. Based on these values, the comparator input noise is 200 µVrms. However, in other embodiments, these may have different values.

[0060] Modulator 701 includes less circuitry than modulator 201 because it does not include current-guiding or non-overlapping circuitry. However, the high resistance (6 MΩ) of resistor 703 makes it difficult to change the feedback current at high sampling frequencies (e.g., 50 MHz).

[0061] Figure 8 This is a circuit diagram of a Δ-Σ modulator 801 according to another embodiment. Figure 8 In, it has the same Figure 2 Items with the same reference numerals perform similar functions. Figure 8 In this circuit, the input signal is a differential signal (VINN, VINP). Therefore, modulator 801 includes an additional continuous-time path (which includes resistor 816, integrator node 820, resistor 818, and integrator node 810) from the input receiving the VINN signal to the inverting input of comparator 207. Modulator 801 includes a feedback loop that includes resistor 824 connected to the output of comparator circuit 205, which provides an OUTP signal to provide feedback current to integrator node 820, which is controlled by the comparator circuit output. Another feedback loop includes current-directing circuit 823 that provides feedback current (IFBN) to node 810. Circuit 823 includes a current source 833 for supplying current to nodes 810, PFETs 825 and 829, and NFETs 827 and 831, and a current source 835 for sinking current to node 810. Current-directing circuit 823 is similar to current-directing circuit 223, but when circuit 203 supplies current to node 210 (IFBP), circuit 823 draws current from node 810 (IFBN), and when circuit 203 draws current from node 210 (IFBP), circuit 823 supplies current to node 801 (IFBN). To achieve this, modulator 801 includes four inverters 840 for inverting the N, P, PN, and NN signals from non-overlapping circuit 221 to generate inverted NB, PB, PNB, and NNB signals, which are provided to the gates of PFET 825, NFET 827, NFET 831, and PFET 829, respectively. However, in other embodiments, the modulator may include a second overlapping circuit (not shown) similar to circuit 221 for generating control signals to circuit 823. In other embodiments, the modulator may include other types of current-generating circuitry for generating feedback signals.

[0062] In the illustrated embodiment, integrating capacitor 815 includes one electrode connected to node 220 and another electrode connected to node 820. Integrating capacitor 819 includes one electrode connected to node 210 and another electrode connected to node 810. However, in other embodiments, each integrating node will include its own capacitor. In some embodiments, modulator 801 may include common-mode control circuitry (not shown) that regulates the common-mode voltage of nodes 210 and 810 by simultaneously controlling the currents of current sources 235 and 835.

[0063] Figure 9This is a circuit diagram of a Δ-Σ modulator 901 according to another embodiment. Figure 9 In, it has the same Figure 8 Items with the same reference numerals perform similar functions. Modulator 901 is similar to modulator 801 in that it receives differential input signals (VINP, VINN). However, the comparator circuit 903 of modulator 901 does not include a zero-return block (e.g., similar to block 209), so that the output signals OUTP and OUTN do not have zero-return characteristics. Another difference is that the drains of the PFET 225 and NFET 227 in the current-guiding circuit 923 provide feedback current (IFBN) to node 810. Return to Reference Figure 6 , it is Figure 5 In the timing diagram of the non-return-to-zero embodiment, signals PN and N are differential signals, and signals NN and P are differential signals. Therefore, when current IFBP is drawn from node 210, current IFBN is supplied to node 810, and when current IFBP is supplied to node 210, current IFBN is drawn from node 810. However, in other embodiments, modulator 901 may include another current guiding circuit or other types of current generating circuitry for generating IFBN. In one embodiment, modulator 901 may include a common-mode control circuit (not shown).

[0064] Figure 10 This is a circuit diagram of a Δ-Σ modulator 1001 according to another embodiment. Figure 10 In, it has the same Figure 2 Items with the same reference numerals perform similar functions. Figure 10 modulator 1001 and Figure 2 The modulator 201 differs in that it includes a current-guiding circuit 1023 for providing feedback current (IFB1) to the integrator node 220 for output control of the comparator circuit.

[0065] The current-guiding circuit 1023 includes NFETs 1027 and 1031, PFETs 1025 and 1029, a current source 1033 for supplying current to node 220, and a current source 1035 for drawing current from node 220. Circuit 1023 responds to P, N, PN, and NN signals in a manner similar to circuit 223, such that currents IFB and IFB1 are both draw currents and both supply currents. However, the amounts of source current and sink current provided by current sources 1033 and 1035 are both greater than those provided by current sources 233 and 235. In one embodiment, the current from sources 1033 and 1035 is 40 times greater than the current from sources 233 and 235. In other embodiments, modulator 1001 may implement a non-return-to-zero comparator circuit (similar to...). Figure 5(Comparator circuit 503). In other embodiments, modulator 1001 may be configured to receive differential input signals, such as pass modulators 801 and 901, wherein it includes two additional current-guiding circuits and a second continuous-time path.

[0066] In other embodiments, the modulator described herein may include other circuit systems with other configurations and / or operate in different ways. For example, other embodiments may use other types of transistors. Additionally, in some embodiments, the resistor may be replaced with other types of resistive circuitry, such as a transistor with its control terminals biased by a fixed voltage.

[0067] The modulators shown and described herein can be used in a variety of applications to provide digital indications of single-ended or differential voltages. Such modulators can be used in a wide range of systems, such as computers, mobile phones, automotive electronics, wearable devices, IoT systems, industrial systems, embedded systems, or communication systems.

[0068] In some embodiments, providing a feedback current (IFB) to the integrating node connected to the comparator input and the integrating capacitor can provide a loop filter zero at the integrating node at the comparator input, which may help stabilize the Δ-Σ loop filter of the passive Δ-Σ modulator. This configuration allows the removal of a zero resistor (e.g., resistor 108), as described above regarding... Figure 1 The existing modulator described. Removing the zero resistor (e.g.) Figure 1 Resistor 108 allows high-frequency noise from the integrating resistor (e.g., resistor 217) to be filtered out by integrating capacitors (e.g., capacitors 219, 819) connected to the input of a comparator (e.g., comparators 207, 707), thereby reducing the voltage swing generated by thermal noise at the comparator input. Additionally, noise generated by the zero resistor (resistor 108) can also be removed. The reduced voltage swing increases the comparator gain, improving noise shaping of the Δ-Σ modulator. However, a disadvantage of removing the zero resistor (resistor 108) is that it can lead to instability in the Δ-Σ modulator. The embodiments described herein include a feedback loop connected to an integrating node (210) that provides a zero point for loop stability. This can be done without significantly increasing the voltage swing caused by thermal noise because the integrating capacitors (e.g., capacitors 219, 819) are connected to the integrating node 210. High-frequency noise from the feedback loop or integrator resistor (e.g., resistor 217) is filtered out by integrating capacitors (e.g., capacitors 219, 819) connected to the input of comparators (e.g., comparators 207, 707). Simulations of some embodiments show that, with Figure 1Compared to existing Δ-Σ modulators of the type shown, the SNR is improved by 11 dB. Therefore, the configuration described herein can provide an improved Δ-Σ modulator, such as an improved passive Δ-Σ modulator, which may be particularly beneficial in low-power applications.

[0069] Furthermore, noise shaping of the modulator described herein can be further improved by implementing a continuous-time path from the modulator input to the comparator input instead of a discrete-time path. Using a discrete-time implementation makes achieving a high signal-to-noise ratio more difficult, primarily due to charge injection and timing issues. Larger switched capacitors can alleviate this problem, but this requires a corresponding increase in the integrating capacitor, which occupies more integrated circuit space. Therefore, using a continuous-time input path (instead of a discrete-time path) in the embodiments described herein reduces the complexity of driving the Δ-Σ modulator input because it is resistive, rather than using a sampling capacitor.

[0070] As used herein, an article is “coupled” to another article by connecting to it or by coupling it to a current or signal path via at least one other article. For example, in Figure 2 In this circuit, resistor 211 is coupled to node 210 via resistor 217. Resistor 211 is also coupled to resistor 217 via one end of its connection to one end of resistor 217. The gate is the control terminal of the FET. The drain and source are the current terminals of the FET. A continuous-time path is a path in which there are no switches configured to open and close during circuit operation.

[0071] Features specifically shown or described in one embodiment described herein may be implemented in other embodiments described herein.

[0072] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, other changes and modifications may be made without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. A Δ-Σ modulator circuit, characterized in that, include: The circuit input terminal is configured to receive a first input signal; A comparator circuit includes a comparator having a first input coupled to an input of the circuit via a continuous time path, and the comparator circuit including an output for providing a digital signal indicating a voltage of the first input signal; The first integration node is located in the continuous time path; A first feedback loop is connected to the first integrator node and configured to provide a first feedback current to the first integrator node, the first feedback current being controlled by the output of the comparator circuit. A second integration node is located in the continuous time path and connected to the first input of the comparator; A capacitor, which includes a first electrode connected to the second integration node; A second feedback loop is connected to the second integrator node, the second feedback loop being configured to provide a second feedback current to the second integrator node, the second feedback current being characterized by being controlled by the output of the comparator circuit.

2. The Δ-Σ modulator circuit according to claim 1, characterized in that, The continuous-time path is configured to provide a continuous-time voltage to the first input of the comparator, wherein the comparator is configured to compare the continuous-time voltage in response to a sampling clock signal.

3. The Δ-Σ modulator circuit according to claim 1, characterized in that, The second feedback loop includes a current generation circuit responsive to the output of the comparator circuit, the current generation circuit being configured to draw current from the second integrator node in response to the output of the comparator circuit being in a first output state, and configured to supply current to the second integrator node in response to the output of the comparator being in a second output state.

4. The Δ-Σ modulator circuit according to claim 3, characterized in that: The output of the comparator circuit includes a first output terminal and a second output terminal; The current generation circuit includes a first transistor that turns on in response to the first output to supply current to the second integration node, and the current generation circuit includes a second transistor that turns on in response to the second output to draw current from the second integration node.

5. The Δ-Σ modulator circuit according to claim 4, characterized in that, The first transistor turns on in response to a negative comparison result of the comparator at its first input, indicated by the first output, to supply current to the second integrating node, and the second transistor turns on in response to a positive comparison result of the comparator at its first input, indicated by the second output, to draw current from the second integrating node.

6. The Δ-Σ modulator circuit according to claim 4, characterized in that: The current generating circuit includes a third transistor of the same conductivity type as the first transistor and a fourth transistor of the same conductivity type as the second transistor. The first transistor and the second transistor are connected in series in a first circuit path, and the third transistor and the fourth transistor are connected in series in a second circuit path. The first circuit path and the second circuit path are connected in parallel. The current generating circuit provides the second feedback current at a node in the first circuit path located between the first transistor and the second transistor. The current generating circuit is characterized by a current guiding circuit. The second feedback loop further includes a non-overlapping circuit, which includes: The first input terminal is coupled to the first output terminal; The second input terminal is coupled to the second output terminal; A first output terminal is coupled to the control terminal of the first transistor and is responsive to the first output terminal of the comparator circuit; The second output terminal is coupled to the control terminal of the second transistor and is responsive to the second output terminal of the comparator circuit; The third output terminal is coupled to the control terminal of the third transistor and is responsive to the first output terminal of the comparator circuit. The fourth output terminal is coupled to the control terminal of the fourth transistor and is responsive to the second output terminal of the comparator circuit; The non-overlapping circuit drives its first output terminal and its third output terminal with a margin to prevent the first transistor and the third transistor from being turned on simultaneously. The non-overlapping circuit drives its second output terminal and its fourth output terminal with a margin to prevent the second transistor and the fourth transistor from being turned on simultaneously.

7. The Δ-Σ modulator circuit according to claim 3, characterized in that, The first feedback loop includes a second current generation circuit responsive to the output of the comparator circuit, the second current generation circuit being configured to draw current from the first integrator node in response to the output of the comparator circuit being in the first output state, and configured to supply current to the first integrator node in response to the output of the comparator being in the second output state.

8. The Δ-Σ modulator circuit according to claim 1, characterized in that, The second feedback loop includes a resistor circuit that includes a first terminal coupled to the output of the comparator circuit and a second terminal connected to the second integrator node.

9. The Δ-Σ modulator circuit according to claim 1, characterized in that, Also includes: A second circuit input is configured to receive a second input signal, wherein the first input signal and the second input signal are differential signals, and wherein the second circuit input is coupled to the second input of the comparator via a second continuous time path. The third integration node is located in the second continuous time path; A third feedback loop is connected to the third integrator node and configured to provide a third feedback current to the third integrator node, the third feedback current being characterized by being controlled by the output of the comparator circuit. The fourth integration node is located in the second continuous time path and is connected to the second input of the comparator; A fourth feedback loop, connected to the fourth integrator node, is configured to provide a fourth feedback current to the fourth integrator node, the fourth feedback current being controlled by the output of the comparator circuit.

10. A method for operating a passive Δ-Σ modulator, characterized in that, The method includes: An input signal is provided to the circuit input of the passive Δ-Σ modulator circuit, the circuit input being coupled in a continuous time path to the input of the comparator of the comparator circuit of the passive Δ-Σ modulator circuit; A first feedback current is provided to the first integral node of the continuous time path through a first feedback loop, wherein the first feedback current is characterized by being controlled by the output of the comparator circuit. A second feedback current is provided to the second integral node of the continuous time path through a second feedback loop. The second feedback current is characterized by being controlled by the output of the comparator circuit. The second integral node is connected to the input terminal of the comparator and the electrode of the capacitor. A digital signal indicating the voltage of the input signal is provided at the output of the comparator circuit.

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