A dynamically matched DAC for a multi-bit quantized Sigma-Delta ADC
By using a dynamic matching circuit that separates high and low bits, the control logic and hardware design are simplified, solving the problems of control complexity and hardware overhead of multi-bit Sigma-Delta ADCs, and achieving high-speed and high-precision signal conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-05
AI Technical Summary
Existing dynamic matching circuits for multi-bit Sigma-Delta ADCs suffer from high control complexity, large hardware overhead, and difficulty in balancing high speed and high accuracy, especially in the binary-to-temperature code conversion process, which increases complexity and power consumption.
A dynamic matching circuit with high and low bit splitting is adopted. The high bit control code is directly connected to the large capacitor array, while the low bit control code is dynamically rotated through a simplified dynamic element matching circuit. This simplifies the control logic and suppresses small capacitor mismatch errors. It is combined with binary code control switch array and differentiated sampling switch design.
It significantly reduces control complexity and hardware overhead, improves signal-to-noise ratio and linearity, and is suitable for high-speed, high-precision multi-bit quantization Sigma-Delta ADC applications, meeting real-time requirements.
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Figure CN122159885A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a multi-bit quantization Sigma. - DeltaADC's dynamic matching circuit is suitable for multi-bit quantization Sigma-Delta analog-to-digital conversion scenarios that require high-fidelity signal restoration. It can effectively balance the mismatch compensation accuracy of multi-bit DAC units with the complexity of control circuits. Background Technology
[0002] In the Sigma-Delta ADC architecture, DAC nonlinearity in the feedback path is one of the key factors limiting the overall system performance (such as signal-to-noise ratio SNR and spurious-free dynamic range SFDR). When multi-bit quantization is used to improve noise shaping efficiency, the feedback DAC is usually implemented by a capacitor array consisting of multiple unit capacitors. However, due to the fluctuations in CMOS process technology, there is an unavoidable mismatch between these capacitor units, resulting in nonlinear errors in the DAC output, which manifest as harmonic distortion or increased in-band noise in the spectrum, severely affecting the dynamic performance of the ADC.
[0003] To overcome the aforementioned problems, Dynamic Element Matching (DEM) technology is widely used. Among these, Data-Weighted Averaging (DWA) is one of the most commonly used methods. It activates different capacitor cells sequentially according to the input code values, modulating the mismatch error to a high frequency and filtering it out by a noise shaping loop. However, in traditional multi-bit Sigma... - In Delta ADCs, the DWA circuit typically needs to process the complete N-bit temperature code input, leading to the following problems:
[0004] High control complexity: N-bit quantization requires 2 N-1 Each unit capacitor corresponds to a large number of control signal lines and complex decoding logic;
[0005] High hardware overhead: The size of a complete DWA circuit increases exponentially with the number of bits, resulting in a large footprint and high power consumption;
[0006] Speed limitation: Large-scale DWA circuits introduce significant delays, making it difficult to meet the timing requirements of high-speed ADCs;
[0007] Binary-to-Thermometer conversion bottleneck: If the original control code is in binary form, an additional binary-to-thermometer conversion circuit is required, further increasing complexity and power consumption.
[0008] CN119652322A, titled "A Randomized Data Weighted Averaging Algorithm Circuit Applied to Sigma-Delta ADC," discloses a randomized data weighted averaging algorithm circuit that converts mismatch noise into white noise, effectively improving the signal-to-noise ratio and linearity. However, it introduces an additional digital processing module and requires at least 2... N - It has one capacitor unit and control signal, which is quite complex and has a high degree of time delay sensitivity.
[0009] CN120074529A, "A Dynamic Component Matching Circuit for a High-Speed Multi-Bit Sigma-Delta Modulator," discloses a method for dynamic component matching that embeds dynamic matching within a Flash ADC, disrupting the reference voltage distribution at its source to randomize capacitor mismatch errors. However, dynamic matching at the analog end suffers from setup errors, leading to reduced loop accuracy, and still requires 2... N -1 control bit.
[0010] CN121124818A, titled "Cardcapacitor Mismatch Error Shaping Circuit and Method for Multi-Bit Quantization Sigma-Delta ADCs," discloses a method for separately processing high-order and low-order capacitors. The high-order capacitors utilize dynamic component matching, while the low-order capacitors employ mismatch error shaping. During sampling, the current low-order codeword is maintained, and the difference between two adjacent low-order codewords is calculated. This scheme is applicable to multi-bit Sigma-Delta ADCs; however, some steps still require binary-to-temperature code conversion, and the digital processing complexity is also relatively high.
[0011] Although existing research has attempted to simplify DWA, it still falls short in balancing accuracy, speed, and area. Therefore, there is an urgent need for a dynamic matching circuit that is structurally simple, highly efficient in control, and can effectively suppress nonlinear distortion to meet the application requirements of high-speed multi-bit quantization Sigma-Delta ADCs. Summary of the Invention
[0012] To address the problems of complex control, high hardware overhead, and difficulty in balancing high speed and high precision in existing dynamic matching circuits, this invention provides a dynamic matching circuit for a multi-bit quantized Sigma-Delta ADC. Its core lies in splitting the DAC control code into high and low bits and performing lightweight dynamic matching only on the mismatch-sensitive low-bit portion, thereby significantly reducing circuit complexity while ensuring performance.
[0013] The technical solution of the present invention is as follows:
[0014] A binary dynamic matching DAC for a multi-bit quantized Sigma-Delta ADC is characterized by comprising an MSB capacitor array, an LSB capacitor array, a simplified dynamic element matching (DWA) circuit, and a switch array; the DAC receives an N-bit control code, splits it into high-order control code B[N-1:2] and low-order control code B[1:0], and uses binary encoding to control the switch array. The high-order control code B[N-1:2] directly connects to and controls the corresponding branch in the switch array, driving the MSB capacitor array composed of low-mismatch large capacitors. One end of each capacitor in the MSB capacitor array is selectively connected to VREFP or VREFN through a corresponding switch, and the other end is connected to form a common node for charge redistribution. The low-order control code B[1:0] is connected to the simplified dynamic element matching circuit, which controls the corresponding branch of the switch array after processing, driving the LSB capacitor array composed of small capacitors. One end of each capacitor in the LSB capacitor array is selectively connected to VREFP or VREFN through a corresponding switch, and the other end is connected to the common node of the MSB capacitor array. Dynamic rotation matching compensates for the mismatch error of small capacitors and reduces the nonlinearity of the Sigma-Delta ADC.
[0015] Furthermore, the MSB capacitor array is composed of large capacitor units, which have a smaller impact from mismatch and therefore do not require dynamic matching, thus simplifying the control logic. The LSB capacitor array is composed of small capacitor units, which have a larger impact from mismatch. By controlling the selection logic of the corresponding switches through a simplified dynamic element matching circuit, the dynamic rotation of the small capacitor units can be realized, effectively suppressing nonlinear distortion and ensuring the accuracy of charge redistribution.
[0016] Furthermore, the simplified dynamic element matching circuit includes a modulo-3 adder, a pointer register, and a selection decoder; the modulo-3 adder receives the low-order control code B[1:0] and updates the current pointer in the pointer register, and the selection decoder cyclically selects LSB capacitor units according to the current pointer to achieve dynamic matching.
[0017] Furthermore, the MSB capacitor array is composed of large capacitor units, which have a smaller impact from mismatch and therefore do not require dynamic matching, thus simplifying the control logic. The LSB capacitor array is composed of small capacitor units, which have a larger impact from mismatch. By controlling the selection logic of the corresponding switches through a simplified dynamic element matching circuit, the dynamic rotation of the small capacitor units can be realized, effectively suppressing nonlinear distortion and ensuring the accuracy of charge redistribution.
[0018] Furthermore, the MSB capacitor array adopts an independent sampling switch design, with each large capacitor unit corresponding to an independent sampling switch. One end of each sampling switch is connected to the corresponding large capacitor unit, and the other end is connected to the sampling signal, thereby realizing independent sampling of each large capacitor unit and reducing the load pressure on a single switch.
[0019] Furthermore, the LSB capacitor array adopts a shared sampling switch design, in which all small capacitor units share a single sampling switch. One end of the sampling switch is connected to all small capacitor units simultaneously, while the other end is connected to the sampling signal, thus adapting to the sampling requirements of small capacitors and simplifying the switch layout.
[0020] Furthermore, each capacitor unit in the MSB capacitor array adopts a binary weighting ratio, and the capacitance value of each small capacitor unit in the LSB capacitor array is equal and is the minimum weighted capacitance value; the capacitance ratio of the large capacitor unit and the small capacitor unit is adapted to the sampling and holding and binary quantization requirements, and the two achieve charge redistribution by sharing a common node.
[0021] The entire operation of the DAC is controlled by various signals. The core signals include the sampling input signal Vin, the clock control signal CLKD, and the selection control signal SEL. Combined with high and low bit control codes, sampling, charge redistribution, and dynamic matching are completed step by step. The functions and working steps of each signal are as follows:
[0022] The first step is signal initialization and clock synchronization. CLKD serves as the core clock signal, providing a timing reference for the entire DAC operation. All switching actions and signal processing strictly adhere to the timing of CLKD to avoid signal interference. Vin is the sampling input signal, which is the original signal used by the DAC to complete charge acquisition and conversion. SEL is the selection control signal, mainly acting on the dynamic matching link of the LSB capacitor array. It works in conjunction with the simplified dynamic element matching circuit to achieve cyclic selection of small capacitor units.
[0023] The second step, the sampling phase (controlled by CLKD timing): At this stage, CLKD triggers the sampling phase. Each large capacitor unit in the MSB capacitor array synchronously connects to the Vin signal through its own independent sampling switch, completing independent charging. Because the MSB capacitor array uses a binary weighting ratio (the capacitance values of the large capacitors increase in integer powers of 2), large capacitors with different weights will store corresponding charge amounts according to the Vin signal. Simultaneously, all small capacitor units in the LSB capacitor array synchronously connect to the Vin signal through a shared sampling switch, completing unified charging. The small capacitor values are consistent, ensuring initial charging consistency. During this stage, the SEL signal is in standby mode, the branch switch is turned off to prevent premature charge leakage, and CLKD continuously outputs timing pulses to maintain stable sampling.
[0024] The third step, charge redistribution and dynamic matching stage (controlled by CLKD, SEL, and control codes): CLKD switches to the charge redistribution phase, the sampling switch is turned off, and the branch switch is turned on. The high-order control code B[N-1:2] directly drives the branch switch corresponding to the MSB array, controlling the major capacitor units to selectively connect to VREFP or VREFN, completing the high-order charge redistribution based on binary weights. The charge is transmitted to the loop filter of the Sigma-Delta ADC through the common node. At the same time, the low-order control code B[1:0] triggers the simplified dynamic element matching circuit to work, the SEL signal is activated, and it is linked with the modulo-3 adder and pointer register to update the current selection pointer. Then, through the selection decoder, the LSB capacitor units are selected cyclically according to the pointer to realize the dynamic rotation matching of small capacitors and compensate for the mismatch error of small capacitors. In this stage, CLKD maintains timing synchronization to ensure that the SEL signal selection and the high and low order charge redistribution are carried out in coordination. Finally, the overall charge output is completed through the common node to realize the signal conversion function of the DAC.
[0025] The DAC, through the coordinated linkage of three core signals—CLKD, Vin, and SEL—and high- and low-bit control codes, strictly follows the timing process of "clock synchronization-sampling charging-charge redistribution and dynamic matching." Combined with the differentiated sampling switch design of MSB and LSB arrays, binary capacitor weighting ratio, and common node shared structure, it achieves accurate charge conversion of binary quantization and compensates for mismatch errors through LSB dynamic rotation matching. At the same time, it reduces the switching load pressure and hardware implementation complexity, effectively improving the signal-to-noise ratio and linearity of multi-bit quantization Sigma-Delta ADC, and is suitable for high-speed and high-precision sampling scenarios.
[0026] The beneficial effects of this invention include:
[0027] Significantly reduces control complexity: Dynamic matching is only performed on the low-order small capacitors, avoiding the large control network required for full-position DWA;
[0028] No temperature code conversion required: operates directly based on binary code, eliminating the need for a Binary-to-Thermometer conversion circuit;
[0029] Reduce the number of signal lines: The control signal requires only 2 lines, which is less than the traditional temperature code. N - One line is simplified to N binary lines, which greatly saves wiring resources and reduces latency sensitivity;
[0030] Suppressing key nonlinear sources: Small capacitor mismatch is the main source of nonlinearity. Targeted dynamic matching is implemented to address this, offering high cost-effectiveness.
[0031] Differentiated sampling switch for DAC: Reduces switching load and hardware complexity, and improves the signal-to-noise ratio and linearity of the sampling stage of multi-bit quantization Sigma-Delta ADC;
[0032] Suitable for high-speed applications: The simplified structure results in lower latency and power consumption, meeting the real-time requirements of high-speed Sigma-Delta ADCs.
[0033] In summary, this invention provides a compact, efficient, and high-performance dynamic matching circuit, which is particularly suitable for high-speed, high-resolution multi-bit quantization Sigma-Delta ADCs and has significant engineering application value. Attached Figure Description
[0034] Figure 1 This is an overall block diagram of the dynamic matching circuit for a multi-bit quantization Sigma-Delta ADC as described in this invention.
[0035] Figure 2 This is a circuit diagram of the MSB section of the binary dynamic matching DAC described in this invention.
[0036] Figure 3 This is a circuit diagram of the LSB section of the binary dynamic matching DAC described in this invention.
[0037] Figure 4 The output spectrum of a multi-bit quantized Sigma-Delta ADC using a conventional temperature code DAC under 1% capacitance mismatch is shown.
[0038] Figure 5 The output spectrum of the multi-bit quantization Sigma-Delta ADC with binary dynamic matching DAC described in this invention is shown under 1% capacitor mismatch. Detailed Implementation
[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
[0040] This embodiment provides a dynamic matching circuit for a multi-bit quantized Sigma-Delta ADC, applied to a 3-bit (N=3) quantized, third-order single-loop Sigma-Delta modulator. The modulator's DAC employs a capacitor array structure, and its control is achieved by the dynamic matching circuit described in this invention.
[0041] like Figure 1As shown, the dynamic matching circuit receives the 3-bit binary control code B[2:0] from the quantizer output and splits it into a high-order control code B[2] and a low-order control code B[1:0]. The high-order control code B[2] is directly connected to the MSB capacitor array, which consists of a large capacitor unit with an equivalent capacitance of 4C0, where C0 is the unit capacitance. Since the area of this large capacitor unit is large, the relative mismatch error caused by the process is less than 0.1%, and its impact on the linearity of the system is negligible. Therefore, dynamic matching processing is not required.
[0042] The low-order control code B[1:0] is input to the simplified dynamic matching circuit constructed in this invention. This circuit includes a modulo-3 adder, a pointer register, and a selection decoder, which are connected sequentially. Wherein:
[0043] The pointer register is a 2-bit register used to store the current rotating pointer ptr∈{0,1,2}, with an initial value set to 0;
[0044] The modulo-3 adder receives the low-order control code D = B[1:0] (its value range is 0 to 3) and calculates the next pointer value:
[0045] ptr_next = (ptr + D) mod 3
[0046] And update the pointer register in each clock cycle;
[0047] The selection decoder selects D consecutive capacitor cells from the LSB capacitor array for activation based on the current pointer ptr and the input value D. When D = 0, no cell is selected; when D = 3, all three cells are selected; when the selection exceeds the end of the array, it automatically wraps back to the starting position to achieve cyclic rotation.
[0048] The LSB capacitor array consists of three unit capacitors C0. (0) C0 (1) C0 (2) The capacitors are configured such that each capacitor has a nominal value of C0, but in actual manufacturing, there is a random mismatch of about ±1%. Through the aforementioned dynamic rotation mechanism, the average number of uses of each small capacitor tends to be consistent over a long period of operation, thereby converting the nonlinear error caused by mismatch into high-frequency noise, which is effectively suppressed by the noise shaping characteristics of the Sigma-Delta modulator.
[0049] like Figure 2 and Figure 3 As shown, the DAC receives 3 bits of control code B[2:0], which is split into high-order bits B[2:2] and low-order bits B[1:0]. The operation is completed by the coordinated signals of VIN, CLKD, and SEL, and the specific process is as follows:
[0050] The first step, clock synchronization stage: CLKD provides the timing reference, VIN is connected to the sampling terminal through the CLK_SAMPLE switch to charge the capacitor array; SEL is the output of the simplified dynamic element matching circuit, used for gating control of the LSB small capacitor.
[0051] The second step is the sampling phase: CLKD triggers the sampling phase, and the large capacitor 4C of MSB is connected to VIN through an independent CLK_SAMPLE switch to complete the charging (its capacitance is 4 times that of the small capacitor C of LSB); all the small capacitors C of LSB are connected to VIN through a shared CLK_SAMPLE switch for unified charging; at this time, SEL is in standby mode, the switches of VREFP and VREFN branches are turned off, and CLKD maintains stable sampling.
[0052] The third step, charge redistribution and dynamic matching stage: CLKD switches to this phase, all sampling switches are turned off, and branch switches are turned on; high-order B[2] and BN[2] drive the MSB branch switch, control the large capacitor 4C to connect to VREFP or VREFN, and the charge is transmitted to the loop filter through the common node 1; low-order B[1:0] triggers the dynamic matching circuit, SEL is activated, and the modulo 3 adder and pointer register are linked to update the pointer. The decoder selects SEL[2], SEL[1], SEL[0] and SELN[2], SELN[1], SELN[0] to realize the rotation selection of the small LSB capacitor, average the mismatch error, and finally complete the overall charge output.
[0053] This DAC eliminates the need for a binary-to-thermometer conversion circuit, and its 3-bit control requires only 3 binary lines (replacing the traditional 5 lines), saving on wiring. The MSB-independent and LSB-shared sampling switch design reduces hardware complexity, and the simplified dynamic matching circuit suppresses LSB mismatch distortion, making it suitable for high-speed and high-precision scenarios.
[0054] In this embodiment, the entire Sigma-Delta modulator adopts a third-order single-loop structure with a sampling frequency of 6.144MHz and an oversampling ratio (OSR) of 128. Figure 4 The output spectrum of the Sigma-Delta ADC without DWA processing is shown below, using a traditional temperature code DAC. Figure 5The output spectrum of the Sigma-Delta ADC using the binary dynamic matching DAC of this invention is shown. Simulation results show that the Sigma-Delta ADC using the dynamic matching circuit of this invention achieves an average signal-to-noise ratio (SNDR) of 91.1 dB under the condition of an input 5.25 kHz sine wave signal; compared with the temperature code DAC without dynamic matching (SNDR≈59 dB), the linearity is significantly improved; compared with the temperature code DAC using DWA, the linearity optimization effect is basically the same, but the number of control signals is reduced from 7 to 3, eliminating the need for a binary-to-temperature code conversion circuit, reducing the overall hardware area by about 30%, and reducing the critical path delay by about 35%.
[0055] In summary, this embodiment verifies the effectiveness of the dynamic matching circuit described in this invention in a 3-bit multi-level Sigma-Delta ADC. It can achieve excellent linearity and dynamic performance while significantly reducing control complexity and hardware overhead, making it suitable for high-speed and high-precision ADC applications.
Claims
1. A binary dynamically matched DAC for a multi-bit quantized Sigma-Delta ADC, characterized in that, The DAC includes an MSB capacitor array, an LSB capacitor array, a simplified dynamic element matching (DWA) circuit, and a switch array. It receives an N-bit control code, splits it into high-order control code B[N-1:2] and low-order control code B[1:0], and uses binary encoding to control the switch array. The high-order control code B[N-1:2] directly connects to and controls the corresponding branch in the switch array, driving the MSB capacitor array composed of large, low-mismatch capacitors. One end of each capacitor in the MSB array is selectively connected to VREFP or VREFN via a corresponding switch, and the other end is connected to form a common node for charge redistribution. The low-order control code B[1:0] connects to the simplified dynamic element matching circuit, which processes it and controls the corresponding branch of the switch array, driving the LSB capacitor array composed of small capacitors. One end of each capacitor in the LSB array is selectively connected to VREFP or VREFN via a corresponding switch, and the other end is connected to the common node of the MSB capacitor array. Dynamic rotation matching compensates for the small capacitor mismatch error, reducing the nonlinearity of the Sigma-Delta ADC.
2. The binary dynamically matched DAC of a multi-bit quantized Sigma-Delta ADC according to claim 1, characterized in that, The MSB capacitor array is composed of large capacitor units, and its mismatch has a small impact, so dynamic matching is not required, which simplifies the control logic. The LSB capacitor array is composed of small capacitor units, and its mismatch has a large impact. By controlling the selection logic of the corresponding switches through a simplified dynamic element matching circuit, the dynamic rotation of small capacitor units can be realized, which effectively suppresses nonlinear distortion and ensures the accuracy of charge redistribution.
3. The binary dynamically matched DAC of a multi-bit quantized Sigma-Delta ADC according to claim 1, characterized in that, The simplified dynamic element matching circuit includes a modulo-3 adder, a pointer register, and a selection decoder; the modulo-3 adder receives the low-order control code B[1:0] and updates the current pointer in the pointer register, and the selection decoder cyclically selects LSB capacitor units according to the current pointer to achieve dynamic matching.
4. The binary dynamically matched DAC of a multi-bit quantized Sigma-Delta ADC according to claim 1, characterized in that, The MSB capacitor array adopts an independent sampling switch design, with each large capacitor unit corresponding to an independent sampling switch. One end of each sampling switch is connected to the corresponding large capacitor unit, and the other end is connected to the sampling signal, realizing independent sampling of each large capacitor unit and reducing the load pressure of a single switch.
5. The binary dynamically matched DAC of a multi-bit quantized Sigma-Delta ADC according to claim 1, characterized in that, The LSB capacitor array adopts a shared sampling switch design, in which all small capacitor units share a single sampling switch. One end of the sampling switch is connected to all small capacitor units simultaneously, and the other end is connected to the sampling signal, which adapts to the sampling requirements of small capacitors and simplifies the switch layout.
6. The binary dynamically matched DAC of a multi-bit quantized Sigma-Delta ADC according to claim 1, characterized in that, In the MSB capacitor array, each capacitor unit adopts a binary weighting ratio. In the LSB capacitor array, each small capacitor unit has the same capacitance value and is the minimum weighted capacitance value. The capacitance ratio of the large capacitor unit and the small capacitor unit is adapted to the requirements of sampling and holding and binary quantization. The two achieve charge redistribution by sharing a common node.