A high-speed imaging device and method based on dynamic vision sensor

Abstract

The application belongs to the technical field of high-speed imaging, and discloses a high-speed imaging device and method based on a dynamic visual sensor.The application comprises an optical sensing subsystem, a data processing subsystem, a target imaging subsystem and a communication interaction subsystem connected in sequence.The optical sensing subsystem comprises an optical sensing module, and the optical sensing module comprises a dynamic visual sensor.The dynamic visual sensor is used for converting optical information generated by a moving target into an analog electric signal, and the optical sensing subsystem is used for compiling the analog electric signal into a digital signal.The data processing subsystem is used for generating high-speed event information according to the digital signal.The target imaging subsystem is used for generating a real-time image according to the high-speed event information.The communication interaction subsystem is used for compiling the real-time image into a video stream.The application can realize high-speed imaging under complex light conditions.

Description

Technical Field

[0001] This invention belongs to the field of high-speed imaging technology, and more specifically, relates to a high-speed imaging device and method based on a dynamic vision sensor. Background Technology

[0002] The rapid development of technologies such as low-altitude economy and autonomous driving has placed new pressure on the real-time observation of high-speed targets in the air, on the ground, and at sea. However, traditional cameras are slow to image and cannot operate under complex optical conditions such as low light. The industry urgently needs high-speed imaging under complex optical conditions. The development of advanced technologies such as computer vision has provided technical support for the research and deployment of high-speed imaging devices. The application of these technologies makes it possible to observe high-speed targets more clearly and to image them at higher speeds in a wider range of scenarios. The challenge of high-speed imaging technology lies in the coordinated operation of its devices and methods. A high-speed target imaging system should include functions such as clear imaging of high-speed scenes, resistance to ambient light interference, and interaction with operators. The system's imaging clarity, imaging speed, and ability to resist ambient light interference determine the overall performance of the high-speed imaging system.

[0003] Although developing high-speed imaging systems with high imaging speed, strong anti-interference ability, and high reliability has become an important research direction, achieving stable imaging under different ambient light conditions while ensuring certain key technical indicators such as imaging accuracy and imaging speed remains a recognized challenge in the industry. Summary of the Invention

[0004] This invention provides a high-speed imaging device and method based on a dynamic vision sensor, which solves the problem of high-speed imaging under complex lighting conditions in existing technologies.

[0005] The present invention provides a high-speed imaging device based on a dynamic vision sensor, comprising an optical sensing subsystem, a data processing subsystem, a target imaging subsystem, and a communication interaction subsystem connected in sequence; the optical sensing subsystem includes an optical sensing module, and the optical sensing module includes a dynamic vision sensor; The dynamic vision sensor is used to convert optical information generated by a moving target into analog electrical signals; the optical sensing subsystem is used to compile the analog electrical signals into digital signals; the data processing subsystem is used to generate high-speed event information based on the digital signals; the target imaging subsystem is used to generate real-time images based on the high-speed event information; and the communication interaction subsystem is used to compile the real-time images into a video stream.

[0006] Preferably, the optical sensing subsystem further includes a first configuration module and a first data interface module; the optical sensing module further includes a trajectory filter, an event filter, and a strobe filter; The first data interface module is used to receive chip configuration information from the data processing subsystem and transmit it to the first configuration module. The first configuration module is used to send the chip configuration information to the optical sensing module. The optical sensing module is also used to parse the chip configuration information and drive the activation or deactivation of three filters according to the parsed information. When the trajectory filter is activated, it counts the event triggers for each pixel and outputs only events in a specific order by setting trajectory definition parameters to eliminate redundant trajectory tails. When the event filter is activated, it calculates the discard rate based on the total number of events within the sampling time and randomly discards events with dynamic probability in the X-axis, Y-axis, and time dimensions. When the flicker filter is activated, it continuously monitors the burst cycle of positive polarity events. If periodic flicker is detected, it marks and blocks the data of the corresponding pixel area.

[0007] Preferably, the first configuration module includes an analog voltage modulation unit, a digital voltage modulation unit, a clock signal generation unit, a power-on timing control unit, a communication initialization unit, and a data pass-through unit; The analog voltage modulation unit is used to provide analog voltage; the digital voltage modulation unit is used to provide digital voltage; the clock signal generation unit is used to generate clock signal; the power-on timing control unit is used to receive the clock signal and control the first data interface module and the optical sensing module to power on according to a preset timing sequence; the communication initialization unit is used to perform communication initialization; the data pass-through unit is used to send the chip configuration information to the optical sensing module after the communication initialization is completed.

[0008] Preferably, the data processing subsystem includes a second data interface module, a register control module, a data decoding module, and a high-speed buffer module; The second data interface module is used to perform preliminary parsing of the digital signal from the optical sensing subsystem and send it to the data decoding module, and to compile the register control information sent by the register control module into chip configuration information and send it to the optical sensing subsystem; the register control module is used to convert the imaging mode selection information sent by the communication interaction subsystem into the register control information; the data decoding module is used to decode the digital signal initially parsed by the second data interface module into high-speed event information, which only includes polarity, timestamp, and coordinates; the high-speed buffer module is used to cache the high-speed event information and send it to the target imaging subsystem.

[0009] Preferably, the data decoding module includes a protocol decoding submodule and an event parsing submodule; the protocol decoding submodule is used to identify and strip the packet header, length field and checksum of the data packet; the event parsing submodule is used to receive the valid data stream output by the protocol decoding submodule, extract the time and coordinate information required for the event, generate an event queue and output it to the high-speed buffer module; the high-speed buffer module uses an asynchronous FIFO to connect the data decoding module and the target imaging subsystem.

[0010] Preferably, the target imaging subsystem includes an imaging control module, an imaging computation module, and a memory control module; The imaging control module is used to send a data read control command to the memory control module according to the imaging mode selection information sent by the communication interaction subsystem, and simultaneously send a periodic control command to the imaging calculation module; the imaging calculation module is used to perform imaging calculations on the high-speed event information according to the periodic control command and the imaging mode selection information sent by the communication interaction subsystem, and send the real-time calculation results to the memory control module; the memory control module performs memory readout control according to the data read control command, and writes the real-time calculation results into memory to obtain the real-time image.

[0011] Preferably, the imaging processing module has three parallel data links: event frame, histogram, and time surface. The imaging processing module selects one of these data links to operate based on the imaging mode selection information. The memory control module has three parallel memory access links corresponding to the three data links of the imaging processing module, and automatically switches when the data links of the imaging processing module switch. The memory control module includes two random access memories, a read data controller, and a write data controller. The read and write operations of the two random access memories are interleaved.

[0012] Preferably, the high-speed imaging device based on the dynamic vision sensor further includes: peripheral equipment; the peripheral equipment includes an optical lens, an operating device, and a display device; the optical lens is connected to the optical sensing subsystem; the data processing subsystem, the target imaging subsystem, and the communication interaction subsystem are all deployed in the imaging assembly electronic device, and the operating device and the display device are both connected to the imaging assembly electronic device; The optical lens is configured to capture optical information corresponding to the visible light band and near-infrared band within the lens's field of view in real time; the operating device is used to display and store the real-time image, and to receive configuration instructions input by the operator; the display device is used to display the video stream.

[0013] Preferably, the communication interaction subsystem is further configured to receive configuration instructions from the operating device, and parse them to form imaging mode selection information.

[0014] On the other hand, the present invention provides a high-speed imaging method based on a dynamic vision sensor, implemented using the aforementioned high-speed imaging device based on a dynamic vision sensor, the high-speed imaging method comprising the following steps: The optical sensing subsystem utilizes a dynamic vision sensor to convert optical information generated by a moving target into analog electrical signals, and then uses the optical sensing subsystem to encode the analog electrical signals into digital signals. Using the data processing subsystem, high-speed event information is generated based on the digital signal; Real-time images are generated using the target imaging subsystem based on the high-speed event information; The real-time images are compiled into a video stream using the communication interaction subsystem.

[0015] One or more technical solutions provided in this invention have at least the following technical effects or advantages: (1) This invention utilizes a dynamic vision sensor to convert the optical information generated by a moving target into an analog electrical signal, and uses an optical sensing subsystem to compile the analog electrical signal into a digital signal. Since the working principle of the dynamic vision sensor is different from the full-frame integration exposure mode of a traditional camera, its internal pixels independently and asynchronously detect changes in light intensity. Only when the change in light intensity exceeds a certain threshold will it be activated and output a signal. The background and static areas other than the pixel where the event occurred do not generate data. Therefore, this event-response-based mechanism makes the imaging process no longer dependent on the absolute brightness of the environment, but on the logarithmic change in light intensity. Under strong backlight or high exposure conditions, the sensor can ignore the oversaturated static background and only capture the edge changes of the moving target, thereby avoiding the situation where the target cannot be identified due to the background being too bright. Under low illumination conditions, as long as there is a light intensity contrast between the moving target and the background, the sensor can capture the light intensity change signal, without being limited by insufficient overall light intake. The mechanism of the dynamic vision sensor means that the sensor does not need to wait for the entire frame of image exposure to complete, but can respond instantly to every tiny displacement of a high-speed target with microsecond-level time precision. This enables the invention to achieve high-speed imaging in complex lighting scenarios such as low light and high exposure, where traditional cameras cannot clearly image or have difficulty imaging. Furthermore, because the dynamic vision sensor only generates data for moving targets in the field of view, i.e., areas of light intensity change, and automatically filters out static background areas that do not produce light intensity changes, the amount of data output by the system is extremely small and highly sparse. This data sparsity greatly reduces the transmission bandwidth pressure between the optical sensing subsystem and the data processing subsystem, eliminating the transmission delay and computational bottleneck caused by traditional high-speed cameras processing massive amounts of full-frame pixel data. Thanks to the dynamic vision sensor's characteristic of responding only to changes and outputting asynchronously, the invention can achieve real-time capture of high-speed moving targets while ensuring low latency, achieving an imaging speed equivalent to thousands of frames per second or even higher, completely solving the problem of insufficient imaging speed when dealing with high-speed targets.

[0016] (2) The present invention provides the optical sensing module with precise digital and analog voltage and power-on timing control signals through the first configuration module. The discrete analog voltage modulation unit and digital voltage modulation unit ensure extremely low noise and ripple in the power supply of the photosensitive element, which is beneficial to improve the signal-to-noise ratio and capture weak light intensity changes in low illumination environments. In addition, the first configuration module is responsible for forwarding the chip configuration data sent by the first data interface module. This configuration data includes key parameters such as trajectory filtering, event filtering and stroboscopic filtering. Therefore, when facing complex artificial lighting environments, such as fluorescent lamp stroboscopic or high noise interference, the device can dynamically load the filtering parameters through this module, so that the front-end sensor can directly suppress the interference events caused by periodic flickering light sources at the hardware level, thereby outputting a pure target signal under complex lighting conditions, ensuring the clarity of the image, and further ensuring that the present invention can effectively image under harsh lighting conditions.

[0017] (3) The data processing subsystem in this invention is not only responsible for generating high-speed event information, but also for configuring the characteristics of the optical sensing subsystem. This means that under complex lighting conditions, such as flicker or noise, the subsystem can optimize the response characteristics of the sensor and perform preliminary analysis and denoising of the original signal to ensure that the output event information contains key elements such as polarity and timestamp, thereby eliminating invalid data caused by ambient light interference. The second data interface module and the register control module inside the data processing subsystem work together to play a role in configuration and feedback adjustment of the system. The register control module translates the imaging instructions sent by the communication interaction subsystem into register control information, which is then compiled into chip configuration instructions by the second data interface module and sent back to the optical sensing subsystem. This reverse control mechanism enables the device to dynamically enable or adjust the trajectory filtering, event filtering, and flicker filtering functions of the front-end sensor according to the current lighting environment. For example, under complex lighting conditions, invalid background noise events can be filtered out through instruction configuration to ensure that the data entering the subsequent processing flow only contains the feature information of the effective target, thereby ensuring the signal-to-noise ratio and clarity of imaging under extreme lighting conditions. In addition, the target imaging subsystem utilizes high-speed event information to generate real-time images. Through specific algorithms, the target imaging subsystem reconstructs discrete event streams into visualized images, enabling it to extract target motion features against high-exposure backgrounds without being affected by background brightness saturation, or to form clear target outlines by accumulating events in low-light conditions.

[0018] In summary, this invention enables high-speed imaging under complex lighting conditions. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the framework of a high-speed imaging device based on a dynamic vision sensor provided in Embodiment 1 of the present invention.

[0020] Figure 2 This is a schematic diagram of the working process of the optical sensing module in Embodiment 1 of the present invention.

[0021] Figure 3 This is a schematic diagram of the workflow of the first configuration module in Embodiment 1 of the present invention.

[0022] Figure 4 This is a schematic diagram of the workflow of the first data interface module in Embodiment 1 of the present invention.

[0023] Figure 5 This is a schematic diagram of the internal structure of the data processing subsystem in Embodiment 1 of the present invention.

[0024] Figure 6 This is a schematic diagram of the working process of the register control module in Embodiment 1 of the present invention.

[0025] Figure 7 This is a schematic diagram of the workflow of the data decoding module in Embodiment 1 of the present invention.

[0026] Figure 8 This is a schematic diagram of the working process of the high-speed buffer module in Embodiment 1 of the present invention.

[0027] Figure 9 This is a schematic diagram of the workflow of the imaging control module in Embodiment 1 of the present invention.

[0028] Figure 10 This is a schematic diagram of the workflow of the imaging calculation module in Embodiment 1 of the present invention.

[0029] Figure 11 This is a schematic diagram of the memory control module in Embodiment 1 of the present invention operating in the event frame link.

[0030] Figure 12 This is a schematic diagram of the memory control module in Embodiment 1 of the present invention operating in the histogram link mode.

[0031] Figure 13 This is a schematic diagram of the memory control module in Embodiment 1 of the present invention operating in the time surface link.

[0032] Figure 14 This is a schematic diagram of the working process of the HDMI display module and the USB data module in Embodiment 1 of the present invention.

[0033] Among them, 100-Optical sensing subsystem, 200-Data processing subsystem, 300-Target imaging subsystem, 400-Communication interaction subsystem, 500-Optical lens, 600-Operating device, and 700-Display device; 110 - Optical sensing module, 120 - First configuration module, 130 - First data interface module; 121-Analog voltage modulation unit, 122-Digital voltage modulation unit, 123-Clock signal generation unit, 124-Power-on timing control unit, 125-Communication initialization unit, 126-Data transparent transmission unit; 210 - Second data interface module, 220 - Register control module, 230 - Data decoding module, 240 - High-speed buffer module; 231 - Protocol Decoding Submodule; 232 - Event Parsing Submodule; 310 - Imaging control module, 320 - Imaging calculation module, 330 - Memory control module; 410 - HDMI display module, 420 - USB data module; 610 - Parameter Configuration Module, 620 - Storage and Visualization Module. Detailed Implementation

[0034] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0035] Example 1: Example 1 provides a high-speed imaging device based on a dynamic vision sensor, see [link to example]. Figure 1 The system mainly comprises an optical sensing subsystem 100, a data processing subsystem 200, a target imaging subsystem 300, and a communication interaction subsystem 400, connected in sequence. The optical sensing subsystem 100 includes an optical sensing module 110, which includes a dynamic vision sensor. The dynamic vision sensor converts optical information generated by a moving target into analog electrical signals, and the optical sensing subsystem 100 converts these analog electrical signals into digital signals. The data processing subsystem 200 generates high-speed event information based on the digital signals. The target imaging subsystem 300 generates real-time images based on the high-speed event information. The communication interaction subsystem 400 compiles the real-time images into a video stream.

[0036] The optical sensing subsystem 100 further includes a first configuration module 120 and a first data interface module 130; the optical sensing module 110 further includes a trajectory filter, an event filter, and a strobe filter.

[0037] The first data interface module 130 is used to receive chip configuration information from the data processing subsystem 200 and transmit it to the first configuration module 120. The first configuration module 120 is used to send the chip configuration information to the optical sensing module 110. The optical sensing module 110 is also used to parse the chip configuration information and drive the activation or deactivation of three types of filters (i.e., trajectory filter, event filter, and flicker filter) according to the parsed information.

[0038] The trajectory filtering uses a counter mechanism. When the trajectory filter is enabled, it counts the event triggers for each pixel. By setting the trajectory definition parameter str, it only outputs events in a specific order (such as the first or second event), thereby eliminating redundant trajectory trails generated by high-speed motion.

[0039] Event filtering abandons the traditional simple threshold truncation and instead adopts a dynamic probability-based discarding mechanism based on lookup tables (LUTs). For example, the event filter has a built-in LUT containing 576 values. When the event filter is enabled, it calculates the discard rate based on the total number of events within the sampling period and randomly discards events with dynamic probability in the X-axis, Y-axis, and time dimensions.

[0040] When the strobe filter is enabled, it continuously monitors the burst cycle of positive events. If periodic flickering is detected, the data in the corresponding pixel area is marked and blocked. For example, the strobe filter introduces a local adaptive monitoring mechanism for a 4×4 pixel area to continuously monitor the burst cycle of positive events. Once periodic flickering is detected, the data in that area is marked and blocked. When the interference disappears, the marking is automatically removed and the output is restored.

[0041] Specifically, the first configuration module 120 starts working first, generating analog and digital voltages to provide precise power to the optical sensing module 110, and at the same time, by powering the first data interface module 130, it sends chip configuration data to the optical sensing module 110.

[0042] See Figure 1 and Figure 2When the system starts working, the optical sensing module 110 maintains two data links simultaneously. The first data link parses the chip configuration data sent by the first configuration module 120. This chip configuration data includes two parts: chip configuration instructions and register configuration data. The module prioritizes parsing the chip configuration instructions and determines whether to enable or disable the trajectory filtering, event filtering, and strobe filtering functions based on these instructions. The enabling or disabling of these functions does not affect each other; when a function is disabled, the corresponding data processing step is skipped. The register configuration data corresponds to the internal parameters of the trajectory filtering parameter register, event filtering parameter register, and photosensitivity parameter register, respectively. The module stores these parameters in the corresponding registers for use in the data processing steps of the corresponding functions. Simultaneously, the second data link receives optical information through the dynamic vision sensor in the optical sensing module 110. The dynamic vision sensor has a high dynamic range and does not capture and output the entire scene image at fixed time intervals. It can be set with 1280×720 photosensitive pixels. Each pixel independently and asynchronously detects changes in light intensity. Only pixels whose light intensity changes exceed a specific threshold will be activated and report data. The threshold setting is determined by the electrical characteristics of the internal chip of the sensor. This embodiment does not operate its internal electrical components. Its internal photodiode continuously converts incident light into current. The current is converted into a voltage signal through a logarithmic current-to-voltage converter. When the change in voltage signal relative to its internal reference voltage exceeds a set positive or negative threshold, it is marked as an event. Light intensity exceeding the positive threshold is called a positive polarity event, and exceeding the negative threshold is called a negative polarity event. An event-encoded electrical signal is output. Each event-encoded electrical signal contains event coordinates, timestamp, and event polarity. No data is generated in the background and static areas other than the pixel where the event occurred. The optical sensing module 110 sets the coordinate range of the received event encoded electrical signal according to the photosensitive area parameters x and y stored in the photosensitive area parameter register. The coordinate range is based on the leftmost bottom pixel of the dynamic vision sensor as (0,0). When the coordinate is set to (x,y), it means that events with coordinates less than x and less than y will be received, and other events will be ignored. The maximum value of x is 1280, and the maximum value of y is 640.

[0043] When the aforementioned trajectory filtering function is enabled, the optical sensing module 110 calls the trajectory filtering parameters stored in the trajectory filter. The filtering parameters include a counter parameter and a trajectory definition parameter. When the trajectory filtering function is working, a counter is called, and the counter parameter is used as the counting endpoint. When an event is generated by a pixel, counting begins. Each time an event is generated, the counter is incremented by 1 until the counter value reaches the counting endpoint. Before reaching the counting endpoint, the pixel only outputs a specific event and blocks the output of other events. The specific event is determined by the trajectory definition parameter str, which can be specified as the first, second, or first and second events of the current count of the pixel. The trajectory filtering function can call multiple counters simultaneously for multiple pixels, effectively filtering out the trajectory generated by the same pixel when a high-speed target moves.

[0044] When the aforementioned event filtering function is enabled, the optical sensing module 110 calls the event filtering parameters stored in the event filter. The filtering parameters include the sampling duration parameter T, the total event quantity limit parameter r0, and the discard rate parameter group LUT. The reference event parameter T is a time unit, with a minimum value of 200 microseconds. The LUT contains 576 values ​​and their corresponding 576 indices, including 512 time axis discard rates lutt and their 9-bit binary index slutt, 32 x-axis discard rates lutx and their 5-bit binary index slutx, and 32 y-axis discard rates luty and their 5-bit binary index sluty. When the event filtering function is working, it calculates the total number of events within time T using a counter, denoted as rin. When r0 > rin, the total discard rate α = 0. When r0 ≦ rin, the total discard rate α = (1 - lut0) × (1 - lut1) × (1 - lut2). When this function is working, the total number of events output is rout = rin × α. Calculate r0 / rin = αr and take the decimal of αr. Partially denoted as α0, α0 is a 9-bit binary number. Based on α0, the slutt of lutt in the LUT is retrieved. When α0 = slutt, lut0 = lutt. The first five bits of α0 are taken and denoted as α1. The index slutx of lutx in the LUT is retrieved. When α1 = slutx, lut1 = lutx. The index sluty of luty in the LUT is retrieved. When lut1 = slut, lut2 = luty. Thus, the output event quantity rout when this function is working can be obtained as rout = rin × (1 - lutx) × (1 - luty) × (1 - lutt). At the same time, after receiving an event at a certain moment, this module randomly discards all events in the x direction with probability value slutx and all events in the x direction with probability value sluty. At the same time, all events T within time T are randomly discarded with probability value slutt. This method of randomly discarding events with dynamic probability values ​​avoids the limitation of the event quantity threshold due to crude event quantity threshold, which is beneficial to the overall dynamic range of this device.

[0045] The strobe filtering function effectively suppresses interference events caused by periodically flickering light sources (such as fluorescent lamps and LED lights) under complex lighting conditions, improving the capture quality of high-speed target motion information. This non-conflicting function uses a 4×4 pixel area as the processing unit, continuously monitoring the time interval of positive events within each area. When a periodicity is detected in the interval between event bursts, the area is marked as being affected by strobe interference. Subsequently, all event data generated within this area will be automatically filtered out. When the flicker pattern of the light source changes or disappears, the marking of the area will be automatically removed, restoring normal event output.

[0046] After the above-mentioned functions are completed, the optical sensing module 110 re-encodes the event data and sends the encoded electrical signal to the first data interface module 130.

[0047] Specifically, this invention integrates three dedicated hardware filters within the optical sensing module 110, which are directly driven by chip configuration instructions. The invention utilizes trajectory filtering to effectively solve the motion blur and trailing problems common in high-speed target imaging, resulting in sharper target contours; probabilistic event filtering preserves the spatiotemporal structural features of the target while ensuring uninterrupted data throughput, avoiding data gaps; and stroboscopic filtering enables the device to operate in complex artificial lighting environments, automatically isolating ambient light interference without affecting the capture of the real target. These designs significantly improve the signal-to-noise ratio and effectiveness of the front-end data, and these pre-processing steps greatly reduce the computational burden on the back-end data processing subsystem.

[0048] See Figure 1 and Figure 3 The first configuration module 120 includes an analog voltage modulation unit 121, a digital voltage modulation unit 122, a clock signal generation unit 123, a power-on timing control unit 124, a communication initialization unit 125, and a data pass-through unit 126. The analog voltage modulation unit 121 provides analog voltage; the digital voltage modulation unit 122 provides digital voltage; the clock signal generation unit 123 generates a clock signal; the power-on timing control unit 124 receives the clock signal and controls the first data interface module 130 and the optical sensing module 110 to power on according to a preset timing sequence; the communication initialization unit 125 performs communication initialization; and the data pass-through unit 126 sends the chip configuration information to the optical sensing module 110 after communication initialization is completed.

[0049] See Figure 3The first configuration module 120 provides controlled power distribution, timing management, and communication initialization support to the optical sensing module 110, the first data interface module 130, and subsequent communication units during the power-on phase, thereby ensuring stable startup and reliable operation of the overall data link. The analog voltage modulation unit 121 provides a 3.00V analog voltage to power the VINP, VINA, VDDHCP, and VDDSUB pins of the dynamic vision sensor, maintaining a maximum voltage swing of no more than 10mV per microsecond during power-on to reduce noise and ripple. The digital voltage modulation unit 122 generates 1.10V and 1.80V digital voltages, respectively supplying the clock signal generation unit 123, the clock signal generation unit 123, and subsequent logic circuits, ensuring isolation between the digital and analog domains. After obtaining the 1.10V digital voltage, the clock signal generation unit 123 generates a system clock and provides a synchronization reference to the power-on timing control unit 124. The power-on timing control unit 124 receives the clock signal and releases the enable control of each functional unit according to a preset timing sequence. The preset timing sequence is as follows: after the clock signal is generated, the first data interface module 130 is powered on 30ms later, and the optical sensing module 110 is powered on 75ms later, ensuring that each module is gradually and controlled to power on, avoiding the risk of transient impact. After the analog / digital voltage stabilizes and is released by the power-on timing control unit 124, the communication initialization unit 125 detects the idle state of the serial data line SDA and the serial clock line SCL, releases the pull-up resistors and input buffers in sequence, sets the rate to 115200, and outputs 9 consecutive pulses on the SCL signal line and issues a STOP command when a line abnormality is detected, and re-initializes to prevent data pass-through. After initialization, the data pass-through unit 126 sends the chip configuration information sent by the first data interface module 130 to the optical sensing module 110 to realize the parameter configuration of the dynamic vision sensor.

[0050] See Figure 1 and Figure 4 The first data interface module 130 is configured to complete the signal access, configuration instruction conversion and data forwarding of the chip configuration instruction sent from the second data interface module 210, and to work in cooperation with the second data interface module 210 through a flexible printed circuit board (FPC) multi-channel interface to compile the electrical signal sent from the optical sensing module 110 into a digital signal and then send it to the second data interface module 210.

[0051] Specifically, the FPC multiplexer sends the chip configuration command to the first data interface module 130. The signal decomposer parses the header of each signal frame of the input signal, generating two outputs: one is the chip configuration data, and the other is the photosensitive control signal group. The photosensitive control signal sequentially confirms the clock enable signal XCLR, the power ready signal CLKI, and the reset disable signal RSTN. The information in the chip configuration data begins to be interpreted and forwarded only when all three signals are at a high level and remain high for 200ns. If any condition is not met, the configuration command is postponed or rejected to avoid misconfiguration caused by abnormal timing. One chip configuration requires 297 configuration groups consisting of 32-bit indexes and 32-bit instructions, including 1 track filter enable configuration group, 1 event filter enable configuration group, 1 strobe filter enable configuration group, 2 track filter parameter configuration groups, 288 event filter parameter configuration groups, 2 photosensitive area configuration groups, and 2 event filter parameter supplementary configuration groups. The translation rules for these configuration groups are as follows: After confirming the instruction object through the index, the trajectory filter enable configuration group, event filter enable configuration group, and strobe filter enable configuration group will form the 32-bit instruction into a chip configuration instruction; the lower 16 bits of the 32-bit index of the two trajectory filter parameter configuration groups and the two photosensitive area configuration groups will be compiled into register addresses, and the 32-bit instruction will be compiled into register contents, forming the photosensitive area parameters x, y and trajectory filter parameters str in the register configuration data; among the 288 event filter parameter configuration groups, there are 256 time dimension parameter configuration groups and 32 spatial dimension parameter configuration groups, and the 3... The 2-bit index is divided into 16-bit register address a and 16-bit register address b. Bits 1 to 9 of the 32-bit instruction are split into 9-bit binary indices slutt-a, bits 10 to 18 into 9-bit binary indices slutt-b, bits 19 to 25 into time axis discard rate lutt-a, and bits 26 to 32 into time axis discard rate lutt-b. slutt-a + lutt-a and slutt-b + lutt-b form the discard rate parameter group LUT. Two event filtering parameter supplementary configuration groups compile the 32-bit instruction into a sampling duration parameter T and a total event limit parameter r0. The above instructions and parameters are sent to the optical sensing module 110. To reduce signal transmission interference, the electrical signals sent from the optical sensing module 110 are compiled into a data frame format with a packet header, packet trailer, and 32 event packets. Each event packet consists of a 4-bit identification header and 12 data bits. The frame header and trailer are used for start / end marking and verification. The identification header is used to identify field types, including event coordinate information, time information, and continuous event coordinate information, with data bits carrying the corresponding information. The compiled data frame is sent to the second data interface module 210 as a digital signal via the FPC multiplexing interface.

[0052] In summary, the optical sensing subsystem 100 of this invention has made substantial improvements in terms of photosensitive mechanism, signal preprocessing, and underlying hardware support, thereby achieving significant and advantageous technical effects. These include: (1) The optical sensing subsystem 100 improves the core photosensitive method by adopting a dynamic visual sensor. Unlike the full-frame integral exposure mode used by traditional image sensors, the photosensitive element in this scheme is composed of, for example, 1280×720 independent pixels. Each pixel independently monitors changes in light intensity and outputs a signal asynchronously only when the change exceeds a threshold. The technical effect of this improvement is that it gives the device an extremely high dynamic range and microsecond-level temporal resolution, enabling it to keenly capture weak light intensity fluctuations under low illumination and to directly extract the target contour under strong backlight without ignoring background saturation. At the same time, the sparse event stream data generated eliminates redundant background information, laying a low-bandwidth data foundation for high-speed real-time processing in the backend. (2) The optical sensing subsystem 100 directly drives the hardware logic through chip configuration instructions. It has built-in a counter-based trajectory filter, a lookup table (LUT)-based probabilistic event filter, and a region-adaptive strobe filter, which significantly improves the signal-to-noise ratio of the output signal and ensures the purity of the data in complex lighting and artificial lighting environments, greatly reducing the computational burden of the subsequent data processing subsystem. (3) The first configuration module 120 introduces discrete analog and digital voltage modulation units and performs strict power-on timing control to ensure extremely low noise and ripple in the power supply of the photosensitive element, effectively preventing power-on transient impacts. In conjunction with the first data interface module 130, the original electrical signal is compiled into a digital frame format containing the identification head and check bits, and high-speed differential transmission is achieved through the FPC multi-channel interface, ensuring the integrity and real-time performance of massive amounts of tiny event data during transmission, providing reliable front-end support for the entire high-speed imaging system.

[0053] See Figure 1 and Figure 5 The data processing subsystem 200 parses and compiles digital signals into high-speed event information containing polarity, timestamps, and trajectory vectors. The data processing subsystem 200 includes a second data interface module 210, a register control module 220, a data decoding module 230, and a high-speed buffer module 240.

[0054] The second data interface module 210 is used to perform preliminary analysis on the digital signal from the optical sensing subsystem 100 and send it to the data decoding module 230, and to compile the register control information sent by the register control module 220 into the chip configuration information (i.e., chip configuration instructions) and send it to the optical sensing subsystem 100.

[0055] The register control module 220 is used to convert the imaging mode selection information sent by the communication interaction subsystem 400 into the register control information.

[0056] The data decoding module 230 is used to decode the digital signal initially parsed by the second data interface module 210 into high-speed event information, which only includes polarity, timestamp, and coordinates. The data decoding module 230 includes a protocol decoding submodule 231 and an event parsing submodule 232. The protocol decoding submodule 231 is used to identify and strip the packet header, length field, and checksum of the data packet. The event parsing submodule 232 is used to receive the valid data stream output by the protocol decoding submodule, extract the time and coordinate information required for the event, and generate an event queue to output to the high-speed buffer module.

[0057] The high-speed buffer module 240 is used to cache the high-speed event information and send it to the target imaging subsystem. The high-speed buffer module 240 utilizes an asynchronous FIFO to connect the data decoding module and the target imaging subsystem.

[0058] See Figure 5The data processing subsystem 200 has a relatively complex signal line connection. These signal lines connect important hardware within the subsystem. The reliability of the system is ensured by stable physical signal line connections. There are two main parallel data streams: one is the data stream SD, which consists of the IIC configuration submodule, IIC register, and IIC controller; the other is the data stream SA, which consists of the physical parsing layer, MIPI parsing layer, protocol decoding submodule, event parsing submodule, and asynchronous FIFO. The core hardware of the data stream SD is the IIC register. It receives the start command from the IIC controller via EN_IIC, the read command from the IIC controller via WR_IIC, sends the register address to the IIC controller via ADDR[31:0], sends the register data to the IIC controller via DATA[31:0], sends the update complete signal to the IIC controller via Done, and receives the communication reset command via RSTN. The IIC controller is connected to the first data interface module 130 via the chip instruction interface. The chip instruction interface has four signal lines. The IIC controller sends the chip configuration command via SCL and SDA, ensures the clock synchronization of the first data interface module 130 via CLK, and receives the communication reset command via RSTN. The IIC configuration submodule is connected to the communication interaction subsystem 400 via the imaging command data line. It receives the ready command from the IIC register via Free, sends the register address to the IIC register via D_B[31:0], sends new register data to the IIC register via AD_B[31:0], and sends the ready command to the IIC register via Up_B. In the data stream SD, the physical resolution layer is connected to the first data interface module 130 through a high-speed digital interface. In the high-speed digital interface, clk_p and clk_n are clock signal lines, and data_p[1:0] and data_n[1:0] are high-speed differential data signal lines used to transmit digital signals to the physical resolution layer at high speed. The physical resolution layer receives, terminates, and equalizes the digital signals from the high-speed differential data signal lines.It arranges matching terminating resistors on the high-speed digital interface side to convert differential signals into internal signals with controlled swing. The physical resolution layer classifies differential signals into high-speed differential signals and low-speed differential signals. The MIPI resolution layer receives the clock of the high-speed differential signal from the physical resolution layer through clk_hs_p and clk_hs_n, receives the high-speed differential signal from the physical resolution layer through data_hs_p[1:0] and data_hs_n[1:0], receives the clock of the low-speed differential signal through clk_ls_p and clk_ls_n, and receives the low-speed differential signal through data_ls_p[1:0] and data_ls_n[1:0]. Since the device operates in a high-speed scenario for a long time, the four signal lines for low-speed differential signal transmission exist as backups for the high-speed differential signal lines. The MIPI resolution layer uses clk_hs_p and clk_hs_n clock signals. The clock signal is sampled at the optimal phase point, converting the serial bit stream of the high-speed differential signal into a parallel 8-bit high-speed digital signal, generating a synchronization flag and aligning the data, and generating a data valid signal; the protocol decoding submodule 231 receives the high-speed digital signal sent by the MIPI parsing layer through the parallel signal line d0data[7:0], and receives the high-speed digital signal ready instruction through d0_valid; the event parsing submodule 232 receives the data valid instruction sent by the protocol decoding submodule 231 through mipi_csi_data_en, and receives the high-speed digital signal sent by the protocol decoding submodule 231 through mipi_csi_data[15:0]; the asynchronous FIFO receives the high-speed event information sent by the event parsing submodule 232 through event[63:0], and connects to the imaging calculation module 320 through the buffer read data line.

[0059] See Figure 6 The register control module 220 adopts a serial structure. Its internal IIC configuration submodule receives the imaging command from the communication interaction subsystem 400, parses the command, verifies its data compliance, generates a 32-bit binary address code based on the command content, and compiles the command content into 32-bit binary register data. The specific compilation rules are the same as the chip configuration command interpretation rules in the first data interface module 130. The register readiness determination unit decides whether to initiate an access based on the busy / idle status of the IIC register: if the register is idle, a read / write operation on the IIC register is triggered; if the register is busy, it waits or retryes. The busy / idle determination is completed based on the aforementioned Free and Up_B signal lines. After completing one access, the IIC register feeds back its status and data to the outside via the register configuration data line, realizing a closed-loop transmission and update of configuration commands from USB to the IIC configuration submodule to the IIC register.

[0060] See Figure 7The data decoding module 230 comprises two parts: a protocol decoding submodule 231 and an event parsing submodule 232. The protocol decoding submodule 231 receives 16-bit parallel data and its valid indication signal from the second data interface module 210, extracts the payload from the data stream, and outputs it to the subsequent event parsing submodule 232. In the link idle state, the protocol decoding submodule 231 continuously monitors the high byte of the input data. When it detects a header identifier that meets a preset rule, it determines that a new data packet has started, thus completing header verification and synchronization. The preset rule is hexadecimal 0x30. After successful header recognition, the protocol decoding submodule 231 considers the following data to be a length information field related to the packet. The length field is loaded in two clock cycles (beats), which is equivalent to dividing the length information into a high-order part and a low-order part and sending them separately. In the first beat (the current beat when the header is successfully recognized), the lower 8 bits of the current word are written as the high-order part of the length field into the corresponding bit segment of the internal length register. In the second beat, the higher 8 bits are extracted from the following word and written as the low-order part of the length field, finally obtaining the payload length statistics. After entering the valid verification stage, the protocol decoding submodule 231... Module 231 continuously observes the high 4 bits of the type field of the input valid data word. When it detects that the type field is equal to the preset flag, it considers that a payload segment that can be interpreted downstream has begun to appear, thus completing a valid verification. In this embodiment, the flag is 0x8. After the verification is successful, the protocol decoding submodule 231 enters the data forwarding state and forwards the current data to the downstream event parsing submodule 232. As long as the input valid indication is true, the protocol decoding submodule 231 forwards the 16-bit data as is and sets the output valid flag to true. At the same time, the submodule maintains a payload counter. When it is in the data forwarding state and the input is valid, the counter increments according to the clock cycle. When the counter data is consistent with the aforementioned payload length, it enters the packet tail verification state. The protocol decoding submodule 231 performs continuous counting monitoring on two typical packet tails. 0x0000 or 0x00FF will trigger the counting. When the count reaches 3 consecutive times, it is determined that it has entered the packet tail region and switches to the packet header verification state. At the same time, this state switch retains a certain delay to avoid residual data at the tail disturbing the packet header recognition of the next packet.

[0061] The event parsing submodule 232 receives the valid data stream output by the protocol decoding submodule 231, performs field division and semantic interpretation on each 16-bit data word, extracts the time information and coordinate information required for the event, and generates an event queue to be output to the high-speed buffer module 240. Specifically, the event parsing submodule 232 first performs a reset and cache clearing. During reset, the time high-order and low-order cache registers, the X / Y coordinate cache register, and the event valid output are cleared. Whenever the input is valid (true), the event parsing submodule 232 reads the current 16-bit data word and takes its high 4 bits as the type field. The type field is used to divide the data word into 6 categories: time high-order word, time low-order word, Y coordinate word, X coordinate word, continuous event X start coordinate word, and continuous event length word. When the type is time high-order word and the input is valid, the low 12 bits of the word are written to the time high-order cache, which remains unchanged until the next time a time high-order word is encountered. When the type is time low-order word and the input is valid, the low 12 bits of the word are written to the time low-order cache. When the type is Y coordinate word and the input is valid, the low 11 bits of the word are written to the Y coordinate cache. When the type is X coordinate word and the input is valid, the low 12 bits of the word are written to the X coordinate cache. When the type is continuous event X start coordinate word and the input is valid, the low 12 bits of the word are written to the X coordinate cache. If the starting coordinate word of event X is valid, the lower 12 bits of the word are written into the continuous event starting point X coordinate buffer. At the same time, the lower 11 bits of the next data word are used as the continuous event length n. Based on the continuous event starting point X coordinate, the n consecutive coordinates of this event away from the 0 end along the x-axis are identified as X coordinate words. The lower 12 bits of each word are written into the X coordinate buffer in the same way as the X coordinate words. The event parsing submodule 232 takes the received continuous event starting coordinate word as the trigger point for the completion of a group of events. When the type of continuous event starting coordinate word X is detected and the input is valid, the fields of the current buffer are packaged into a 64-bit event data and output. The output 64-bit event is composed of four segments concatenated in a fixed order: time high-order buffer (16 bits), time low-order buffer (16 bits), Y-coordinate buffer (16 bits), and X-coordinate buffer (16 bits). The generated high-speed event data is sent to the high-speed buffer module 240 through the high-speed event data line.

[0062] See Figure 8Before writing event data, the high-speed buffer module 240 determines whether the buffer is ready. It first reads the full flag of the FIFO. When full=0, it means the FIFO is not full, and the buffer is ready to write. When full=1, it means the FIFO is full, and the upstream needs to pause writing and wait. Under the same clock, the upstream writes the data to be cached into the buffer and updates the write pointer. As the write pointer advances, the internal storage usage of the FIFO increases. When the usage reaches the threshold limit, full is set to 1 to notify the upstream to stop writing. When the downstream imaging calculation module is ready to read, it first reads the empty flag of the FIFO. When empty=0, it means the FIFO is not empty, the buffer is ready, and reading is allowed. When empty=1, it means the FIFO is empty, and the downstream needs to wait for the upstream to write before reading. The downstream initiates reading and advances the read pointer when empty=0. The FIFO read port is a 64-bit parallel port, that is, the downstream obtains data in 64-bit units each time it reads. During system initialization or abnormal recovery, the FIFO content is actively cleared, the read and write pointers are reset, and the system is restored to its initial state.

[0063] To address the issue of insufficient imaging speed when dealing with high-speed targets, the data decoding module 230 and the high-speed buffer module 240 within the data processing subsystem 200 provide efficient data throughput guarantees. The data decoding module 230 not only receives digital signals but also removes redundant overhead from communication protocols, such as packet headers and checksums, efficiently converting the original signal into pure high-speed event information containing only polarity, timestamps, and coordinates. This process significantly reduces the data processing load of downstream modules. The high-speed buffer module 240 then receives this high-speed event information for caching and rhythm shaping. Since high-speed targets often generate explosive bursts of massive event data within a very short time, the high-speed buffer module 240 uses an asynchronous FIFO mechanism to smooth out peak data flow pressure, preventing frame drops or delays caused by data congestion. Therefore, these modules ensure that the system maintains the continuity and real-time performance of the data flow when facing extremely high-speed moving targets, achieving microsecond-level rapid response imaging.

[0064] In summary, the data processing subsystem 200 of this invention achieves significant technical improvements and performance enhancements by constructing a dedicated hardware decoding pipeline and a closed-loop configuration feedback mechanism. These include: (1) First, the data processing subsystem 200 improves the way traditional general-purpose processors process data by introducing a fully hardware-level protocol parsing and event resolution architecture. The protocol decoding submodule 231 can directly identify and strip the packet header, length field, and check bit of the data packet at the hardware level, while the event parsing submodule 232 divides the original data words into six types of fields in parallel, including time high bit, time low bit, X / Y coordinates, and continuous event coordinates, and reassembles them into standard 64-bit event data in real time. The beneficial technical effect of this improvement is that it completely eliminates the high latency and CPU interrupt overhead when the software protocol stack processes massive amounts of tiny data packets, realizes "zero-copy" line-speed processing of sensor raw data arriving at the nanosecond level, ensures that there is no backlog of high-speed event streams at the transmission level, and provides a clean and time-accurate data source for back-end imaging. (2) The data processing subsystem 200 establishes a two-way interactive dynamic configuration closed loop. Through the collaboration of register control module 220 and second data interface module 210, data processing subsystem 200 is not only a one-way data receiver, but also an intelligent controller of front-end sensors. Register control module 220 can translate high-level imaging instructions from communication interaction subsystem 400 into low-level register control information in real time, and compile them into chip configuration instructions through second data interface module 210 and send them back to optical sensing subsystem 100. The technical effect of this improvement is that the system can dynamically adjust the photosensitive parameters of the front-end sensor or enable hardware filtering function in milliseconds according to the real-time detected image quality (such as excessive noise or background flicker), thereby optimizing the signal quality at the data source in real time and significantly improving the device's adaptability in complex lighting environments. (3) Data processing subsystem 200 adopts asynchronous high-speed buffer and rhythm shaping mechanism. In view of the extremely high burstiness of dynamic vision sensor output data, high-speed buffer module 240 uses asynchronous FIFO to connect data decoding module 230 and target imaging subsystem 300, and integrates hardware flow control logic for "full / empty" states. This improvement effectively smooths out the instantaneous data surges generated by high-speed moving targets, prevents data loss caused by instantaneous busy processing at the backend, and provides a stable and continuous data cycle for parallel imaging operations at the backend, ensuring the reliability and stability of the entire imaging link under extreme high-speed conditions.

[0065] See Figure 1 The target imaging subsystem 300 generates high-speed real-time images based on high-speed event information and stores them in memory. The target imaging subsystem 300 includes an imaging control module 310, an imaging calculation module 320, and a memory control module 330.

[0066] The imaging control module 310 is used to send a data read control command to the memory control module 330 according to the imaging mode selection information sent by the communication interaction subsystem 400, and at the same time send a period control command to the imaging calculation module 320.

[0067] The imaging calculation module 320 is used to perform imaging calculations on the high-speed event information according to the periodic control command and the imaging mode selection information sent by the communication interaction subsystem 400, and send the real-time calculation results to the memory control module 330.

[0068] The memory control module 330 performs memory readout control according to the read data control instruction and writes the real-time calculation result into the memory to obtain the real-time image.

[0069] The imaging processing module 320 is equipped with three parallel data links: Event-Frame, Histogram, and Timesurface. The imaging processing module 320 selects one of these data links to operate based on the imaging mode selection information. The Event-Frame data link of the imaging processing module 320 uses a simple overwrite method to process high-speed event information, the Histogram data link uses an accumulation method, and the Timesurface data link uses a linear decay method. The memory control module 330 is equipped with three parallel memory access links corresponding to the three data links of the imaging processing module 320, and automatically switches between them when the data links of the imaging processing module 320 are switched.

[0070] Specifically, the imaging control module 310 receives imaging instructions from the communication interaction subsystem 400. These instructions select one of three imaging modes: Event-Frame, Histogram, and Timesurface. This selection instruction instructs the imaging calculation module 320 to choose between Event-Frame, Histogram, or Timesurface link operation, and the memory control module 330 to select the corresponding memory operation mode. The imaging control module 310 also executes different frame reading schemes based on these instructions. It generates a frame reading control signal based on the imaging instructions and sends it to the memory control module 330. Simultaneously, it generates a frame calculation control signal and sends it to the imaging calculation module 320. The imaging calculation module 320 receives the imaging instructions from the communication interaction subsystem 400 and high-speed event information, writes the calculation results to the memory control module 330, and then sends the high-speed real-time image to the communication interaction subsystem 400.

[0071] See Figure 9 The imaging control module 310 has two synchronization lines: a frame reading control thread and a frame operation control thread. The frame reading control thread modifies different frame verification methods based on imaging instructions sent by the communication interaction subsystem 400, systematically reading the real-time high-speed target image obtained through imaging operations from memory. The frame operation control thread performs counting operations to calculate the imaging time and generates the periodic control instructions required by the imaging operation module 320 to assist in completing the imaging operation. When the frame operation control thread begins calculating a new frame, the imaging control module 310 records the timestamp of the first event or the first valid time information of the current frame as a reference time ref_t. This reference time serves as the starting point of the current frame. For each subsequent event, the imaging control module 310 extracts its event timestamp evt_t and calculates the relative time difference Δt = evt_t. The frame period T = 1000000 / frame_rate is obtained from the internal parameter frame_rate. When Δt reaches or exceeds T, it is determined that the frame calculation of the current frame has reached the boundary. The frame operation control signal is set high and sent to the imaging operation module 320. The imaging control module 310 does not immediately enter the control of the next frame after the frame operation control signal is set high. Instead, it waits for one clock cycle before generating a frame switching pulse, entering the write start point of the next frame, and updating the new ref_t, thereby avoiding frame loss or incomplete frame data caused by read-write overlap. The frame read control thread has two operating modes, and in either mode, it maintains real-time communication with the memory control module. When it receives an imaging command from the communication interaction subsystem 400 to set the imaging mode to Event Frame, it first clears the read address index to zero, and then automatically increments it by a fixed step size on each rising clock edge to traverse the address space corresponding to the frame in RAM. As the read address increments, the module continuously issues memory read commands, and the RAM port sequentially outputs data0, data1, ..., datan to continuously send out the frame header and intra-frame data in a fixed timing sequence. To prevent the residue of the previous frame from affecting the next frame, the imaging control module 310, while reading the event frame data from RAM, performs a zeroing operation on the already read address through another port of RAM to achieve real-time recycling of the previous frame data. After the read address has traversed the entire frame address space, the index is cleared, and the next frame is read again. When it receives an imaging command from the communication interaction subsystem 400 to set the imaging mode to Histogram... When using a Frame or Timesurface, the overall workflow follows the same steps of sequential reading and zeroing / erasing, the difference being the different memory read commands issued.

[0072] See Figure 10The imaging processing module 320 has three synchronous links: Event-Frame, Histogram, and Timesurface. The imaging processing module 320 adopts a high-speed parallel design, synchronously receiving imaging control commands from the imaging control module 310, high-speed event information output by the data processing subsystem 200, and imaging control commands from the communication interaction subsystem 400, and sending read / write operations to the memory control module 330. The imaging processing module 320 sets up three parallel data processing links, selecting one to complete the processing according to the aforementioned commands. The three parallel data links adopt a dynamic multiplexing strategy; overlapping parts in the processing steps of the three links are time-divisionally reused, effectively saving computing resources. The selected link performs timing alignment, field parsing, address calculation, and data mapping on the input events, ultimately forming the data to be written to RAM and the write address. In the Event-Frame data link, for each arriving event data, the target storage unit address corresponding to the target pixel is calculated based on its coordinates (evt_x, evt_y). The data is expanded in row-major order, and the RAM address ram_addr = evt_y × W + evt_x is calculated, where W is the imaging width, and the maximum value of W is 1280. The value of W is consistent with the W in the aforementioned optical sensing subsystem 100. The above address is further mapped to the physical address space accessible by the memory control module 330. The mapping result, along with the write data control information, is sent to the memory control module 330 to complete one imaging operation. In Event-Frame mode, the write data is the polarity information of the event data itself, with only two state values: positive and negative. The memory control module, which works in conjunction with it, will synchronously adopt this information compilation rule.In Histogram imaging operation mode, the event count is recorded for each pixel position according to its polarity. The imaging operation module 320 determines whether the event is positive or negative based on the event polarity evt_p, and selects the storage area to write to accordingly. It calculates the storage address ram_addr = evt_y × W + evt_x corresponding to the pixel based on the event coordinates. Events of different polarities are stored in two independent RAMs, significantly accelerating the operation. A read request is sent to the memory control module 330 via the imaging operation data line to read the current cumulative count value r at that address. There is a delay between the read request and the read return for am_dout, so a clock delay step is needed to align the returned data with the event information. After am_dout is read, the imaging calculation module 320 performs an increment operation on it to obtain a new value, am_din = am_dout + 1. The calculated new count value am_din is used as the write data, and together with the address information and write data control information, it is sent to the memory control module 330 to complete the write-back update. Each event will trigger its pixel position count to increment automatically, thereby forming a histogram image within one frame period. The Timesurface mode reflects the relative position of the most recent event time of each pixel with respect to the current frame reference time, and maps it to the visible grayscale image range of 0–254. This mode also selects the storage area to be written according to evt_p, and uses a read-write synchronization strategy to accelerate the operation. The storage address corresponding to the pixel is calculated based on the event coordinates: ram_addr = evt_y × W + evt_x. At this time, the module reads the current frame reference time t_ref obtained by the imaging control module 310 at the beginning of the frame, and obtains the event timestamp evt_t. The frame period T is calculated by the imaging control module 310, and the time difference Δt = evt_t is used. ref_t generates pixel values ​​ram_din = 254 × (evt_t) The result is quantized to a valid integer range of 0-254, ensuring that the output is a displayable grayscale value. Its physical meaning is that the closer the event occurs to the end of the current frame, the larger the mapping value. Unlike the Histogram mode, the Timesurface mode adopts a strategy of writing over time according to the event: for each event, the calculated ram_din is directly sent to the memory control module 330 and written to the corresponding pixel address. The value of each pixel is continuously refreshed with the latest event. With the frame period update, continuous imaging can be formed.

[0073] The imaging processing module 320 in this invention does not employ a general serial processing logic. Instead, it constructs independent hardware pipelines for the three core imaging modes, while reusing common steps such as timing alignment and address calculation in a time-division multiplexing manner. This improvement allows the system to flexibly switch processing logic within nanoseconds based on imaging commands. Furthermore, when handling massive concurrent events, multiple links can operate in parallel or pipelined fashion, avoiding resource contention for a single processing unit. This ensures that the device maintains extremely high computational efficiency and response speed when facing different detection requirements. In addition, the imaging processing module 320 introduces hardware-level time decay and accumulation calculation logic, completely replacing traditional software post-processing calculations. In the Timesurface link, the imaging processing module 320 directly reads the frame reference time and event timestamp, completing 254×(evt_t) internally in hardware. The linear attenuation calculation and grayscale quantization of ref_t / T eliminate the need for CPU-based floating-point operations, significantly reducing latency. The imaging computation module 320 implements direct physical address mapping based on event coordinates. For each arriving event, the imaging computation module 320 directly calculates ram_addr = evt_y × W + evt_x in hardware based on its coordinates (evt_x, evt_y), and converts it into a physical address and control signal directly accessible to the memory control module. This design eliminates the virtual address translation overhead at the operating system level, achieving a direct path from event triggering to memory writing. It significantly shortens the end-to-end latency of the imaging link, ensuring that the target imaging subsystem 300 can keep up with the motion changes of high-speed targets at microsecond speeds, providing the most timely image data for subsequent real-time display and detection.

[0074] The memory control module 330 includes two random access memories (RAMs), a read data controller, and a write data controller; the read and write operations of the two random access memories are interleaved.

[0075] like Figure 11 , Figure 12 , Figure 13As shown, the memory control module 330 includes three memory access links, which share the same name as the links built into the imaging computation module 320 and automatically switch when the links in the imaging computation module 320 switch. This link switching strategy effectively ensures efficient collaboration between the two modules and significantly improves imaging speed. The memory control module 330 of this invention achieves significant technical improvements and performance enhancements by constructing three high-speed parallel memory access links. This design improvement changes the single, universal access mode of traditional storage controllers, configuring dedicated hardware data paths for different imaging data characteristics. This enables the system to achieve seamless and real-time switching between different imaging modes, and each mode has independently optimized storage logic, avoiding instruction redundancy and efficiency loss caused by universal storage architecture, thereby ensuring the highest data throughput efficiency when processing different types of computation results. Addressing the extreme demand for data concurrency in high-speed imaging, two independent RAM memories are used alternately in the Event-Frame link, maximizing the advantages of parallel processing. This allows the device to maintain absolute synchronization between writing and display even at high imaging speeds, achieving zero-latency response to microsecond-level moving targets. In the Histogram and Timesurface links, the A and B physical ports of RAM are used to simultaneously perform data read-modify-write-back operations and display data read / clear operations. Positive and negative events are stored in independent RAM_P and RAM_N respectively based on event polarity. This design allows for the simultaneous accumulation / fading update of historical data and the output of image frames within a single clock cycle, achieving a significant speedup compared to traditional serial processing. Furthermore, by optimizing the data bit width (using only 2 bits for Event-Frame and 8 bits for other modes), storage resources are further saved and transmission bandwidth utilization is improved. These design features ensure that memory access does not become a system bottleneck during complex statistical or attenuation calculations, thus guaranteeing real-time imaging quality at high frame rates.

[0076] Specifically, when operating on an Event-Frame link, each pixel position in the image includes three states: no event, positive event, or negative event. One pixel corresponds to one RAM storage address. To improve storage and transmission efficiency, each pixel is encoded with 2 bits: 00 represents no event, 10 represents a negative event, and 11 represents a positive event. 01 is reserved as a special data type, used as the frame header of the event frame during data transmission. Each pixel in the Event Frame is represented by only 2 bits of data to minimize storage resource consumption. Simultaneously, leveraging its low data volume, a read-write synchronization strategy is used to improve the algorithm's processing efficiency. For example... Figure 11As shown, to improve data throughput, two RAM memories, a read data controller, and a write data controller are configured. To avoid data conflicts caused by simultaneous reading and writing to the RAM, the read and write operations of the RAM are interleaved. In the first frame, imaging data is written to RAM_A through the w02 data path and the image frame is read from RAM_B through the r02 data path. In the second frame, imaging data is written to RAM_B through the w01 data path and the event frame is read from RAM_A through the r01 data path. This alternation is completed every two frames, maximizing the advantages of parallel processing to accelerate the imaging speed. When working in conjunction with the imaging calculation module 320, the typical imaging speed reaches 1000 frames per second, providing microsecond-level response capability for moving targets.

[0077] Figure 12 As shown, when operating on a Histogram link, each pixel in the image is counted for the cumulative number of events at that location within a time window. Each pixel is represented by 8 bits of data, representing 0 to 254 events. Events exceeding 254 are also represented by 254. 255 is reserved as special data, used as the header of the event frame during data transmission. Since positive and negative events are processed separately, two 8-bit data blocks are used. The dual-port RAM stores data and uses an arithmetic controller and a frame read controller for storage control. In the Histogram link, according to the imaging process of the imaging arithmetic module 320 and the frame read control of the imaging control module, the RAM is read and written, so that the read and write operations are performed simultaneously on different ports, maximizing the acceleration of the imaging process. The arithmetic controller is controlled by the imaging arithmetic module and reads and writes RAM_P or RAM_N according to the event polarity. First, it reads the number of historical events from the B port of RAM_P or RAM_N through the r31 data path or the r35 data path, and then writes the calculation result back to RAM_P or RAM_N from the A port of RAM_P or RAM_N through the w32 data path or the w36 data path. The frame read controller is controlled by the imaging control module 310. After reading the image from the A port of RAM_P or RAM_N through the r33 data path or the r37 data path, it writes the clear data from the B port through the z34 data path or the z38 data path, completing the effective coordination of imaging arithmetic and imaging data reading, achieving a significant acceleration compared to traditional serial processing.

[0078] like Figure 13As shown, in the Time Surface link, each pixel location of the image stores the most recent time decay value, represented by 8 bits of data. For each pixel, the time decay value is quantized to between 0 and 254. 255 is reserved as special data, used as the frame header of the event frame during data transmission. Since the Time Surface operating mode processes positive and negative events separately, two 8-bit dual-port RAMs are used to store the data, and an arithmetic controller and a frame read controller are used for storage control. According to the imaging process of the imaging calculation module 320 and the frame reading control of the imaging control module 310, read and write control is performed on the RAM, so that read and write operations are performed on different ports. The calculation controller is controlled by the imaging calculation module 320 and reads and writes RAM_P or RAM_N according to the event polarity. The calculation result is written from port A to RAM_P or RAM_N through data path w21 or w24. The frame reading controller is controlled by the imaging control module 310. After reading the image from port A of RAM_P or RAM_N through data path r22 or r25, it writes zeroing data from port B of RAM_P or RAM_N through data path z23 or z26, thus completing the effective parallel fusion of imaging calculation and imaging data reading. As described above, the memory control module 330 inserts a preset frame header at the beginning of a frame of valid data. Only the frame header needs to be identified to accurately locate the frame boundary, without being interfered with by valid data within the frame.

[0079] The target imaging subsystem 300 of this invention employs highly parallel processing logic in its architecture design, fundamentally ensuring the real-time performance of imaging operations. Internally, the target imaging subsystem 300 includes an imaging control module 310, an imaging computation module 320, and a memory control module 330. The imaging control module 310 has two parallel threads: frame readout control and frame computation control, enabling simultaneous control of data readout and computation cycles. The imaging computation module 320 features three parallel data links and employs a dynamic multiplexing strategy. Since high-speed event information is discrete and occurs at high frequencies, traditional serial image processing methods easily lead to data accumulation. This invention, through the aforementioned parallel links, can rapidly process massive amounts of event data for different imaging modes. Therefore, this hardware-level parallel design allows the system to process new data in a pipeline manner without waiting for the previous frame to finish processing when faced with high-speed event streams arriving at the microsecond level, thereby maximizing the utilization of computing resources and significantly accelerating the imaging process.

[0080] The target imaging subsystem 300 of this invention breaks through the data read / write bottleneck in high-speed imaging through an optimized memory control strategy. The memory control module 330 sets up a high-speed parallel memory access link corresponding to the imaging computation module 320, and adopts read / write synchronous or interleaved control strategies, such as ping-pong operation of dual-port RAM. In Event-Frame mode, a read / write synchronous strategy is used; in Histogram mode, RAM read / write operations are interleaved, with data writing and historical data reading or clearing performed simultaneously through different data paths. By eliminating memory access conflicts and achieving real-time data read / write, the target imaging subsystem 300 can convert high-speed event streams into image frames in real time with extremely high data throughput. This collaborative working mode enables a typical imaging speed of up to 1000 frames per second, providing microsecond-level response capability for moving targets. Therefore, relying on this efficient "event-image" conversion engine of the target imaging subsystem 300, this invention ensures that the device can capture extremely fast-moving targets without delay or frame loss, completely solving the technical problem of insufficient high-speed imaging speed.

[0081] This invention achieves the solidification and parallel acceleration of the event imaging algorithm through specific hardware logic modules. The target imaging subsystem 300 incorporates dedicated functional units such as the imaging control module 310, the imaging computation module 320, and the memory control module 330. These modules do not simply rely on a general-purpose processor to execute software code sequentially; instead, they work collaboratively through hardware-level parallel threads, avoiding the limitations of operating system scheduling latency or instruction pipeline serial blocking found in general-purpose CPUs. This invention employs a hardware-level direct control strategy at the memory access level, significantly improving data throughput efficiency. The memory control module 330 directly controls the read and write operations of the RAM physical ports according to the instructions of the imaging computation module 320, utilizing dual-port RAM to achieve interleaved or synchronous read and write operations. This design avoids the data copy overhead and bus contention problems common in pure software designs based on CPUs / GPUs. Especially for high-speed event stream data, the hardware logic can pipeline a microsecond-level instant response and mapping for each arriving event, achieving "data processing as soon as it arrives." In contrast, pure software solutions typically require waiting for data packets to be cached to a certain size before batch processing, inevitably leading to latency. Therefore, this invention, through a dedicated hardware and software architecture, achieves high-speed performance with microsecond-level response to moving targets while ensuring algorithm flexibility.

[0082] See Figure 1 and Figure 14 The communication and interaction subsystem 400 includes an HDMI display module 410 and a USB data module 420.

[0083] The HDMI display module 410 receives high-speed real-time images from the target imaging subsystem 300, generates horizontal and vertical signals to compile the real-time images into video stream data, and sends the video stream to the display device 700.

[0084] The HDMI display module 410 is driven by an internal clock pixel_clk. The module schedules a horizontal counter cnt_h and a vertical counter cnt_v, which increment within the line / frame cycle and return to zero after reaching the total cycle. According to preset display timing parameters (taking 1280×720 as an example), the module compares the count values ​​in each clock cycle, generating a horizontal synchronization signal video_hs. When cnt_h < 1280, it is a valid synchronization level; otherwise, it is a non-synchronous level. A vertical synchronization signal video_vs is generated; when cnt_v < 720, it is a valid synchronization level; otherwise, it is a non-synchronous level. Simultaneously, a data enable signal video_de is generated. Before entering the effective display window, the module requests pixel data for the next moment from the upstream memory control module and outputs the currently requested pixel coordinates. The X coordinate of the current effective pixel is calculated from cnt_h, and the Y coordinate is calculated from cnt_v. Simultaneously, the module renders visible RGB colors based on the image data. For Time... Images captured by Surface imaging are rendered using blue, white, and black colors to represent negative, positive, and no events, respectively. Images from other imaging methods are colored using 254 grayscale values. When `video_de` is active, the module directly outputs the colored RGB signal as `video_rgb`; when `video_de` is inactive, it outputs a black field. To ensure stable synchronization signals and data enable, `video_hs`, `video_vs`, and `video_de` are output using two levels of registers, thus avoiding display instability caused by combined jitter.

[0085] The USB data module 420 receives the configuration command sent by the operating device 600, parses it to form an imaging command, and simultaneously sends it to the target imaging subsystem 300 and the data processing subsystem 200. At the same time, it receives the real-time image from the target imaging subsystem 300 and sends it to the operating device 600 via USB.

[0086] In addition, see Figure 1 Embodiment 1 may further include: peripheral devices; the peripheral devices include an optical lens 500, an operating device 600, and a display device 700.

[0087] The optical sensing subsystem 100 can be deployed in the photosensitive assembly electronic device. The optical sensing subsystem 100 is connected to the optical lens 500 to receive optical information captured by the optical lens 500. The data processing subsystem 200, the target imaging subsystem 300, and the communication interaction subsystem 400 are all deployed in the imaging assembly electronic device. The operating device 600 and the display device 700 are both connected to the imaging assembly electronic device.

[0088] The optical lens 500 is positioned in the working area, facing the space where high-speed imaging is required. The optical lens 500 is configured to capture optical information corresponding to the visible light band and near-infrared band within the lens's field of view in real time. This wide-spectrum acquisition capability enables the device to compensate for the lack of visible light by utilizing information from the near-infrared band in low-light environments, thereby still being able to acquire effective optical signals in dark environments that are difficult for the human eye to perceive.

[0089] The operating device 600 is used to display and store the real-time image, and to receive configuration commands input by the operator; the display device 700 is used to display the video stream. Correspondingly, the communication interaction subsystem 400 is also used to receive configuration commands from the operating device 600, and after parsing, to form imaging mode selection information.

[0090] The operating device 600 includes a parameter configuration module 610 and a storage and visualization module 620, both of which can be flexibly deployed on a general-purpose computer to function as the operating device. The parameter configuration module 610 collects imaging commands input by the operator and sends them to the USB data module 420. The storage and visualization module 620 displays image data in real time and guides the operator in saving the required images.

[0091] Through the cooperation of the communication interaction subsystem 400 and the operating device 600, the system can parse and guide the operator to give configuration instructions. This enables the system to adjust imaging parameters manually or dynamically according to the current actual lighting environment, further enhancing the device's adaptability and imaging effect in extreme and complex lighting environments.

[0092] In summary, Example 1 solves the problems of difficulty in high-speed imaging and real-time detection of high-speed targets under extreme optical conditions such as low illumination and high exposure. It can effectively filter out ambient light interference, clearly extract the features of high-speed targets under extreme optical conditions, and achieve stable imaging under complex lighting conditions.

[0093] Example 2: Example 2 provides a high-speed imaging method based on a dynamic vision sensor, implemented using the high-speed imaging device based on a dynamic vision sensor as described in Example 1. The high-speed imaging method provided in Example 2 mainly includes the following steps: S1. The optical information generated by the moving target is converted into an analog electrical signal using the dynamic vision sensor included in the optical sensing subsystem, and the analog electrical signal is compiled into a digital signal using the optical sensing subsystem. S2. Using the data processing subsystem, generate high-speed event information based on the digital signal; S3. Using the target imaging subsystem, generate a real-time image based on the high-speed event information; S4. Using the communication interaction subsystem, the real-time images are compiled into a video stream.

[0094] In addition, prior to S1, it may include: acquiring optical information of a high-speed target using an optical lens and connecting the optical information to the optical sensing subsystem.

[0095] For example, it may also include: displaying and storing the real-time image using an operating device, and guiding and receiving configuration instructions input by the operator. For example, it may also include: displaying the video stream using a display device.

[0096] It should be noted that the explanation of the high-speed imaging device in Example 1 also applies to the high-speed imaging method in Example 2, and will not be repeated here.

[0097] Example 3: Example 3 provides an electronic device, comprising two parts: a photosensitive assembly and an imaging assembly. Each part includes an independent memory, a processor, a communication interface, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the high-speed imaging method as described in Example 2.

[0098] The photosensitive assembly stores and runs programs that enable the optical sensing subsystem; the imaging assembly stores and runs programs that enable the data processing subsystem, target imaging subsystem, and communication interaction subsystem.

[0099] Example 4: Example 4 provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the high-speed imaging method as described in Example 2.

[0100] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-speed imaging device based on a dynamic vision sensor, characterized in that, It includes an optical sensing subsystem, a data processing subsystem, a target imaging subsystem, and a communication interaction subsystem connected in sequence; the optical sensing subsystem includes an optical sensing module, and the optical sensing module includes a dynamic vision sensor; The dynamic vision sensor is used to convert optical information generated by a moving target into analog electrical signals; the optical sensing subsystem is used to compile the analog electrical signals into digital signals; the data processing subsystem is used to generate high-speed event information based on the digital signals; the target imaging subsystem is used to generate real-time images based on the high-speed event information; and the communication interaction subsystem is used to compile the real-time images into a video stream.

2. The high-speed imaging device based on a dynamic vision sensor according to claim 1, characterized in that, The optical sensing subsystem further includes a first configuration module and a first data interface module; the optical sensing module further includes a trajectory filter, an event filter, and a strobe filter; The first data interface module is used to receive chip configuration information from the data processing subsystem and transmit it to the first configuration module. The first configuration module is used to send the chip configuration information to the optical sensing module. The optical sensing module is also used to parse the chip configuration information and drive the activation or deactivation of three filters according to the parsed information. When the trajectory filter is activated, it counts the event triggers for each pixel and outputs only events in a specific order by setting trajectory definition parameters to eliminate redundant trajectory tails. When the event filter is activated, it calculates the discard rate based on the total number of events within the sampling time and randomly discards events with dynamic probability in the X-axis, Y-axis, and time dimensions. When the flicker filter is activated, it continuously monitors the burst cycle of positive polarity events. If periodic flicker is detected, it marks and blocks the data of the corresponding pixel area.

3. The high-speed imaging device based on a dynamic vision sensor according to claim 2, characterized in that, The first configuration module includes an analog voltage modulation unit, a digital voltage modulation unit, a clock signal generation unit, a power-on timing control unit, a communication initialization unit, and a data pass-through unit; The analog voltage modulation unit is used to provide analog voltage; the digital voltage modulation unit is used to provide digital voltage; the clock signal generation unit is used to generate clock signal; the power-on timing control unit is used to receive the clock signal and control the first data interface module and the optical sensing module to power on according to a preset timing sequence; the communication initialization unit is used to perform communication initialization; the data pass-through unit is used to send the chip configuration information to the optical sensing module after the communication initialization is completed.

4. The high-speed imaging device based on a dynamic vision sensor according to claim 2, characterized in that, The data processing subsystem includes a second data interface module, a register control module, a data decoding module, and a high-speed buffer module; The second data interface module is used to perform preliminary parsing of the digital signal from the optical sensing subsystem and send it to the data decoding module, and to compile the register control information sent by the register control module into chip configuration information and send it to the optical sensing subsystem; the register control module is used to convert the imaging mode selection information sent by the communication interaction subsystem into the register control information; the data decoding module is used to decode the digital signal initially parsed by the second data interface module into high-speed event information, which only includes polarity, timestamp, and coordinates; the high-speed buffer module is used to cache the high-speed event information and send it to the target imaging subsystem.

5. The high-speed imaging device based on a dynamic vision sensor according to claim 4, characterized in that, The data decoding module includes a protocol decoding submodule and an event parsing submodule. The protocol decoding submodule is used to identify and strip the packet header, length field, and checksum of the data packet. The event parsing submodule is used to receive the valid data stream output by the protocol decoding submodule, extract the time and coordinate information required for the event, and generate an event queue to output to the high-speed buffer module. The high-speed buffer module uses an asynchronous FIFO to connect the data decoding module and the target imaging subsystem.

6. The high-speed imaging device based on a dynamic vision sensor according to claim 1, characterized in that, The target imaging subsystem includes an imaging control module, an imaging computation module, and a memory control module; The imaging control module is used to send a data read control command to the memory control module according to the imaging mode selection information sent by the communication interaction subsystem, and at the same time send a period control command to the imaging calculation module. The imaging calculation module is used to perform imaging calculations on the high-speed event information according to the periodic control command and the imaging mode selection information sent by the communication interaction subsystem, and send the real-time calculation results to the memory control module. The memory control module performs memory readout control according to the read data control instruction, and writes the real-time calculation result into the memory to obtain the real-time image.

7. The high-speed imaging device based on a dynamic vision sensor according to claim 6, characterized in that, The imaging processing module has three parallel data links: event frame, histogram, and time surface. The imaging processing module selects one of these data links to operate based on the imaging mode selection information. The memory control module has three parallel memory access links corresponding to the three data links of the imaging processing module, and automatically switches when the data links of the imaging processing module switch. The memory control module includes two random access memories, a read data controller, and a write data controller. The read and write operations of the two random access memories are interleaved.

8. The high-speed imaging device based on a dynamic vision sensor according to claim 1, characterized in that, Also includes: Peripheral equipment; the peripheral equipment includes an optical lens, an operating device, and a display device; the optical lens is connected to the optical sensing subsystem; the data processing subsystem, the target imaging subsystem, and the communication interaction subsystem are all deployed in the imaging assembly electronic device, and the operating device and the display device are both connected to the imaging assembly electronic device; The optical lens is configured to capture optical information corresponding to the visible light band and near-infrared band within the lens's field of view in real time; the operating device is used to display and store the real-time image, and to receive configuration instructions input by the operator; the display device is used to display the video stream.

9. The high-speed imaging device based on a dynamic vision sensor according to claim 8, characterized in that, The communication and interaction subsystem is also used to receive configuration instructions from the operating device, and parse them to form imaging mode selection information.

10. A high-speed imaging method based on a dynamic vision sensor, characterized in that, The high-speed imaging method, implemented using a high-speed imaging device based on a dynamic vision sensor as described in any one of claims 1 to 9, comprises the following steps: The optical sensing subsystem utilizes a dynamic vision sensor to convert optical information generated by a moving target into analog electrical signals, and then uses the optical sensing subsystem to encode the analog electrical signals into digital signals. Using the data processing subsystem, high-speed event information is generated based on the digital signal; Real-time images are generated using the target imaging subsystem based on the high-speed event information; The real-time images are compiled into a video stream using the communication interaction subsystem.

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