Clamp control circuit and image sensing device including the same

Abstract

The present disclosure relates to a clamp control circuit and an image sensing device including the same. An image sensing device for generating image data is disclosed. A clamp control circuit included in the image sensing device includes a sensing circuit configured to sense a voltage level of a pixel signal to output a sensing signal, and a clamp circuit coupled to a column line and configured to control a voltage level of a clamp voltage control signal in response to the voltage level of the sensing signal, and to control a level of a clamp voltage in response to a clamp enable signal, wherein the clamp voltage is controlled based on the voltage level of the clamp voltage control signal and provided to the column line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0178905, filed on December 4, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques and embodiments disclosed herein generally relate to an image sensing apparatus for generating image data. Background Technology

[0004] Generally speaking, Complementary Metal-Oxide-Semiconductor (CMOS) image sensors have evolved to offer lower power consumption, lower cost, and smaller size than competing products, leading to their extensive research and rapid widespread adoption. Specifically, CMOS image sensors have developed to offer superior image quality compared to competing products, enabling their application scope to recently expand into video applications requiring higher resolution and higher frame rates.

[0005] However, in high-light environments, when the amount of light exceeds the dynamic range of a pixel, a sunspot phenomenon may occur in the image sensor. The sunspot phenomenon refers to the situation where, when photographing highly illuminated objects such as the sun or strong light, areas that should appear bright are instead displayed as dark due to charge overflow within the pixels. As a result, some areas may appear black, like sunspots. When the light intensity sensed by the image sensor is high, a signal charge exceeding the total capacity of the photodiode is generated, causing charge overflow into the unit pixel or floating diffusion area, resulting in the sunspot phenomenon. Summary of the Invention

[0006] Various embodiments of this disclosure relate to an image sensing device that can prevent sun-dark phenomena by controlling a clamping voltage level in response to a voltage level of a pixel signal.

[0007] According to one embodiment of this disclosure, a clamping control circuit may include: a sensing circuit configured to sense the voltage level of a pixel signal to output a sensing signal; and a clamping circuit coupled to a column line and configured to control the voltage level of a clamping voltage control signal in response to the voltage level of the sensing signal, and to control the level of a clamping voltage in response to a clamping enable signal, wherein the clamping voltage is controlled based on the voltage level of the clamping voltage control signal and is provided to the column line.

[0008] According to another embodiment of this disclosure, an image sensing device may include: a pixel configured to output a pixel signal to a column line; a clamping control circuit configured to sense the voltage level of the pixel signal to output a sensing signal, and to control a clamping voltage in response to the sensing signal in a clamping operation mode, the clamping voltage being controlled to a level greater than or equal to a reference voltage and provided to the column line; and an analog-to-digital converter (ADC) configured to perform analog-to-digital conversion operation on the voltage of the column line based on a ramp signal.

[0009] It should be understood that the foregoing general description of the embodiments of this disclosure and the following detailed description are illustrative and intended to provide further description of the claimed embodiments. Attached Figure Description

[0010] The above and other advantageous features and benefits of embodiments of the present disclosure will become apparent from the accompanying drawings and the following detailed description.

[0011] Figure 1 This is a block diagram illustrating an image sensing apparatus based on some embodiments of the present disclosure.

[0012] Figure 2 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the pixels in the pixel array shown.

[0013] Figure 3 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the clamping control circuit shown is shown.

[0014] Figure 4 and Figure 5 This illustrates some embodiments based on the present disclosure. Figure 3 The diagram shows the operation of the clamping control circuit.

[0015] Figure 6 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the analog-to-digital converter (ADC) shown is shown.

[0016] Figure 7 It shows the basis Figure 3 A timing diagram of the operation of the image sensing device in an embodiment.

[0017] Figure 8 This is based on the disclosure. Figure 1 The circuit diagram shows another embodiment of the clamping control circuit.

[0018] Figure 9 It shows the basis Figure 8 A timing diagram of the operation of the image sensing device in an embodiment. Detailed Implementation

[0019] This disclosure provides embodiments and examples of an image sensing apparatus for generating image data, which can be used in configurations that substantially solve one or more technical or engineering problems and mitigate limitations or drawbacks encountered in other image signal processors. Some embodiments of this disclosure relate to an image sensing apparatus that prevents sunken effects by controlling clamping voltage levels in response to the voltage levels of pixel signals. In view of the above problems, the image sensing apparatus based on some embodiments of this disclosure can prevent sunken effects by improving the clamping margin of pixel signals, thereby improving dynamic range.

[0020] Reference will now be made in detail to some embodiments of this disclosure, which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. Since various modifications and alternatives may exist for the disclosed embodiments, specific embodiments are shown in the drawings only by way of example. However, the invention should not be construed as being limited to the embodiments described herein.

[0021] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the specific embodiments, but includes various modifications, equivalents, and / or alternatives to these embodiments. The embodiments disclosed herein can provide various beneficial effects, which can be recognized directly or indirectly by those skilled in the art.

[0022] Figure 1 This is a block diagram illustrating an image sensing device 10 based on some embodiments of the present disclosure.

[0023] refer to Figure 1 The image sensing device 10 may include a pixel array (PA), a clamping control circuit 100, a ramp generator 200, an analog-to-digital converter (ADC) 300, and a timing controller 400. Figure 1 The components of the image sensing device 10 shown are discussed as examples only, and this embodiment may cover many other changes, substitutions, variations, alterations and modifications.

[0024] A pixel array (PA) may include a plurality of pixels (PX) arranged in rows and columns. In one embodiment, the plurality of pixels (PX) may be arranged into a two-dimensional (2D) pixel array (PA) including rows and columns. In another embodiment, the plurality of pixels may be arranged into a three-dimensional (3D) pixel array (PA). The plurality of pixels (PX) may convert optical signals into electrical signals on a pixel-by-pixel or pixel-by-group basis and may output pixel signals (VPX) to column lines (CL). For example, the voltage of the pixel signal (VPX) may be a voltage generated by a reset operation of the corresponding pixel (PX) or a voltage generated by an integration operation of the corresponding pixel (PX).

[0025] In one embodiment, pixels (PX) in a pixel group of a pixel array (PA) may share at least one internal circuit. The pixel array (PA) may receive drive signals (described later) from a row driver, including row selection signals, pixel reset signals, transfer signals, etc. Upon receiving a drive signal, the corresponding imaging pixel (PX) in the pixel array (PA) can be activated to perform operations corresponding to the row selection signal, pixel reset signal, and transfer signal.

[0026] The clamp control circuit 100 can detect the voltage level of the pixel signal (VPX) based on at least one control signal (CON), bias voltage (VB), sense enable signal (S_EN), sense auto-zero signal (S_AZ), and clamp enable signal (C_EN) received from the timing controller 400, and can control the level of the clamp voltage (CLP) according to the sensed voltage level. When the pixel signal (VPX) for the reset sampling operation is output, the clamp control circuit 100 can control the level of the clamp voltage (CLP) provided to the column line (CL).

[0027] In some embodiments, the clamping control circuit 100 can operate in either a bias operation mode or a clamping operation mode. In the bias operation mode, the clamping control circuit 100 can bias the voltage level of the pixel signal (VPX) and transmit the biased pixel signal (VPX) to the ADC 300. In the bias operation mode, the clamping control circuit 100 can control the clamping voltage (CLP) applied to the column line (CL) to be less than or equal to a preset reference voltage, so that the clamping control circuit 100 does not affect the voltage level of the pixel signal (VPX). In the clamping operation mode, the clamping control circuit 100 can detect the voltage level of the pixel signal (VPX) and, if the detected pixel signal (VPX) voltage level is less than the preset reference voltage, control the level of the clamping voltage (CLP) to increase. That is, in the clamping operation mode, the clamping control circuit 100 can, in response to the level of the clamping voltage (CLP), increase the voltage level of the column line (CL) to be greater than or equal to the preset reference voltage, so that the clamping control circuit 100 can ensure clamping operation margin. In some embodiments, the preset reference voltage may be set to the voltage level of the reset signal (i.e., the RG signal described later).

[0028] Please refer to later Figures 3 to 5 and Figure 7 A more detailed description of the clamping control circuit 100's circuitry and operation is provided.

[0029] The ramp generator 200 can generate the ramp signal (VRAMP) required for the analog-to-digital conversion (ADC) operation of the ADC 300 when it receives the control signal (RCON) from the timing controller 400, and can provide the ramp signal (VRAMP) to the ADC 300.

[0030] ADC 300 can sequentially sample and maintain the voltage levels of reference signals and image signals provided from each of the multiple column lines of the pixel array (PA), convert the generated reference signals and generated image signals into digital signals, and output digital signals. The reference signal can be an electrical signal provided to ADC 300 when the sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, while the image signal can be an electrical signal provided to ADC 300 when photocharge generated by the imaging pixel accumulates in the sensing node. The reference signal, indicating the unique reset noise of each pixel, and the image signal, indicating the intensity of the incident light, can be collectively referred to as the pixel signal (VPX) as needed. ADC 300 can receive a ramp signal (VRAMP) from ramp generator 200, receive the pixel signal (VPX) from the pixel array (PA), and generate and output ADC data (ADC_OUT) based on the ramp signal (VRAMP) and pixel signal (VPX). ADC 300 can be implemented as a ramp comparator-type ADC using the ramp signal (VRAMP) from ramp generator 200.

[0031] The timing controller 400 can control at least one of the clamp control circuit 100, the ramp generator 200, and the ADC 300. The timing controller 400 can generate a control signal (CON), a bias voltage (VB), a sense enable signal (S_EN), a sense auto-zero signal (S_AZ), and a clamp enable signal (C_EN) to control the operation of the clamp control circuit 100. The timing controller 400 can generate a control signal (RCON) to control the operation of the ramp generator 200. The timing controller 400 can generate an auto-zero signal (AZ) and a counter enable signal (CNT_EN) to control the operation of the ADC 300.

[0032] Figure 2 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the pixels (PX) of the pixel array shown is shown.

[0033] refer to Figure 2 A pixel (PX) can be one of several pixels included in a pixel array (PA). However, for convenience, Figure 2 Only one pixel (PX) is shown, but the scope and concept of this disclosure are not limited thereto, and other pixels may have substantially the same structure and operation as that pixel (PX).

[0034] A pixel (PX) may include a photoelectric conversion unit (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a first capacitor (C1), a source follower transistor (SF), and a select transistor (SX). Although Figure 2 The illustration shows a pixel (PX) including a photoelectric conversion unit (PD), but the scope and concept of this disclosure are not limited thereto. According to another embodiment, a pixel (PX) can also be implemented as a shared pixel having multiple photoelectric conversion units (PDs). In this embodiment, multiple transmission transistors corresponding to the multiple photoelectric conversion units can be provided.

[0035] Each photoelectric conversion device (PD) can generate and accumulate photocharge corresponding to the intensity of incident light. For example, each photoelectric conversion device (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. If the photoelectric conversion device (PD) is implemented as a photodiode, then the photoelectric conversion device (PD) can be a region in a substrate including a first conductive impurity (e.g., a P-type impurity) doped with a second conductive impurity (e.g., an N-type impurity).

[0036] A transfer transistor (TX) can be coupled between the photoelectric conversion device (PD) and the floating diffusion region (FD). The transfer transistor (TX) can be turned on or off in response to a transfer control signal (TG). If the transfer transistor (TX) is turned on by a logic high-level transfer signal (TG), the photocharge accumulated in the corresponding photoelectric conversion device (PD) can be transferred to the floating diffusion region (FD).

[0037] The reset transistor (RX) can be positioned between the floating diffuser region (FD) and the power supply voltage (VDDPX) input terminal. The voltage of the floating diffuser region (FD) can be reset to the power supply voltage (VDD) in response to the reset control signal (RG).

[0038] A floating diffusion region (FD) can accumulate photocharge received from a transmission transistor (TX). The floating diffusion region (FD) can be coupled to a first capacitor (C1) connected to a ground terminal. For example, the floating diffusion region (FD) can be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate (e.g., a P-type substrate) including a first conductive impurity. For example, the substrate and the impurity-doped region can be modeled as a first capacitor (C1) acting as a junction capacitor. The floating diffusion region (FD) can be referred to as a sensing node.

[0039] In some embodiments, a logic high level may represent a voltage level used to activate (e.g., turn on) a corresponding component (e.g., a transistor), while a logic low level may represent a voltage level used to deactivate (e.g., turn off) a corresponding component (e.g., a transistor).

[0040] Although Figure 2 For simplicity, an embodiment using a floating diffusion region (FD) with only one capacitor is shown, but other embodiments are possible, and the floating diffusion region (FD) may also have two or more capacitors. For example, the floating diffusion region (FD) can selectively receive additional capacitors by being connected to a dual conversion gain (DCG) transistor, so that the floating diffusion region (FD) may have two capacitors.

[0041] A source follower transistor (SF) can be coupled between a select transistor (SX) and a power supply voltage (VDDPX) input terminal. It can amplify the potential change of the floating diffusion region (FD) of the photocharge accumulated in the photoelectric conversion device (PD) and transmit the amplified result to the select transistor (SX).

[0042] The select transistor (SX) can be coupled between the source follower transistor (SF) and the column line (CL). The select transistor (SX) can be turned on by the select control signal (SEL), so that the select transistor (SX) can output the electrical signal received from the source follower transistor (SF) as a pixel signal (VPX).

[0043] In some embodiments, the operation of outputting a pixel signal (VPX) to transfer the voltage of the floating diffuser region (FD) to the column line (CL) via a source follower transistor (SF) and a select transistor (SX) will be referred to hereinafter as a readout operation. The process of receiving charge from the photoelectric conversion unit (PD) and turning on and off the transfer transistor (TX) to reduce the voltage of the floating diffuser region (FD) will be referred to hereinafter as an integration operation. The operation of charging the floating diffuser region (FD) based on the supply voltage (VDDPX) via a reset transistor (RX) will be referred to hereinafter as a reset operation.

[0044] Figure 3 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the clamping control circuit 100 shown is shown.

[0045] refer to Figure 3 The clamping control circuit 100 may include a bias circuit 110, a sensing circuit 120, and a clamping circuit 130.

[0046] The bias circuit 110 can bias the column lines (CL) of its output pixel signal (VPX) to the bias voltage (VB) level based on the control signals (CON1 to CON4) received from the timing controller 400.

[0047] The bias circuit 110 may include multiple transistors (N1 to N6). The multiple transistors (N1 to N6) may be implemented as NMOS transistors. For example, when the control signal (CON1 to CON4) transitions to a logic high level, the bias circuit 110 may bias node (ND1) to a bias voltage (VB) level.

[0048] Transistors (N1-N3) can be connected in series between node (N1) and the ground voltage (VSSPX) input terminal. Transistor (N1) can receive the control signal (CON1) through its gate terminal. Transistor (N2) can receive the control signal (CON2) through its gate terminal. The gate terminals of transistors (N3, N6) can be connected to each other. Transistor (N4) can be connected between the bias voltage (VB) input terminal and transistor (N5), so that transistor (N4) can receive the control signal (CON3) through its gate terminal. Transistor (N5) can be connected between the drain terminal of transistor (N4) and the gate terminal of transistor (N3), so that transistor (N5) can receive the control signal (CON4) through its gate terminal. The source and drain terminals of transistor (N6) are connected to the ground voltage (VSSPX) input terminal, so that transistor (N6) can operate as a MOS capacitor.

[0049] When the sensing enable signal (S_EN) is activated, the sensing circuit 120 can detect the voltage level of the pixel signal (VPX) applied to the sensing node (ND1), enabling the sensing circuit 230 to output a sensing signal (VSEN). The sensing circuit 120 can output a clamping voltage control signal (CV) corresponding to the voltage level of the detected sensing signal (VSEN). The sensing circuit 120 can perform an automatic zeroing operation based on the sensing auto-zeroing signal (S_AZ) and can store the voltage of nodes (ND1, ND2) in a capacitor (C2).

[0050] The sensing circuit 120 may include a plurality of transistors (P1, P2, N7) and a capacitor (C2). In one embodiment, the plurality of transistors (P1, P2) may be implemented as PMOS transistors. The transistor (N7) may be an NMOS transistor.

[0051] Transistor (P1) can be connected between the power supply voltage (VDDPX) input terminal and node (ND3) so that transistor (P1) can receive the sense signal (VSEN) through its gate terminal. Transistor (P2) can be connected between node (ND2) and node (ND3) so that transistor (P2) can receive the sense auto-zero signal (S_AZ) through its gate terminal. Capacitor (C2) can be connected between node (ND1) and node (ND2).

[0052] Transistor (N7) can be connected between node (ND3) and ground voltage (VSSPX) input terminal, so that transistor (N7) can receive a sense enable signal (S_EN) through its gate terminal. Transistor (N7) can also be referred to as a "sense activation circuit", which controls whether the sense circuit 120 is activated based on the sense enable signal (S_EN).

[0053] When the clamp enable signal (C_EN) is activated, the clamp circuit 130 can control the level of the clamp voltage (CLP) output to the column line (CL) based on the clamp voltage control signal (CV).

[0054] The clamping circuit 130 may include a plurality of transistors (N8, N9). In one embodiment, the plurality of transistors (N8, N9) may be implemented as NMOS transistors.

[0055] Transistors (N8, N9) can be connected in series between the power supply voltage (VDDPX) input terminal and the column line (CL). Transistor (N8) can receive the clamp voltage control signal (CV) through its gate terminal. Transistor (N8) can be called a clamp transistor and is used to control the level of the clamp voltage (CLP). Transistor (N9) can receive the clamp enable signal (C_EN) through its gate terminal.

[0056] The transistor (N8) can operate as a source follower transistor, with its input terminals connected to the sensing circuit 120. The clamping voltage (CLP) can be determined based on the voltage of the clamping voltage control signal (CV). The column line (CL) voltage can be determined based on the pixel signal (VPX) voltage and the clamping voltage (CLP).

[0057] In other words, when both transistors (N8) and (N9) are turned on, the voltage output through the column line (CL) can be the higher of the pixel signal (VPX) voltage and the clamping voltage (CLP). For example, when the pixel signal (VPX) voltage is greater than the clamping voltage (CLP), the column line (CL) voltage can be determined based on the pixel signal (VPX) voltage. When the pixel signal (VPX) voltage is less than the clamping voltage (CLP), the column line (CL) voltage can be determined based on the clamping voltage (CLP).

[0058] For example, the voltage of the floating diffusion region (FD) may drop drastically compared to the target voltage. Therefore, the voltage of the pixel signal (VPX) may drop drastically. In one embodiment, the voltage of the column line (CL) can be determined based on a clamping voltage (CLP). The clamping control circuit 100 can adjust the voltage level of the column line (CL) based on a clamping voltage control signal (CV) corresponding to the sensing signal (VSEN) to prevent it from dropping to a specific voltage level or lower. More detailed operation of the clamping control circuit 100 will be described later. Figure 4 and Figure 5 Describe it.

[0059] Figure 4 and Figure 5 Based on some embodiments of this disclosure Figure 3 The diagram shows the operation of the clamping control circuit 100.

[0060] In some embodiments, the clamping control circuit 100 can operate in either a bias operation mode or a clamping operation mode. The operation mode of the clamping control circuit 100 can be controlled based on a clamping enable signal (C_EN). For example, when the clamping circuit 130 is not operating during the deactivation period of the clamping enable signal (C_EN), the clamping control circuit 100 can operate in the bias operation mode to sense the voltage level of the pixel signal (VPX). On the other hand, when the clamping circuit 130 is operating during the activation period of the clamping enable signal (C_EN), the clamping control circuit 100 can operate in the clamping operation mode to clamp the voltage level of the pixel signal (VPX).

[0061] First, refer to Figure 4 This describes an embodiment of the clamp control circuit 100 operating in bias mode.

[0062] When the control signals (CON1 to CON4) are activated, transistors (N1 to N6) are turned on, allowing node (ND1) to be biased to the bias voltage (VB) level. When the level of the sense voltage (VSEN) increases in response to the pixel signal (VPX), transistor (P1) can be turned off. When the sense auto-zero signal (S_AZ) is at a logic low level and transistor (P2) is turned on, the clamp voltage control signal (CV) can maintain a low voltage level (i.e., a voltage level at which clamping operation is not performed (V2, described later)).

[0063] In bias operation mode, the clamp enable signal (C_EN) is deactivated and the transistor (N9) is turned off, preventing the clamp circuit 130 from operating. Therefore, as shown in path (A), the voltage level of the pixel signal (VPX) can be biased according to the voltage level of node (ND1) and transmitted to ADC 300.

[0064] Reference Figure 5 An embodiment of the clamp control circuit 100 operating in clamp operation mode is described.

[0065] When control signals (CON1~CON4) are activated, transistors (N1~N6) are turned on, allowing node (ND1) to be biased to the bias voltage (VB) level. During auto-zero operation, when the auto-zero signal (S_AZ) is sensed to be at a logic low level, transistor (P2) is turned on, allowing the voltage at nodes (ND1, ND2) to be stored in capacitor (C2). When the auto-zero signal (S_AZ) transitions to a logic high level, transistor (P2) can be turned off.

[0066] When the clamp enable signal (C_EN) is activated to a logic high level in clamp operation mode, transistor (N9) can be turned on. When the level of the sense voltage (VSEN) decreases in response to the voltage level of the pixel signal (VPX), transistor (P1) can be turned on. Therefore, the voltage level of the clamp voltage control signal (CV) increases in response to the supply voltage (VDDPX) level, and transistor (N8) can be turned on. As a result, as shown in path (B), the voltage level of the column line (CL) can be raised to a level higher than the reference voltage (V3, described later) and then transmitted to ADC 300.

[0067] To improve the reliability of image data by eliminating noise from the image sensor, an analog-to-digital conversion (ADC) operation using correlated double sampling (CDS) technology can be performed. A reset sampling operation can be performed for the ADC operation.

[0068] When performing a reset sampling operation, if the light intensity incident on the image sensor is too high, the voltage level of the reset signal (RG) may drop drastically. Therefore, in environments where the light intensity incident on the pixel (PX) is high, the image sensing device may be unable to correctly identify sunspots in the image (i.e., a blackout). When a blackout occurs, the pixel voltage decreases, and due to the operating margin of the bias circuit 110, the pixel signal (VPX) can be sufficiently sensed (or detected). To avoid this problem, a clamping circuit 130 can be used to prevent the voltage level of the column lines from falling below a predetermined level.

[0069] However, if the voltage level of the clamp voltage control signal (CV) applied to the gate terminal of the transistor (N8) included in the clamp circuit 130 is fixed to a specific clamp voltage level, the leakage current generated in the clamp transistor may affect the sensing of the pixel signal (VPX). To address this issue, the operating area of ​​the pixel may be limited when the clamp margin is increased. That is, the input range of the ADC 300 may decrease when a low supply voltage level or a pixel output signal with a large swing range is required.

[0070] Therefore, the image sensing apparatus according to this disclosure can use the sensing circuit 120 to detect the voltage level of the pixel signal (VPX) and can control the level of the clamping voltage (CLP) of the clamping transistor in response to the detected sensing signal (VSEN). Thus, leakage current caused by the clamping transistor can be prevented, and sufficient clamping margin can be ensured even under dark conditions.

[0071] Figure 6 This illustrates some embodiments based on the present disclosure. Figure 1 The circuit diagram of the analog-to-digital converter (ADC) 300 shown is shown.

[0072] refer to Figure 6 The ADC 300 can perform reset sampling operations and pixel sampling operations, and can output the difference between the resulting values ​​of the sampling operations as a digital signal (i.e., ADC data ADC_OUT). The ADC 300 can obtain a reset voltage through the reset sampling operation and a data voltage through the pixel sampling operation. In one embodiment, the reset voltage can be obtained when the voltage of the ramp signal (VRAMP) and the voltage of the column line (CL) become equal after the reset operation is completed. The data voltage can be obtained when the voltage of the ramp signal (VRAMP) and the voltage of the column line (CL) become equal after the accumulation operation is completed. The ADC 300 can generate a digital signal for the image based on the difference between the data voltage and the reset voltage. In some embodiments, input and input (I / O) circuitry can receive the digital signal from the ADC 300 and output the digital signal as image data.

[0073] The ADC 300 may include a capacitor (C3), a capacitor (C4), a comparator 310, and a counter 320.

[0074] Capacitor (C3) can receive the ramp signal (VRAMP) and transmit the delayed ramp signal (VR) to one input terminal of comparator 310. Capacitor (C4) can receive the pixel signal (VPX) and transmit the delayed pixel signal (VP) to the other input terminal of comparator 310.

[0075] Comparator 310 compares the delayed ramp signal (VR) with the delayed pixel signal (VP), generates comparison data (CMP_OUT) based on the comparison result, and transmits the comparison data (CMP_OUT) to counter 320. According to one embodiment, if the voltage level of the delayed ramp signal (VR) is greater than the voltage level of the delayed pixel signal (VP), comparator 310 generates logic high comparison data (CMP_OUT). When the voltage level of the delayed ramp signal (VR) is less than the voltage level of the delayed pixel signal (VP), comparator 310 generates logic low comparison data (CMP_OUT). That is, the comparison data (CMP_OUT) can represent the amplitude relationship between the ramp signal (VRAMP) and the pixel signal (VPX).

[0076] Comparator 310 can perform an auto-zero operation based on an auto-zero signal (AZ). In one embodiment, the auto-zero operation can refer to performing an adjustment between the voltage level of a delayed ramp signal (VR) and the voltage level of a delayed pixel signal (VP) for comparison. Comparator 310 can perform the auto-zero operation during the period when the auto-zero signal (AZ) is at a logic high level. The auto-zero signal (AZ) can be generated and provided by timing controller 400.

[0077] Counter 320 can be activated in response to a counter enable signal (CNT_EN) received from timing controller 400. Counter 320 can perform a counting operation until the ramp signal (VRAMP) matches the analog pixel signal (VPX). Then, the activated counter 320 can perform counting in response to a logic high level comparison data (CMP_OUT) and can output the counting result as ADC data (ADC_OUT).

[0078] Figure 7 It shows the basis Figure 3 A timing diagram of the operation of the image sensing device in an embodiment.

[0079] refer to Figure 7 The operation of converting pixel signals (VPX) into image data can be divided into a reset period (RST) and a signal period (SIG). The reset period (RST) is the time interval during which an analog-to-digital (AD) conversion is performed on the reference signal of the pixel (PX), while the signal period (SIG) is the time interval during which an AD conversion is performed on the image signal of the pixel (PX). The time interval from T1 to T6 will be defined as the reset period. The time intervals following each of time points T7, T8, and T9 will be defined as the signal period. For example, a reset sampling operation can be performed during the time interval from T1 to T6.

[0080] At time point (T1), a read operation can be performed to execute a reset sampling operation. For the read operation, the select transistor (SX) can be turned on, and the voltage of the column line (CL) can be determined based on the pixel signal (VPX). The voltage of the pixel signal (VPX) can be determined based on the voltage level of the floating diffusion region (FD). The floating diffusion region (FD) can be in a reset state obtained through a reset operation. The voltage of the floating diffusion region (FD) can be the voltage at which it is reset based on the supply voltage (VDDPX). Therefore, when the select transistor (SX) is turned on to perform the reset sampling operation, the voltage level of the column line (CL) can be determined based on the voltage of the reset floating diffusion region (FD).

[0081] In other words, when the reset signal (RG) is logic high, a pixel signal (VPX) corresponding to the voltage of the reset floating diffusion region (FD) can be output from the pixel (PX). Then, the sensing circuit 120 can output a sensing signal (VSEN) corresponding to the voltage level of the pixel signal (VPX). When the clamp enable signal (C_EN) is deactivated, the clamp control circuit 100 can operate in bias operation mode, as described above. Figure 4 As stated above.

[0082] At time point (T2), the reset signal (RG) can transition to a logic low level. Then, since the auto-zero signal (AZ) is at a logic high level, comparator 310 can perform an auto-zero operation between the ramp signal (VRAMP) and the pixel signal (VPX). When the blackout occurs, the voltage level of the sensing signal (VSEN) can decrease with a negative (-) slope.

[0083] At time point (T3), the sense auto-zero signal (S_AZ) and sense enable signal (S_EN) can transition to logic high. Therefore, the voltage level of the sense signal (VSEN) will discharge and gradually decrease according to the voltage level of the pixel signal (VPX). At time point (T3), the voltage level of the sense signal (VSEN) will instantaneously increase by an offset value due to the transistor switching noise (NV). As the voltage level of the sense signal (VSEN) decreases, the voltage level of the clamp voltage control signal (CV) will gradually increase.

[0084] At time point (T4), the clamp enable signal (C_EN) can transition to a logic high level. When the clamp enable signal (C_EN) is activated, the clamp control circuit 100 can, as... Figure 5 It operates in the clamping mode shown.

[0085] When the voltage level of the sensing signal (VSEN) drops to a low voltage level, the voltage level of the clamping voltage control signal (CV) can be maintained at the V1 voltage level. In one embodiment, the V1 voltage can be obtained by subtracting the drain-source voltage (VDS) of the transistor (P1) from the supply voltage (VDDPX). When the voltage level of the clamping voltage control signal (CV) increases the V1 voltage level, the voltage level of the column line (CL) may also rise above the reference voltage (V3). In one embodiment, the reference voltage (V3) can be set to the voltage level of the reset signal (RG) as described above.

[0086] For example, in bias operation mode, since the clamping circuit 130 is not operational, the voltage level of the pixel signal (referred to as "VPX1" in bias operation mode) can be the V4 voltage level. In one embodiment, the V4 voltage can be the voltage level corresponding to the leakage current of the select transistor (SX). In another embodiment, the V4 voltage can be the voltage level corresponding to the bias voltage (VB).

[0087] In clamping operation mode, clamping circuit 130 operates to raise the voltage level of the pixel signal (referred to as "VPX2" in clamping operation mode) above the reference voltage (V3).

[0088] As described above, the image sensing apparatus according to embodiments of this disclosure can ensure clamping margin by raising the voltage level of the pixel signal (VPX) to a level higher than the reference voltage (V3) in clamping operation mode. That is, the operating margin of the pixel signal (VPX) applied to the ADC 300 should be greater than or equal to D1, ensuring the maximum swing range of the ADC 300's input range and generating the maximum code from the digital code output from the ADC 300.

[0089] Subsequently, at time T5, the auto-zeroing operation of comparator 310 can be stopped because the auto-zeroing signal (AZ) is at a logic low level. At this time, the pixel signal (VPX1 or VPX2) can maintain its voltage level.

[0090] Subsequently, to perform a reset sampling operation, an offset can be applied to the ramp signal (VRAMP). Therefore, the ramp generator 200 can output a ramp signal (VRAMP) that first maintains a voltage level with the added ramp offset, and then decreases with a negative (-) slope. In one embodiment, the ramp offset can be a value indicating the degree of change in the voltage level of the ramp (rising or falling) from the voltage level at the time of auto-zeroing, due to the characteristics of the ramp generator 200. After a predetermined time has elapsed, and after a delay caused by the capacitor (C3) in the ADC 300, the ramp delay signal (VR) can decrease with a negative (-) slope in response to the ramp signal (VRAMP).

[0091] Subsequently, at time point (T6), the clamping operation mode can be terminated when the sense auto-zero signal (S_AZ) and clamp enable signal (C_EN) go low. The level of the sense voltage (VSEN) may rise again in response to the voltage level of the pixel signal (VPX). Then, as the level of the sense voltage (VSEN) rises, the voltage level of the clamp voltage control signal (CV) drops to the level of the clamp reference voltage (V2). In one embodiment, the clamp reference voltage (V2) can be set to a low voltage level at which the transistor (N8) of the clamping circuit 130 will not be turned on (not exceeding a threshold voltage). That is, the voltage of the column line (CL) when the selection transistor (SX) is turned on to perform the reset sampling operation can be referred to as the clamp reference voltage (V2). With the start of the signal period (SIG), the delayed ramp signal (VR) may return to the upper limit of the ramp and may decrease with a negative (-) slope after a predetermined time has elapsed.

[0092] Then, at time point (T7), since the transmission signal (TG) is temporarily at a logic high level, a pixel signal (VPX) corresponding to the voltage of the floating diffusion region (FD) in which the photocharge generated from the pixel (PX) has accumulated can be output from the pixel (PX). The voltage level of the pixel signal (VPX) can decrease depending on the amount of photocharge accumulated in the floating diffusion region (FD).

[0093] Subsequently, at time point (T8), the delayed pixel signal (VP) can be converted to a low level corresponding to the voltage level of the pixel signal (VPX).

[0094] Figure 8 Based on this disclosure Figure 1 The circuit diagram shows another embodiment of the clamping control circuit.

[0095] refer to Figure 8 The clamping control circuit 100_1 may include a bias circuit 110, a sensing circuit 120_1, and a clamping circuit 130. According to... Figure 8 The clamping control circuit 100_1 in the embodiment and Figure 3 The difference in the clamping control circuit 100 lies in the configuration of the sensing circuit (120_1). Therefore, in Figure 8 In the embodiments described, for the sake of brevity, the pairs and Figure 3 For redundant descriptions of the same configuration and operation, please refer to [reference]. Figure 8 Only detailed description of the relationship with Figure 3 The rest are different.

[0096] The sensing circuit 120_1 may include multiple transistors (P1, P2, N7), a capacitor (C2), and a switch (SW). In one embodiment, the switching operation of the switch (SW) can be controlled by a switch control signal (SCON). The switch control signal (SCON) may be a signal received from the timing controller 400.

[0097] When the switch control signal (SCON) is activated, the switch (SW) can be turned on. As a result, the operation of storing the voltage of the pixel signal (VPX) in the capacitor (C2) can be performed. On the other hand, when the switch control signal (SCON) is deactivated, the switch (SW) can be turned off, and one terminal of the capacitor (C2) can be in a floating state. Therefore, the voltage level of the sensing signal (VSEN) can be reduced by a certain level in response to the voltage stored in the capacitor (C2).

[0098] Figure 9 It shows the basis Figure 8 A timing diagram of the operation of the image sensing device in an embodiment.

[0099] exist Figure 9 In the embodiments described, for the sake of brevity, the terms and conditions will be omitted here. Figure 7 Repeated descriptions of the same operations, and references Figure 9 Only detailed description of the relationship with Figure 7 Different components.

[0100] refer to Figure 9 During time period (T3), before the clamp enable signal (C_EN) transitions to a logic high level, the switch control signal (SCON) can be activated to a logic high level. Therefore, the switch (SW) can be turned on, allowing the voltage level of the sensing signal (VSEN) to discharge and gradually decrease based on the voltage level of the pixel signal (VPX). During time period (T3), the voltage level of the pixel signal (VPX) can be detected based on the on / off state of the switch (SW) and stored in the capacitor (C2).

[0101] During the time period (T4), the control signal (SCON) can transition to a logic low level, while the clamp enable signal (C_EN) can transition to a logic high level. Therefore, the switch (SW) turns off, reducing the voltage level of the sensing signal (VSEN) to maintain a constant voltage level.

[0102] During time period (T4), switch (SW) is turned off, thus blocking the path between capacitor (C2) and column line (CL). Subsequently, the path of leakage current flowing to column line (CL) is blocked, allowing the charging voltage in capacitor (C2) to rise, and the voltage level of the sense signal (VSEN) to decrease by a range comparable to... Figure 7 Larger. Therefore, in Figure 9 In this embodiment, the voltage level of the pixel signal (VPX2) in clamping operation mode can be compared to Figure 7 Increase.

[0103] As can be clearly seen from the above description, the image sensing device according to the embodiments of the present disclosure can prevent sunken phenomena by increasing the clamping margin of pixel signals, thereby improving the dynamic range.

[0104] The embodiments disclosed herein can provide a variety of beneficial effects that can be directly or indirectly recognized by those skilled in the art.

[0105] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be devised based on what is described and / or shown in this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A clamping control circuit, comprising: A sensing circuit, which: senses the voltage level of a pixel signal to output a sensing signal; and A clamping circuit coupled to a column line, the clamping circuit: controls the voltage level of a clamping voltage control signal in response to the voltage level of the sensing signal; and controls the level of a clamping voltage in response to a clamping enable signal, wherein the clamping voltage is controlled based on the voltage level of the clamping voltage control signal and is provided to the column line.

2. The clamping control circuit according to claim 1, wherein, The sensing circuit includes: A first capacitor is connected between a first node and a second node to which the pixel signal is applied; A first transistor, connected between the second and third nodes, performs a switching operation in response to a sensed auto-zero signal; and The second transistor is connected between the power supply voltage input terminal and the third node, and its gate terminal is connected to the second node.

3. The clamping control circuit according to claim 2, wherein, The sensing circuit further includes: A switch is connected between the first node and the first capacitor and performs a switching operation in response to a switch control signal.

4. The clamping control circuit according to claim 1, wherein, The sensing circuit includes: A sensing activation circuit, which controls the activation of the sensing circuit based on a sensing enable signal.

5. The clamping control circuit according to claim 4, wherein, The clamping circuit also includes: A third transistor is connected between the power supply voltage input terminal and the fourth node, and receives the clamping voltage control signal through its gate terminal; and A fourth transistor is connected between the fourth node and the column line, and receives the clamp enable signal through its gate terminal.

6. The clamping control circuit according to claim 1, wherein, In bias operation mode, the clamping circuit deactivates the clamping enable signal to control the column lines to reach the voltage level corresponding to the pixel signal.

7. The clamping control circuit according to claim 1, wherein, In clamping operation mode, the clamping circuit activates the clamping enable signal to control the column lines to reach the level of the clamping voltage.

8. The clamping control circuit according to claim 1 further includes: A biasing circuit that biases the column lines to a bias voltage level based on a control signal.

9. The clamping control circuit according to claim 8, wherein, The bias circuit includes: A fifth transistor is connected between the first node and the fifth node to which the pixel signal is applied, and is controlled in response to a first control signal; A sixth transistor, which is connected between the fifth and sixth nodes, and is controlled in response to a second control signal; The seventh transistor is connected between the sixth node and the ground voltage input terminal, and its gate terminal is connected to the seventh node; The eighth transistor is connected between the bias voltage input terminal and the eighth node to receive the third control signal; A ninth transistor, connected between the eighth and seventh nodes, and controlled in response to a fourth control signal; and The tenth transistor includes a source terminal and a drain terminal commonly connected to the ground voltage input terminal, and a gate terminal connected to the seventh node. The control signals include the first control signal to the fourth control signal.

10. An image sensing device, comprising: Pixel: Outputs pixel signals to column lines; A clamping control circuit, comprising: sensing a voltage level of the pixel signal to output a sensing signal; and, in a clamping operation mode, controlling a clamping voltage in response to the sensing signal, the clamping voltage being controlled to a level greater than or equal to a reference voltage and provided to the column lines; and An analog-to-digital converter that performs analog-to-digital conversion on the voltage of the column lines based on a ramp signal.

11. The image sensing device according to claim 10, wherein, The voltage of the column line is determined based on the voltage level of the pixel signal when the reset signal is activated at a first time point.

12. The image sensing device according to claim 11, wherein, The analog-to-digital converter also performs an automatic zeroing operation at a second time point after the first time point in response to an automatic zeroing signal.

13. The image sensing device according to claim 10, wherein, The clamping control circuit includes: A sensing circuit, comprising: sensing the voltage level of the pixel signal to output the sensing signal; and A clamping circuit that: controls the voltage level of a clamping voltage control signal in response to the voltage level of the sensing signal; and controls the level of the clamping voltage in response to a clamping enable signal, wherein the level of the clamping voltage is controlled based on the voltage level of the clamping voltage control signal.

14. The image sensing device according to claim 13, wherein, The sensing circuit operates in response to a sensing auto-zero signal, such that the voltage level of the sensing signal decreases according to the voltage level of the pixel signal.

15. The image sensing device according to claim 13, wherein, The sensing circuit includes: A first capacitor is connected between a first node and a second node to which the pixel signal is applied; A first transistor, connected between the second and third nodes, performs a switching operation in response to a sensed auto-zero signal; and The second transistor is connected between the power supply voltage input terminal and the third node, and its gate terminal is connected to the second node.

16. The image sensing device according to claim 15, wherein, The sensing circuit further includes: A switch is connected between the first node and the first capacitor and performs a switching operation in response to a switch control signal.

17. The image sensing device according to claim 15, wherein, The sensing circuit further includes: A sensing activation circuit, which controls the activation of the sensing circuit based on a sensing enable signal.

18. The image sensing device according to claim 13, wherein, The clamping circuit also includes: A third transistor is connected between the power supply voltage input terminal and the fourth node, and receives the clamping voltage control signal through its gate terminal; and A fourth transistor is connected between the fourth node and the column line, and receives the clamp enable signal through its gate terminal.

19. The image sensing apparatus according to claim 10, wherein, The pixels include: A reset transistor, which: in response to a reset signal, resets the voltage of the floating diffusion region to the power supply voltage; and A transmission transistor that, in response to a transmission signal, transfers the photocharge accumulated in the photoelectric conversion component to the floating diffusion region.

20. The image sensing device according to claim 19, wherein, The reference voltage is set to the voltage level of the reset signal.

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