An array readout control circuit based on synchronous control code multiplexing and bus multiplexing

By using synchronous control code multiplexing and bus multiplexing, combined with a two-level bus and phase-locked loop design, the problems of hardware redundancy, bus load and misalignment in high-resolution image sensor arrays are solved, achieving stability and efficient transmission of high-precision data output, and optimizing the hardware resource utilization of the readout control circuit.

CN122160646APending Publication Date: 2026-06-05PEKING UNIV
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV
Filing Date
2026-04-20
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Existing readout control circuits face bottlenecks in hardware redundancy and integration in high-resolution and high-frame-rate image sensor arrays, issues related to bus load and signal integrity, bit faults in high-speed serial output, and bandwidth utilization pressure under continuous transmission of high-bit-width data, making it difficult to maintain the accuracy and stability of data output at high speed and high precision.

Method used

An array readout control circuit based on synchronous control code multiplexing and bus multiplexing is adopted. Synchronous control codes are generated by column selection Gray code counters to realize the multiplexing of hot column selection signals and segmented phase signals. Combined with the innovative design of two-level bus structure and phase-locked loop, hardware resource utilization and timing matching are optimized, power consumption is reduced, and signal integrity and data throughput are improved.

Benefits of technology

It significantly reduces the chip physical area occupied by the bus and parasitic interference, reduces power consumption and timing complexity, improves the accuracy and stability of data output, enhances pixel integration and data throughput, and is suitable for high-speed readout of high-precision image sensor arrays.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122160646A_ABST
    Figure CN122160646A_ABST
Patent Text Reader

Abstract

The application provides an array readout control circuit based on synchronous control code multiplexing and bus multiplexing, and relates to the technical field of integrated circuits. A column selection gray code counter is connected with a decoder, and is used for generating a synchronous control code. After being decoded by the decoder, the synchronous control code generates a one-hot column selection signal and a segmented phase signal. A column-level register unit is connected with the decoder, and includes a plurality of group register units and a plurality of column readout register units. Each group register unit stores two columns of pixel quantization data of an odd column and a right adjacent even column based on the segmented phase signal. Each column readout register unit stores pixel quantization data in the corresponding group register unit based on the segmented phase signal. The application significantly reduces the chip physical area occupied by the bus and the parasitic interference introduced by a large number of parallel buses, improves the pixel integration, reduces the power consumption, and reduces the time sequence complexity. The two-level bus structure can shorten the bus establishment time, improve the establishment accuracy, and enhance the accuracy and stability of data output.
Need to check novelty before this filing date? Find Prior Art