Integrated circuit comprising a fill unit

Abstract

The present disclosure relates to an integrated circuit including a fill cell, the integrated degree of which is improved. An example integrated circuit includes a first cell and a second cell, each of which includes a first active region and a second active region, and a pitch-sized fill cell arranged between the first cell and the second cell and adjacent to the first cell and the second cell in a first direction. The fill cell includes a first gate stack and a second gate stack adjacent to each other in the first direction, and a separation structure arranged between the first gate stack and the second gate stack. The separation structure at least partially separates the first active region and the second active region.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit. Background Technology

[0002] Integrated circuits can be designed based on standard cells. Specifically, the layout of an integrated circuit can be generated by placing standard cells according to the data defining the integrated circuit and routing the placed standard cells. These standard cells are pre-designed and stored in a cell library.

[0003] As semiconductors produced through semiconductor manufacturing processes become smaller, the pattern size within a standard cell may decrease, and the size of the standard cell may also decrease. Summary of the Invention

[0004] This disclosure relates to integrated circuits with improved layout integration.

[0005] Furthermore, this disclosure is not limited to the issues mentioned above, and other issues will become clear to those skilled in the art from the following description.

[0006] Generally, according to some aspects, an integrated circuit includes: a first unit and a second unit, each of the first unit and the second unit including a first active region and a second active region; and a one-pitch sized fill unit disposed between the first unit and the second unit and adjacent to the first unit and the second unit in a first direction, wherein the fill unit includes: a first gate stack and a second gate stack adjacent to each other in the first direction; and a partition structure disposed between the first gate stack and the second gate stack, and the partition structure at least partially dividing the first active region and the second active region.

[0007] Generally, according to some aspects, an integrated circuit includes: a first unit and a second unit, each of the first unit and the second unit including an integrated transistor; a filler unit of a pitch size disposed between the first unit and the second unit and adjacent to the first unit and the second unit in a first direction; and a plurality of gate stacks extending in a second direction and spaced apart from each other in the first direction, the second direction intersecting the first direction. The filler unit includes: two adjacent gate stacks among the plurality of gate stacks; and a separator structure disposed between the two gate stacks and extending in the second direction; and a first semiconductor pattern included in the first unit adjacent to one sidewall of the separator structure and a second semiconductor pattern included in the second unit adjacent to another sidewall opposite to the one sidewall of the separator structure are doped with impurities of different conductivity types.

[0008] Generally, according to some aspects, an integrated circuit includes: a fill cell having a pitch dimension and including a first sidewall and a second sidewall opposite to the first sidewall; a first unit and a third unit adjacent to the first sidewall of the fill cell; a second unit adjacent to the second sidewall of the fill cell; and a plurality of gate stacks spaced apart from each other in a first direction and extending in a second direction intersecting the first direction. The fill cell includes: two adjacent gate stacks among the plurality of gate stacks; and a separator structure disposed between the two gate stacks and extending in the second direction. The height of each of the fill cell and the second unit in the second direction is twice the height of each of the first unit and the third unit in the second direction. The first unit and the third unit include an active region having a first width in the second direction, and the second unit includes a first active region each having the first width and a second active region having a second width in the second direction, the second width being twice the first width. Attached Figure Description

[0009] The embodiments will be more clearly understood in conjunction with the accompanying drawings and the following detailed description.

[0010] Figure 1 and Figure 2 This is a conceptual diagram of a logic unit used to illustrate an example of an integrated circuit device.

[0011] Figure 3This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0012] Figure 4 It is along Figure 3 Example sectional view taken by line A-A'.

[0013] Figure 5 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0014] Figure 6 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0015] Figure 7 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0016] Figure 8 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0017] Figure 9 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0018] Figure 10 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits.

[0019] Figure 11 This is an integrated circuit layout diagram used to illustrate examples of integrated circuits. Detailed Implementation

[0020] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements, and repeated descriptions thereof will be omitted.

[0021] The embodiments described herein can have various variations and forms, and therefore, some embodiments will be shown in the accompanying drawings and described in detail in the description. However, this is not intended to limit this disclosure to a particular mode of practice, but it will be understood that all variations, equivalents, and substitutions without departing from the spirit and scope of this disclosure are included herein. In the description of embodiments, certain detailed explanations of related technologies are omitted where they are deemed likely to unnecessarily obscure the essence of this disclosure.

[0022] An integrated circuit according to some implementations may include one or more standard cells arranged in an integrated circuit layout according to predetermined rules. One or more standard cells may be reused repeatedly in the integrated circuit design. Therefore, standard cells can be pre-designed according to manufacturing techniques and stored in a standard cell library. Integrated circuit designers can take such standard cells, include them in the integrated circuit design, and place them in the integrated circuit layout according to predefined placement rules.

[0023] Standard cells can include a variety of basic circuit devices commonly used in digital circuit designs for electronic devices, such as inverters, and AND, NAND, OR, XOR, and NOR logic circuits, typically found in designs for central processing units (CPUs), graphics processing units (GPUs), and system-on-a-chip (SoCs). Standard cells can also include other circuit devices commonly used in circuit blocks, such as flip-flops and latches.

[0024] A filler cell can be a design block in an integrated circuit, inserted between two standard cells to conform to integrated circuit design and manufacturing rules. Proper design and arrangement of standard cells and filler cells can improve package density and circuit performance.

[0025] Figure 1 and Figure 2 This is a conceptual diagram of a logic unit used to illustrate an example of an integrated circuit device.

[0026] refer to Figure 1 A single-height cell (SHC) can be provided. Specifically, a first power supply trace M1_R1 and a second power supply trace M1_R2 can be disposed below the substrate 100. The first power supply trace M1_R1 can be a path through which a source voltage VSS, such as a ground voltage, is provided. The second power supply trace M1_R2 can be a path through which a drain voltage VDD, such as a power supply voltage, is provided.

[0027] A single-height cell SHC can be defined between a first power supply line M1_R1 and a second power supply line M1_R2. A single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. In other words, a single-height cell SHC may have a CMOS structure disposed between the first power supply line M1_R1 and the second power supply line M1_R2.

[0028] The PMOSFET region PR and the NMOSFET region NR can have the same width in the second direction D2. The length of the single-height cell SHC in the second direction D2 can be defined as a first height HE1. The first height HE1 can be substantially the same as the distance (e.g., pitch) between the first power trace M1_R1 and the second power trace M1_R2.

[0029] A single-height cell (SHC) can form a single logic cell. Here, a logic cell can refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic cell can include transistors used to form logic elements and wiring connecting the transistors to each other.

[0030] refer to Figure 2 A dual-height cell DHC can be provided. Specifically, a first power supply trace M1_R1, a second power supply trace M1_R2, and a third power supply trace M1_R3 can be disposed on the substrate 100. The second power supply trace M1_R2 can be arranged between the first power supply trace M1_R1 and the third power supply trace M1_R3. The third power supply trace M1_R3 can be a path through which the source voltage VSS is provided.

[0031] The dual-height cell DHC can be defined between the first power supply wiring M1_R1 and the third power supply wiring M1_R3. The dual-height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0032] The first NMOSFET region NR1 may be adjacent to the first power supply wiring M1_R1. The second NMOSFET region NR2 may be adjacent to the third power supply wiring M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 may be adjacent to the second power supply wiring M1_R2. In the top view, the second power supply wiring M1_R2 may be arranged between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0033] The length of the dual-height unit DHC in the second direction D2 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is nearly twice that of the second height. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can be combined to operate as a single PMOSFET region. Therefore, the channel size of the PMOS transistor in the dual-height cell DHC can be larger than... Figure 1 The channel size of the PMOS crystal in a single-height cell SHC.

[0034] For example, the channel size of a PMOS transistor in a dual-height cell DHC can be nearly twice the channel size of a PMOS transistor in a single-height cell SHC. As a result, a dual-height cell DHC can operate at a higher speed compared to a single-height cell SHC. In this disclosure, Figure 2 The dual-height unit DHC shown can be defined as a multi-height unit. Although not shown, a multi-height unit may include a tri-height unit having a unit height nearly three times that of a single-height unit SHC.

[0035] Figure 3 This is an example of an integrated circuit layout diagram 1000 used to illustrate an integrated circuit. Figure 4 It is along Figure 3 Example sectional view taken by line A-A'.

[0036] refer to Figure 3 and Figure 4 The first unit 10a, the second unit 10b and the first filling unit 10 can be formed on the substrate 100.

[0037] The substrate 100 may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0038] A first active region 112 can be defined on the first direction D1. The first active region 112 can be a location where a p-type transistor is formed. The first active region 112 can include, for example, a well region doped with an n-type impurity. In the following text, the first active region 112 can correspond to... Figure 1 PMOSFET region PR, Figure 2 The first PMOSFET region PR1 or Figure 2 The second PMOSFFET region PR2.

[0039] The first active region 112 may include a first lower active region 112B, a first upper active region 112U, and a first nanosheet 112NS. The first lower active region 112B may have sidewalls defined by deep trenches. The first upper active region 112U may have a needle-like shape protruding from the first lower active region 112B. The first upper active region 112U may have sidewalls defined by shallow trenches instead of deep trenches. The first nanosheet 112NS may be spaced apart from the first upper active region 112U. Figure 3 The illustration shows two nanosheets 112NS, but this is merely an example for illustrative purposes and is not limited thereto.

[0040] A second active region 114 may be defined in the first direction D1. The second active region 114 may be spaced apart from the first active region 112 in the second direction D2. The first active region 112 and the second active region 114 may be spaced apart from each other by a deep trench. The second active region 114 may be the site where an n-type transistor is formed. The second active region may include, for example, a well region doped with p-type impurities. In the following, the second active region 114 may correspond to Figure 1 NMOSFET region NR, Figure 2 The first NMOSFET region NR1 or Figure 2 The second NMOSFET region NR2.

[0041] Despite Figure 3 and Figure 4Although not shown, the second active region 114 may also include a second lower active region, a second upper active region, and a second nanosheet, similar to the structure of the first active region 112.

[0042] Refer again Figure 3 Each of the first unit 10a, the second unit 10b, and the first filling unit 10 may include a first active region 112 and a second active region 114.

[0043] An active region separation film 105 may be formed on a substrate 100. The active region separation film 105 may span between a first active region 112 and a second active region 114. The active region separation film 105 may extend in a first direction D1. The active region separation film 105 may occupy a deep trench that separates the first active region 112 and the second active region 114 from each other.

[0044] A cell separator 106 may be formed on a substrate 100. The cell separator 106 may occupy a deep trench separating the first active region 112 and the second active region 114 from each other. The cell separator 106 may extend in a first direction D1 along the boundary of the first cell 10a, the boundary of the second cell 10b, and the boundary of the first filling cell 10. Each of the active region separator 105 and the cell separator 106 may include an insulating material.

[0045] Each of the active zone separator 105 and the cell separator 106 may include an insulating material that occupies a deep trench defining the first active region 112 and the second active region 114. In the following description, the active zone separator 105 may be an insulating material film disposed between the first active region 112 and the second active region 114 included in a cell. In other words, the active zone separator 105 may be an insulating material film disposed within the cell. The cell separator 106 may not be disposed within the cell and may be an insulating material film extending along a cell boundary in a first direction D1. In other words, the cell separator 106 may be an insulating material film disposed along a cell boundary.

[0046] The integrated circuit device according to the embodiment may include a plurality of gate stacks 120 and a plurality of insulated gates 150. The gate stacks 120 and the insulated gates 150 may each extend in a second direction D2. The plurality of gate stacks 120 may be adjacent to each other in a first direction D1.

[0047] Multiple gate stacks 120 adjacent to each other in the first direction D1 can be spaced apart from each other by a contact polysilicon pitch (1 CPP). Similarly, adjacent gate stacks 120 and insulating gates 150 can be spaced apart from each other by 1 CPP.

[0048] In other words, when there are first gate stacks and second gate stacks that are adjacent to each other, if the distance between the center line of the first gate stack extending along the second direction D2 and the center line of the second gate stack extending along the second direction D2 is 1 CPP, this can mean that there are no other gate stacks or insulating gates arranged between the first gate stack and the second gate stack.

[0049] Each of the gate stack 120 and the insulating gate 150 may be disposed on the first active region 112 and the second active region 114. Each of the gate stack 120 and the insulating gate 150 may extend from the first active region 112 to the second active region 114. The gate stack 120 and the insulating gate 150 may intersect with the active region separator 105. A portion of the gate stack 120 and a portion of the insulating gate 150 may each extend on the cell separator 106.

[0050] refer to Figure 4 The gate stack 120 may include a main gate 122M, a sub-gate 122S, a gate insulating film 124, a gate spacer 126, and a gate capping film 128. In some cases, the gate stack 120 may not include the gate capping film 128. The gate spacer 126 may define a gate trench in which the gate insulating film 124 and the main gate 122M may be formed. The gate spacer 126 may include, for example, an insulating material. The gate insulating film 124 may be formed along the outer edge of a first nanosheet 112NS. Although not shown, the gate insulating film 124 may be formed along the outer edge of a second nanosheet. The gate insulating film 124 may include at least one of, for example, silicon oxide or a high-k material. The high-k material may be, for example, a material with a dielectric constant greater than that of silicon oxide. The main gate 122M and the sub-gate 122S may be formed on the gate insulating film 124. The sub-gate 122S may surround the first nanosheet 112NS. Although not shown, the sub-gate 122S may surround the second nanosheet. Each of the main gate 122M and the sub-gate 122S may include at least one of, for example, a metal (including a metal alloy containing two or more metals), a metal nitride, a metal carbide, a metal silicide, or a semiconductor material. A gate capping film 128 may be disposed on the main gate 122M. The gate capping film 128 may include, for example, an insulating material.

[0051] The insulating gate 150 may at least partially divide the first active region 112 and the second active region 114. In some embodiments, a portion of the sidewall of the insulating gate 150 may contact a semiconductor material film included in each of the first active region 112 and the second active region 114.

[0052] The insulating gate 150 may intersect with the active partition membrane 105. The insulating gate 150 may be disposed on the active partition membrane 105, and in some embodiments, a portion of the insulating gate 150 may be recessed into the active partition membrane 105. The insulating gate 150 may include, for example, an insulating material. The insulating gate 150 may be a single membrane, and in some embodiments, the insulating gate 150 may have a multilayer structure comprising two or more membranes.

[0053] Semiconductor patterns 130 can be formed between adjacent gate stacks 120. Semiconductor patterns 130 can be formed by removing portions of the first active region 112 and the second active region 114 to form recesses, and then filling the recesses by an epitaxial process. At least a portion of the semiconductor pattern 130 can be included in the source / drain regions of a transistor. The semiconductor pattern 130 formed on the first active region 112 can be doped with impurities of a different conductivity type than the semiconductor pattern 130 formed on the second active region 114.

[0054] A cell gate dicing pattern 160 may be disposed on the cell separator film 106. The cell gate dicing pattern 160 may extend in a first direction D1. The cell gate dicing pattern 160 may extend in the first direction D1 along the boundary of the first cell 10a, the boundary of the first filled cell 10, and the boundary of the second cell 10b. A gate stack 120 and an insulating gate 150 may be disposed between the cell gate dicing patterns 160 spaced apart from each other in the first direction D1. The cell gate dicing pattern 160 may include, for example, an insulating material.

[0055] The cell gate dicing pattern 160 can be cut at the cell boundary through a region within the gate stack 120. The cell gate dicing pattern 160 can contact the gate stack 120 and the insulating gate 150. The cell gate dicing pattern 160 can contact the ends of the gate stack 120 and the ends of the insulating gate 150, both of which extend in the first direction D1. The first cell 10a, the first filling cell 10, and the second cell 10b may also include the cell gate dicing pattern 160 formed along their respective boundaries extending in the first direction D1.

[0056] The first filling unit 10 may be arranged between the first unit 10a and the second unit 10b. The first unit 10a and the second unit 10b may be adjacent to each other in the first direction D1, with the first filling unit 10 located between them. The boundary between the first filling unit 10 and the first unit 10a extends in the second direction D2, and the boundary between the first filling unit 10 and the second unit 10b also extends in the second direction D2.

[0057] The first filling unit 10 may intersect with the first active region 112 and the second active region 114, and may include two gate stacks 120 that are adjacent to each other in the first direction D1. Each of the gate stacks 120 may be arranged at the boundary of the first filling unit 10 extending in the second direction D2. A separator structure DB may be arranged between the two gate stacks 120 that are adjacent to each other in the first direction D1.

[0058] The partitioned structure DB can at least partially divide the first active region 112 and the second active region 114. (See reference) Figure 4 The partition structure DB can divide the first active region 112U of the first active region 112. Although a portion of the first lower active region 112B of the first active region 112 is shown in the partition structure DB, this is merely an example and this disclosure is not limited thereto.

[0059] The first filler unit 10 may have a pitch dimension in the first direction D1. A pitch dimension may be 1 CPP. In other words, when the first filler unit 10 has a first filler unit boundary and a second filler unit boundary that both extend in the second direction D2, the first filler unit 10 may extend from the first filler unit boundary to the second filler unit boundary across a pitch dimension.

[0060] The first cell 10a may form a boundary with the first fill cell 10. The first fill cell 10 may form a boundary with the first cell 10a located at one of the gate stacks 120 included in the first fill cell 10. Adjacent first cells 10a and first fill cells 10 may share the gate stack 120 at a common boundary. Although Figure 3 The first unit 10a is shown to have a width of 5 CPP, but this is merely an example and the present disclosure is not limited thereto.

[0061] The second cell 10b may form a boundary with the first fill cell 10. The first fill cell 10 may form a boundary with the second cell 10b located at one of the gate stacks 120 included in the first fill cell 10. Adjacent second cells 10b and first fill cells 10 may share the gate stack 120 at a common boundary. Although Figure 3 The second unit 10b is shown to have a width of 5 CPP, but this is merely an example and this disclosure is not limited thereto.

[0062] The first unit 10a may further include a first active region 112 and a second active region 114. The gate stack 120 included in the first unit 10a may intersect with the first active region 112 and the second active region 114. The first unit 10a may include a first p-type transistor 132_1 and a first n-type transistor 134_1, both of which are integrated. The first p-type transistor 132_1 may be formed at the location where the gate stack 120 and the first active region 112 intersect, and the first n-type transistor 134_1 may be formed at the location where the gate stack 120 and the second active region 114 intersect. For example, the first p-type transistor 132_1 may include a main gate 122M, a sub-gate 122S, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0063] The second unit 10b may further include a first active region 112 and a second active region 114. The gate stack 120 included in the second unit 10b may intersect with the first active region 112 and the second active region 114. The second unit 10b may include a second p-type transistor 132_2 and a second n-type transistor 134_2, both of which are integrated. The second p-type transistor 132_2 may be formed at the location where the gate stack 120 and the first active region 112 intersect, and the second n-type transistor 134_2 may be formed at the location where the gate stack 120 and the second active region 114 intersect. For example, the second p-type transistor 132_2 may include a main gate 122M, a sub-gate 122S, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0064] The first p-type transistor 132_1 and the second p-type transistor 132_2 are formed on the first active region 112, and the first n-type transistor 134_1 and the second n-type transistor 134_2 are formed on the second active region 114.

[0065] The first filling cell 10, disposed between the first cell 10a and the second cell 10b, includes two gate stacks 120 and a partition structure DB disposed between the two adjacent gate stacks 120. Because the partition structure DB at least partially divides the first active region 112 and the second active region 114, each of the first active region 112 and the second active region 114 can be divided into at least three portions along the first direction D1. In the first filling cell 10, the partition structure DB can be arranged to extend across the first active region 112 and the second active region 114 between the gate stacks 120 in the second direction D2.

[0066] In some embodiments, the separator structure DB may include a nitride-based material, but this disclosure is not limited thereto. Furthermore, in some embodiments, the separator structure DB may not include oxides.

[0067] Figure 5 This is an integrated circuit layout diagram 2000 used to illustrate an example of integrated circuits. (Reference) Figure 5 The described integrated circuit layout diagram 2000 and reference Figure 3 and Figure 4 The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0068] refer to Figure 5 The second filling unit 20 can be arranged between the first unit 20a and the second unit 20b.

[0069] The first unit 20a may include a second active region 114, the second unit 20b may include a first active region 112, and the second filling unit 20 may include the first active region 112 and the second active region 114.

[0070] Each of the gate stack 120 and the insulating gate 150 may be disposed on the first active region 112 and the second active region 114. The gate stack 120 and the insulating gate 150 may extend across the active region separator 105 located in the first active region 112 and the second active region 114 in a second direction D2. A portion of the gate stack 120 and a portion of the insulating gate 150 may each extend on the cell separator 106.

[0071] The first unit 20a and the second unit 20b may be adjacent to each other in the first direction D1, with the second filling unit 20 located between them. The boundary between the second filling unit 20 and the first unit 20a extends in the second direction D2, and the boundary between the second filling unit 20 and the second unit 20b also extends in the second direction D2.

[0072] The second filling unit 20 may include both the first active region 112 and the second active region 114, and may include the boundary region between the first active region 112 and the second active region 114. Although the boundary between the first active region 112 and the second active region 114 is shown to be arranged at the center of the second filling unit 20, this is merely an example and the present disclosure is not limited thereto.

[0073] The second filling unit 20 may include two gate stacks 120 that are adjacent to each other in the first direction D1. Each of the gate stacks 120 may be disposed at the boundary of the second filling unit 20 extending in the second direction D2. A separator structure DB may be disposed between the two gate stacks 120 that are adjacent to each other in the first direction D1. The separator structure DB may separate the first active region 112 and the second active region 114 from each other at the boundary between the first active region 112 and the second active region 114.

[0074] The first unit 20a may include two second active regions 114. The gate stack 120 included in the first unit 20a may intersect with the two second active regions 114. The first unit 20a may include a first n-type transistor 134_1 and a second n-type transistor 134_2, both of which are integrated. Each of the first n-type transistor 134_1 and the second n-type transistor 134_2 may be formed at the location where the gate stack 120 and the second active region 114 intersect. For example, each of the first n-type transistor 134_1 and the second n-type transistor 134_2 may include a main gate 122M, a sub-gate 122S, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0075] The second unit 20b may include two first active regions 112. The gate stack 120 included in the second unit 20b may intersect with the two first active regions 112. The second unit 20b may include a first p-type transistor 132_1 and a second p-type transistor 132_2, both of which are integrated. Each of the first p-type transistor 132_1 and the second p-type transistor 132_2 may be formed at the location where the gate stack 120 and the first active regions 112 intersect. For example, each of the first p-type transistor 132_1 and the second p-type transistor 132_2 may include a main gate 122M, a sub-gate 122S, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0076] The first p-type transistor 132_1 and the second p-type transistor 132_2 are formed on the first active region 112, and the first n-type transistor 134_1 and the second n-type transistor 134_2 are formed on the second active region 114.

[0077] The second filling cell 20 disposed between the first cell 20a and the second cell 20b may include two gate stacks 120 and a partition structure DB disposed between the two adjacent gate stacks 120. The partition structure DB can separate the first active region 112 and the second active region 114 that are adjacent to each other in the first direction D1. In other words, the partition structure DB can be formed at the boundary of the active regions including transistors of different conductivity types.

[0078] In the second fill cell 20, the separator structure DB can be arranged to extend in a second direction D2 across the first active region 112 and the second active region 114 between the two gate stacks 120. The gate stack 120 arranged at the boundary between the first cell 20a and the second fill cell 20 extends in the second active region 114 along the second direction D2, while the gate stack 120 arranged at the boundary between the second cell 20b and the second fill cell 20 extends in the first active region 112 along the second direction D2.

[0079] Figure 6 This is an integrated circuit layout diagram 3000 used to illustrate an example of an integrated circuit. (Reference) Figure 6 The described integrated circuit layout diagram 3000 and reference Figure 3 and Figure 4 The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0080] refer to Figure 6 The integrated circuit may include a first unit 30a, a second unit 30b, a third unit 30c, a fourth unit 30d, and a third filling unit 30.

[0081] Each of the first unit 30a, the second unit 30b, the third unit 30c, and the fourth unit 30d may have a width of 5 CPP in the first direction D1, and the third filling unit 30 may have a width of 1 CPP in the first direction D1. When each of the first unit 30a, the second unit 30b, the third unit 30c, and the fourth unit 30d has a height of H in the second direction D2, the third filling unit 30 may have a height of 2H.

[0082] The third filling unit 30 may be arranged between the first unit 30a and the second unit 30b and between the third unit 30c and the fourth unit 30d, and the third filling unit 30 may include a partition structure DB extending along the second direction D2 between the two gate stacks 120.

[0083] The first unit 30a and the third unit 30c can be adjacent to each other in the second direction D2, the second unit 30b and the fourth unit 30d can be adjacent to each other in the second direction D2, and the third filling unit 30 can be adjacent to the first unit 30a, the second unit 30b, the third unit 30c and the fourth unit 30d in the first direction D1.

[0084] The cell gate dicing pattern 160 can be arranged between the first cell 30a and the third cell 30c, and between the second cell 30b and the fourth cell 30d, and can additionally be arranged at the boundaries connecting the first cell 30a, the third fill cell 30, and the second cell 30b, and at the boundaries connecting the third cell 30c, the third fill cell 30, and the fourth cell 30d. The cell gate dicing pattern 160 arranged between the first cell 30a and the third cell 30c, and between the second cell 30b and the fourth cell 30d, may not extend into the third fill cell 30.

[0085] Each of the first unit 30a, the second unit 30b, the third unit 30c, and the fourth unit 30d includes a p-type transistor and an n-type transistor formed on the first active region 112 and the second active region 114. Specifically, the first unit 30a may include a first p-type transistor 132_1 located on the first active region 112 and a first n-type transistor 134_1 located on the second active region 114; the second unit 30b may include a second p-type transistor 132_2 located on the first active region 112 and a second n-type transistor 134_2 located on the second active region 114; the third unit 30c may include a third p-type transistor 132_3 located on the first active region 112 and a third n-type transistor 134_3 located on the second active region 114; and the fourth unit 30d may include a fourth p-type transistor 132_4 located on the first active region 112 and a fourth n-type transistor 134_4 located on the second active region 114.

[0086] The partition structure DB included in the third filling unit 30 may have a greater height in the second direction D2 than the height of each of the first unit 30a, second unit 30b, third unit 30c, and fourth unit 30d, and may extend in the second direction D2. The partition structure DB may extend across the two first active regions 112 and the two second active regions 114, and may at least partially divide each active region. The third filling unit 30 is adjacent to a total of four units, and... Figure 3 Integrated circuit layout diagram 1000 and Figure 5 Unlike the 2000 integrated circuit layout diagram, three or more units can be divided by a partition structure DB.

[0087] Figure 7 This is an integrated circuit layout diagram 4000 used to illustrate an example of an integrated circuit. (Reference) Figure 7 The described integrated circuit layout diagram 4000 and reference Figure 3 and Figure 4 The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0088] refer to Figure 7 The integrated circuit may include a first unit 40a, a second unit 40b, a third unit 40c, a fourth unit 40d, and a fourth filling unit 40.

[0089] The arrangement of the first unit 40a, the second unit 40b, the third unit 40c, the fourth unit 40d, the fourth filling unit 40, and the unit gate dicing pattern 160 is similar to... Figure 6 The arrangement relationship of the first unit 30a, the second unit 30b, the third unit 30c, the fourth unit 30d, the third filling unit 30, and the unit gate cutting pattern 160 will be omitted, and therefore its description will be omitted.

[0090] Each of the first unit 40a and the third unit 40c includes a p-type transistor formed on the first active region 112 and an n-type transistor formed on the second active region 114. The second unit 40b includes an n-type transistor formed on the second active region 114, and the fourth unit 40d includes a p-type transistor formed on the first active region 112. Specifically, the first unit 40a may include a first p-type transistor 132_1 located on the first active region 112 and a first n-type transistor 134_1 located on the second active region 114, and the third unit 40c may include a second p-type transistor 132_2 located on the first active region 112 and a fourth n-type transistor 134_4 located on the second active region 114. The second unit 40b may include a second n-type transistor 134_2 and a third n-type transistor 134_3 located on the second active region 114, and the fourth unit 40d may include a third p-type transistor 132_3 and a fourth p-type transistor 132_4 located on the first active region 112.

[0091] The partition structure DB included in the fourth filling unit 40 may have a greater height in the second direction D2 than the height of each of the first unit 40a, second unit 40b, third unit 40c, and fourth unit 40d, and may extend in the second direction D2. The partition structure DB may extend across both boundaries of the first active region 112 and the second active region 114. This is similar to the third filling unit 30 crossing the mutually spaced-apart first active region 112 and second active region 114 (see...). Figure 6 In contrast, the fourth filling unit 40 can separate the first active region 112 and the second active region 114 that are adjacent to each other in the first direction D1. In other words, the separating structure DB can be formed at the boundary of the active regions including transistors of different conductivity types. Although not shown in the accompanying drawings of this specification, in Figure 7 In the integrated circuit layout 4000, well-tap cells can be arranged in the second cell 40b and / or the fourth cell 40d. In some embodiments, well-tap cells can mitigate latch-up problems in MOSFETs caused by coupling effects. Even when one or more well-tap cells are included in the integrated circuit layout, fill cells according to this disclosure can be applied while maintaining a width of 1 CPP, thereby increasing the integration density of the integrated circuit shown in the layout.

[0092] Figure 8 This is an integrated circuit layout diagram 5000 used to illustrate an example of an integrated circuit. (Reference) Figure 8 The described integrated circuit layout diagram 5000 and reference Figure 3 and Figure 4 The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0093] refer to Figure 8 The integrated circuit may include a first unit 50a, a second unit 50b, a third unit 50c, a fourth unit 50d, and a fifth filling unit 50.

[0094] The arrangement of the first unit 50a, the second unit 50b, the third unit 50c, the fourth unit 50d, the fifth filling unit 50, and the unit gate dicing pattern 160 is similar to... Figure 6 The arrangement relationship of the first unit 30a, the second unit 30b, the third unit 30c, the fourth unit 30d, the third filling unit 30, and the unit gate cutting pattern 160 will be omitted, and therefore its description will be omitted.

[0095] Each of the first unit 50a and the fourth unit 50d includes an n-type transistor formed on the second active region 114, and each of the second unit 50b and the third unit 50c includes a p-type transistor formed on the first active region 112. Specifically, the first unit 50a may include a first n-type transistor 134_1 and a second n-type transistor 134_2 located on the second active region 114, and the fourth unit 50d may include a third n-type transistor 134_3 and a fourth n-type transistor 134_4 located on the second active region 114. The second unit 50b may include a first p-type transistor 132_1 and a second p-type transistor 132_2 located on the first active region 112, and the third unit 50c may include a third p-type transistor 132_3 and a fourth p-type transistor 132_4 located on the first active region 112.

[0096] The partition structure DB included in the fifth filling unit 50 may have a greater height in the second direction D2 than the height of each of the first unit 50a, the second unit 50b, the third unit 50c, and the fourth unit 50d, and may extend in the second direction D2. The partition structure DB may extend across both boundaries of the first active region 112 and the second active region 114. The third filling unit 30 crosses the first active region 112 and the second active region 114, which are spaced apart from each other (see...). Figure 6 In contrast, the fifth filling unit 50 can separate the first active region 112 and the second active region 114 that are adjacent to each other in the first direction D1. In other words, the separating structure DB can be formed at the boundary of the active regions including transistors of different conductivity types.

[0097] Figure 9 This is an integrated circuit layout diagram 6000 used to illustrate an example of an integrated circuit. (Reference) Figure 9 The described integrated circuit layout diagram 6000 and reference Figure 3 and Figure 4 The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0098] refer to Figure 9 The integrated circuit may include a first unit 60a, a second unit 60b, a third unit 60c, and a sixth filling unit 60.

[0099] Each of the first unit 60a, the second unit 60b, and the third unit 60c may have a width of 5 CPP in the first direction D1, and the sixth filling unit 60 may have a width of 1 CPP in the first direction D1. When each of the first unit 60a and the third unit 60c has a height of H in the second direction D2, each of the second unit 60b and the sixth filling unit 60 may have a height of 2H.

[0100] The second cell 60b can not only have a larger cell height than the first cell 60a and the third cell 60c, but can also be formed by connecting identical active regions to each other in the second direction D2. Specifically, the second cell 60b may include two second active regions 114 and a first active region 112 with a width twice the width of the second active regions 114, instead of a dual-height cell DHC including a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2 (see [link to DHC]). Figure 2 That includes two first active regions 112 and two second active regions 114.

[0101] The sixth filling unit 60 may be arranged between the first unit 60a and the second unit 60b and between the third unit 60c and the second unit 60b, and the sixth filling unit 60 may include a partition structure DB extending along the second direction D2 between the two gate stacks 120.

[0102] The first unit 60a and the third unit 60c may be adjacent to each other in the second direction D2, and the sixth filling unit 60 may be adjacent to each of the first unit 60a, the second unit 60b and the third unit 60c in the first direction D1.

[0103] The cell gate dicing pattern 160 may be arranged between the first cell 60a and the third cell 60c, and may additionally be arranged at the boundaries connecting the first cell 60a, the sixth fill cell 60, and the second cell 60b, as well as at the boundaries connecting the third cell 60c, the sixth fill cell 60, and the second cell 60b. The cell gate dicing pattern 160 arranged between the first cell 60a and the third cell 60c may not extend into the sixth fill cell 60.

[0104] Each of the first unit 60a, the second unit 60b, and the third unit 60c may include a p-type transistor and an n-type transistor formed on the first active region 112 and the second active region 114. Specifically, the first unit 60a may include a first p-type transistor 132_1 located on the first active region 112 and a first n-type transistor 134_1 located on the second active region 114; the second unit 60b may include a second n-type transistor 134_2 and a third n-type transistor 134_3 located on the second active region 114, and a second p-type transistor 132_2 located on the first active region 112, which has a relatively larger width; and the third unit 60c may include a third p-type transistor 132_3 located on the first active region 112 and a fourth n-type transistor 134_4 located on the second active region 114.

[0105] The partition structure DB included in the sixth filling unit 60 may have a greater height in the second direction D2 than the height of each of the first unit 60a and the third unit 60c, and may extend in the second direction D2. The partition structure DB may extend across multiple first active regions 112 and second active regions 114, and may at least partially divide each active region. In particular, the sixth filling unit 60 may be arranged while maintaining a width of 1 CPP, even between units with different active region widths.

[0106] In the case of cells with different active region widths, the second cell 60b may be included in the cell adjacent to the adjacent cell (e.g., in...). Figure 9 In the case of the first element 60a and the third element 60c), at least one portion of the active region width changes at the boundary, and there are two 90-degree bends (or jogs) at each portion of the active region width change. In this case, a dummy element with a larger area may be required compared to elements with the same active region width that are adjacent to each other side by side in the first direction D1 and the second direction D2. However, as Figure 9 As shown in the integrated circuit layout diagram 6000, even when cells with different active region widths are adjacent to each other, adjacent active regions can be separated from each other using only a single dummy cell with a width of 1 CPP, thereby contributing to the improvement of the integration density of the integrated circuit.

[0107] Figure 10 This is an integrated circuit layout diagram 7000 used to illustrate an example of an integrated circuit. (Reference) Figure 10 The described integrated circuit layout diagram 7000 and reference Figure 3 and Figure 4The integrated circuit layout diagram 1000 described herein is not mutually exclusive, and it will be understood that elements with the same reference numerals refer to the same elements. In the following text, redundant descriptions of identical components may be simplified or omitted, and the main focus will be on... Figure 3 and Figure 4 The difference in the integrated circuit layout diagram 1000.

[0108] refer to Figure 10 The integrated circuit may include a first unit 70a, a second unit 70b, a third unit 70c, a fourth unit 70d, and a seventh filling unit 70.

[0109] Each of the first unit 70a, the second unit 70b, the third unit 70c, and the fourth unit 70d may have a width of 5 CPP in the first direction D1, and the seventh filling unit 70 may have a width of 1 CPP in the first direction D1. When each of the first unit 70a, the second unit 70b, and the third unit 70c has a height of H in the second direction D2, each of the fourth unit 70d and the seventh filling unit 70 may have a height of 3H.

[0110] The seventh filler cell 70 may be arranged between the first cell 70a and the fourth cell 70d, between the second cell 70b and the fourth cell 70d, and between the third cell 70c and the fourth cell 70d, and the seventh filler cell 70 may include a partition structure DB extending along the second direction D2 between the two gate stacks 120.

[0111] The first unit 70a and the second unit 70b can be adjacent to each other in the second direction D2, the second unit 70b and the third unit 70c can be adjacent to each other in the second direction D2, and the seventh filling unit 70 can be adjacent to the first unit 70a, the second unit 70b, the third unit 70c and the fourth unit 70d in the first direction D1.

[0112] The cell gate dicing pattern 160 can be arranged between the first cell 70a and the second cell 70b, and between the second cell 70b and the third cell 70c. It can also be additionally arranged at the boundaries connecting the first cell 70a, the seventh fill cell 70, and the fourth cell 70d, and at the boundaries connecting the third cell 70c, the seventh fill cell 70, and the fourth cell 70d. The cell gate dicing pattern 160 arranged between the first cell 70a and the second cell 70b, and between the second cell 70b and the third cell 70c, may not extend into the seventh fill cell 70.

[0113] The fourth unit 70d can not only have a larger unit height than the first unit 70a, the second unit 70b, and the third unit 70c, but can also be formed by connecting two identical active regions to each other in the second direction D2. Specifically, the fourth unit 70d does not include three first active regions 112 and three second active regions 114, but rather includes two first active regions 112 and two second active regions 114. Furthermore, the width of one of the two first active regions 112 in the second direction D2 can be twice the width of the other of the two first active regions 112 in the second direction D2, and the width of one of the two second active regions 114 in the second direction D2 can be twice the width of the other of the two second active regions 114 in the second direction D2.

[0114] Each of the first unit 70a, the second unit 70b, the third unit 70c, and the fourth unit 70d may include a p-type transistor and an n-type transistor formed on the first active region 112 and the second active region 114. Specifically, the first unit 70a may include a first p-type transistor 132_1 located on the first active region 112 and a first n-type transistor 134_1 located on the second active region 114; the second unit 70b may include a second p-type transistor 132_2 located on the first active region 112 and a second n-type transistor 134_2 located on the second active region 114; and the third unit 70c may include a third p-type transistor 132_3 located on the first active region 112 and a third n-type transistor 134_3 located on the second active region 114. The fourth unit 70d may include: a fourth p-type transistor 132_4 located on a first active region 112 having a relatively larger width; a fifth p-type transistor 132_5 located on a first active region 112 having the same width as the first active region 112 in each of the first units 70a, the second unit 70b, and the third unit 70c; a fourth n-type transistor 134_4 located on a second active region 114 having a relatively larger width; and a fifth n-type transistor 134_5 located on a second active region 114 having a relatively larger width.

[0115] The partition structure DB included in the seventh filling unit 70 may have a greater height in the second direction D2 than the height of each of the first unit 70a, the second unit 70b, and the third unit 70c in the second direction D2, and may extend in the second direction D2. The partition structure DB may extend across multiple first active regions 112 and multiple second active regions 114, and may at least partially divide each active region. In particular, the seventh filling unit 70 can be arranged while maintaining a 1 CPP width, even when multiple portions with different active region widths are included.

[0116] Similar to Figure 9Unit 2, 60b Figure 10 The fourth unit 70d can be connected with adjacent units (e.g., in...) Figure 10 In this case, the active region width changes at the boundaries of the first unit 70a, the second unit 70b, and the third unit 70c, where there is a 90-degree bend. In this situation, compared to units with the same active region width arranged side-by-side adjacent to each other in the first direction D1 and the second direction D2 as described above, a dummy unit with a larger area may be required, but reference... Figure 10 The integrated circuit layout diagram 7000, even when including cells with two different active region widths, can separate adjacent active regions from each other using only a single dummy cell with a width of 1 CPP, thereby contributing to the improvement of the integration density of the integrated circuit.

[0117] Figure 11 This is an example of an integrated circuit layout diagram 7000' used to illustrate an integrated circuit. Except for the height of the seventh fill cell 70 in the second direction D2, which is... Figure 10 Besides the differences, refer to Figure 11 The described integrated circuit layout diagram 7000' can be compared with the reference. Figure 10 The integrated circuit layout diagram 7000 described is the same. Therefore, in the following text, the description of the first cell 70a, the second cell 70b, the third cell 70c, and the fourth cell 70d is omitted, and the seventh filling cell 70 will be described in detail.

[0118] refer to Figure 11 The two ends of the seventh filling unit 70 may be different. Figure 10 It extends to the two ends of the layout diagram in the second direction D2, as shown in the middle. Figure 11 The first active region 112, located at the lowest end, can extend along the first direction D1 across the third unit 70c and the fourth unit 70d without changing its conductivity type. Similarly, Figure 11 The second active region 114, located at the uppermost end, can extend along the first direction D1 across the first unit 70a and the fourth unit 70d without changing its conductivity type. Even when units with different active region widths are adjacent to each other, active regions with the same conductivity type and the same width can extend along the first direction D1 in at least some regions, and therefore, the seventh filling unit 70 may not extend into said at least some regions. Instead, the first additional unit 70' and the second additional unit 70" can be arranged in said at least some regions.

[0119] Figure 11 Only an example is shown, and therefore, either a first additional unit 70' or a second additional unit 70" can be formed. The configuration of the first additional unit 70' and the second additional unit 70" is not limited to this specification, and as such... Figure 11As shown in the integrated circuit layout diagram 7000', additional cells can be formed in the remaining space by flexibly adjusting the length of the seventh filling cell 70 in the second direction D2, thereby providing freedom for integrated circuit design.

[0120] While this specification contains numerous specific details of implementation, these details should not be construed as limiting the scope of any invention or any claimable scope, but rather as descriptions of features specific to particular embodiments of the invention. Certain features described in this specification within the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0121] Although this disclosure has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, the integrated circuit comprising: The first unit includes a first active region and a second active region; The second unit includes a third active region and a fourth active region; and A filling unit is located between the first unit and the second unit, and is adjacent to the first unit and the second unit in a first direction. The filling unit has a pitch dimension. The filling unit includes: A first gate stack and a second gate stack, the first gate stack and the second gate stack being adjacent to each other in the first direction; and A partition structure is located between the first gate stack and the second gate stack, wherein the partition structure at least partially divides the first active region, the second active region, the third active region and the fourth active region.

2. The integrated circuit according to claim 1, wherein, The separation structure comprises a nitride-based material.

3. The integrated circuit according to claim 1, wherein The first boundary between the filling unit and the first unit extends in a second direction intersecting the first direction. The second boundary between the filling unit and the second unit extends in the second direction. The first gate stack is located at the first boundary, and The second gate stack is located at the second boundary.

4. The integrated circuit according to claim 1, wherein The first unit includes a first plurality of gate stacks, which extend from the first active region to the second active region along a second direction intersecting the first direction. The second unit includes a second plurality of gate stacks extending from the third active region to the fourth active region along the second direction. The first plurality of gate stacks are spaced apart from the first gate stack and the second gate stack in the first direction, and The second plurality of gate stacks are spaced apart from the first gate stack and the second gate stack in the first direction.

5. The integrated circuit according to claim 1, wherein the integrated circuit includes a cell gate dicing pattern extending along the boundary of the first cell, the boundary of the filling cell, and the boundary of the second cell.

6. The integrated circuit according to claim 1, wherein, The separation structure does not contain oxides.

7. The integrated circuit according to claim 1, further comprising: p-type transistor, wherein the p-type transistor is located on the first active region; and An n-type transistor is located on the second active region.

8. An integrated circuit, the integrated circuit comprising: A first unit, the first unit including a first integrated transistor; The second unit includes a second integrated transistor; A filling unit is located between the first unit and the second unit and is adjacent to the first unit and the second unit in a first direction, the filling unit having a pitch dimension; and A plurality of gate stacks extending in a second direction intersecting the first direction and spaced apart from each other in the first direction. The filling unit includes: Two adjacent gate stacks among the plurality of gate stacks; and A separator structure, the separator structure being located between the two gate stacks and extending in the second direction, and Wherein, the first semiconductor pattern in the first unit and the second semiconductor pattern in the second unit are doped with impurities of different conductivity types, the first semiconductor pattern is adjacent to the first sidewall of the partition structure, and the second semiconductor pattern is adjacent to the second sidewall of the partition structure opposite to the first sidewall.

9. The integrated circuit according to claim 8, wherein, The separation structure comprises a nitride-based material.

10. The integrated circuit according to claim 8, wherein, The first unit includes a first active region and a p-type transistor located on the first active region, and the second unit includes a second active region and an n-type transistor located on the second active region.

11. The integrated circuit of claim 8, further comprising a cell gate dicing pattern extending along the boundary of the first cell, the boundary of the filling cell, and the boundary of the second cell.

12. The integrated circuit according to claim 8, wherein, The separation structure does not contain oxides.

13. An integrated circuit, the integrated circuit comprising: A filling unit having a pitch dimension and including a first sidewall and a second sidewall opposite to the first sidewall; The first unit and the third unit are adjacent to the first sidewall of the filling unit; The second unit is adjacent to the second sidewall of the filling unit; and A plurality of gate stacks, the plurality of gate stacks being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction. The filling unit includes: Two adjacent gate stacks among the plurality of gate stacks; and A separator structure is located between the two gate stacks and extends in the second direction. Wherein, the height of the filling unit in the second direction is twice the height of the first unit in the second direction and twice the height of the third unit in the second direction, and the height of the second unit in the second direction is twice the height of the first unit in the second direction and twice the height of the third unit in the second direction. The first unit and the third unit include a plurality of active regions having a first width in the second direction, and The second unit includes a plurality of first active regions and a second active region, each of the plurality of first active regions having a first width in the second direction, and the second active region having a second width that is twice the first width.

14. The integrated circuit according to claim 13, wherein, The separation structure comprises a nitride-based material.

15. The integrated circuit of claim 13, further comprising a cell gate dicing pattern located at the boundary between the first cell and the third cell, wherein, The cell gate dicing pattern does not extend into the filling cell.

16. The integrated circuit according to claim 13, wherein, The partition structure includes a first sidewall and a second sidewall opposite to the first sidewall, and The first active region adjacent to the first sidewall of the partition structure and the second active region adjacent to the second sidewall of the partition structure have different widths in at least some regions.

17. The integrated circuit according to claim 16, wherein, The first semiconductor pattern adjacent to the first sidewall of the partition structure and the second semiconductor pattern adjacent to the second sidewall of the partition structure are doped with impurities of the same conductivity type.

18. The integrated circuit according to claim 13, wherein, The separation structure does not contain oxides.

19. The integrated circuit according to claim 13, wherein, The height of the partition structure in the second direction is greater than the height of the first unit in the second direction and greater than the height of the third unit in the second direction.

20. The integrated circuit according to claim 13, wherein, The p-type transistor is located on the plurality of first active regions, and the n-type transistor is located on the second active region.

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