Display device and electronic device

Abstract

A display device and an electronic apparatus including the same are disclosed. The display device can include a substrate, a plurality of transistors, a plurality of light emitting diodes, an encapsulation layer disposed on the plurality of light emitting diodes and including a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer, a plurality of inorganic insulation layers, a partition wall, a concavo-convex structure disposed between the partition wall and an edge of the substrate, defined in the plurality of inorganic insulation layers, and including a plurality of protrusions and a groove between two adjacent protrusions, and a cover bank layer on the concavo-convex structure, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer extend on the cover bank layer and directly contact each other on the cover bank layer while being separated from the edge of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0177901, filed on December 3, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display device and an electronic device including the display device. Background Technology

[0004] Recently, display devices have been used in electronic devices for one or more suitable purposes. As the application of display devices expands, the demand for or expectation of high-quality display devices with excellent durability and various shapes is also increasing. Summary of the Invention

[0005] During the manufacturing process and / or during use after manufacturing, internal cracks and other defects may easily develop due to external impacts.

[0006] One or more aspects of the embodiments of this disclosure are directed to a display device robust against external shocks and an electronic device including the display device. However, such technical aspects and / or features are merely examples, and the embodiments of this disclosure are not limited thereto.

[0007] Additional aspects of the embodiments will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area outside the display area; a plurality of transistors disposed in the display area of ​​the substrate; a plurality of light-emitting diodes disposed in the display area of ​​the substrate and electrically connected to the plurality of transistors; an encapsulation layer disposed on the plurality of light-emitting diodes and including a first inorganic encapsulation layer, a second inorganic encapsulation layer above the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer; a plurality of inorganic insulating (e.g., electrically insulating) layers disposed in the peripheral area of ​​the substrate and separated from the edge of the substrate; a partition wall disposed in the peripheral area of ​​the substrate; a bump structure located or disposed between the partition wall and the edge of the substrate, defined in the plurality of inorganic insulating layers, and including a plurality of protrusions and a groove between two adjacent protrusions among the plurality of protrusions; and a cover dam layer on the bump structure, wherein the edge of the organic encapsulation layer is located or disposed on one side of the partition wall, and each of the first and second inorganic encapsulation layers extends on the cover dam layer and is separated from the edge of the substrate (e.g., spaced apart).

[0009] The edge of the second inorganic encapsulation layer may be located or arranged between the edge of the first inorganic encapsulation layer and the edge of the substrate.

[0010] The edges of the first inorganic encapsulation layer and the edges of the second inorganic encapsulation layer can be aligned substantially on the same line.

[0011] The first inorganic encapsulation layer can be in direct contact with the second inorganic encapsulation layer on the cover layer.

[0012] The plurality of inorganic insulating layers may include a buffer layer disposed between the substrate and the semiconductor layer of each of the plurality of transistors, and the edges of the buffer layer may be separated from the edges of the substrate (e.g., spaced apart).

[0013] The bottom surface of the groove can correspond to the top surface of the buffer layer.

[0014] The bottom surface of the groove can correspond to the top surface of the substrate.

[0015] The substrate may include: a first polymer resin layer; a first inorganic isolation layer on the first polymer resin layer; a second polymer resin layer on the first inorganic isolation layer; and a second inorganic isolation layer on the second polymer resin layer, wherein the edge of the substrate may be defined by an edge of at least one selected from the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer, and wherein the edge of the second inorganic isolation layer may be separated (e.g., spaced apart) from an edge of at least one selected from the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer.

[0016] The groove can extend to the second inorganic isolation layer.

[0017] According to one or more embodiments, an electronic device includes: a display device including a display area and a peripheral area; and a lower cover forming an appearance, the lower cover including an opening in its front surface that exposes a portion of the display device, and the lower cover overlapping the peripheral area of ​​the display device, wherein the display device includes: a substrate; a plurality of transistors disposed on the substrate corresponding to the display area; a plurality of light-emitting diodes disposed on the substrate corresponding to the display area and electrically connected to the plurality of transistors; an encapsulation layer disposed on the plurality of light-emitting diodes and including a first inorganic encapsulation layer, a second inorganic encapsulation layer above the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer; and a plurality of inorganic insulators (e.g., electrical insulators). A layer, disposed on a substrate to correspond to a peripheral region and separated from the edge of the substrate (e.g., spaced apart); a partition wall, disposed on the substrate to correspond to the peripheral region; a relief structure, located or disposed between the partition wall and the edge of the substrate, defined in a plurality of inorganic insulating layers, and including a plurality of protrusions and a groove between two adjacent protrusions among the plurality of protrusions; and a cover dam layer on the relief structure, wherein the edge of the organic encapsulation layer is located or disposed on one side of the partition wall, and each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends on the cover dam layer, and the edges of the first inorganic substrate layer and the second inorganic substrate layer are separated from the edge of the substrate (e.g., spaced apart), and wherein a portion of the area of ​​the substrate corresponding to the peripheral region is bent to have curvature.

[0018] The edge of the second inorganic encapsulation layer may be located or arranged between the edge of the first inorganic encapsulation layer and the edge of the substrate.

[0019] The edges of the first inorganic encapsulation layer and the edges of the second inorganic encapsulation layer can be aligned substantially on the same line.

[0020] The first inorganic encapsulation layer can be in direct contact with the second inorganic encapsulation layer on the cover layer.

[0021] The plurality of inorganic insulating layers may include a buffer layer disposed between the substrate and the semiconductor layer of each of the plurality of transistors, and the edges of the buffer layer may be separated from the edges of the substrate (e.g., spaced apart).

[0022] The bottom surface of the groove can correspond to the top surface of the buffer layer.

[0023] The bottom surface of the groove can correspond to the top surface of the substrate.

[0024] The substrate may include: a first polymer resin layer; a first inorganic isolation layer on the first polymer resin layer; a second polymer resin layer on the first inorganic isolation layer; and a second inorganic isolation layer on the second polymer resin layer, wherein the edge of the substrate may be defined by an edge of at least one selected from the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer, and wherein the edge of the second inorganic isolation layer may be separated (e.g., spaced apart) from an edge of at least one selected from the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer.

[0025] The edges of the second inorganic encapsulation layer and the second inorganic isolation layer can be aligned substantially on the same line.

[0026] The groove can extend to the second inorganic isolation layer. Attached Figure Description

[0027] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 It is a perspective view of an electronic device according to one or more embodiments;

[0029] Figure 2 It is an exploded perspective view of an electronic device according to one or more embodiments;

[0030] Figure 3 It is a block diagram of an electronic device according to one or more embodiments;

[0031] Figure 4 This is a schematic plan view of a display device according to one or more embodiments;

[0032] Figure 5 and Figure 6 This is a schematic side view of a display device according to one or more embodiments;

[0033] Figure 7 This is a schematic cross-sectional view of a display device according to one or more embodiments;

[0034] Figure 8 It is a plan view of the raised and recessed structure of the display device and the cover layer according to one or more embodiments;

[0035] Figure 9 This is a schematic side view of the display device and the lower cover portion as an electronic device according to one or more embodiments;

[0036] Figures 10A to 10C Each is a cross-sectional view of the concave-convex structure and the covering layer of a display device according to one or more embodiments;

[0037] Figure 11 This is a schematic cross-sectional view of a display device according to one or more embodiments;

[0038] Figures 12A to 12C Each is a cross-sectional view of the concave-convex structure and the covering layer of a display device according to one or more embodiments;

[0039] Figure 13A and Figure 13B This is a cross-sectional view illustrating the manufacturing process of a display device according to one or more embodiments;

[0040] Figure 14A and Figure 14B This is a cross-sectional view illustrating the manufacturing process of a display device according to one or more embodiments; and

[0041] Figure 15 It is a perspective view of an electronic device employing a display device according to one or more embodiments. Detailed Implementation

[0042] Reference will be made in more detail to one or more embodiments illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout the accompanying drawings and the written description, and such repeated descriptions of these elements may not be provided in this specification. In this regard, the subject matter of this disclosure may be embodied in different forms and should not be construed as limited to the one or more embodiments set forth herein. Rather, these embodiments are provided by way of example to explain aspects and features of this disclosure to those skilled in the art by reference to the accompanying drawings.

[0043] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items.

[0044] In describing embodiments of this disclosure, the word "may" refers to "one or more embodiments of this disclosure".

[0045] In the context of this application and unless otherwise specified, the terms “use”, “used” and “used” may be regarded as synonyms with the terms “utilization”, “utilized” and “utilized”, respectively.

[0046] Throughout this disclosure, the expression “at least one of a, b and c” or “at least one selected from a, b and c” means only a, only b, only c, both a and b (e.g., both a and b), both a and c (e.g., both a and c), both b and c (e.g., both b and c), all a, b and c, or variations thereof.

[0047] Because this disclosure allows for one or more suitable modifications to the disclosed subject matter and embodiments, certain embodiments will be illustrated in the accompanying drawings and described in more detail in the written description. Aspects, effects, and / or embodiments of this disclosure, as well as methods of implementing them, will be illustrated with reference to one or more embodiments described in more detail below and the accompanying drawings. However, this disclosure is not limited to the disclosed embodiments and may be embodied in one or more suitable forms.

[0048] While terms such as “first” and / or “second” may be used to describe one or more suitable elements, these elements are not necessarily limited by the aforementioned terms. The aforementioned terms are used to distinguish one element from another.

[0049] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” used in this document are intended to include the plural forms as well.

[0050] It will be understood that the terms “having,” “comprising,” “including,” and / or “including” as used herein specify the presence of a described feature or element, but do not preclude the addition of one or more other features or elements. For example, it should be understood that the terms “comprising / including,” “including / including,” or “having / having” specify the presence of a described feature, integral, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising / including,” “including / including,” “having / having,” or similar terms include or support the terms “consisting of” and “essentially composed of,” used to indicate the presence of a described feature, integral, step, operation, element, and / or component without or essentially without other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0051] It will be further understood that if (for example, when) a layer, area, or element is referred to as being "on" another layer, area, or element, it can be directly or indirectly on that other layer, area, or element. For example, an intervening layer, area, or element may exist between them. Conversely, if (for example, when) a layer, area, or element is referred to as being "directly on" another layer, area, or element, an intervening layer, area, or element may not exist between them.

[0052] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. As an example, for ease of description, the dimensions and thickness of each element shown in the drawings may be arbitrarily represented, and therefore, the embodiments of this disclosure are not necessarily limited thereto.

[0053] In cases where a particular embodiment can be implemented differently, the specific processing order can be executed in a different order than that described. As an example, two processes described consecutively can be executed substantially synchronously (e.g., simultaneously) or in reverse order.

[0054] It will be understood that if (for example, when) a layer, area, or component is referred to as being “connected” to another layer, area, or component, it can be “directly connected” to that other layer, area, or component, or it can be “indirectly connected” to that other layer, area, or component with other layers, areas, or components arranged between them. For example, it will be understood that if (for example, when) a layer, area, or element is referred to as being “electrically connected” to another layer, area, or element, it can be “directly electrically connected” to that other layer, area, or element, or it can be “indirectly electrically connected” to that other layer, area, or element with other layers, areas, or elements arranged between them.

[0055] Figure 1 This is a perspective view of an electronic device 1 according to one or more embodiments. Figure 2 This is an exploded perspective view of an electronic device 1 according to one or more embodiments, and Figure 3 This is a block diagram of an electronic device 1 according to one or more embodiments.

[0056] refer to Figure 1 and Figure 2 An electronic device 1 according to one or more embodiments can display moving images and / or still images. The electronic device 1 according to one or more embodiments may include a cover window 70, a display device 10, a data driver 20, a display circuit board 30, a bracket 60, a main circuit board 50 (including component 40), a battery 80, and a lower cover 90.

[0057] In the plan view of this specification, "left", "right", "up" and "down" indicate the direction when (e.g., when) the display device 10 is viewed from a direction normal to (e.g., perpendicular to) the display device 10. As an example, "left" represents the -x direction, "right" represents the +x direction, "up" represents the +y direction, and "down" represents the -y direction.

[0058] Electronic device 1 can have a rectangular shape (e.g., essentially a rectangular shape) in a plan view. For example, as... Figure 1As illustrated, electronic device 1 in a planar view can have a quadrilateral shape (e.g., a substantially quadrilateral shape) having a shorter side in the x-direction and a longer side in the y-direction. The corner where the shorter side in the x-direction intersects the longer side in the y-direction can be rounded with a preset (e.g., set or predetermined) curvature, or formed to have a right angle. The planar shape of electronic device 1 (e.g., a substantially planar shape) is not limited to a rectangle (e.g., a substantially rectangular shape), but can be other polygons (e.g., substantially polygonal), ellipses (e.g., substantially elliptical), or irregular shapes.

[0059] A cover window 70 can be arranged on the display device 10 to cover the upper surface of the display device 10. Accordingly, the cover window 70 can be used to protect the upper surface of the display device 10.

[0060] The cover window 70 may include a transmissive cover portion DA 70 and a light-blocking cover portion NDA 70, wherein the transmissive cover portion DA 70 corresponds to the display area DA of the display device 10, and the light-blocking cover portion NDA 70 surrounds (e.g., encloses) the transmissive cover portion DA 70. The light-blocking cover portion NDA 70 may include an opaque material (e.g., a colored opaque material) that blocks light. The light-blocking cover portion NDA 70 may overlap with the peripheral area PA of the display device 10.

[0061] Display device 10 may be arranged below cover window 70. Display device 10 may include display area DA and peripheral area PA outside display area DA. Display area DA may be an area in which an image is displayed. In one or more embodiments, display area DA may include an area (hereinafter referred to as component area) through which light emitted from component 40 arranged below display device 10 is transmitted. Component 40 may include sensors and cameras for using visible light, infrared light and / or sound, etc.

[0062] Display device 10 may be a light-emitting display device including light-emitting diodes (LEDs). The LED may include an organic light-emitting diode containing an organic emitting layer. The LED may also be an inorganic light-emitting diode containing inorganic materials. An inorganic light-emitting diode may include a PN diode (or pn diode, or pn junction diode) containing inorganic semiconductor materials. If a forward voltage is applied to a PN junction diode (e.g., when), holes and electrons can be injected, and the energy generated by the recombination of holes and electrons can be converted into light energy, thus emitting light of a preset (e.g., set or predetermined) color. Inorganic LEDs may have a width ranging from a few micrometers to several hundred micrometers. In one or more embodiments, the inorganic LED may be represented by a micro LED.

[0063] The display device 10 can be a rigid display device or a flexible display device that is easy to bend. In one or more embodiments, the display device 10 can be assembled between the cover window 70 and the lower cover 90, and a portion of the peripheral region PA is bent. For example, in Figure 2 The middle figure shows that portions of the peripheral region PA of the display device 10, arranged on two opposite sides of the display area DA, can be bent with a curvature. The bent portions of the peripheral region PA of the display device 10 can overlap with the lower cover 90, and their specific structure will be referred to herein. Figure 9 To provide a more detailed description.

[0064] The data driver 20 may be arranged on the display device 10 in the form of an integrated circuit (IC). In one or more embodiments, the data driver 20 may be arranged on the display circuit board 30.

[0065] The display circuit board 30 can be attached to one side of the display device 10. The display circuit board 30 can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is strong and not easily bent, or a composite printed circuit board that includes both rigid and flexible printed circuit boards (e.g., including both rigid and flexible printed circuit boards).

[0066] In one or more embodiments, a touch sensor driver may be disposed on a display circuit board 30. The touch sensor driver may include an integrated circuit. The touch sensor driver may be attached to the display circuit board 30. The touch sensor driver may be electrically connected via the display circuit board 30 to the touch electrodes of the touchscreen layer of the display device 10.

[0067] The touchscreen layer of the display device 10 can sense user touch input using at least one of one or more suitable touch methods (such as resistive layer methods and / or capacitive methods). As an example, when the touchscreen layer of the display device 10 senses user touch input using a capacitive method, the touch sensor driver can determine whether the user has touched the touchscreen layer by applying a drive signal to a drive electrode in the touch electrodes and sensing the voltage charged in the mutual capacitance between the drive electrode and the sensing electrode using a sensing electrode in the touch electrodes. User touches can include contact touches and / or proximity touches. A contact touch indicates that an object (such as a user's finger and / or pen) is in direct contact with a cover window 70 disposed on the touchscreen layer. A proximity touch (such as hovering) indicates that an object (such as a user's finger and / or pen) may be located or disposed near or above the cover window 70, but away from the cover window 70. The touch sensor driver can be arranged to transmit sensor data to a main processor 5100 based on the sensed voltage, and the main processor 5100 can be arranged to calculate the touch coordinates at the location of the touch input by analyzing the sensor data.

[0068] The controller can be arranged on the display circuit board 30, wherein the controller is arranged to supply driving voltage to drive the pixel, gate driver and data driver 20 of the display device 10.

[0069] A bracket 60 for supporting the display device 10 may be disposed below the display device 10. The bracket 60 may include plastic, metal, or both (e.g., both plastic and metal). A first camera hole CMH1 in which a camera device 5310 is inserted, a battery hole BH in which a battery 80 is disposed, and a cable hole CAH through which a cable connected to the display circuit board 30 passes may be formed or disposed in the bracket 60. A component hole CPH overlapping with the display device 10 may be provided in the bracket 60. The component hole CPH may overlap with a component 40 of the main circuit board 50 in a third direction (e.g., the z-direction). In one or more embodiments, the display area DA of the display device 10 may overlap with a component 40 of the main circuit board 50 in a third direction (e.g., the z-direction). In one or more embodiments, the component hole CPH may not be formed or disposed in the bracket 60.

[0070] In one or more embodiments, component 40 may include a first component 41, a second component 42, a third component 43, and a fourth component 44, each overlapping the display device 10. The first component 41, second component 42, third component 43, and fourth component 44 may include a proximity sensor, an illumination sensor, an iris sensor, a facial recognition sensor, and a camera (or image sensor). An infrared proximity sensor may be used to detect objects positioned near the upper surface of the electronic device 1, and an illumination sensor may be used to detect the brightness of light incident on the upper surface of the electronic device 1. In one or more embodiments, an iris sensor may be used to capture the iris of a human being positioned above the upper surface of the electronic device 1, and a camera may be used to capture objects positioned on the upper surface of the electronic device 1. Component 40 is not limited to proximity sensors, illumination sensors, iris sensors, facial recognition sensors, and cameras. One or more suitable sensors as described herein may be arranged.

[0071] The main circuit board 50 and the battery 80 can be arranged below the bracket 60. The main circuit board 50 can be a rigid printed circuit board or a flexible printed circuit board.

[0072] The main circuit board 50 may include a main processor 5100, a camera device 5310, a main connector 55, and a component 40. The main processor 5100 may include an integrated circuit. The camera device 5310 may be disposed on both the upper and lower surfaces of the main circuit board 50 (e.g., simultaneously on both surfaces), and the main processor 5100 and the main connector 55 may each be disposed on one of the selected upper and lower surfaces of the main circuit board 50.

[0073] The main processor 5100 can be arranged to control all functions of the electronic device 1. As an example, the main processor 5100 can be arranged to output digital video data to the data driver 20 via the display board 30, causing the display device 10 to display an image. The main processor 5100 can be arranged to receive sensed data from a touch sensor driver. The main processor 5100 can be used to determine whether a user has touched the touchscreen layer based on the sensed data and to perform operations corresponding to the user's direct touch and / or proximity touch. The main processor 5100 can be an application processor, a central processing unit, or a system-on-a-chip (SoC) including integrated circuits.

[0074] Camera device 5310 can be used to process image frames (such as still images and / or moving images) acquired by an image sensor in camera mode, and output the image frames to main processor 5100. Camera device 5310 may include at least one selected from camera sensors (e.g., charge-coupled devices (CCDs) and / or complementary metal-oxide-semiconductor (CMOS), light sensors (or image sensors), and / or laser sensors. Camera device 5310 can be connected to an image sensor in component 40 overlapping with display area DA, and can be used to process images input to the image sensor.

[0075] The cable passing through the cable hole CAH of the bracket 60 can be connected to the main connector 55, and thus the main circuit board 50 can be electrically connected to the display circuit board 30.

[0076] In addition to the main processor 5100, camera device 5310, and main connector 55, the main circuit board 50 may further include, for example, Figure 3 The diagram shows a wireless communication unit 5200, an input unit 5300, a sensor unit 5400, an output unit 5500, an interface unit 5600, a memory 5700, and / or a power supply unit 5800.

[0077] The wireless communication unit 5200 may include at least one selected from the broadcast receiving module 5210, the mobile communication module 5220, the wireless internet module 5230, the short-range communication module 5240, and / or the location information module 5250.

[0078] The broadcast receiving module 5210 can be configured to receive broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel and a terrestrial wave channel.

[0079] The mobile communication module 5220 may be configured to transmit / receive radio signals to / from at least one of a base station, external terminal, and / or server on a mobile communication network established according to mobile communication technology standards or communication schemes (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and / or Advanced Long Term Evolution (LTE-A), etc.). The radio signals may include voice call signals, image communication call signals, and / or one or more appropriate types (categories) of data corresponding to text / multimedia message transmission / reception.

[0080] Wireless Internet module 5230 represents a module for wireless Internet access. Wireless Internet module 5230 can be arranged to transmit / receive radio signals over a communication network according to wireless Internet technologies. Examples of wireless Internet technologies may include Wireless Local Area Network (WLAN), Wi-Fi, Wi-Fi Direct, and / or Digital Living Network Alliance (DLNA).

[0081] The short-range communication module 5240 can be used for short-range communication and can support short-range communication by using at least one technology selected from Bluetooth, Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), ZigBee, Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and / or Wireless Universal Serial Bus (Wireless USB). The short-range communication module 5240 can be used to support wireless communication between electronic device 1 and a wireless communication system, between electronic device 1 and another electronic device, or between electronic device 1 and other electronic devices (or external servers) located / deployed in a network via a short-range wireless local area network. The short-range wireless local area network can be a wireless personal area network. Other electronic devices can be wearable devices that can be used to exchange data with or operate alongside electronic device 1.

[0082] The location information module 5250, which is used to obtain the location (or current location) of the electronic device 1, may include a Global Positioning System (GPS) module or a Wi-Fi module.

[0083] The input unit 5300 may include an image input unit (such as a camera device 5310) for inputting image signals, an audio input unit (such as a microphone 5320) for inputting audio signals, and an input device 5330 for receiving information from a user.

[0084] Camera device 5310 can be used to process image frames (such as still images and / or moving images) acquired by an image sensor in image communication mode or capture mode. The processed image frames can be displayed on display device 10 or stored in memory 5700.

[0085] Microphone 5320 can be used to process external sound signals into electronic voice data. The processed voice data can be used appropriately according to the function (or application) being performed in electronic device 1.

[0086] The main processor 5100 can be used to control the operation of the electronic device 1 in response to information input via the input device 5330. The input device 5330 may include mechanical input devices (such as buttons, spring switches, dials, and / or microswitches) and / or touch input devices located on or arranged on the lower and / or side surfaces of the electronic device 1. The touch input device may include the touchscreen layer of the display device 10.

[0087] Sensor unit 5400 may include at least one sensor for sensing at least one selected from information inside electronic device 1, information about the surrounding (e.g., enclosing) environment of electronic device 1, and / or user information, and generating a corresponding sensing signal. Main processor 5100 may be used to control the driving or operation of electronic device 1 based on the sensing signal, or to perform data processing, functions, or operations related to applications installed in electronic device 1. Sensor unit 5400 may include at least one selected from proximity sensors, illuminance sensors, accelerometers, magnetic sensors, G-sensors, gyroscopes, motion sensors, RGB sensors, infrared sensors, fingerprint scanners, ultrasonic sensors, optical sensors, battery gauges, environmental sensors (e.g., barometers, hygrometers, thermometers, radiation sensors, thermal sensors, and / or gas sensors), and / or chemical sensors (e.g., electronic noses, health monitoring sensors, and / or biometric sensors).

[0088] The output unit 5500 can be used to generate outputs related to vision, hearing and / or touch, and may include at least one selected from the display device 10, the sound output unit 5510, the haptic module 5520 and / or the light output unit 5530.

[0089] Display device 10 can be used to display (or output) information processed by electronic device 1. As an example, display device 10 can be used to display execution screen information of an application driven in electronic device 1, or to display user interface (UI) information and graphical user interface (GUI) information corresponding to the execution screen information. Display device 10 may include a display layer and a touchscreen layer, wherein the display layer is used to display images, and the touchscreen layer is used to sense touch input from a user. Accordingly, display device 10 can be used as one of the input devices 5330 for providing an input interface between electronic device 1 and a user, and synchronously (e.g., simultaneously) as one of the output units 5500 for providing an output interface between electronic device 1 and a user.

[0090] The sound output unit 5510 can be used to output sound data received by the wireless communication unit 5200 or stored in the memory 5700 in call receiving mode, communication mode, recording mode, voice recognition mode, and / or broadcast receiving mode, etc. The sound output unit 5510 can be used to output sound signals related to functions performed by the electronic device 1 (e.g., call signal receiving tone and / or message receiving tone, etc.). The sound output unit 5510 may include a receiver and a speaker. At least one selected from the receiver and speaker may be a sound generator attached below the display device 10 and causing the display device 10 to vibrate to output sound. The sound generator may be a piezoelectric element or piezoelectric actuator that contracts or expands according to an electrical signal, or an exciter that generates magnetic force by using a voice coil to cause the display device 10 to vibrate.

[0091] The haptic module 5520 can be used to generate one or more appropriate haptic effects that can be felt by a user. The haptic module 5520 can provide vibrations to the user as a haptic effect. The haptic module 5520 can not only transmit haptic effects through direct contact, but also enable haptic effects that the user can perceive through muscle sensation in their fingers and / or arms.

[0092] The light output unit 5530 can be used to output a signal to notify of an event by using light from a light source. Examples of events generated in the electronic device 1 may include message reception, call signal reception, missed call, alarm, calendar notification, email reception, and / or information reception via an application. The signal output by the light output unit 5530 can be realized if (for example, when) the electronic device 1 emits light of a single color or multiple colors onto its front or rear surface. The signal output can be terminated if (for example, when) the electronic device 1 detects that the user has acknowledged the event.

[0093] Interface unit 5600 can serve as a pathway for one or more suitable types of external devices to connect to electronic device 1. Interface unit 5600 may include at least one selected from a wired / wireless headphone port, an external charger port, a wired / wireless data port, a memory card portion, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, and / or a headphone port. If (for example, when) an external device is connected to interface unit 5600, electronic device 1 can perform appropriate or suitable control associated with the connected external device.

[0094] Memory 5700 can be used to store data supporting one or more suitable functions of electronic device 1. Memory 5700 can be used to store multiple applications driven in electronic device 1, as well as data and commands for the operation of electronic device 1. At least one or more of the multiple applications can be downloaded wirelessly from an external server. Memory 5700 can be used to store applications for the operation of main processor 5100 and temporarily store input / output data (e.g., data such as phone books, messages, still images, and / or moving images). In one or more embodiments, memory 5700 can be used to store tactile data for one or more suitable vibration modes provided to tactile module 5520, and sound data related to one or more suitable sounds provided to sound output unit 5510. The memory 5700 may include at least one type of storage medium selected from the following categories: flash memory, hard disk, solid-state drive (SSD), silicon disk drive (SDD), multimedia card micro, card type (e.g., secure digital (SD) memory or extreme digital (XD) memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, magnetic disk, and / or optical disk.

[0095] Power supply unit 5800 can be used to receive external and internal power under the control of main processor 5100 and to supply power to various components included in electronic device 1. Power supply unit 5800 may include battery 80. In one or more embodiments, power supply unit 5800 may include a connection port. The connection port may be arranged as an example of an interface unit 5600 to which an external charger is electrically connected, wherein the external charger supplies power to charge battery 80. In one or more embodiments, power supply unit 5800 may be arranged to wirelessly charge battery 80 without using the connection port. Battery 80 may be arranged not to overlap with main circuit board 50 in a third direction (e.g., the z-direction). Battery 80 may overlap with battery hole BH of bracket 60.

[0096] The lower cover 90 can be disposed below the main circuit board 50 and the battery 80. The lower cover 90 can be fastened and fixed to the bracket 60. The lower cover 90 can form the lower appearance of the electronic device 1. The lower cover 90 can include plastic, metal, or both plastic and metal (e.g., both plastic and metal).

[0097] The lower surface of camera device 5310, through which its exposed second camera aperture CMH2 is formed or arranged in the lower cover portion 90. The positions of camera device 5310 and the corresponding first camera aperture CMH1 and second camera aperture CMH2 are not limited to, for example... Figure 1 and Figure 2 The one or more embodiments illustrated herein may be modified as appropriate.

[0098] Figure 4 This is a schematic plan view of a display device 10 according to one or more embodiments, and Figure 5 and Figure 6 This is a schematic side view of a display device 10 according to one or more embodiments.

[0099] Display device 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the area for displaying an image, and multiple pixels may be arranged in the display area DA. The display area DA may have one or more suitable shapes, such as a circular shape (e.g., a substantially circular shape), an elliptical shape (e.g., a substantially elliptical shape), a polygonal shape (e.g., a substantially polygonal shape), or a shape of a specific pattern. As an example, in Figure 4 The middle diagram shows that the display area DA can have a basically rectangular shape with rounded corners.

[0100] The peripheral region PA can be arranged outside the display region DA. The peripheral region PA can surround (e.g., enclose) at least a portion of the display region DA. As an example, the peripheral region PA can completely (e.g., substantially completely) surround (e.g., enclose) the display region DA.

[0101] like Figure 4 As illustrated, the planar shape (e.g., substantially planar shape) of the display device 10 can be substantially equivalent to the substrate 100 included in the display device 10 (see Figure 10). Figure 7 The shape of the substrate 10. If (for example, when) the display device 10 includes a display area DA and a peripheral area PA outside the display area DA, this can represent the substrate 100 (see Figure 7 The substrate 100 includes a display area DA and a peripheral area PA outside the display area DA. For convenience, the following description is based on the assumption that the substrate 100 includes a display area DA and a peripheral area PA.

[0102] The display device 10 may include a main region MR, a first bent region BR1 outside the main region MR, and a sub-region SR separated from (e.g., spaced apart from) the main region MR, with the first bent region BR1 located between them. The main region MR may be arranged on one side of the first bent region BR1, and the sub-region SR may be arranged on the other side of the first bent region BR1. Figure 5 As illustrated, the display device 10 can be bent within a first bending region BR1, and if (e.g., when) viewed from a third direction (e.g., the z-direction), at least a portion of the sub-region SR can overlap with the main region MR. The main region MR can include a display area DA and a portion of the peripheral region PA that surrounds (e.g., encloses) the display area DA. The first bending region BR1 and the sub-region SR can be non-display areas in which no image is displayed, and can include another portion of the peripheral region PA.

[0103] refer to Figure 4 and Figure 5 ,exist Figure 5 The middle figure shows that a portion of the peripheral region PA of the display device 10 can be bent about an axis extending in a first direction (e.g., the x-direction), but embodiments of this disclosure are not limited thereto. Figure 6 As illustrated in the diagram, the portions of the peripheral region PA arranged on two opposite sides of the display region DA, with the display region DA located between them (e.g., the second bending region BR2), can each be bent around an axis extending in a second direction (e.g., the y-direction) with a preset (e.g., set or predetermined) curvature. See reference... Figure 2 As described in one or more embodiments, each of the bent portions of the peripheral region PA can be arranged in the lower cover 90 (see...). Figure 2 The inner side of the cover 90, and can be connected with the lower cover 90 (see Figure 2 A portion of the surface (e.g., the side surface) overlaps.

[0104] refer to Figure 4 The data driver 20 can be arranged in the peripheral area PA (e.g., the sub-area SR). The data driver 20 can be arranged on the display device 10 in the form of an integrated circuit (IC). As an example, the data driver 20 can be a data driver integrated circuit that generates data signals.

[0105] The display circuit board 30 can be attached to the end of the sub-region SR of the display device 10. The display circuit board 30 can be electrically connected to the data driver 20, etc., through the pads of the sub-region SR of the display device 10.

[0106] Figure 7 This is a schematic cross-sectional view of a display device 10 according to one or more embodiments, and Figure 8This is a plan view of the raised / lowered structure 630 and the covering layer 650 of the display device 10 according to one or more embodiments.

[0107] refer to Figure 7 The display device 10 may include a substrate 100. One or more suitable elements forming the display device 10 may be arranged on the substrate 100.

[0108] Substrate 100 may include glass, metal, and / or polymer resin. The glass may include ultrathin glass. The polymer resin may include, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. In one or more embodiments, substrate 100 may include a single layer comprising glass, metal, and / or polymer resin (e.g., a single-layer structure). In one or more embodiments, substrate 100 may have a multilayer structure comprising two resin layers (comprising polymer resins as described in one or more embodiments) and an inorganic insulating layer disposed between the two resin layers.

[0109] Pixels can be arranged in a display area DA, and the display area DA can be used to display images using light emitted from the pixels. Each pixel can include a light-emitting diode 300, and the light-emitting diode 300 can be a light-emitting diode containing organic materials, a light-emitting diode containing inorganic materials, or a light-emitting diode containing quantum dots. The light-emitting diode 300 can be arranged in the display area DA and is electrically connected to a transistor 210 arranged in the display area DA.

[0110] Transistor 210 may include a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217, wherein the semiconductor layer 211 includes amorphous (e.g., non-crystalline) silicon, polycrystalline silicon, oxide semiconductor, and / or organic semiconductor materials. To planarize the surface of substrate 100 and / or to prevent impurities from penetrating the semiconductor layer 211 (or to reduce the degree or occurrence of impurity penetration into the semiconductor layer 211), a buffer layer 110 comprising an inorganic insulating (e.g., electrically insulating) material (such as silicon oxide, silicon nitride, and / or silicon oxynitride) may be disposed on substrate 100, and the semiconductor layer 211 may be disposed on the buffer layer 110.

[0111] Gate electrode 213 may be disposed on semiconductor layer 211. Gate electrode 213 may comprise at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may comprise a single-layer structure or a multilayer structure. In one or more embodiments, to ensure insulation (e.g., electrical insulation) between semiconductor layer 211 and gate electrode 213, a gate insulating layer 120 may be disposed between semiconductor layer 211 and gate electrode 213, wherein gate insulating layer 120 comprises an inorganic insulating (e.g., electrically insulating) material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0112] Interlayer insulating layer 130 may be disposed on gate electrode 213. Interlayer insulating layer 130 may comprise inorganic insulating (e.g., electrically insulating) materials such as silicon oxide, silicon nitride and / or silicon oxynitride, and may comprise a single-layer structure or a multilayer structure.

[0113] Source electrode 215 and drain electrode 217 may be disposed on interlayer insulating layer 130. Each of source electrode 215 and drain electrode 217 may be electrically connected to semiconductor layer 211 through contact holes formed or disposed in interlayer insulating layer 130 and gate insulating layer 120. Taking into account conductivity (e.g., electrical conductivity), source electrode 215 and drain electrode 217 may comprise at least one selected from, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may comprise a single-layer structure or a multilayer structure.

[0114] Planarization layer 140 may be disposed on interlayer insulating layer 130. Planarization layer 140 typically planarizes the upper portion of the protective layer covering transistor 210. Planarization layer 140 may comprise organic insulating (e.g., electrically insulating) materials such as acrylic acid, benzocyclobutene (BCB), and / or hexamethyldisiloxane (HMDSO). Figure 7 The diagram shows that planarization layer 140 is a single layer, but planarization layer 40 can be multiple layers. However, one or more appropriate modifications can be made.

[0115] The light-emitting diode 300 may include a pixel electrode 310, an intermediate layer 320 and a counter electrode 330 on the planarization layer 140, wherein the intermediate layer 320 includes an emitting layer.

[0116] Pixel electrode 310 can be electrically connected to transistor 210 through contact holes formed or disposed in planarization layer 140. Pixel electrode 310 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof (e.g., any suitable). In one or more embodiments, pixel electrode 310 may further include a conductive (e.g., electrically conductive) oxide material layer on and / or below the reflective layer. The conductive oxide material layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (e.g., ZnO), indium oxide (e.g., In₂O₃), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one or more embodiments, pixel electrode 310 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0117] A pixel defining layer 150 may be disposed on the pixel electrode 310. The pixel defining layer 150 may include an opening overlapping the pixel electrode 310 and cover the edge of the pixel electrode 310. The pixel defining layer 150 may include an organic insulating (e.g., electrically insulating) material. The pixel defining layer 150 may define a pixel by including an opening that exposes a central portion of the pixel electrode 310.

[0118] like Figure 7 As illustrated, the pixel defining layer 150 can prevent (or reduce the degree or occurrence of arcing, etc., at the edge of the pixel electrode 310) by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 located above the pixel electrode 310. The pixel defining layer 150 may include organic materials such as polyimide and / or HMDSO.

[0119] Intermediate layer 320 may include an emitter layer. The emitter layer may include a low molecular weight material (e.g., a non-polymer material) and / or a high molecular weight material (e.g., a polymer material). Intermediate layer 320 may include a first functional layer and / or a second functional layer, wherein the first functional layer is disposed below the emitter layer and the second functional layer is disposed on the emitter layer. The first functional layer may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Each of the first and second functional layers may include an organic material. In one or more embodiments, intermediate layer 320 may include a tandem structure comprising multiple stacked structures of the first functional layer, the emitter layer, and the second functional layer.

[0120] The counter electrode 330 may comprise a conductive (e.g., electrically conductive) material having a low work function. As an example, the counter electrode 330 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof (e.g., any suitable). In one or more embodiments, the counter electrode 330 may further comprise a layer on the (semi-)transparent layer comprising ITO, IZO, ZnO, and / or In2O3. The counter electrode 330 may be integrally formed or arranged throughout a plurality of light-emitting diodes 300 to correspond to a plurality of pixel electrodes 310.

[0121] In order to emit light from the light-emitting diode 300, it is desirable or necessary to apply a voltage to the counter electrode 330. Accordingly, an electrode power supply line 410 for providing a preset (e.g., set or predetermined) voltage to the counter electrode 330 may be located or arranged in the peripheral region PA.

[0122] If (for example, when) one or more suitable conductive (e.g., electrically conductive) layers are formed or arranged in the display area DA, the electrode power lines 410 can be formed or arranged synchronously (e.g., simultaneously) using a material substantially the same as the material of the one or more suitable conductive (e.g., electrically conductive) layers. In one or more embodiments, Figure 7 The electrode power line 410 may include a material substantially the same as that of the source electrode 215 or drain electrode 217 of the transistor 210, and may be located or arranged on a layer substantially the same as that of the source electrode 215 or drain electrode 217 (e.g., on the interlayer insulating layer 130).

[0123] The counter electrode 330 may extend to the peripheral region PA and be electrically connected to the electrode power line 410. As an example, the counter electrode 330 may be electrically connected to the electrode power line 410 via the conductive layer 420.

[0124] The conductive layer 420 may be located or disposed on the planarization layer 140 and may extend over the electrode power line 410 to electrically connect the electrode power line 410 to the counter electrode 330. The counter electrode 330 may contact the conductive layer 420 in the peripheral region PA, and the conductive layer 420 may contact the electrode power line 410 in the peripheral region PA. The conductive layer 420 may comprise a material substantially the same as that of the pixel electrode 310.

[0125] A capping layer 160 may be located on or disposed on the counter electrode 330, wherein the capping layer 160 improves or enhances the efficiency of light generated by the light-emitting diode 300. The capping layer 160 may cover the counter electrode 330 and extend to the outside of the counter electrode 330 to contact the conductive layer 420 located or disposed below the counter electrode 330. The counter electrode 330 may cover the display area DA and extend to the outside of the display area DA, and the capping layer 160 may also cover the display area DA and extend to the peripheral area PA outside the display area DA. The capping layer 160 may include an organic material.

[0126] Encapsulation layer 500 may be disposed on light-emitting diode 300. If, for example, encapsulation layer 500 is formed or disposed, a protective layer 170 may be disposed between encapsulation layer 160 and encapsulation layer 500 to prevent damage to capping layer 160 (or reduce the degree or occurrence of damage). Protective layer 170 may include LiF. In an embodiment, edge 160a of capping layer 160 may be covered by protective layer 170. When viewed in a direction perpendicular to the upper surface of substrate 100, edge 170a of protective layer 170 may be located between edge 160a of capping layer 160 and edge 140a of planarization layer 140.

[0127] The encapsulation layer 500 may include an inorganic encapsulation layer and / or an organic encapsulation layer. In one or more embodiments, the encapsulation layer 500 may include a first inorganic encapsulation layer 510, a second inorganic encapsulation layer 530, and an organic encapsulation layer 520, wherein the organic encapsulation layer 520 is located between the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530.

[0128] The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 may (e.g., each may) comprise at least one inorganic material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 may comprise a single layer or multiple layers comprising the materials described in one or more embodiments. The organic encapsulation layer 520 may comprise a polymeric material. The polymeric material may comprise acrylic resins, epoxy resins, polyimides, and / or polyethylene. In one or more embodiments, the organic encapsulation layer 520 may comprise acrylates.

[0129] If (for example, when) an organic encapsulation layer 520 is formed or arranged, a partition wall may be arranged in the peripheral region PA to prevent the flow of material forming the organic encapsulation layer 520. As an example, such as Figure 7As illustrated, the first partition wall 610 and the second partition wall 620 can be arranged to be separated from each other (e.g., spaced apart) in the peripheral region PA. Inorganic insulating (e.g., electrical insulating) layers (such as buffer layer 110, gate insulating layer 120 and / or interlayer insulating layer 130) can extend into the peripheral region PA, and the first partition wall 610 and the second partition wall 620 can be arranged on the inorganic insulating layer.

[0130] Each of the first partition wall 610 and the second partition wall 620 may have a multilayer structure. The first partition wall 610 may include a first layer 611, a second layer 612, and a third layer 613 stacked in a direction normal (e.g., perpendicular) to the upper surface of the substrate 100 (e.g., the z-direction). The first layer 611 may include a material substantially the same as the material of the planarization layer 140, the second layer 612 may include a material substantially the same as the material of the pixel defining layer 150 in the display area DA, and the third layer 613 may include a material substantially the same as the material of the spacers that may be disposed on the pixel defining layer 150 in the display area DA. Each of the first layer 611, the second layer 612, and the third layer 613 may include an organic insulating (e.g., electrically insulating) material. The second partition wall 620 may include a first layer 622 and a second layer 623 stacked in a direction normal (e.g., perpendicular) to the upper surface of the substrate 100 (e.g., the z-direction). The first layer 622 of the second partition wall 620 may include a material substantially the same as the material of the pixel defining layer 150 in the display area DA, and the second layer 623 may include a material substantially the same as the material of the spacer.

[0131] The second partition wall 620 may be disposed between the first partition wall 610 and the display area DA. The second partition wall 620 may overlap with the electrode power line 410. The second partition wall 620 may be located on or disposed on a portion of the conductive layer 420 disposed on the electrode power line 410. Each of the first partition wall 610 and the second partition wall 620 may be separated from the planarization layer 140 (e.g., spaced apart) and located on or disposed in the peripheral area PA.

[0132] like Figure 7As illustrated, the first inorganic encapsulation layer 510 may cover the first partition wall 610 and the second partition wall 620. The first inorganic encapsulation layer 510 may extend toward the edge 100E of the substrate 100 beyond the first partition wall 610 and the second partition wall 620. The position of the organic encapsulation layer 520 may be limited by the second partition wall 620, and during the process of forming or placing the organic encapsulation layer 520, material used to form or place the organic encapsulation layer 520 may be prevented from overflowing to the outside of the second partition wall 620 (or the extent or occurrence of material overflow to the outside of the second partition wall 620 may be reduced). Even if material used to form or place the organic encapsulation layer 520 partially overflows to the outside of the second partition wall 620, the material used to form or place the organic encapsulation layer 520 may not move toward the edge 100E of the substrate 100 because the position of the organic encapsulation layer 520 is also limited by the first partition wall 610.

[0133] In addition to the first partition wall 610 and the second partition wall 620, a concave-convex structure 630 can also be arranged in the peripheral region PA. (See reference...) Figures 4 to 6 In the event that the peripheral region PA described in one or more embodiments is bent, the convex-concave structure 630 can prevent cracks from forming in the peripheral region PA (or reduce the degree or occurrence of crack formation). Even if cracks do form, the convex-concave structure 630 can prevent crack propagation to the display region DA (or reduce the degree or occurrence of crack propagation to the display region DA). The convex-concave structure 630 may include a plurality of protrusions 632 and a plurality of grooves 634. Each of the grooves 634 may be located or arranged between two adjacent protrusions 632. The convex-concave structure 630 may have a structure in which the protrusions 632 and the grooves 634 are alternately arranged.

[0134] The protrusion 632 can have one or more suitable shapes. For example... Figure 7As illustrated, protrusion 632 may include material substantially the same as that of the elements arranged in the display area DA. As an example, the uneven structure 630 may be defined in (or by) an insulating (e.g., electrically insulating) layer (e.g., an inorganic insulating (e.g., electrically insulating) layer) extending to the peripheral region PA. In one or more embodiments, the inorganic insulating layer (such as buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130) may extend to the peripheral region PA, and grooves 634 having a predetermined (e.g., set or predetermined) depth in the inorganic insulating layer and protrusions 632 between adjacent grooves 634 may be defined in the inorganic insulating layer. In one or more embodiments, the protrusions 632 may have a multilayer structure comprising a material substantially the same as that of each of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130. In one or more embodiments, the depth of the groove 634 may be substantially equal to the sum of the thicknesses of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130.

[0135] like Figure 8 As illustrated, the bump structure 630 may extend along at least a portion of the edge 100E of the substrate 100 in a plan view. In one or more embodiments, the bump structure 630 may have a shape that surrounds the display area DA. In one or more embodiments, the bump structure 630 may completely (e.g., substantially completely) surround (e.g., enclose) the display area DA and have a discontinuous shape in one or more segments.

[0136] As an example, such as Figure 8 As illustrated, the protrusion 632 may extend along at least a portion of the edge 100E of the substrate 100 in a plan view. In one or more embodiments, the protrusion 632 may have a shape that surrounds the display area DA. In one or more embodiments, the protrusion 632 may completely (e.g., substantially completely) surround (e.g., enclose) the display area DA and have a discontinuous shape in one or more segments. Figure 8 As illustrated in the figure, protrusion 632 can be provided in multiple forms. Protrusion 632 may include multiple protrusions.

[0137] A cover layer 650 may be disposed on the uneven structure 630. The cover layer 650 may comprise an organic insulating (e.g., electrically insulating) material. In one or more embodiments, the cover layer 650 may comprise a material substantially the same as that of the planarization layer 140. In one or more embodiments, the cover layer 650 may cover the edges of inorganic insulating layers extending into the peripheral region PA (e.g., the edges of each of the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130), and cover the uneven structure 630. A portion of the cover layer 650 may at least partially fill the recess 634 of the uneven structure 630.

[0138] like Figure 8 As illustrated, the cover dam 650 may extend along at least a portion of the edge 100E of the substrate 100 in a plan view. In one or more embodiments, the cover dam 650 may have a shape that completely (e.g., substantially completely) surrounds (e.g., encloses) the display area DA along the protrusion 632. In one or more embodiments, the cover dam 650 may completely (e.g., substantially completely) surround (e.g., encloses) the display area DA and have a discontinuous shape in one or more segments. The cover dam 650 may have a preset (e.g., set or predetermined) width to cover the protrusion 632. The cover dam 650 may be separated (e.g., spaced apart) from a partition wall (e.g., a first partition wall 610 disposed in the outermost portion).

[0139] The inorganic encapsulation layers (e.g., each of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530) may extend toward the edge 100E of the substrate 100 beyond the first partition wall 610, the second partition wall 620, the cover dam 650, and the bump structure 630. The edge 510E of the first inorganic encapsulation layer 510 and the edge 530E of the second inorganic encapsulation layer 530 may be separated from the edge 100E of the substrate 100 (e.g., spaced apart).

[0140] In one or more embodiments, the edge 510E of the first inorganic encapsulation layer 510 may be located or arranged at a location different from the position of the edge 530E of the second inorganic encapsulation layer 530. As an example, each of the edges 510E of the first and second inorganic encapsulation layers 530E may be located or arranged between the edge 100E of the overlay layer 650 and the substrate 100, and the edge 530E of the second inorganic encapsulation layer 530E may be located or arranged between the edge 510E of the first inorganic encapsulation layer 510E and the edge 100E of the substrate 100. Each of the edges 510E of the first and second inorganic encapsulation layers 530E may be in direct contact with the upper surface of the substrate 100.

[0141] An insulating (e.g., electrically insulating) layer (e.g., an inorganic insulating layer) located or disposed in the display area DA of the substrate 100 can be as follows: Figure 7 The figure shows an extension to the peripheral region PA, and the peripheral region PA may not exist between the edge of the inorganic encapsulation layer and the edge 100E of the substrate 100. As an example, the region between the edge of the inorganic encapsulation layer and the edge 100E of the substrate 100 can be a type (variety) of inorganic removal region (e.g., inorganic insulation (e.g., electrical insulation) removal region) NIR, in which no inorganic material exists on the substrate 100. For example, in Figure 7 The figure shows that the space between the edge 530E of the second inorganic encapsulation layer 530 and the edge 100E of the substrate 100 can correspond to the inorganic removal region NIR.

[0142] Figure 9 This is a schematic side view of the display device 10 and the lower cover 90 as an electronic device 1 according to one or more embodiments.

[0143] Figure 9 The display device 10 can be as referenced Figure 7 As described in one or more embodiments. Because the convex-concave structure 630 includes a structure in which protrusions 632 and grooves 634 are alternately arranged, it can prevent cracks that may penetrate the display area DA due to stress applied to the display device 10 when the display device 10 is bent (or can reduce the extent or occurrence of cracks that may penetrate the display area DA due to stress applied to the display device 10 when the display device 10 is bent).

[0144] As a comparative example, in the case where the convex-concave structure 630 and the covering dam 650 are separated (e.g., spaced apart) from the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 to prevent crack propagation (or reduce the degree or occurrence of crack propagation), the width of the peripheral region PA may increase due to the spaces prepared for arranging the convex-concave structure 630 and the covering dam 650 respectively. However, as in accordance with... Figure 7 and Figure 9 In the display device 10 of one or more embodiments illustrated herein, when the convex-concave structure 630 and the cover dam 650 overlap with the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530, the width of the peripheral region PA can be reduced, and the space of the display device 10 can be used effectively or appropriately.

[0145] In one or more embodiments, since the covering layer 650 separates the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 from the uneven structure 630, even if cracks are generated in the protrusions 632 of the uneven structure 630 due to the stress applied to the display device 10 when it is bent, the cracks can be prevented from propagating to the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 (or the extent or occurrence of crack propagation can be reduced).

[0146] like Figure 9 As illustrated, the display device 10 can be assembled to the lower cover 90 while being bent, such that a portion of the peripheral region PA (e.g., the inorganic removal region NIR) has a preset (e.g., set or predetermined) curvature. The inorganic removal region NIR may correspond to the following as shown in the reference. Figure 6 The second bending region BR2 is described in one or more embodiments. A portion of the display device 10 (e.g., the inorganic removal region NIR or the second bending region BR2) may overlap with the lower cover portion 90.

[0147] When the display device 10 is bent, the layer containing inorganic insulating (e.g., electrical insulating) material may be relatively easily damaged by the stress applied to the display device 10. However, since not only are the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 absent in the inorganic removal region NIR, but also the inorganic insulating layer (e.g., buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130) that can be arranged between the substrate 100 and the first inorganic encapsulation layer 510, the problems described in one or more embodiments can be prevented or reduced. For example, since the inorganic removal region NIR is provided or arranged between the edge 100E of the substrate 100 and the edge of the inorganic encapsulation layer (the edge 530E of the second inorganic encapsulation layer 530) as in one or more embodiments, cracking due to the stress applied when the second bending region BR2 is bent can be effectively or appropriately prevented (or the extent or occurrence of cracking due to the stress applied when the second bending region BR2 is bent can be effectively or appropriately reduced).

[0148] Figures 10A to 10C Each is a cross-sectional view of the convex-concave structure 630 and the covering layer 650 of the display device 10 according to one or more embodiments.

[0149] The concave-convex structure 630 may have a structure in which protrusions 632 and grooves 634 are alternately arranged. The concave-convex structure 630 may be defined in (or defined by) an inorganic insulating layer extending to the peripheral region PA, and the inorganic insulating layer may include a buffer layer 110, a gate insulating layer 120, and an interlayer insulating layer 130.

[0150] exist Figure 10A The middle figure shows that the inorganic insulating (e.g., electrically insulating) layers of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130 can extend to the peripheral region PA, and the protrusion / recess structure 630 can be defined within (or by) the inorganic insulating layer. As an example, the protrusion 632 can have a multilayer structure comprising a material substantially the same as that of each of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130. The depth of the recess 634 can be substantially equal to the sum of the thicknesses of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130.

[0151] In one or more embodiments, the edges 110E of the buffer layer 110, 120E of the gate insulating layer 120, and 130E of the interlayer insulating layer 130 may be located or arranged closer to the display area DA than the edge 510E of the first inorganic encapsulation layer 510 (see [link]). Figure 7 ), and was covered by a 650-layer embankment.

[0152] In one or more embodiments, the substrate 100 may include a first polymer resin layer 101, a first inorganic isolation layer 102 on the first polymer resin layer 101, a second polymer resin layer 103 on the first inorganic isolation layer 102, and a second inorganic isolation layer 104 on the second polymer resin layer 103. In one or more embodiments, as Figure 10A As shown in the figure, the bottom surface of the groove 634 can be substantially equivalent to (or correspond to) the upper surface of the substrate 100, for example, the upper surface of the second inorganic isolation layer 104.

[0153] An inorganic removal region NIR can be formed or arranged by removing a portion of an inorganic insulating (e.g., electrically insulating) layer disposed within the inorganic removal region NIR. As an example, an inorganic removal region NIR can be formed or arranged by forming or arranging a bump structure 630, a cover layer 650, a first inorganic encapsulation layer 510, and a second inorganic encapsulation layer 530 on a substrate 100, and subsequently etching the portion of each of the first and second inorganic encapsulation layers 510 and 530 corresponding to the inorganic removal region NIR. During the etching process that removes a portion of each of the first and second inorganic encapsulation layers 510 and 530, a portion of a layer (e.g., a second inorganic isolation layer 104) located below or disposed under the first and second inorganic encapsulation layers 510 and comprising inorganic insulating (e.g., electrically insulating) material can also be etched. In one or more embodiments, as Figure 10AAs illustrated, the edge 104E of the second inorganic isolation layer 104 can be substantially aligned with the edge 530E of the second inorganic encapsulation layer 530. In the event that a portion of the second inorganic isolation layer 104 is removed, the edge 100E of the substrate 100 can be defined as the edge of at least one selected from the first polymer resin layer 101, the first inorganic isolation layer 102, and / or the second polymer resin layer 103.

[0154] For example, an inorganic removal region (NIR) can be created by removing a portion of the inorganic insulating layer within the inorganic removal region (NIR). This may involve forming a structure on substrate 100 including a bump structure 630, a cover dam layer 650, and a first inorganic encapsulation layer 510 and a second inorganic encapsulation layer 530. A portion of these encapsulation layers can then be etched away. During this etching process, a portion of the underlying second inorganic isolation layer 104 may also be removed. In one or more embodiments, the edges 104E of the second inorganic isolation layer 104 and the edges 530E of the second inorganic encapsulation layer 530 may be aligned. If (e.g., when) a portion of the second inorganic isolation layer 104 is removed, the edge 100E of the substrate 100 may be defined by the edges of the selected first polymer resin layer 101 and / or second polymer resin layer 103 and / or first inorganic isolation layer 102.

[0155] although Figure 10A The middle figure shows that the depth of the groove 634 in the uneven structure 630 is substantially equal to the sum of the thicknesses of the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130, but embodiments of this disclosure are not limited thereto. In one or more embodiments, such as Figure 10B As illustrated, the groove 634 may extend toward the second inorganic isolation layer 104 of the substrate 100. In one or more embodiments, the depth of the groove 634 may be substantially equal to the sum of the thicknesses of the second inorganic isolation layer 104, the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130. The bottom surface of the groove 634 may be substantially equivalent to the upper surface of the second polymer resin layer 103. Because the groove 634 extends to the second inorganic isolation layer 104, the protrusion 632 may have a multilayer structure comprising a material substantially the same as that of each of the second inorganic isolation layer 104, the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130.

[0156] Despite Figure 10A The middle figure shows that the depth of the groove 634 in the uneven structure 630 is substantially equal to the sum of the thicknesses of the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130, but embodiments of this disclosure are not limited thereto. In one or more embodiments, such as Figure 10CAs illustrated, the depth of the groove 634 can be substantially equal to the sum of the thicknesses of the gate insulating layer 120 and the interlayer insulating layer 130. In one or more embodiments, the bottom surface of the groove 634 can be substantially equivalent to (or correspond to) the upper surface of the buffer layer 110. The protrusion 632 can have a multilayer structure comprising a material substantially the same as that of each of the gate insulating layer 120 and the interlayer insulating layer 130.

[0157] For example, the convex-concave structure 630 may be defined within (or by) an inorganic insulating (e.g., electrically insulating) layer comprising a buffer layer 110, a gate insulating layer 120, and an interlayer insulating layer 130, and the depth of the groove 634 may be less than the sum of the thicknesses of the inorganic insulating layers as described in one or more embodiments. As an example, upper layers of adjacent protrusions 632 (and having grooves 634 therebetween) (e.g., upper layers comprising material substantially the same as that of the gate insulating layer 120 and / or the interlayer insulating layer 130) may be separated from each other (e.g., spaced apart), and lower layers of adjacent protrusions 632 (e.g., lower layers comprising material substantially the same as that of the buffer layer 110) may be connected to each other.

[0158] In one or more embodiments, during an etching process that removes a portion of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 to form or arrange the inorganic removal region NIR, a portion of the buffer layer 110 and a portion of the second inorganic isolation layer 104 may be removed. In one or more embodiments, the edge 110E of the buffer layer 110 and the edge 104E of the second inorganic isolation layer 104 may be substantially aligned with the edge 530E of the second inorganic encapsulation layer 530.

[0159] Figure 11 This is a schematic cross-sectional view of a display device 10 according to one or more embodiments.

[0160] like Figure 11 The display device 10 shown in the figure can have the same characteristics as the reference. Figure 7 The structures of one or more embodiments described in one or more embodiments are substantially the same. For example... Figure 11 As illustrated, a portion of the peripheral region PA of the display device 10 (e.g., the inorganic removal region NIR of insulation (e.g., electrical insulation)) can be bent at a preset (e.g., set or predetermined) curvature, and can be as shown in the reference. Figure 9 The lower cover 90 described in one or more embodiments (see...) Figure 9 (overlap). In, for example Figure 11In one or more embodiments illustrated herein, there may be differences in the location of the edge 510E of the first inorganic encapsulation layer 510 and the edge 530E of the second inorganic encapsulation layer 530. These differences will be described in more detail herein, primarily or primarily.

[0161] refer to Figure 11 The inorganic encapsulation layers (e.g., each of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530) may extend toward the edge 100E of the substrate 100 beyond the first partition wall 610, the second partition wall 620, the cover dam 650, and the undulation structure 630. The edges 510E of the first inorganic encapsulation layer 510 and the edges 530E of the second inorganic encapsulation layer 530 may be separated from the edge 100E of the substrate 100 (e.g., spaced apart) and substantially aligned on the same line.

[0162] The edges 510E of the first inorganic encapsulation layer 510 and the edges 530E of the second inorganic encapsulation layer 530 may be located or arranged between the edges 100E of the overlay layer 650 and the substrate 100, and are substantially aligned on the same line.

[0163] Figures 12A to 12C Each is a cross-sectional view of the convex-concave structure 630 and the covering layer 650 of the display device 10 according to one or more embodiments.

[0164] The concave-convex structure 630 may have a structure in which protrusions 632 and grooves 634 are alternately arranged. The concave-convex structure 630 may be defined in (or defined by) an inorganic insulating layer extending to the peripheral region PA, and the inorganic insulating layer may include a buffer layer 110, a gate insulating layer 120, and an interlayer insulating layer 130.

[0165] refer to Figure 12A The inorganic insulating (e.g., electrically insulating) layers of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130 may extend to the peripheral region PA, and the protrusion / recess structure 630 may be defined within (or by) the inorganic insulating layer. In one or more embodiments, the protrusion 632 may have a multilayer structure comprising a material substantially the same as that of each of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130. The depth of the recess 634 may be substantially equal to the sum of the thicknesses of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130.

[0166] The edges 110E of the buffer layer 110, 120E of the gate insulating layer 120, and 130E of the interlayer insulating layer 130 may be located or arranged closer to the display area DA than the edge 510E of the first inorganic encapsulation layer 510 (see [link]). Figure 7), and was covered by a 650-layer embankment.

[0167] The inorganic removal region NIR can be formed or arranged by removing a portion of the inorganic insulating layer disposed in the inorganic removal region NIR. As an example, the inorganic removal region NIR can be formed or arranged by forming or arranging the bump structure 630, the cover layer 650, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 on the substrate 100, and then etching the portion of each of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 corresponding to the inorganic removal region NIR.

[0168] In one or more embodiments, the substrate 100 may include a first polymer resin layer 101, a first inorganic isolation layer 102 on the first polymer resin layer 101, a second polymer resin layer 103 on the first inorganic isolation layer 102, and a second inorganic isolation layer 104 on the second polymer resin layer 103. A portion of the second inorganic isolation layer 104 may also be removed during an etching process that removes a portion of each of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 to form or arrange the inorganic removal region (NIR). Accordingly, the edge 104E of the second inorganic isolation layer 104 may be substantially aligned with the edge 510E of the first inorganic encapsulation layer 510 and the edge 530E of the second inorganic encapsulation layer 530. When a portion of the second inorganic isolation layer 104 is removed by etching, the edge 100E of the substrate 100 may be defined as an edge selected from at least one of the first polymer resin layer 101, the first inorganic isolation layer 102, and the second polymer resin layer 103.

[0169] An etching process for forming or arranging insulating inorganic removal regions (NIRs) may include forming or arranging each of a first inorganic encapsulation layer 510 and a second inorganic encapsulation layer 530 to completely (e.g., substantially completely) cover the substrate 100, and subsequently removing portions of each of the first and second inorganic encapsulation layers 510 and 530 corresponding to the inorganic removal regions (NIRs). In one or more embodiments, damage to the second polymer resin layer 103 that may occur during the etching process can be reduced because a portion of the first inorganic encapsulation layer 510, a portion of the second inorganic encapsulation layer 530, and the second inorganic isolation layer 104 also have substantially uniform thickness. In one or more embodiments, the edges 510E of the first inorganic encapsulation layer 510, the edges 530E of the second inorganic encapsulation layer 530, and the edges 104E of the second inorganic isolation layer 104 may be substantially aligned on the same line.

[0170] Despite Figure 12AThe middle figure shows that the depth of the groove 634 in the uneven structure 630 is substantially equal to the sum of the thicknesses of the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130, but embodiments of this disclosure are not limited thereto. In one or more embodiments, such as Figure 12B As illustrated, the groove 634 may extend toward the second inorganic isolation layer 104 of the substrate 100. In one or more embodiments, the depth of the groove 634 may be substantially equal to the sum of the thicknesses of the second inorganic isolation layer 104, the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130. The bottom surface of the groove 634 may be substantially equivalent to the upper surface of the second polymer resin layer 103.

[0171] Despite Figure 12A The middle figure shows that the depth of the groove 634 in the uneven structure 630 is substantially equal to the sum of the thicknesses of the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130, but embodiments of this disclosure are not limited thereto. In one or more embodiments, such as Figure 12C As illustrated, the depth of the groove 634 can be substantially equal to the sum of the thicknesses of the gate insulating layer 120 and the interlayer insulating layer 130. In one or more embodiments, the bottom surface of the groove 634 can be substantially equivalent to the upper surface of the buffer layer 110. The protrusion 632 can have a multilayer structure comprising a material substantially the same as that of each of the gate insulating layer 120 and the interlayer insulating layer 130.

[0172] For example, the convex-concave structure 630 may be defined within (or by) an inorganic insulating (e.g., electrically insulating) layer comprising a buffer layer 110, a gate insulating layer 120, and an interlayer insulating layer 130, and the depth of the groove 634 may be less than the sum of the thicknesses of the inorganic insulating layers as described in one or more embodiments. As an example, upper layers of adjacent protrusions 632 (and having grooves 634 therebetween) (e.g., upper layers comprising material substantially the same as that of the gate insulating layer 120 and / or the interlayer insulating layer 130) may be separated from each other (e.g., spaced apart), and lower layers of adjacent protrusions 632 (e.g., lower layers comprising material substantially the same as that of the buffer layer 110) may be connected to each other.

[0173] Figure 13A and Figure 13B This is a cross-sectional view illustrating the manufacturing process of the display device 10 according to one or more embodiments.

[0174] refer to Figure 7The process of manufacturing the display device 10 may include: forming or arranging transistors 210 and light-emitting diodes 300 electrically connected to transistors 210 in the display area DA of substrate 100; forming or arranging partition walls (e.g., first partition wall 610 and second partition wall 620) located or arranged in the peripheral area PA of substrate 100; forming or arranging a bump structure 630 between the partition wall and the edge 100E of substrate 100; and forming or arranging a covering layer 650 on the bump structure 630. Next, a process of forming or arranging an encapsulation layer 500 may be included. For example, Figure 13A The figure shows the convex and concave structure 630 arranged in the peripheral region PA and the encapsulation layer 500 on the covering embankment 650.

[0175] The process of forming or disposing of encapsulation layer 500 may include forming or disposing of a first inorganic encapsulation layer 510; forming or disposing of an organic encapsulation layer 520; and forming or disposing of a second inorganic encapsulation layer 530. Different masks may be used to form or dispose of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530. In one or more embodiments, the opening of the mask used to form or dispose of the first inorganic encapsulation layer 510 may be smaller than the opening of the mask used to form or dispose of the second inorganic encapsulation layer 530. In one or more embodiments, the first inorganic encapsulation layer 510 may be formed or disposed of by using a mask having an opening corresponding to the area where the first inorganic encapsulation layer 510 is located or disposed, but the second inorganic encapsulation layer 530 may be formed or disposed of without a mask. Accordingly, during the process of forming or disposing of the second inorganic encapsulation layer 530, the second inorganic encapsulation layer 530 may extend to the edge 100E of the substrate 100 and beyond the edge 510E of the first inorganic encapsulation layer 510.

[0176] Next, as Figure 13B As illustrated, the inorganic removal region (NIR) can be formed or arranged by removing a portion of the second inorganic encapsulation layer 530. This portion of the second inorganic encapsulation layer 530 can be removed by an etching process.

[0177] In one or more embodiments, where the substrate 100 includes a first polymer resin layer 101, a first inorganic isolation layer 102 on the first polymer resin layer 101, a second polymer resin layer 103 on the first inorganic isolation layer 102, and a second inorganic isolation layer 104 on the second polymer resin layer 103, a portion of the uppermost second inorganic isolation layer 104 provided or disposed on the substrate 100 may also be removed during the etching process. For example, in Figure 13BThe figure shows that the edges 104E of the second inorganic isolation layer 104 and the edges 530E of the second inorganic encapsulation layer 530 are substantially aligned on the same line. The edge 530E of the second inorganic encapsulation layer 530 may be located or arranged between the edge 510E of the first inorganic encapsulation layer 510 and the edge 100E of the substrate 100 (e.g., the edge of the second polymer resin layer 103).

[0178] Figure 14A and Figure 14B This is a cross-sectional view illustrating the manufacturing process of the display device 10 according to one or more embodiments.

[0179] refer to Figure 7 The process of manufacturing the display device 10 may include: forming or arranging transistors 210 and light-emitting diodes 300 electrically connected to transistors 210 in the display area DA of substrate 100; forming or arranging partition walls (e.g., first partition wall 610 and second partition wall 620) located or arranged in the peripheral area PA of substrate 100; forming or arranging a bump structure 630 between the partition wall and the edge 100E of substrate 100; and forming or arranging a covering layer 650 on the bump structure 630. Next, a process of forming or arranging an encapsulation layer 500 may be included. For example, Figure 14A The figure shows the convex and concave structure 630 arranged in the peripheral region PA and the encapsulation layer 500 on the covering embankment 650.

[0180] The process of forming or arranging the encapsulation layer 500 may include forming or arranging a first inorganic encapsulation layer 510; forming or arranging an organic encapsulation layer 520; and forming or arranging a second inorganic encapsulation layer 530. The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 may be formed or arranged using substantially the same mask, or may be formed or arranged to completely (e.g., substantially completely) cover the substrate 100 without using a mask. Accordingly, as Figure 14A As illustrated, a portion of the second inorganic encapsulation layer 530 may extend continuously (e.g., substantially continuously) between the uneven structure 630 and the edge 100E of the substrate 100, while overlapping a portion of the first inorganic encapsulation layer 510.

[0181] Next, as Figure 14B As illustrated, an inorganic removal region (NIR) can be formed or arranged by removing a portion of the second inorganic encapsulation layer 530. The process of removing a portion of the second inorganic encapsulation layer 530 may include removing a portion of the underlying first inorganic encapsulation layer 510. For example, a portion of the second inorganic encapsulation layer 530 and a portion of the first inorganic encapsulation layer 510 may be removed together during substantially the same process. A portion of the second inorganic encapsulation layer 530 and a portion of the first inorganic encapsulation layer 510 may be removed by an etching process.

[0182] In one or more embodiments, where the substrate 100 includes a first polymer resin layer 101, a first inorganic isolation layer 102 on the first polymer resin layer 101, a second polymer resin layer 103 on the first inorganic isolation layer 102, and a second inorganic isolation layer 104 on the second polymer resin layer 103, a portion of the uppermost second inorganic isolation layer 104 provided or disposed on the substrate 100 may also be removed during the etching process. Figure 14B As illustrated in the figure, the edges 104E of the second inorganic isolation layer 104, the edge 510E of the first inorganic encapsulation layer 510, and the edge 530E of the second inorganic encapsulation layer 530, which are formed or arranged when removed in substantially the same process, can be aligned substantially on the same line.

[0183] Figure 15 This is a perspective view of an electronic device employing a display device 10 according to one or more embodiments.

[0184] refer to Figure 15 Electronic devices employing display devices according to one or more embodiments may include not only electronic devices for displaying images (such as smartphone 1a, tablet PC 1b, laptop 1c, TV 1d and / or desktop monitor 1e), but also wearable electronic devices (such as smart glasses 1f, head-mounted display 1g and / or smartwatch 1h) and / or vehicle electronic devices 1i (such as a car dashboard, center console, center information display (CID) arranged on the dashboard and / or rearview mirror display).

[0185] According to one or more embodiments, a display device and an electronic device including the display device can be provided to prevent or reduce defects generated during the manufacturing process. Aspects and features of the embodiments disclosed herein are merely examples and are not limited thereto.

[0186] For example, a display device designed to prevent or reduce defects during the manufacturing process and an electronic device including the display device may be provided. The display device may include a substrate having a display area and a peripheral area, transistors and light-emitting diodes in the display area, and an encapsulation layer including a first inorganic layer and a second inorganic layer and an organic layer between them. In the peripheral area, an inorganic insulating (e.g., electrically insulating) layer, partition walls, and an uneven structure with protrusions and grooves covered by a covering layer may be provided. The edges of the encapsulation layer and the inorganic insulating layer may be strategically positioned to enhance durability and performance. The described aspects and features are exemplary and are not limited to embodiments of this disclosure.

[0187] The display device, electronic device, electronic device, means for manufacturing substantially the same device or apparatus, and / or any other related device or component according to one or more embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware (e.g., any suitable). For example, one or more components of the device may be provided on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, one or more components of the device may be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), and / or printed circuit board (PCB), or provided on a substrate. Additionally, one or more components of the device may be a process or thread that runs in one or more computing devices, on one or more processors, executes computer program instructions, and interacts with other system components to perform one or more functions described herein. The computer program instructions may be stored in memory, which may be implemented in the computing device using standard memory devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs and / or flash drives. Furthermore, those skilled in the art will recognize that the functions of one or more computing devices can be combined or integrated into a single computing device, or that the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of this disclosure.

[0188] It should be understood that the embodiments described herein should be considered in a descriptive sense only and are not intended to be limiting. Descriptions of features or aspects within each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments. While the subject matter of this disclosure has been described with reference to the accompanying drawings, those skilled in the art will understand that one or more suitable modifications in form and detail may be made herein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: The substrate includes a display area and a peripheral area outside the display area; Multiple transistors are located in the display area of ​​the substrate; Multiple light-emitting diodes are arranged in the display area of ​​the substrate and electrically connected to the multiple transistors; An encapsulation layer is disposed on the plurality of light-emitting diodes and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer above the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer. Multiple inorganic insulating layers are disposed in the peripheral region of the substrate and are separated from the edge of the substrate; A partition wall in the peripheral region of the substrate; The concave-convex structure is disposed between the partition wall and the edge of the substrate, is defined in the plurality of inorganic insulating layers, and includes a plurality of protrusions and a groove between two adjacent protrusions selected from the plurality of protrusions. as well as Covering the dike layer, on the uneven structure, The edge of the organic encapsulation layer is on one side of the partition wall, and each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends on the cover embankment and is separated from the edge of the substrate.

2. The display device according to claim 1, wherein, The edge of the second inorganic encapsulation layer lies between the edge of the first inorganic encapsulation layer and the edge of the substrate.

3. The display device according to claim 1, wherein, The edges of the first inorganic encapsulation layer and the edges of the second inorganic encapsulation layer are aligned on the same line.

4. The display device according to claim 1, wherein, The first inorganic encapsulation layer is in direct contact with the second inorganic encapsulation layer on the cover layer.

5. The display device according to claim 1, wherein, The plurality of inorganic insulating layers include a buffer layer between the substrate and the semiconductor layer of each of the plurality of transistors, and the edge of the buffer layer is separated from the edge of the substrate.

6. The display device according to claim 5, wherein, The bottom surface of the groove corresponds to the upper surface of the buffer layer.

7. The display device according to claim 5, wherein, The bottom surface of the groove corresponds to the upper surface of the substrate.

8. The display device according to claim 1, wherein, The substrate includes: First polymer resin layer; A first inorganic isolation layer is formed on the first polymer resin layer; A second polymer resin layer is disposed on the first inorganic isolation layer; and The second inorganic isolation layer is located on the second polymer resin layer. The edge of the substrate is defined by the edge of at least one of the first polymer resin layer, the first inorganic insulating layer, and the second polymer resin layer, and The edge of the second inorganic isolation layer is separated from the edge of at least one of the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer.

9. The display device according to claim 8, wherein, The groove extends into the second inorganic isolation layer.

10. The display device according to claim 8, wherein, The edges of the second inorganic encapsulation layer and the edges of the second inorganic isolation layer are aligned on the same line.

11. An electronic device, comprising: A display device, including a display area and a peripheral area; as well as A lower cover portion forms the appearance, the lower cover portion including an opening in its front surface that exposes a portion of the display device, and the lower cover portion overlapping the peripheral area of ​​the display device. The display device includes: substrate; Multiple transistors are arranged on the substrate to correspond to the display area; Multiple light-emitting diodes are arranged on the substrate to correspond to the display area and are electrically connected to the multiple transistors; An encapsulation layer is disposed on the plurality of light-emitting diodes and includes a first inorganic encapsulation layer, a second inorganic encapsulation layer above the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer. Multiple inorganic insulating layers are disposed on the substrate to correspond to the peripheral region and are separated from the edge of the substrate; A partition wall is provided on the substrate to correspond to the peripheral region; A concave-convex structure, disposed between the partition wall and the edge of the substrate, is defined within the plurality of inorganic insulating layers and includes a plurality of protrusions and a groove between two adjacent protrusions selected from the plurality of protrusions; and Covering the dike layer, on the uneven structure, The edge of the organic encapsulation layer is located on one side of the partition wall, each of the first and second inorganic encapsulation layers extends on the cover layer, and the edges of the first and second inorganic encapsulation layers are separated from the edge of the substrate. A portion of the area of ​​the substrate corresponding to the peripheral region is bent to have curvature.

12. The electronic device according to claim 11, wherein, The edge of the second inorganic encapsulation layer lies between the edge of the first inorganic encapsulation layer and the edge of the substrate.

13. The electronic device according to claim 11, wherein, The edges of the first inorganic encapsulation layer and the edges of the second inorganic encapsulation layer are aligned on the same line.

14. The electronic device according to claim 11, wherein, The first inorganic encapsulation layer is in direct contact with the second inorganic encapsulation layer on the cover layer.

15. The electronic device according to claim 11, wherein, The plurality of inorganic insulating layers include a buffer layer between the substrate and the semiconductor layer of each of the plurality of transistors, and the edge of the buffer layer is separated from the edge of the substrate.

16. The electronic device according to claim 15, wherein, The bottom surface of the groove corresponds to the upper surface of the buffer layer.

17. The electronic device according to claim 15, wherein, The bottom surface of the groove corresponds to the upper surface of the substrate.

18. The electronic device according to any one of claims 11 to 17, wherein, The substrate includes: First polymer resin layer; A first inorganic isolation layer is formed on the first polymer resin layer; A second polymer resin layer is disposed on the first inorganic isolation layer; and The second inorganic isolation layer is located on the second polymer resin layer. The edge of the substrate is defined by the edge of at least one of the first polymer resin layer, the first inorganic insulating layer, and the second polymer resin layer, and The edge of the second inorganic isolation layer is separated from the edge of at least one of the first polymer resin layer, the first inorganic isolation layer, and the second polymer resin layer.

19. The electronic device according to claim 18, wherein, The edges of the second inorganic encapsulation layer and the edges of the second inorganic isolation layer are aligned on the same line.

20. The electronic device according to claim 18, wherein, The groove extends into the second inorganic isolation layer.

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