Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first lead including a carbon-based thin layer upper portion; a variable resistance layer disposed on the first lead; a selector layer disposed on the variable resistance layer, the selector layer having a carbon-based thin layer disposed thereon; and a second lead disposed on the selector layer.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0177199, filed on December 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to semiconductor technology, and more specifically, to semiconductor devices including variable resistor elements and selectors, and methods of manufacturing such semiconductor devices. Background Technology

[0003] In recent years, the demand for miniaturization, low power consumption, high performance, and versatility in electronic devices has required semiconductor devices to store data in various electronic devices, such as computers and portable communication devices. Researchers and industry are working to develop such semiconductor devices. These devices include those that can store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse). Summary of the Invention

[0004] Embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the same. By directly depositing a variable resistance layer on top of a first conductive line, the completeness of the stacked structure of the variable resistance layer can be improved. By forming a second conductive line on top of a selector layer, a wet cleaning process is fully performed during the patterning of the second conductive line, and electrical short circuits between the second conductive lines are improved.

[0005] Furthermore, embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same, which can control the occurrence of shunt faults during the patterning of a variable resistance layer and prevent the degradation of the selector layer by depositing a carbon-containing conductive thin layer on top of the selector and the first conductor.

[0006] According to one embodiment of the present disclosure, a semiconductor device includes: a first conductor including a carbon-based thin film upper portion; a variable resistance layer disposed on the first conductor; a selector layer disposed on the variable resistance layer; and a second conductor disposed on the selector layer.

[0007] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a variable resistance layer on a first conductive line, the first conductive line having a carbon-based thin layer upper portion and a conductive material lower portion; patterning the variable resistance layer into a columnar shape; forming a selector layer on the variable resistance layer; performing a first photolithography process and a first etching process on the selector layer, and performing a second photolithography process and a second etching process on the selector layer to provide a patterned selector layer; and forming a second conductive line on the patterned selector layer. Attached Figure Description

[0008] Figure 1A This is a perspective view showing a semiconductor device according to a comparative scale.

[0009] Figure 1B This is a cross-sectional view of a semiconductor device based on a comparative example.

[0010] Figure 2 This is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 3A to 3H A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0012] Figure 4A and Figure 4B A semiconductor device according to another embodiment of the present disclosure is shown. Detailed Implementation

[0013] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0014] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure more comprehensive and to fully convey the scope of the disclosure to those skilled in the art. In the various drawings and embodiments of this disclosure, the same reference numerals denote the same parts.

[0015] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate. When a first element is referred to as being "on" the second element, it refers not only to the case where the first element is formed directly on the second element, but also to the case where a third element exists between the first element and the second element.

[0016] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element described below may also be referred to as the second or third element without departing from the scope and range of this disclosure.

[0017] Furthermore, it should be understood that when an element is referred to as being located “between” two elements, it can be the only element between the two elements, or there may be one or more intermediate elements.

[0018] As used herein, a “layer” refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire bottom or top layer structure, or its extent may be less than that of the bottom or top layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between or above any pair of horizontal planes between or above the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, may include one or more layers therein, or may have one or more layers located on, above, and / or below it.

[0019] It should be understood that the accompanying drawings are simplified schematic diagrams of the device and may not include well-known details in order to avoid obscuring the features of the embodiments.

[0020] It should also be noted that, without departing from the scope of this disclosure, a feature present in one embodiment may be used in conjunction with one or more features of another embodiment.

[0021] As used in this article, the singular form also includes the plural form, unless the context clearly indicates otherwise.

[0022] Before describing a semiconductor device according to one embodiment of the present disclosure, a semiconductor device according to a comparative example is first described to more clearly reveal the stacked structure of the variable resistor layer and selector layer according to an embodiment of the present disclosure and the resulting effects. Figure 1A This is a perspective view showing a semiconductor device according to a comparative scale. Figure 1B It is along Figure 1A The cross-sectional view shown is taken from lines A-A' and B-B'.

[0023] refer to Figure 1A and Figure 1BThe semiconductor device according to the comparative example may include: a substrate 100; a plurality of first conductive lines 110 disposed on the substrate 100 and extending along a first direction; a plurality of second conductive lines 120 disposed on the first conductive lines 110 and extending along a second direction intersecting the first direction; and a plurality of memory cells MC respectively overlapping the intersection region between the first conductive lines 110 and the second conductive lines 120. The first direction and the second direction may refer to directions substantially parallel to the surface of the substrate 100. Directions substantially perpendicular to the surface of the substrate 100 are hereinafter referred to as perpendicular directions.

[0024] Each of the plurality of storage cells MC may include a storage unit MU (which is the portion where the actual data is stored) and a selector unit SU (which controls access to the storage unit MU). For example, the storage cell MC may include a stacked structure of a lower electrode layer 130, a selector layer 140, an intermediate electrode layer 150, a variable resistor layer 160, and an upper electrode layer 170. The lower electrode layer 130, the selector layer 140, and the intermediate electrode layer 150 may form the selector unit SU. The intermediate electrode layer 150, the variable resistor layer 160, and the upper electrode layer 170 may form the storage unit MU. The intermediate electrode layer 150 may be shared by the selector unit SU and the storage unit MU.

[0025] As shown in the comparative example, SC-MRAM can be fabricated on the first conductor 110 by performing two line patterning processes and two pillar patterning processes. The selector layer 140, variable resistor layer 160, and second conductor 110 have the same design rules. Specifically, the pillar patterning process may require repeated stacking of different hard masks, which significantly increases the total number of processes. As the number of processes increases, the time required to manufacture semiconductor devices becomes longer and the cost becomes higher, and the possibility of errors also increases due to process complexity. Furthermore, alignment with the underlying layers can be problematic in the pillar patterning process. SC-MRAM can be formed from multiple layers, and accurate alignment between layers is crucial. A small error during alignment can significantly affect the performance of the entire device, especially in high-density semiconductor devices, where it can cause serious problems. When patterning multiple layers including the metal layers of SC-MRAM, metal residues can remain in adjacent cells during the etching process. These metal residues can cause bridging, leading to electrical short circuits. The occurrence of bridging can increase electrical interference between cells and reduce the reliability of the memory device.

[0026] To address the issues of the semiconductor devices in the comparative examples, a semiconductor device according to one embodiment of this disclosure may include: a variable resistance layer formed below a selector layer using an ion beam etching process; and a second conductor formed above the selector layer. This improves the completion of the stacked structure of the variable resistance layer, allows for sufficient wet cleaning processes to be performed during the patterning of the second conductor, and improves electrical short circuits between the second conductors.

[0027] Figure 2 This is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure. Reference Figure 2 In the layer structure of the storage cell MC according to an embodiment of the present disclosure, the variable resistor layer 160 may be disposed on the first conductor 110, and the selector layer 140 may be disposed on the variable resistor layer 160.

[0028] The semiconductor device may include a substrate 100, a plurality of first wires 110 disposed on the substrate 100 and extending along a first direction, a plurality of second wires 120 disposed on the first wires 110 and extending along a second direction intersecting the first direction, and a plurality of memory cells MC disposed between the first wires 110 and the second wires 120 and overlapping the intersection region between the first wires 110 and the second wires 120.

[0029] The substrate 100 may contain a semiconductor material, such as silicon. Furthermore, a desired underlying structure (not shown) may be formed in the substrate 100. For example, an integrated circuit for driving the first wire 110 and / or the second wire 120 may be formed in the substrate 100.

[0030] The first conductive wires 110 may be spaced apart from each other along a second direction. The first conductive wires 110 may contain conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc.; metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc.; or combinations thereof. In addition, the first conductive wires 110 may have a single-layer structure or a multi-layer structure.

[0031] The second conductors 120 may be spaced apart from each other in the first direction. The second conductors 120 may contain various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta); metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN); or combinations thereof. The second conductors 120 may have a single-layer structure or a multi-layer structure.

[0032] The lower electrode layer 130 and the upper electrode layer 170 can be disposed at both ends of the memory cell MC, i.e., at the bottom and top of the memory cell MC respectively, and can be used to transmit the voltage or current required for the operation of the memory cell MC. The lower electrode layer 130 can be electrically connected to the variable resistor layer 160, and the upper electrode layer 170 can be electrically connected to the selector layer 140. The intermediate electrode layer 150 can be used to electrically connect the selector layer 140 and the variable resistor layer 160 to each other, and physically disconnect them from each other. The lower electrode layer 130, the intermediate electrode layer 150, and the lower electrode layer 170 can all be formed of the same material or different materials. The lower electrode layer 130, the intermediate electrode layer 150, and the upper electrode layer 170 can all contain conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), etc.; metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc.; or combinations thereof. Furthermore, the lower electrode layer 130, the intermediate electrode layer 150, and the upper electrode layer 170 may all include carbon electrodes. The lower electrode layer 130, the intermediate electrode layer 150, and the lower electrode layer 170 may have the same thickness or different thicknesses.

[0033] Selector layer 140 may have the function of preventing current leakage that may occur between memory cells MC sharing the first conductor 110 or the second conductor 120, and control access to variable resistor layer 160. To this end, selector layer 140 may have threshold switching characteristics: when the voltage levels applied to the upper and lower portions of selector layer 140 are lower than a predetermined threshold voltage level, current is blocked or almost completely suppressed, and then current is allowed to flow rapidly at voltage levels equal to or higher than the threshold voltage level. Selector layer 140 may be turned on at voltage levels equal to or higher than the threshold voltage level, and turned off at voltage levels lower than the threshold voltage level.

[0034] Selector layer 140 may include bidirectional threshold switch (OTS) materials, such as diodes, chalcogenide-based materials, etc.; mixed ion-electron conduction (MIEC) materials, such as metal chalcogenide-based materials; metal-insulator transition (MIT) materials, such as NbO2, VO2, etc.; or tunneling dielectric materials with relatively wide band gaps, such as SiO2, Al2O3, etc.

[0035] Furthermore, selector layer 140 may comprise a dielectric material doped with a dopant. The dielectric material may include silicon-containing dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), dielectric metal oxides, dielectric metal nitrides, or combinations thereof. The dopant may be used to trap conductive carriers migrating within the dielectric material or to create trap sites, providing a pathway for the trapped conductive carriers to migrate again. To form trap sites, various elements capable of generating energy levels in the dielectric material that can accommodate conductive carriers can be used as dopants. For example, when the dielectric material contains silicon, the dopant may comprise a metal with a different valence state than silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or combinations thereof. Furthermore, when the dielectric material contains a metal, the dopant may comprise a metal with a different valence state than that metal or silicon. For example, selector layer 140 may comprise silicon dioxide (SiO2) doped with arsenic (As) or germanium (Ge). When a voltage equal to or higher than a threshold voltage level is applied to the selector layer 140, which contains a dielectric material doped with dopants, a conduction state is achieved in which current flows through the selector layer 140 because conductive charge carriers migrate through trap sites. When the voltage applied to the selector layer 140 is reduced to a voltage level below the threshold voltage, a turn-off state is achieved in which current does not flow because conductive charge carriers do not migrate.

[0036] The variable resistance layer 160 can be a portion used to store data in the memory cell MC. For this purpose, the variable resistance layer 160 can have variable resistance characteristics that switch between different resistance states according to the applied voltage. The variable resistance layer 160 can have a single-layer or multi-layer structure, including various materials used in resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc., such as metal oxides like transition metal oxides, perovskite-based materials, etc., phase-change materials like chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc. For example, the variable resistance layer 160 can include a magnetic tunnel junction structure that can switch between different resistance states by changing the magnetization direction, thereby storing data. When the variable resistance layer 160 has a high resistance state, the memory cell MC can store, for example, data "0", and when the variable resistance layer 160 has a low resistance state, the memory cell MC can store, for example, data "1".

[0037] The storage cell MC may have a columnar shape that overlaps with the intersection area between the first conductor 110 and the second conductor 120. In this figure, the storage cell MC may be shown as a cylinder, but the field and scope of this disclosure are not limited thereto, and the storage cell MC may have various shapes, such as a square cylinder, an elliptical cylinder, etc.

[0038] Furthermore, the layer structure of the memory cell MC is not limited to the structure shown; one or more layers may be omitted or added. For example, one or more of the lower electrode layer 130, the intermediate electrode layer 150, and the upper electrode layer 170 may be omitted. For instance, when the lower electrode layer 130 is omitted, the first conductor 110 may replace the omitted lower electrode layer 130 and perform the function of the lower electrode layer 130; when the upper electrode layer 170 is omitted, the second conductor 120 may replace the omitted upper electrode layer 170 and perform the function of the upper electrode layer 170. Additionally, one or more layers (not shown) may be added to the memory cell MC to improve the process or characteristics of the memory cell MC.

[0039] The following will refer to Figures 3A to 3H This disclosure describes a method for manufacturing a semiconductor device according to the embodiments described above. Detailed descriptions of the constituent elements also appear in [the following text is missing from the original extract]. Figure 2 In the embodiments shown, detailed descriptions may be omitted.

[0040] refer to Figure 3A A first conductive line 210 is formed on a substrate (not shown) having a predetermined lower structure. The first conductive line 210 can be formed by forming a gap-filling layer (not shown) having trenches for forming the first conductive line 210 on the substrate and depositing a conductive layer for forming the first conductive line 210 in the trenches.

[0041] The lower portion of the first conductive wire 210 may contain a metallic material (which is a conductive material), while the upper portion of the first conductive wire 210 may contain carbon or a carbon-based material. The first metal layer 211 can be formed by depositing a metallic material such as tungsten (W), titanium nitride (TiN), titanium (Ti), aluminum (Al), tantalum (Ta), or cobalt (Co) on a substrate using methods such as sputtering or chemical vapor deposition (CVD). After forming the first metal layer 211, the surface can be activated by plasma treatment to increase the adhesion of the carbon-based thin layer deposited thereon, remove impurities, and planarize the surface, or surface contaminants can be removed by a wet cleaning process. A first carbon-based thin layer 212 containing carbon or carbon-based materials such as graphite, carbon nanotubes, graphene, doped carbon, or amorphous carbon can be deposited on the first metal layer 211 using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) processes. Furthermore, when the variable resistance layer 260 is formed on a non-planar surface, the characteristics of the variable resistance layer 260 may deteriorate. Therefore, a planarization process, such as an etch-back process or a chemical mechanical polishing (CMP) process, can be performed on the first carbon-based thin layer 212 to form a stable structure of the variable resistance layer 260. Furthermore, the planarization process can be performed by applying a material with excellent surface roughness to the first carbon-based thin layer 212 to increase density.

[0042] refer to Figure 3BA lower electrode layer material layer and a variable resistance layer material layer are formed on the first conductive line 210. Subsequently, a hard mask layer is formed on the variable resistance layer material layer, and the lower electrode layer material layer and the variable resistance layer material layer are patterned into a columnar shape using the hard mask layer as an etch stop layer. The hard mask layer may include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and may have a single-layer structure or a multilayer structure. The dielectric material may include oxides, nitrides, or a combination thereof. For example, the hard mask layer may include SiO2, SiN4, SiOCN, SiON, polysilicon (Poly-Si), or a combination thereof.

[0043] A columnar lower electrode layer 230 and a variable resistance layer 260 can be formed using a patterning process. The upper portion of the first conductor 210 can be partially recessed, and importantly, this helps control the occurrence of shunt failures that can occur due to the redeposition of etched and lost material from the first metal layer 211 on the sidewalls of the variable resistance layer 260. The presence of a first carbon-based thin layer 212 on the upper portion of the first conductor 210 further facilitates control of these shunt failures.

[0044] refer to Figure 3C After forming the lower electrode layer 230 and the variable resistor layer 260, an interlayer capping layer 261 can be formed to fill the space between the lower electrode layer 230 and the variable resistor layer 260 to effectively prevent interference between memory cells. The interlayer capping layer 261 may contain a dielectric material, polysilicon (Poly-Si), or a combination thereof, and the interlayer capping layer 261 may be formed as a single-layer structure or a multi-layer structure. Oxides, nitrides, or a combination thereof can be used as dielectric materials. For example, the interlayer capping layer 261 may contain SiO2, SiN4, SiOCN, SiON, polysilicon (Poly-Si), or a combination thereof. Subsequently, after planarizing the upper surfaces of the interlayer capping layer 261 and the variable resistor layer 260, an intermediate electrode layer material layer 250 can be formed on the upper surfaces of the interlayer capping layer 261 and the variable resistor layer 260. By planarizing the intermediate electrode layer material layer 250 before depositing the selector layer material layer 240, the intermediate electrode layer material layer 250 can have a planarized upper surface. This process can have a beneficial effect on the formation of the variable resistance layer 260 containing MTJ, where crystal growth and deposition according to the crystallization direction are important, thereby helping to improve the characteristics of the memory cell.

[0045] refer to Figure 3DA selector layer material layer 240 and an upper electrode layer material layer 270 can be formed on top of the intermediate electrode layer material layer 250. To prevent the upper part of the selector layer material layer 240 from directly contacting the second metal layer material layer 272 of the upper electrode layer material layer 270, a second carbon-based thin layer material layer 271 containing carbon or carbon-based materials such as graphite, carbon nanotubes, graphene, doped carbon, or amorphous carbon can be deposited on top of the selector layer material layer 240 using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) processes. The second carbon-based thin layer ( Figure 3E 271A in the middle) can serve as the selector layer formed subsequently ( Figure 3E 240A in the middle) and the upper electrode layer ( Figure 3E The second metal layer of 270A) Figure 3E A physical or chemical barrier is formed between the second metal layer 272A and the selector layer 240A, thereby suppressing reactions or diffusion between them. When the selector layer 240A does not directly contact the second metal layer 272A, performance changes caused by diffusion or chemical reactions of metal atoms that may occur in the selector layer 240A can be reduced. This process maintains the structure and electrical characteristics of the selector layer 240A, improves the performance and stability of the entire memory cell, and prevents the degradation of the selector layer 240A.

[0046] refer to Figure 3E and Figure 3F , can be Figure 3D The stacked structure shown performs a first photolithography process to perform a first patterning process on the selector layer material layer 240, and then performs a second photolithography process to perform a second patterning process on the selector layer material layer 240 to finally form a patterned selector layer 240A.

[0047] refer to Figure 3E , can be Figure 3D The stacked structure shown undergoes a first photolithography process to perform a first patterning and etching process on the selector layer material layer 240. In this process, the first patterning and etching processes are crucial and can significantly impact the pattern accuracy and the final process quality. In the first patterning and etching processes, the etching of the region surrounding the variable resistor layer 260 may be critical. When performing the etching process at this stage, the etching process can be performed up to the height of the variable resistor layer 260 (…). Figure 3E (From the first arrow on the left), it extends to a portion of the first carbon-based thin layer 212 above the first conductor 210 ( Figure 3E (second arrow from the left), or proceed to the first metal layer 211 below the first conductor 210 ( Figure 3E (The third arrow from the left in the middle).

[0048] When the etching process reaches the height of the variable resistance layer 260, the structural stability of the variable resistance layer 260 can be effectively maintained and unnecessary damage can be prevented. Since the variable resistance layer 260 is a very sensitive structure, over-etching can be prevented by etching a stop layer, thereby maintaining the electrical characteristics of the variable resistance layer 260. When the etching process reaches a portion of the first carbon-based thin layer 212 (i.e., the upper part of the first conductor 210), it is beneficial to remove the residue from the etching process of the variable resistance layer 260. Since the residue remaining after the etching process of the variable resistance layer 260 can adversely affect the long-term performance of the memory cell, it is ideal to remove the residue by performing an etching process on the upper part of the first conductor 210. This improves process reliability and helps maintain the accuracy of the electrical connection. When the etching process is performed on the first metal layer 211 below the first conductor 210, the etching depth can be made deep enough to form a pattern on the lower part of the first conductor 210. In this case, it is particularly advantageous to reliably separate the variable resistance layer 260 and the first conductor 210 from each other and remove the residue. Etching the lower part of the first conductor 210 minimizes the possibility of residue residue, thereby further ensuring the long-term performance and reliability of the memory cell.

[0049] Figure 3F A portion of the first carbon-based thin layer 212 is shown (i.e. Figure 3E The stacked structure obtained after the etching process is performed on the upper part of the first conductor 210. (Reference) Figure 3F The first conductor 210 can be patterned using a linear mask pattern (not shown) extending along a first direction. Figure 3E The stacked structure shown undergoes a second photolithography process to perform a second patterning and etching process on the selector layer material layer 240, thereby forming a patterned selector layer 240A. The second patterning and etching process etches at least a portion of the first conductive line 210. This process is important to ensure the accuracy of the pattern formed by the first patterning and etching process and its precise connection to the first conductive line 210. In the second patterning and etching process, a photolithography process can be performed again to further refine the structure formed by the first patterning and etching process. In this process, a conductive line pattern can be formed using a mask, and the first conductive line 210 can be precisely etched. Electrical connection of the first conductive line 210 is ensured in this operation. In the second patterning and etching process, an etching process can be performed on at least a portion of the first conductive line 210, allowing the removal of some material on top of the first conductive line 210 and the formation of the desired pattern. By performing an etching process on a portion of the first conductive line 210, the upper pattern can be reliably connected to the first conductive line 210, minimizing unwanted residue or damage and ensuring the electrical characteristics of the memory cell.

[0050] The upper electrode layer material layer 270, which includes an intermediate electrode layer material layer 250, a second carbon-based thin layer material layer 271, and a second metal layer material layer 272, can be etched together with the selector layer material layer 240 to form a stacked structure in which the intermediate electrode layer 250A, the selector layer 240A, and the upper electrode layer 270A including the second carbon-based thin layer 271A and the second metal layer 272 are stacked sequentially.

[0051] refer to Figure 3G The sidewalls of the patterned variable resistor layer 260 are aligned with the sidewalls of the patterned selector layer 240A, and a gap-filling layer 280 can be formed to fill the space between the aligned variable resistor layer 260 and the selector layer 240A. The gap-filling layer 280 may include a dielectric material. The dielectric material may include oxides, nitrides, or combinations thereof. For example, the gap-filling layer 280 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, such as SiO2, SiN4, SiOCN, SiON, or combinations thereof.

[0052] refer to Figure 3H A second conductive line 220 can be formed on the upper part of the memory cell. The second conductive line 220 can be formed by: forming a trench for forming the second conductive line 220; depositing a conductive layer for forming the second conductive line 220 in the trench; and etching the conductive layer using a line mask pattern (not shown) extending along a second direction. The second conductive line 220 can be patterned along a direction of approximately 90° relative to the first conductive line 210. The first conductive line 210 can be formed along... Figure 2 Extending in the first direction, the second conductor 220 can be formed along... Figure 2 The second direction extends. In this way, a semiconductor device with an intersection structure (in which the memory cells are disposed between the first wire 210 and the second wire 220 that intersect each other) can be manufactured.

[0053] The semiconductor device according to the embodiments of this disclosure can be manufactured using the above-described process. (Reference) Figure 3H It can manufacture semiconductor devices including a first conductor 210 (which includes a first metal layer 211 and a first carbon-based thin layer 212), a lower electrode layer 230, a variable resistor layer 260, an interlayer cover layer 261, an intermediate electrode layer 250A, a selector layer 240A, an upper electrode layer 270A (which includes a second carbon-based thin layer 271 and a second metal layer 272), a gap filler layer 280, and a second conductor 220.

[0054] According to the above-described semiconductor device manufacturing method, since the lower electrode layer 230, variable resistor layer 260, intermediate electrode layer 250A, selector layer 240A, and upper electrode layer 270A are patterned in rows, the number of processes can be reduced compared to existing patterning methods, thereby lowering production costs. By directly depositing the variable resistor layer 260 on the unpatterned but planarized upper portion of the first conductor 210, the effects of heat, plasma, or chemical reactions caused during the patterning of the selector layer 240A on the variable resistor layer 260 can be minimized, and the direct alignment between the variable resistor layer 260 and the first conductor 210 can reduce interlayer alignment errors and improve structural completeness. Furthermore, by forming the variable resistor layer 260 below the selector layer 240A, the variable resistor layer 260 can be deposited before the formation of the selector layer 240A. This simplifies the manufacturing process, improves the reliability of the manufacturing process, and maintains the electrical characteristics of the variable resistor layer 260 well.

[0055] According to embodiments of this disclosure, by forming a second conductor 220 on the upper portion of the selector layer 240A, a wet cleaning process can be freely used as needed during the patterning of the second conductor 220. The wet cleaning process effectively removes impurities or residues remaining from the patterning process. As a result, the clarity and quality of the pattern are improved. Since the selector layer 240A is not affected during the cleaning process, it can be cleaned efficiently without causing any damage. Furthermore, since there is no concern that the selector layer 240A may detach from the lower portion of the second conductor 220 or be damaged, any residues or contaminants that may arise during the wet cleaning process can be thoroughly removed without affecting the selector layer 240A. As a result, performance degradation or defects that may occur due to residues remaining during the patterning process can be reduced, thereby improving the reliability of the storage device. Furthermore, according to embodiments of this disclosure, the interaction between the second conductor 220 and the selector layer 240A during the patterning process can be minimized. After the second conductor 220 is patterned, additional processes or cleaning processes can be performed separately on the top of the selector layer 240A. This reduces the complexity of the patterning process and facilitates process control. Furthermore, since the second conductor 220 is formed on the top of the selector layer 240A, the contact area between the selector layer 240A and the second conductor 220 can be optimized, thereby improving the quality of electrical signal transmission.

[0056] Figure 4A and Figure 4B A semiconductor device according to another embodiment of the present disclosure is shown.

[0057] refer to Figure 4A ,exist Figure 3BIn the process results shown, spacers 265 can be formed on the sidewalls of the variable resistance layer 260. The spacers 265 may include a high-density layer with excellent etch selectivity, for example, a material selected from silicon nitride, tantalum nitride, tungsten, titanium nitride, aluminum oxide, hafnium oxide, and platinum.

[0058] refer to Figure 4B The spacer 265 formed on the sidewall of the variable resistor layer 260 can solve the misalignment problem that may occur during the etching process during the patterning of the selector layer 240A. The side portion of the spacer 265 is self-aligned with the side portion of the selector layer 240A.

[0059] When spacers 265 are formed on the sidewalls of the variable resistor layer 260, the relative alignment with spacers 265 during the etching process is crucial. Therefore, the pattern of the selector layer 240A can automatically align with the pattern of the variable resistor layer 260. This reduces overlap issues and achieves self-alignment. In subsequent processes, when the selector layer 240A is patterned, spacers 265 protect the variable resistor layer 260 and can be used as a reference in the etching process. Because spacers 265 precisely engage with the variable resistor layer 260, the pattern of the selector layer 240A can be aligned via spacers 265 during the etching process. Therefore, the accuracy of the pattern is improved because self-alignment is possible in subsequent processes.

[0060] Furthermore, according to the above-described method for manufacturing semiconductor devices, since the width of the upper portion of the variable resistor layer 260 is reduced according to the patterning characteristics of the variable resistor layer 260, alignment errors relative to the lower portion can be compensated. When the upper portion is smaller and the selector layer 240A and the variable resistor layer 260 require precise alignment, the smaller width of the upper portion makes the alignment error with the wider lower portion less sensitive. Therefore, the permissible misalignment range can be expanded. Furthermore, since the width of the upper portion of the variable resistor layer 260 is smaller, the upper pattern can be formed more precisely within a smaller area. This reduces the likelihood of misalignment, minimizes the possibility of misalignment, reduces the etching range in the patterning process, and facilitates process control. Moreover, according to embodiments of this disclosure, misalignment can be compensated by utilizing a smaller area occupied by the upper portion of the variable resistor layer 260 compared to the lower portion of the variable resistor layer 260. In the patterning process, the smaller structure of the upper portion of the variable resistor layer 260 provides flexibility for the alignment between the lower portion of the variable resistor layer 260 and the selector layer 240A, which effectively reduces the occurrence rate of misalignment.

[0061] According to embodiments of this disclosure, a wet cleaning process can be fully performed during the patterning of the second conductors to prevent electrical short circuits between the second conductors in the semiconductor device, and a method for manufacturing the semiconductor device is also provided.

[0062] Furthermore, according to embodiments of this disclosure, the occurrence of shunt faults during the patterning of the variable resistor layer can be controlled, and the degradation of the selector layer can be prevented.

[0063] While the invention has been described in conjunction with specific embodiments, those skilled in the art will understand that various modifications and improvements can be made without departing from the field and scope of this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: The first conductor includes an upper carbon-based thin layer; A variable resistance layer is disposed on the first conductor; A selector layer is disposed on the variable resistor layer, and a carbon-based thin layer is disposed on the selector layer; and The second conductor is disposed above the selector layer.

2. The semiconductor device according to claim 1, further comprising: A lower electrode layer is disposed between the variable resistance layer and the first wire and is electrically connected to the variable resistance layer.

3. The semiconductor device according to claim 2, wherein, The lower electrode layer contains titanium nitride.

4. The semiconductor device according to claim 1, further comprising: An upper electrode layer is disposed between the selector layer and the second conductor, the upper electrode layer including a lower portion of a carbon-based thin film electrically connected to the selector layer.

5. The semiconductor device according to claim 4, wherein, The upper electrode layer contains titanium nitride.

6. The semiconductor device according to claim 1, further comprising: Spacers disposed on the sidewalls of the variable resistance layer, the spacers comprising a material selected from the group consisting of silicon nitride, tantalum nitride, tungsten, titanium nitride, aluminum oxide, hafnium oxide and platinum.

7. The semiconductor device according to claim 1, further comprising: An intermediate electrode layer having a planarized upper surface is located between the variable resistor layer and the selector layer.

8. The semiconductor device according to claim 1, further comprising: An interlayer cover layer is disposed on the sidewall of the variable resistance layer. The interlayer capping layer has a single-layer structure or a multilayer structure comprising at least one of dielectric material and polycrystalline silicon.

9. The semiconductor device according to claim 1, further comprising: A gap-filling layer is disposed on the sidewalls of the variable resistor layer and the selector layer. The gap filling layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

10. The semiconductor device according to claim 1, wherein: The first conductor extends along a first direction; and The second conductor extends along a second direction that intersects with the first direction.

11. A method for manufacturing a semiconductor device, the method comprising: A variable resistance layer is formed on a first conductor, the first conductor having a carbon-based thin layer upper part and a conductive material lower part; The variable resistance layer is patterned into a columnar shape; A selector layer is formed on top of a patterned variable resistor layer; A first patterning process is performed on the selector layer, including a first photolithography process and a first etching process; A second patterning process, including a second photolithography process and a second etching process, is performed on the selector layer to provide a patterned selector layer; as well as A second conductor is formed on top of the patterned selector layer.

12. The method of claim 11, further comprising: After the selector layer is formed, an upper electrode layer is formed on the selector layer, the upper electrode layer comprising a carbon-based thin film underside.

13. The method of claim 11, further comprising: Spacers are formed by depositing a material selected from the group consisting of silicon nitride, tantalum nitride, tungsten, titanium nitride, aluminum oxide, hafnium oxide, and platinum on the sidewalls of the patterned variable resistance layer.

14. The method according to claim 13, wherein, In the first and second patterning processes of the selector layer, the side portion of the spacer is self-aligned with the side portion of the selector layer.

15. The method of claim 11, further comprising: After patterning the variable resistance layer: Form an intermediate electrode layer; as well as Planarize the intermediate electrode layer.

16. The method of claim 11, further comprising: After the variable resistance layer is patterned, an interlayer capping layer is formed on the side surface of the variable resistance layer. The interlayer capping layer has a single-layer structure or a multilayer structure comprising at least one of dielectric material and polycrystalline silicon.

17. The method of claim 11, further comprising: A gap-filling layer is formed to fill the space between the aligned sidewalls of the variable resistor layer and the selector layer. The gap filling layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

18. The method according to claim 11, wherein, The first etching process is performed on at least a portion of the carbon-based thin layer of the first conductor.

19. The method according to claim 11, wherein, The first etching process is performed on at least a portion of the conductive material of the first wire.

20. The method according to claim 11, wherein, The second etching process is performed on at least a portion of the carbon-based thin layer of the first conductor.

21. The method according to claim 11, wherein, The first conductor is formed to extend along a first direction, and the second conductor is formed to extend along a second direction intersecting the first direction.

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