Advanced logic device oblique interconnect wiring structures and immersion lithography methods
By employing advanced logic device slant interconnect wiring structures and a 193nm immersion lithography platform in semiconductor integrated circuits, the lithography challenges of the traditional Manhattan architecture at the 5nm node have been solved, enabling low-cost, high-yield wiring structure manufacturing and improving device performance and production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT MFG INNOVATION CENT CO LTD
- Filing Date
- 2026-03-16
- Publication Date
- 2026-06-05
AI Technical Summary
In semiconductor integrated circuits at technology nodes of 5nm and below, existing technologies make it difficult to achieve low-cost, high-yield photolithography using traditional Manhattan architecture metal interconnects. Extreme ultraviolet lithography equipment is expensive, and self-aligned quadruple patterning processes are complex and prone to introducing errors.
An advanced logic device slant interconnect wiring structure is adopted, which includes straight lines and slant lines on the same metal layer to form a broken line pattern. The 193nm immersion lithography platform is used for lithography to optimize the wiring topology to reduce wiring track occupation and improve yield.
It enables low-cost, high-yield photolithography of oblique interconnect wiring structures for advanced logic devices, reducing manufacturing costs, increasing wiring density and signal transmission speed, and avoiding the high cost of extreme ultraviolet lithography equipment and the complexity of self-aligned quadruple patterning.
Smart Images
Figure CN122161440A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor design and manufacturing technology, and in particular to an advanced logic device oblique interconnect wiring structure and immersion lithography method. Background Technology
[0002] As semiconductor integrated circuit technology continues to advance towards 5nm and below, following Moore's Law, the number of transistors per unit area is growing exponentially. This high density of device integration poses severe challenges to the interconnect wiring systems in the middle and back ends, especially as the requirements for the minimum linewidth and minimum cycle time of metal interconnects are approaching physical limits. Currently, the traditional Manhattan architecture is commonly used in the layout design of advanced logic devices, where all interconnects are arranged horizontally or vertically. However, when the process node shrinks to 5nm, the cycle time of metal wiring needs to be significantly reduced.
[0003] In existing photolithography solutions, there are mainly two technical paths, but both have significant limitations: The first technical path: multi-patterning technology based on 193nm immersion lithography. This is the main solution when extreme ultraviolet lithography equipment is unavailable. To achieve ultra-fine pitch at 5nm nodes at a wavelength of 193nm, a self-aligned quadruple patterning (SAQP) process is typically required. However, the SAQP process is extremely complex, leading not only to a surge in the number of masks and significantly increasing manufacturing costs, but also to the easy introduction of edge placement errors and linewidth roughness issues during multiple deposition and etching processes, making yield control difficult.
[0004] The second technological path: Extreme Ultraviolet (EUV) lithography. With its ultrashort wavelength of 13.5nm, EUV lithography can solve miniaturization problems through single exposure or simple double exposure, making it the mainstream choice internationally for nodes of 5nm and below. However, EUV lithography equipment is extremely expensive, and maintenance costs are high. Summary of the Invention
[0005] The purpose of this invention is to provide an advanced logic device oblique interconnect wiring structure and an immersion lithography method to solve the problem of how to perform lithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.
[0006] To address the aforementioned technical problems, the present invention provides an advanced logic device oblique interconnect wiring structure, comprising at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a broken line pattern.
[0007] Optionally, in the advanced logic device oblique interconnect wiring structure, the angle between the oblique pattern and the first straight pattern is 0~90°.
[0008] Optionally, in the advanced logic device slanted interconnect wiring structure, the minimum line width of the slanted pattern is determined based on the angle between the slanted pattern and the first straight pattern.
[0009] Optionally, in the aforementioned advanced logic device oblique interconnect wiring structure, when the angle between the oblique pattern and the first straight pattern is 0° to 15°, the minimum linewidth of the oblique pattern is 25nm and the maximum linewidth is 60nm; when the angle between the oblique pattern and the first straight pattern is 15° to 30°, the minimum linewidth of the oblique pattern is 28nm; when the angle between the oblique pattern and the first straight pattern is 30° to 45°, the minimum linewidth of the oblique pattern is 30nm; when the angle between the oblique pattern and the first straight pattern is 45° to 60°, the minimum linewidth of the oblique pattern is 35nm; when the angle between the oblique pattern and the first straight pattern is 60° to 75°, the minimum linewidth of the oblique pattern is 38nm; and when the angle between the oblique pattern and the first straight pattern is 75° to 90°, the minimum linewidth of the oblique pattern is 40nm.
[0010] Optionally, in the aforementioned advanced logic device oblique interconnect wiring structure, the advanced logic device oblique interconnect wiring structure further includes at least one second straight line pattern; the second straight line pattern is located on the same metal layer as the polygonal pattern and is separate from the polygonal pattern.
[0011] Optionally, in the advanced logic device slanted interconnect wiring structure, the minimum spacing between the slanted pattern and the second straight pattern is determined based on the angle between the slanted pattern and the first straight pattern.
[0012] Optionally, in the aforementioned advanced logic device oblique interconnect wiring structure, when the angle between the oblique pattern and the first straight pattern is 0-15°, the minimum spacing between the oblique pattern and the second straight pattern is 45nm; when the angle between the oblique pattern and the first straight pattern is 15°-30°, the minimum spacing between the oblique pattern and the second straight pattern is 50nm; when the angle between the oblique pattern and the first straight pattern is 30°-45°, the minimum spacing between the oblique pattern and the second straight pattern is 55nm; when the angle between the oblique pattern and the first straight pattern is 45°-60°, the minimum spacing between the oblique pattern and the second straight pattern is 65nm; when the angle between the oblique pattern and the first straight pattern is 60°-75°, the minimum spacing between the oblique pattern and the second straight pattern is 60nm; and when the angle between the oblique pattern and the first straight pattern is 75°-90°, the minimum spacing between the oblique pattern and the second straight pattern is 50nm.
[0013] Optionally, in the aforementioned advanced logic device slant interconnect wiring structure, the advanced logic device slant interconnect wiring structure is used for the back-end interconnect process in the 5nm technology node.
[0014] To address the aforementioned technical problems, the present invention also provides an immersion lithography method, the immersion lithography method comprising: Photolithography is used to form the advanced logic device slant interconnect wiring structure as described in any of the preceding items.
[0015] Optionally, in the immersion lithography method, the light source wavelength used for photolithography etching is 193 nm.
[0016] The present invention provides an advanced logic device oblique interconnect wiring structure and an immersion lithography method, comprising at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a broken line pattern. By optimizing the wiring topology and adding the oblique line pattern, it is possible to form a high-yield advanced logic device interconnect wiring structure using a mature and low-cost 193nm immersion lithography platform, thus solving the problem of how to perform photolithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the advanced logic device oblique interconnect wiring structure provided in this embodiment; Figure 2 This is a schematic diagram illustrating the dimensions of the advanced logic device slant interconnect wiring structure provided in this embodiment; Figure 3A schematic diagram of the oblique interconnect wiring structure of an advanced logic device provided in this embodiment; Figure 4 This is a schematic diagram of the advanced logic device slant interconnect wiring structure under scenario two provided in this embodiment; The labels in the attached figures are explained as follows: 110 - First straight line pattern; 120 - Diagonal line pattern; 130 - Second straight line pattern; 200 - Signal node. Detailed Implementation
[0018] The advanced logic device oblique interconnect wiring structure and immersion lithography method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0020] This embodiment provides an advanced logic device oblique interconnect wiring structure, such as Figure 1 As shown, it includes at least two first straight line patterns 110 and at least one oblique line pattern 120 located on the same metal layer; the two ends of the oblique line pattern 120 are respectively connected to the ends of the two first straight line patterns 110 to form a broken line pattern.
[0021] The advanced logic device oblique interconnect wiring structure provided in this embodiment, by optimizing the wiring topology and adding oblique lines, not only occupies fewer wiring tracks in a unit wiring area, but also relies on a mature and low-cost 193nm immersion lithography platform to form a high-yield advanced logic device interconnect wiring structure, thus solving the problem of how to perform lithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.
[0022] Specifically, in this embodiment, the first straight line pattern 110 is used to connect two signal nodes 200 located in different rows and / or different columns. Furthermore, in practical applications, the first straight line pattern 110 and the diagonal line pattern 120 can be located within the first metal layer M1.
[0023] In practical applications, by connecting the ends of two first straight lines 110 located in different rows and columns with diagonal lines 120, a broken line pattern is formed, which greatly reduces the wiring path. While improving the wiring area utilization rate, it can also reduce interconnect resistance and signal transmission delay by utilizing shorter signal transmission paths, thereby improving the overall operating speed of advanced logic devices.
[0024] Of course, in other embodiments, different methods can be obtained according to actual needs. Figure 1 The wiring structure shown is illustrated. Furthermore, the position and connection angle of the diagonal lines can be appropriately set according to actual needs, such as the location of signal nodes and connection requirements. Additionally, multiple polygonal lines can be designed within the same interconnect wiring structure, based on actual needs.
[0025] Preferably, in order to meet the requirements of the all-angle manufacturing process, in this embodiment, such as Figure 2 As shown, the angle α between the oblique line figure 120 and the first straight line figure 110 is 0~90°.
[0026] In practical applications, the minimum line width w of the oblique line pattern 120 is determined according to the angle α between the oblique line pattern 120 and the first straight line pattern 110.
[0027] Specifically, in order to meet the requirements of omnidirectional manufacturing processes, in this embodiment, such as Figure 2 As shown, when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 0~15°, the line width w of the oblique line pattern 120 is at least 25nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 15°~30°, the line width w of the oblique line pattern 120 is at least 28nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 30°~45°, the line width w of the oblique line pattern 120 is at least 30nm. When the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 45°~60°, the line width w of the oblique line pattern 120 is at least 35nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 60°~75°, the line width w of the oblique line pattern 120 is at least 38nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 75°~90°, the line width w of the oblique line pattern 120 is at least 40nm.
[0028] Preferably, to ensure that the electrical performance of the wiring conforms to the wiring logic rules, the maximum line width of the diagonal pattern 120 can also be limited. In this embodiment, such as Figure 2 As shown, when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 0° to 15°, the line width w of the oblique line pattern 120 is at most 60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 15° to 30°, the line width w of the oblique line pattern 120 is at most 60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 30° to 45°, the line width w of the oblique line pattern 120 is at most 60nm. When the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 45°~60°, the line width w of the oblique line pattern 120 is at most 60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 60°~75°, the line width w of the oblique line pattern 120 is at most 45nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 75°~90°, the line width w of the oblique line pattern 120 is at most 45nm.
[0029] In one specific embodiment, when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 15°, the linewidth w of the oblique line pattern 120 is 25nm~60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 30°, the linewidth w of the oblique line pattern 120 is 28nm~60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 45°, the linewidth w of the oblique line pattern 120 is 30nm~60nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 60°, the linewidth w of the oblique line pattern 120 is 35nm~45nm; and when the angle between the oblique line pattern 120 and the first straight line pattern 110 is 75°, the linewidth w of the oblique line pattern 120 is 38nm~45nm.
[0030] Furthermore, in this embodiment, as Figure 2 As shown, the advanced logic device oblique interconnect wiring structure further includes at least one second straight line pattern 130; the second straight line pattern 130 is located on the same metal layer as the polygonal pattern but is separate from the polygonal pattern. That is, the second straight line pattern 130 is not connected to the first straight line pattern 110 and the oblique line pattern 120, and is an independent pattern structure.
[0031] Specifically, in this embodiment, the second straight line pattern 130 is arranged parallel to the first straight line pattern 110, thereby reducing wiring complexity and minimizing circuit interference caused by the angle between disconnected wiring.
[0032] In practical applications, the minimum distance between the oblique line graphic 120 and the second straight line graphic 130 is determined according to the angle α between the oblique line graphic 120 and the first straight line graphic 110.
[0033] Specifically, to meet the electrical insulation and process requirements under the all-angle manufacturing process, and to ensure the process safety distance between the connection between the inclined and straight edges and between the wire ends to avoid circuit interference, in this embodiment, when the angle α between the inclined line pattern 120 and the first straight line pattern 110 is 0~15°, the minimum distance between the inclined line pattern 120 and the second straight line pattern 130 is 45nm; when the angle α between the inclined line pattern 120 and the first straight line pattern 110 is 15°~30°, the minimum distance between the inclined line pattern 120 and the second straight line pattern 130 is 50nm; when the angle α between the inclined line pattern 120 and the first straight line pattern 110 is 30°~45°, The minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 55 nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 45°~60°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 65 nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 60°~75°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 60 nm; when the angle between the oblique line pattern 120 and the first straight line pattern 110 is 75°~90°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 50 nm. Wherein, for example... Figure 2 As shown, the minimum spacing is the point-to-line distance d1 between the end of the second straight line figure 130 closest to the oblique line figure 120 and the oblique line figure 120. Of course, in practical applications, the minimum spacing also includes the distance between two points of the oblique line figure 120 and the second straight line figure 130 that are close to each other.
[0034] In one specific embodiment, when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 15°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 45nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 30°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 50nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 45°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 55nm; when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 60°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 60nm; and when the angle α between the oblique line pattern 120 and the first straight line pattern 110 is 75°, the minimum spacing between the oblique line pattern 120 and the second straight line pattern 130 is 50nm.
[0035] It should be noted that in this embodiment, the first straight line pattern 110, the diagonal line pattern 120, and the second straight line pattern 130 are located in the same mask pattern, that is, the first straight line pattern 110, the diagonal line pattern 120, and the second straight line pattern 130 are formed synchronously in one photolithography process using the same mask. Therefore, in order to ensure the reliability and process feasibility of the formed diagonal interconnect wiring structure, it is necessary to meet the above-mentioned requirements for line width and spacing.
[0036] Of course, in other embodiments, multiple sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 can be formed through multiple photolithography processes. That is, different sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 are located in different mask patterns. In this case, since the different sets of mask patterns are not formed by the same photolithography process, the line width and spacing of the different sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 do not need to follow the above requirements.
[0037] For example, the line width and spacing of the first straight line pattern 110, the diagonal line pattern 120 and the second straight line pattern 130 located in the same mask pattern A need to meet the above requirements, while the spacing between the diagonal line pattern 120 located in mask pattern A and the second straight line pattern 130 located in mask pattern B does not need to meet the above requirements.
[0038] The advanced logic device oblique interconnect wiring structure provided in this embodiment is used in the back-end interconnect process of the 5nm technology node. It can be adapted to dual patterning technology based on 193nm immersion lithography, improving wiring density and lithographic imaging reliability by reducing wiring track occupancy.
[0039] Simulation was performed using a photolithography simulator, setting 193nm immersion lithography conditions, to verify the oblique interconnect wiring structure of the advanced logic device provided in this embodiment. The minimum period of the zigzag pattern is 96nm, resulting in: Scenario 1: For example Figure 3 As shown, for a single broken line pattern, when the included angle of the diagonal line pattern 120 meets the above-mentioned included angle range and the line width meets the above-mentioned line width range, it can be guaranteed to have 8% EL (Exposure Latitude), which meets the requirements of the mid-to-late stage process window.
[0040] Scenario 2: For example Figure 4 As shown, in the case of a broken line graphic and a second straight line graphic, when the included angle of the oblique line graphic 120 meets the above-mentioned included angle range, the line width meets the above-mentioned line width range, and the minimum distance between the oblique line graphic 120 and the second straight line graphic 130 meets the above-mentioned minimum distance requirement, it can be guaranteed to have 8% EL (Exposure Latitude), which meets the requirements of the mid-to-late stage process window.
[0041] This embodiment also provides an immersion lithography method, including: photolithographic etching to form an advanced logic device oblique interconnect wiring structure as described above.
[0042] Specifically, in this embodiment, when there are multiple mask patterns, each mask pattern can be photolithographically etched sequentially, wherein at least one mask pattern contains the advanced logic device oblique interconnect wiring structure provided in this embodiment.
[0043] In practical applications, the existing mature 193nm immersion lithography equipment in China, combined with double exposure technology, can be used to achieve high-quality manufacturing of the interconnect wiring structure of 5nm advanced logic devices without the need for extreme ultraviolet lithography or quadruple patterning processes, thus reducing the process difficulty and manufacturing cost.
[0044] During the design phase, potential lithography defects can be avoided in advance, ensuring the manufacturability of the design scheme under the 193nm lithography process, thereby achieving high yield in mass production.
[0045] When using double exposure technology, the mask can be split into a first mask pattern and a second mask pattern based on the characteristics of the wiring structure and lithography parameters. The splitting principle is to ensure that the pattern period on the same mask meets the minimum resolution requirement of 193 nm lithography (usually greater than 80 nm). In this embodiment, the period of adjacent vertical lines in the same mask is 96 nm.
[0046] The immersion lithography method provided in this embodiment, combined with the advanced logic device oblique interconnect wiring structure provided in this embodiment, can obtain a clear edge contour with good contrast, without the risk of bridging or breakage. It can realize the manufacturing of advanced logic device interconnect wiring structures of technology nodes of 5nm and below using the mass production process of 193 nm immersion lithography.
[0047] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0048] The advanced logic device oblique interconnect wiring structure and immersion lithography method provided in this embodiment include at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a broken line pattern. By optimizing the wiring topology and adding oblique line patterns, it is possible to form a high-yield advanced logic device interconnect wiring structure using a mature and low-cost 193nm immersion lithography platform, thus solving the problem of how to perform photolithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.
[0049] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. An advanced logic device oblique interconnect wiring structure, characterized in that, It includes at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a broken line pattern.
2. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The angle between the oblique line and the first straight line is 0~90°.
3. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The minimum line width of the oblique line graphic is determined based on the angle between the oblique line graphic and the first straight line graphic.
4. The advanced logic device oblique interconnect wiring structure according to claim 3, characterized in that, When the angle between the oblique line and the first straight line is 0° to 15°, the minimum linewidth of the oblique line is 25nm; when the angle is 15° to 30°, the minimum linewidth of the oblique line is 28nm; when the angle is 30° to 45°, the minimum linewidth of the oblique line is 30nm; when the angle is 45° to 60°, the minimum linewidth of the oblique line is 35nm; when the angle is 60° to 75°, the minimum linewidth of the oblique line is 38nm; and when the angle is 75° to 90°, the minimum linewidth of the oblique line is 40nm.
5. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The advanced logic device oblique interconnect wiring structure further includes at least one second straight line pattern; the second straight line pattern is located on the same metal layer as the broken line pattern and is separate from the broken line pattern.
6. The advanced logic device oblique interconnect wiring structure according to claim 5, characterized in that, The minimum distance between the oblique line graphic and the second straight line graphic is determined based on the angle between the oblique line graphic and the first straight line graphic.
7. The advanced logic device oblique interconnect wiring structure according to claim 6, characterized in that, When the angle between the oblique line and the first straight line is 0° to 15°, the minimum spacing between the oblique line and the second straight line is 45nm; when the angle between the oblique line and the first straight line is 15° to 30°, the minimum spacing between the oblique line and the second straight line is 50nm; when the angle between the oblique line and the first straight line is 30° to 45°, the minimum spacing between the oblique line and the second straight line is 55nm; when the angle between the oblique line and the first straight line is 45° to 60°, the minimum spacing between the oblique line and the second straight line is 65nm; when the angle between the oblique line and the first straight line is 60° to 75°, the minimum spacing between the oblique line and the second straight line is 60nm; when the angle between the oblique line and the first straight line is 75° to 90°, the minimum spacing between the oblique line and the second straight line is 50nm.
8. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The advanced logic device slant interconnect wiring structure is used in the back-end interconnect process of the 5nm technology node.
9. An immersion lithography method, characterized in that, The immersion lithography method includes: Photolithography is used to form the advanced logic device oblique interconnect wiring structure as described in any one of claims 1 to 8.
10. The immersion lithography method according to claim 9, characterized in that, The light source used for photolithography etching has a wavelength of 193nm.