Advanced logic device oblique interconnect wiring structures and immersion lithography methods

Abstract

The application provides an advanced logic device oblique interconnection wiring structure and an immersion lithography method, which comprises at least two first straight line patterns and at least one oblique line pattern in the same metal layer; two ends of the oblique line pattern are connected with the end portions of the two first straight line patterns respectively to form a U-shaped pattern. By optimizing the wiring topology structure and increasing the oblique line pattern, the high-yield advanced logic device interconnection wiring structure can be formed by relying on the mature and low-cost 193nm immersion lithography platform, and the problem of how to perform lithography on the advanced logic device oblique interconnection wiring structure at low cost and high yield is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor design and manufacturing technology, and in particular to an advanced logic device oblique interconnect wiring structure and immersion lithography method. Background Technology

[0002] As semiconductor integrated circuit technology continues to advance towards 5nm and below, following Moore's Law, the number of transistors per unit area is growing exponentially. This high density of device integration poses severe challenges to the interconnect wiring systems in the middle and back ends, especially as the requirements for the minimum linewidth and minimum cycle time of metal interconnects are approaching physical limits. Currently, the traditional Manhattan architecture is commonly used in the layout design of advanced logic devices, where all interconnects are arranged horizontally or vertically. However, when the process node shrinks to 5nm, the cycle time of metal wiring needs to be significantly reduced.

[0003] In existing photolithography solutions, there are mainly two technical paths, but both have significant limitations: The first technical path: multi-patterning technology based on 193nm immersion lithography. This is the main solution when extreme ultraviolet lithography equipment is unavailable. To achieve ultra-fine pitch at 5nm nodes at a wavelength of 193nm, a self-aligned quadruple patterning (SAQP) process is typically required. However, the SAQP process is extremely complex, leading not only to a surge in the number of masks and significantly increasing manufacturing costs, but also to the easy introduction of edge placement errors and linewidth roughness issues during multiple deposition and etching processes, making yield control difficult.

[0004] The second technological path: Extreme Ultraviolet (EUV) lithography. With its ultrashort wavelength of 13.5nm, EUV lithography can solve miniaturization problems through single exposure or simple double exposure, making it the mainstream choice internationally for nodes of 5nm and below. However, EUV lithography equipment is extremely expensive, and maintenance costs are high. Summary of the Invention

[0005] The purpose of this invention is to provide an advanced logic device oblique interconnect wiring structure and an immersion lithography method to solve the problem of how to perform lithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.

[0006] To address the aforementioned technical problems, the present invention provides an advanced logic device oblique interconnect wiring structure, comprising at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a U-shaped pattern.

[0007] Optionally, in the advanced logic device oblique interconnect wiring structure, the angle between the oblique pattern and the first straight pattern is 0~90°.

[0008] Optionally, in the aforementioned advanced logic device oblique interconnect wiring structure, the minimum linewidth of the oblique pattern is 50nm~65nm.

[0009] Optionally, in the advanced logic device slanted interconnect wiring structure, when the advanced logic device slanted interconnect wiring structure includes multiple slanted patterns, the minimum spacing between the slanted patterns is 50nm~65nm.

[0010] Optionally, in the aforementioned advanced logic device slanted interconnect wiring structure, the advanced logic device slanted interconnect wiring structure further includes at least one second straight line pattern; the second straight line pattern is located on the same metal layer as the U-shaped pattern and is separate from the U-shaped pattern.

[0011] Optionally, in the advanced logic device slant interconnect wiring structure, the minimum spacing between the end of the second straight line pattern closest to the slant pattern and the slant pattern is 40nm~70nm; the minimum spacing between the end of the second straight line pattern closest to the slant pattern and the end of the slant pattern closest to the second straight line pattern is 40nm~70nm.

[0012] Optionally, in the aforementioned advanced logic device slant interconnect wiring structure, the advanced logic device slant interconnect wiring structure further includes a shearing layer; the shearing layer is used to remove redundant wiring.

[0013] Optionally, in the aforementioned advanced logic device slant interconnect wiring structure, the advanced logic device slant interconnect wiring structure is used for the back-end interconnect process in the 5nm technology node.

[0014] To address the aforementioned technical problems, the present invention also provides an immersion lithography method, the immersion lithography method comprising: Photolithography is used to form the oblique interconnect wiring structure of the advanced logic device as described in any of the preceding items.

[0015] Optionally, in the immersion lithography method, the light source wavelength used for photolithography etching is 193 nm.

[0016] The present invention provides an advanced logic device oblique interconnect wiring structure and an immersion lithography method, comprising at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a U-shaped pattern. By optimizing the wiring topology and adding the oblique line pattern, it is possible to form a high-yield advanced logic device interconnect wiring structure using a mature and low-cost 193nm immersion lithography platform, thus solving the problem of how to perform photolithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the advanced logic device oblique interconnect wiring structure provided in this embodiment; Figure 2 This is a schematic diagram illustrating the dimensions of the advanced logic device slant interconnect wiring structure provided in this embodiment; Figure 3 This is a schematic diagram of the oblique interconnect wiring structure of the advanced logic device with a shear layer provided in this embodiment; Figure 4 A schematic diagram of the oblique interconnect wiring structure of an advanced logic device provided in this embodiment; Figure 5 This is a schematic diagram of the advanced logic device slant interconnect wiring structure under scenario two provided in this embodiment; Figure 6 This is a schematic diagram of the advanced logic device slant interconnect wiring structure under scenario three provided in this embodiment; The labels in the attached figures are explained as follows: 110 - First straight line pattern; 120 - Diagonal line pattern; 130 - Second straight line pattern; 200 - Signal node; 300 - Shear layer. Detailed Implementation

[0018] The advanced logic device oblique interconnect wiring structure and immersion lithography method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] This embodiment provides an advanced logic device oblique interconnect wiring structure, such as Figure 1 As shown, it includes at least two first straight line patterns 110 and at least one oblique line pattern 120 located on the same metal layer; the two ends of the oblique line pattern 120 are respectively connected to the ends of the two first straight line patterns 110 to form a U-shaped pattern.

[0021] The advanced logic device oblique interconnect wiring structure provided in this embodiment, by optimizing the wiring topology and adding oblique lines, not only occupies fewer wiring tracks in a unit wiring area, but also relies on a mature and low-cost 193nm immersion lithography platform to form a high-yield advanced logic device interconnect wiring structure, thus solving the problem of how to perform lithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.

[0022] Specifically, in this embodiment, the first straight line pattern 110 is used to connect two signal nodes 200 located in different rows and / or different columns. Furthermore, in practical applications, the first straight line pattern 110 and the diagonal line pattern 120 can be located within the first metal layer M1.

[0023] In practical applications, by connecting the ends of two first straight lines 110 located in different rows and columns with diagonal lines 120, a U-shaped shape is formed, which greatly reduces the wiring path. While improving the wiring area utilization rate, it can also reduce interconnect resistance and signal transmission delay by utilizing shorter signal transmission paths, thereby improving the overall operating speed of advanced logic devices.

[0024] Of course, in other embodiments, different methods can be obtained according to actual needs. Figure 1 The wiring structure shown can be adjusted according to actual needs, such as the location of signal nodes and connection requirements, by setting the position and connection angle of the diagonal lines. Furthermore, multiple U-shaped patterns can be designed within the same interconnect wiring structure based on actual needs.

[0025] Preferably, in order to meet the requirements of the all-angle manufacturing process, in this embodiment, such as Figure 2 As shown, Figure 2 As shown, the angle α between the oblique line figure 120 and the first straight line figure 110 is 0~90°.

[0026] Furthermore, in order to meet the requirements of omnidirectional manufacturing processes, in this embodiment, such as Figure 2 As shown, the minimum linewidth w of the oblique line pattern 120 is 40nm~70nm. For example, the minimum linewidth w of the oblique line pattern 120 is not less than 60nm. In practical applications, the specific value of the minimum linewidth w can be reasonably set within the above range according to process requirements, device size, and electrical requirements.

[0027] Furthermore, in order to meet the electrical insulation and process requirements under the all-angle manufacturing process, in this embodiment, when the advanced logic device oblique interconnect wiring structure includes multiple oblique lines 120, the minimum spacing between the oblique lines 120 is 50nm~65nm, for example, the minimum spacing between the oblique lines 120 is not less than 60nm.

[0028] Furthermore, in this embodiment, as Figure 2 As shown, the advanced logic device oblique interconnect wiring structure further includes at least one second straight line pattern 130; the second straight line pattern 130 is located on the same metal layer as the U-shaped pattern but is separate from the U-shaped pattern. That is, the second straight line pattern 130 is not connected to the first straight line pattern 110 and the oblique line pattern 120, and is an independent pattern structure.

[0029] Specifically, in this embodiment, the second straight line pattern 130 is arranged parallel to the first straight line pattern 110, thereby reducing wiring complexity and minimizing circuit interference caused by the angle between disconnected wiring.

[0030] In practical applications, the U-shaped figure can wrap around the second straight line figure 130, and can even wrap around all or part of other U-shaped figures. This application does not impose any restrictions on this.

[0031] In order to ensure the process safety distance at the connection between the hypotenuse and the straight edge and between the line ends, in this embodiment, as follows: Figure 2As shown, the minimum distance d1 between the end of the second straight line pattern 130 near the inclined side pattern 120 and the inclined side pattern 120 is 40nm~70nm. For example, the minimum distance d1 between the end of the second straight line pattern 130 near the inclined side pattern 120 and the inclined side pattern 120 is not less than 65nm; the minimum distance d2 between the end of the second straight line pattern 130 near the inclined side pattern 120 and the end of the inclined side pattern 120 near the second straight line pattern 130 is 40nm~70nm. For example, the minimum distance d2 between the end of the second straight line pattern 130 near the inclined side pattern 120 and the end of the inclined side pattern 120 near the second straight line pattern 130 is not less than 60nm.

[0032] Furthermore, in this embodiment, the minimum line-end spacing between adjacent first straight line patterns 110 is 40nm~70nm; the minimum line-end spacing between adjacent second straight line patterns 130 is 40nm~70nm; and the minimum line-end spacing between adjacent first straight line patterns 110 and second straight line patterns 130 is 40nm~70nm.

[0033] In practical applications, the specific value of the minimum spacing between the first straight line pattern 110, the oblique line pattern 120 and the second straight line pattern 130 can be reasonably set within the above range according to process requirements, device size and electrical requirements.

[0034] It should be noted that in this embodiment, the first straight line pattern 110, the diagonal line pattern 120, and the second straight line pattern 130 are located in the same mask pattern, that is, the first straight line pattern 110, the diagonal line pattern 120, and the second straight line pattern 130 are formed synchronously in one photolithography process using the same mask. Therefore, in order to ensure the reliability and process feasibility of the formed diagonal interconnect wiring structure, it is necessary to meet the above-mentioned requirements for line width and spacing.

[0035] Of course, in other embodiments, multiple sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 can be formed through multiple photolithography processes. That is, different sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 are located in different mask patterns. In this case, since the different sets of mask patterns are not formed by the same photolithography process, the line width and spacing of the different sets of first straight line patterns 110, oblique line patterns 120 and second straight line patterns 130 do not need to follow the above requirements.

[0036] For example, the line width and spacing of the first straight line pattern 110, the diagonal line pattern 120 and the second straight line pattern 130 located in the same mask pattern A need to meet the above requirements, while the spacing between the diagonal line pattern 120 located in mask pattern A and the second straight line pattern 130 located in mask pattern B does not need to meet the above requirements.

[0037] Preferably, in order to form the final breakpoint, in this embodiment, as follows: Figure 3 As shown, the advanced logic device oblique interconnect wiring structure also includes a shearing layer 300; the shearing layer 300 is used to remove redundant wiring. In practical applications, the location and number of shearing layers 300 can be reasonably set according to requirements, and this application does not impose any restrictions on this.

[0038] The advanced logic device oblique interconnect wiring structure provided in this embodiment is used in the back-end interconnect process of the 5nm technology node. It can be adapted to dual patterning technology based on 193nm immersion lithography, improving wiring density and lithographic imaging reliability by reducing wiring track occupancy.

[0039] Simulations were performed using a spatial image simulator, with 193nm immersion lithography (numerical aperture NA=1.35, dipole illumination, partial coherence factor σ0.65~0.85) conditions. The advanced logic device oblique interconnect wiring structure provided in this embodiment was then simulated and verified, and the following results were obtained: Scenario 1: For example Figure 4 As shown, for the case where two single first straight lines 110 are connected by a diagonal line 120 to form a U-shaped shape, when the line width of the diagonal line 120 meets the above line width range, it can guarantee 8% EL (Exposure Latitude) at any angle within the included angle range, thus meeting the requirements of the mid-to-late stage process window.

[0040] Scenario 2: For example Figure 5 As shown, for two U-shaped patterns with their diagonal lines 120 facing each other and their first straight lines 110 parallel, as the angle between the diagonal lines 120 increases, the same spacing can achieve a larger EL (determined by the Dipole light source); and when the line width of the diagonal lines 120 meets the above line width range, an 8% EL (Exposure Latitude) can be guaranteed at any angle within the angle range, meeting the requirements of the mid-to-late stage process window.

[0041] Scenario 3: For example Figure 6As shown, for a U-shaped pattern, where the two ends of the diagonal line 120 in the U-shaped pattern are respectively provided with second straight lines 130, and the second straight lines 130 are parallel to the first straight lines, the larger the angle of the diagonal line 120, the smaller the vertical distance from the line end to the diagonal line 120. When the line width of the diagonal line 120 meets the above line width range and the distance between the diagonal line 120 and the second straight line 130 meets the above distance range, the diagonal line 120 can guarantee 8% EL (Exposure Latitude) at any angle within the included angle range, meeting the requirements of the mid-to-late stage process window.

[0042] This embodiment also provides an immersion lithography method, which includes: photolithographic etching to form the advanced logic device oblique interconnect wiring structure as described above.

[0043] Specifically, in this embodiment, when there are multiple mask patterns, each mask pattern can be photolithographically etched sequentially, wherein at least one mask pattern contains the advanced logic device oblique interconnect wiring structure provided in this embodiment. For example, for Figure 3 When photolithographically etching the advanced logic device oblique interconnect wiring structure shown, the U-shaped pattern formed by the first straight line pattern 110 and the oblique line pattern 120 can be used as a mask pattern, and all the second straight line patterns 130 can be used as another mask pattern, thereby obtaining the advanced logic device oblique interconnect wiring structure step by step through photolithography. Of course, in other embodiments, the first straight line pattern 110, the oblique line pattern 120, and the second straight line pattern 130 can also be divided into different mask patterns for step-by-step photolithography formation according to actual needs and wiring logic rules. Furthermore, the number of mask patterns obtained can also be determined according to actual needs, and this application does not impose any limitations on this.

[0044] In practical applications, the existing mature 193nm immersion lithography equipment in China, combined with double exposure technology, can be used to achieve high-quality manufacturing of the interconnect wiring structure of 5nm advanced logic devices without the need for extreme ultraviolet lithography or quadruple patterning processes, thus reducing the process difficulty and manufacturing cost.

[0045] During the design phase, potential lithography defects can be avoided in advance, ensuring the manufacturability of the design scheme under the 193nm lithography process, thereby achieving high yield in mass production.

[0046] When using double exposure technology, the advanced logic device oblique interconnect wiring structure provided in this embodiment can be split into a first mask pattern and a second mask pattern. The splitting principle is to ensure that the pattern period on the same mask meets the minimum resolution requirement of 193 nm lithography (usually greater than 80 nm). In this embodiment, the period of adjacent vertical lines in the same mask is 96 nm.

[0047] The immersion lithography method provided in this embodiment, combined with the advanced logic device oblique interconnect wiring structure provided in this embodiment, can obtain a clear edge contour with good contrast, without the risk of bridging or breakage. It can realize the manufacturing of advanced logic device interconnect wiring structures of technology nodes of 5nm and below using the mass production process of 193 nm immersion lithography.

[0048] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0049] The advanced logic device oblique interconnect wiring structure and immersion lithography method provided in this embodiment include at least two first straight line patterns and at least one oblique line pattern located on the same metal layer; the two ends of the oblique line pattern are respectively connected to the ends of the two first straight line patterns to form a U-shaped pattern. By optimizing the wiring topology and adding oblique line patterns, it is possible to form high-yield advanced logic device interconnect wiring structures using a mature and low-cost 193nm immersion lithography platform, thus solving the problem of how to perform photolithography on the oblique interconnect wiring structure of advanced logic devices at low cost and high yield.

[0050] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An advanced logic device oblique interconnect wiring structure, characterized in that, It includes at least two first straight lines and at least one oblique line on the same metal layer; the two ends of the oblique line are respectively connected to the ends of the two first straight lines to form a U-shaped pattern.

2. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The angle between the oblique line and the first straight line is 0~90°.

3. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The minimum line width of the oblique line pattern is 50nm~65nm.

4. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, When the advanced logic device slant interconnect wiring structure includes multiple slant patterns, the minimum spacing between the slant patterns is 50nm~65nm.

5. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The advanced logic device slant interconnect wiring structure further includes at least one second straight line pattern; the second straight line pattern is located on the same metal layer as the U-shaped pattern and is separate from the U-shaped pattern.

6. The advanced logic device oblique interconnect wiring structure according to claim 5, characterized in that, The minimum distance between the end of the second straight line pattern closest to the inclined edge pattern and the inclined edge pattern is 40nm~70nm; the minimum distance between the end of the second straight line pattern closest to the inclined edge pattern and the end of the inclined edge pattern closest to the second straight line pattern is 40nm~70nm.

7. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The advanced logic device slant interconnect wiring structure also includes a shearing layer; the shearing layer is used to remove redundant wiring.

8. The advanced logic device oblique interconnect wiring structure according to claim 1, characterized in that, The advanced logic device slant interconnect wiring structure is used in the back-end interconnect process of the 5nm technology node.

9. An immersion lithography method, characterized in that, The immersion lithography method includes: Photolithography is used to form the advanced logic device oblique interconnect wiring structure as described in any one of claims 1 to 8.

10. The immersion lithography method according to claim 8, characterized in that, The light source used for photolithography etching has a wavelength of 193nm.

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