Semiconductor chip packaging method and semiconductor chip

Abstract

The application relates to the field of semiconductor chip packaging, in particular to a semiconductor chip packaging method and a semiconductor chip. The semiconductor chip comprises a lead frame, a wafer and a pin arranged on the lead frame, the wafer and the pin are packaged on the lead frame by epoxy resin to form a packaging unit, the packaging unit and the packaging unit are a cutting area to be cut, a half-cut process based on a wettable packaging technology is used to form a cutting groove on the cutting area to be cut, and epoxy resin residues are formed in the cutting groove and between the cutting groove and the pin; the laser cutting is used to remove the epoxy resin residues, so as to clean the inner wall area of the cutting groove. The laser cutting machining mode is used to replace the traditional blade machining mode, the surface quality of copper material is not damaged in the machining process, and the packaging accuracy of the semiconductor chip is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip packaging, and more particularly to a semiconductor chip packaging method and a semiconductor chip. Background Technology

[0002] In the field of semiconductor chip packaging, blade cutting is commonly used to remove epoxy resin residue generated during packaging. However, this method can negatively impact the surface quality of the lead frame. Furthermore, with advancements in chip packaging technology, the processing dimensions of semiconductor chips are gradually decreasing. Consequently, if the surface quality of the lead frame fails to meet standards, it will further affect the packaging quality and operational stability of the semiconductor chip. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a semiconductor chip packaging method and a semiconductor chip to solve the above-mentioned technical problems.

[0004] To achieve the above objectives, this application provides a semiconductor chip packaging method. The semiconductor chip includes a lead frame, a wafer and pins disposed on the lead frame, the wafer and pins being encapsulated on the lead frame with epoxy resin to form a packaging unit, and the area between the packaging units being a region to be diced. The method includes:

[0005] A cutting groove is formed on the area to be cut using a half-cut process based on wettable encapsulation technology, and epoxy resin residue is formed in the cutting groove and between the cutting groove and the pin. Laser cutting is used to remove the epoxy resin residue in order to clean the inner wall area of ​​the cutting groove.

[0006] Optionally, the cutting groove includes a bottom wall, a first side wall, and a second side wall, wherein the first side wall and the second side wall are located on both sides of the bottom wall; Epoxy resin residue is formed within the cutting groove and between the cutting groove and the pin, including: A continuous epoxy resin residue is formed between the first sidewall, the bottom wall, and the second sidewall.

[0007] Optionally, after removing the epoxy resin residue using laser cutting, the method further includes: A secondary laser spot cutting is performed on the cutting groove to remove metal residue that has re-formed between the pins due to the laser cutting.

[0008] Optionally, the secondary laser spot cutting includes: Check for any metal residue between the pins and mark the locations where metal residue is found. The marked points are then subjected to secondary laser spot cutting.

[0009] Optionally, after removing the epoxy resin residue using laser cutting, the method further includes: The cutting groove is cut using a full-cut process to separate the lead frame into individual packaging units.

[0010] Optionally, in the process of cutting the groove using a full-cutting process, the bottom wall is cut, and after cutting, a first step surface and a second step surface for accommodating solder are formed on the first side wall and the second side wall, respectively.

[0011] Optionally, in the process of removing the epoxy resin residue using laser cutting, a laser cutting width w and a laser cutting depth h are set; the formula for calculating the laser cutting width w is: ; Among them, the The width of the cutter in the full-cutting process; The width between the first sidewall and the second sidewall.

[0012] Optionally, the tolerance range for the laser cutting depth h is ±15 micrometers.

[0013] Optionally, the laser cutting includes ultraviolet laser cutting and green laser cutting.

[0014] Based on the same inventive concept, this application also provides a semiconductor chip, including a lead frame and a wafer and pins disposed on the lead frame, wherein the wafer and the pins are encapsulated on the lead frame by epoxy resin; and the semiconductor chip is encapsulated using the semiconductor chip encapsulation method described above.

[0015] As can be seen from the above, the semiconductor chip packaging method and semiconductor chip provided in this application use laser cutting processing to replace the traditional blade processing method. This process does not damage the surface quality of the copper material and is used to improve the packaging accuracy of the semiconductor chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a semiconductor chip packaging method provided in an embodiment of this application; Figure 2 The secondary laser dot-jet cutting method in a semiconductor chip packaging method provided in an embodiment of this application is a flowchart; Figure 3 A schematic diagram of a semiconductor chip packaging method provided in an embodiment of this application; Figure 4 A schematic diagram illustrating a semiconductor chip packaging method provided in another embodiment of this application; Figure 5 This is a schematic diagram of the half-cut process in a semiconductor chip packaging method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the full dicing process in a semiconductor chip packaging method provided in an embodiment of this application.

[0018] Marker explanation: 100. Semiconductor chip; 110. Lead frame; 111. Wafer; 112. Pin; 113. Dig groove; 114. First sidewall; 1141. First step surface; 115. Bottom wall; 116. Second sidewall; 1161. Second step surface; 117. Marker point. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] In the field of semiconductor chip packaging, blade cutting is commonly used to remove epoxy resin residue generated during packaging. However, this method can negatively impact the surface quality of the lead frame. Furthermore, with advancements in chip packaging technology, the processing dimensions of semiconductor chips are gradually decreasing. Consequently, if the surface quality of the lead frame fails to meet standards, it will further affect the packaging quality and operational stability of the semiconductor chip.

[0022] To address the aforementioned issues, this application provides a semiconductor chip packaging method and a semiconductor chip, which uses laser cutting to replace the traditional blade processing method. This process does not damage the surface quality of the copper material, thereby improving the packaging accuracy of the semiconductor chip.

[0023] Reference Figure 1-6 As shown, this application discloses a semiconductor chip packaging method, including a lead frame 110, and a wafer 111 and leads 112 disposed on the lead frame 110. The wafer 111 and leads 112 are encapsulated on the lead frame 110 with epoxy resin to form a packaging unit. The area between the packaging units is a region to be diced. The semiconductor chip packaging method specifically includes: Step S10: A cutting groove 113 is formed on the area to be cut using a half-cutting process based on wettable encapsulation technology. Epoxy resin residue is formed inside the cutting groove 113 and between the cutting groove 113 and the pin 112. Step S20: Use laser cutting to remove epoxy resin residue in order to clean the inner wall area of ​​the cutting groove 113.

[0024] Specifically, in this embodiment, the lead frame 110 is made of copper alloy. The wafer 111 is disposed on the lead frame 110 and connected to the pins 112 disposed on the lead frame 110 to form a current path. An epoxy resin encapsulation is used to form the lead frame 110, which carries the wafer 111 and pins 112, to prevent excessive exposure of the wafer 111 and pins 112 to the external environment, thus preventing contamination and damage and improving the stability of the semiconductor wafer 111 in use.

[0025] Reference Figure 4 In this embodiment, the area between the packaging units is the area to be cut. The area to be cut is generated on the lead frame 110 by chemical etching. Chemical etching can selectively remove part of the thickness on the lead frame to form a groove structure of a specific depth, but does not completely penetrate the copper alloy material on the lead frame.

[0026] In this embodiment, the wettable packaging technology used in step S10 is a quad flat leadless package, with pins 112 disposed inside the semiconductor chip 100. This design offers advantages such as simple structure and reduced package area. A dicing process based on wettable packaging technology is used to form a dicing groove 113 on the area to be diced. Cutting the dicing groove 113 allows for the separation of a single semiconductor chip 100 for subsequent manufacturing processes.

[0027] Here, in the half-cut process of wettable packaging technology, the cutting groove 113 needs to be specially treated so that the pin 112 structure is exposed on the sidewall of the cutting groove 113 and wettable wing is formed. When manufacturing and processing a single semiconductor chip 100, solder is used to solder the single semiconductor chip 100 onto the circuit board. The solder climbs to the wettable wing on the semiconductor chip 100 to form a solder joint at the bottom of the package structure of the semiconductor chip 100. This not only improves the detection performance of the semiconductor chip 100, but also improves the performance of the semiconductor chip 100 in use.

[0028] In step S20 of this embodiment, during the packaging process of semiconductor chip 100, it is necessary to use laser cutting to remove epoxy resin residue. By cleaning the inner wall area of ​​the cutting groove 113, the pin 112 structure is exposed on the side wall of the cutting groove 113. This facilitates the subsequent cutting of the cutting groove 113 and better implementation of the solder crawling function on the wettable side wings of semiconductor chip 100, thereby improving the stability of semiconductor chip 100 in use.

[0029] In some implementations, refer to Figure 5 The cutting groove 113 includes a bottom wall 115, a first side wall 114 and a second side wall 116, with the first side wall 114 and the second side wall 116 located on both sides of the bottom wall 115, respectively. Epoxy resin residue is formed inside the cutting groove 113 and between the cutting groove 113 and the pin 112. At the same time, step S10 includes forming a continuous epoxy resin residue between the first sidewall 114, the bottom wall 115 and the second sidewall 116.

[0030] Specifically, in this embodiment, the first sidewall 114 and the second sidewall 116 are wettable wing components in wettable packaging technology. Laser cutting is used to remove epoxy resin residue from the bottom wall 115 and the first sidewall 114, and from the bottom wall 115 and the second sidewall 116, to expose the pins 112 on the first sidewall 114 and the second sidewall 116. Laser cutting is also used to remove epoxy resin residue between the cutting groove 113 and the pins 112, improving the cleanliness of the wettable wing area and further enhancing the processing accuracy of the semiconductor chip 100 in subsequent soldering processes. The continuous epoxy resin residue formed between the first sidewall 114, the bottom wall 115, and the second sidewall 116 is an epoxy resin structure formed inside the cutting groove 113 after filling it with epoxy resin. Laser cutting of the cutting groove 113 is only to cut out the specified tin-plating area, not to completely remove the epoxy resin structure inside the cutting groove 113.

[0031] In some embodiments, after removing epoxy resin residue using laser cutting, the process further includes: Step S30: Perform secondary laser spot cutting on the cutting groove 113 to remove the metal residue that was re-formed between pins 112 due to laser cutting.

[0032] Specifically, the metal residue is copper alloy residue.

[0033] Reference Figure 3 The secondary laser-assisted spot cutting location is the epoxy resin area between the edges of the first sidewall 114 and the second sidewall 116 on the cutting groove 113 and the pin 112. When processing the cutting groove 113 with laser cutting, copper alloy can sputter onto the epoxy resin area between the edges of the first sidewall 114 and the second sidewall 116 and the pin 112. This sputtered copper alloy can create unwanted conductive paths between the pins 112, leading to short circuits and disrupting the original circuit design of the semiconductor chip 100, causing it to fail. To avoid this problem, a secondary laser-assisted spot cutting is performed on the cutting groove 113, which not only prevents short circuits on the pins 112 but also improves the packaging yield of the semiconductor chip 100.

[0034] In some implementations, refer to Figure 2 Secondary laser spot cutting, including: Step S31: Check whether there is any metal residue between pins 112 and pins 112, and mark the location where there is metal residue. Step S32: Perform secondary laser spot cutting on the marked point 117.

[0035] Specifically, the secondary laser spot cutting is used to control the laser cutting device to cut at a designated point on the cutting groove 113. The designated point is set as a marker point 117, and the position data of the marker point 117 is sent to the laser cutting end to control the cutting head of the laser cutting device to move quickly to the position of the marker point 117, and to perform spot cutting on the metal residue at the marker point 117.

[0036] Therefore, this application, based on the removal of epoxy resin residue by laser cutting, adopts a secondary laser spot cutting method with a shorter cutting path and higher cutting precision, which further improves the yield of semiconductor chip 100 packaging.

[0037] In some embodiments, after removing epoxy resin residue using laser cutting, the process further includes: Step S40: The cutting groove 113 is cut using a full-cut process to separate the lead frame 110 into a single packaging unit.

[0038] Specifically, refer to Figure 5 The full dicing process is based on the half dicing process. It involves cutting the lead frame 110 along the center line of the dicing groove 113 to separate the individual semiconductor wafer 111 from the waste frame, and then using the individual semiconductor wafer 111 for subsequent production. The full dicing process uses blade cutting.

[0039] In some embodiments, the bottom wall 115 is cut during the cutting process of the cutting groove 113 using a full-cutting process. After cutting, a first step surface 1141 and a second step surface 1161 for accommodating solder are formed on the first side wall 114 and the second side wall 116, respectively.

[0040] Specifically, the depth of the first step surface 1141 and the second step surface 1161 is used for tin plating on the first step surface 1141 and the second step surface 1161 during subsequent production and processing.

[0041] In some implementations, when removing epoxy resin residue using laser cutting, a laser cutting width w and a laser cutting depth h are set; the formula for calculating the laser cutting width w is: ; in, This refers to the width of the cutting blade in the full-cut process; The width between the first sidewall 114 and the second sidewall 116.

[0042] Specifically, in the process of removing epoxy resin residue using laser cutting, the cutting accuracy in terms of laser cutting width w and laser cutting depth h is ±3 micrometers, while the cutting accuracy of blades in the prior art is ±25 micrometers.

[0043] In this embodiment, the use of laser cutting to remove epoxy resin residue not only improves the packaging precision of semiconductor chip 100, but also further meets the stringent requirements of the inner wall area of ​​the cutting groove 113 for the step width of tin plating. Here, the step width ranges from 10 micrometers to 60 micrometers.

[0044] In this embodiment, laser cutting is used to remove epoxy resin residue along the cutting groove 113, which will not affect the local copper alloy properties in the cutting groove 113 of the lead frame 110. Compared with the prior art method of removing epoxy resin residue in the cutting groove 113 by using a blade, the cutting force generated by laser cutting is more gentle and will not cause the copper material inside the cutting groove 113 to have abnormal elongation due to external force.

[0045] In some implementations, refer to Figure 5 The tolerance range for laser cutting depth h is ±15 micrometers.

[0046] Specifically, after the lead frame 110 is encapsulated with epoxy resin, the dicing groove 113 is filled with epoxy resin. If blade cutting is used to remove the epoxy resin filler, the cutting depth is greatly affected by the control of external equipment. The tolerance range of the blade cutting depth is ±30 micrometers, which may result in the lead frame 110 being cut through due to excessive cutting depth, and the problem of not leaving a tin-plating area. In this application, laser cutting is used to remove the epoxy resin filler to form a stepped depth on the lead frame 110.

[0047] The stepped depth includes a first stepped depth and a second stepped depth. The first stepped depth is the depth between the first sidewall 114 and the first step surface 1141; the second stepped depth is the depth between the second sidewall 116 and the second step surface 1161. The first and second stepped depths represent the solder penetration depth of the semiconductor chip. During semiconductor chip processing, solder is filled between the first sidewall 114 and the first step surface 1141, and between the second sidewall 116 and the second step surface 1161, respectively, to form solder joints.

[0048] For example, the tolerance of the laser cutting depth h includes -15 micrometers, -10 micrometers, -5 micrometers, 5 micrometers, 10 micrometers, 15 micrometers, etc.

[0049] Preferably, the step depth is not less than 0.1 micrometers.

[0050] In some implementations, laser cutting includes ultraviolet laser cutting and green laser cutting.

[0051] Specifically, this application utilizes laser cutting to remove epoxy resin residue, which has minimal impact on the surface quality of the copper alloy within the cutting groove 113. This avoids the generation of copper burrs within the cutting groove 113 during epoxy resin residue removal. Furthermore, during semiconductor chip 100 packaging, the distance between pins 112 can be controlled within the specification range of 0.3 to 0.4 micrometers, reducing the short-circuit risk of wafer 111 during use and improving the processing precision of wafer 111 structure.

[0052] For example, the distance control between pins 112 includes 0.3 micrometers, 0.38 micrometers, and 0.4 micrometers.

[0053] Here, based on the characteristic that epoxy resin materials are easily decomposed and melted under high temperature environment, this embodiment adopts a laser cutting method based on ultraviolet laser or green laser. During the cutting process, after the ultraviolet laser or green laser is absorbed by the epoxy resin, energy fluctuations are generated inside the epoxy resin and the internal temperature of the epoxy resin rises. Under high temperature conditions, the epoxy resin encapsulation structure can be decomposed and removed.

[0054] Furthermore, compared with blade cutting, the laser cutting method in this embodiment can form a smooth epoxy resin cutting plane. By adjusting the laser cutting parameters to adapt to the decomposition conditions of epoxy resin, the problem of edge turning in the epoxy resin residue on the cutting plane will not occur.

[0055] In summary, referring to Figure 1 The overall process of the semiconductor chip packaging method in this application includes: Step S10: A cutting groove 113 is formed on the area to be cut using a half-cutting process based on wettable encapsulation technology, and epoxy resin residue is formed in the cutting groove 113 and between the cutting groove 113 and the pin 112. Step S20: Use laser cutting to remove epoxy resin residue in order to clean the inner wall area of ​​the cutting groove 113; Step S30: Perform secondary laser spot cutting on the cutting groove 113 to remove the metal residue that is formed again between the pins 112 due to laser cutting. Step S40: The cutting groove 113 is cut using a full-cut process to separate the lead frame 110 into a single packaging unit, and the single packaging unit is used in subsequent production processes.

[0056] Specifically, in this embodiment, during the half-cutting process based on wettable packaging technology, laser cutting is used to remove epoxy resin residue, thus avoiding the generation of copper burrs in the cutting groove due to epoxy resin removal. With improvements in chip packaging technology, the distance between pins on the lead frame is becoming increasingly smaller, further avoiding the risk of short-distance short circuits between pins caused by copper burrs generated in the cutting groove.

[0057] Based on the same inventive concept, this embodiment also provides a semiconductor chip, including a lead frame 110 and a wafer 111 and pins 112 disposed on the lead frame 110. The wafer 111 and pins 112 are encapsulated on the lead frame 110 by epoxy resin; the semiconductor chip 100 packaging method is used for packaging.

[0058] Specifically, in this embodiment, the semiconductor chip 100 is manufactured by laser cutting to remove epoxy resin residue from the inner wall of the cutting groove 113, which will not affect the copper material inside the lead frame 110, thus improving the processing accuracy of the semiconductor chip 100 and better meeting the stringent requirements for the tin plating depth of the semiconductor chip 100 in subsequent production processes.

[0059] It should be noted that some embodiments of this application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result.

[0060] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the above embodiments of this application, which are not provided in detail for the sake of brevity.

[0061] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A semiconductor chip packaging method, the semiconductor chip comprising a lead frame, a wafer and pins disposed on the lead frame, the wafer and the pins being encapsulated on the lead frame by an epoxy to form an encapsulated unit, the encapsulated unit and the encapsulated unit being a cutting region to be cut, characterized in that, The method includes: ​ A cutting groove is formed on the area to be cut using a half-cut process based on wettable encapsulation technology, and epoxy resin residue is formed in the cutting groove and between the cutting groove and the pin. Laser cutting is used to remove the epoxy resin residue in order to clean the inner wall area of ​​the cutting groove.

2. The semiconductor chip packaging method according to claim 1, characterized in that, The cutting groove includes a bottom wall, a first side wall, and a second side wall, with the first side wall and the second side wall located on opposite sides of the bottom wall. Epoxy resin residue is formed within the cutting groove and between the cutting groove and the pin, including: A continuous epoxy resin residue is formed between the first sidewall, the bottom wall, and the second sidewall.

3. The semiconductor chip packaging method according to claim 1, characterized in that, After removing the epoxy resin residue using laser cutting, the process further includes: A secondary laser spot cutting is performed on the cutting groove to remove metal residue that has re-formed between the pins due to the laser cutting.

4. The semiconductor chip packaging method according to claim 3, characterized in that, The secondary laser spot cutting includes: Check for any metal residue between the pins and mark the locations where metal residue is found. The marked points are then subjected to secondary laser spot cutting.

5. The semiconductor chip packaging method according to claim 2, characterized in that, After removing the epoxy resin residue using laser cutting, the process further includes: The cutting groove is cut using a full-cut process to separate the lead frame into individual packaging units.

6. The semiconductor chip packaging method according to claim 5, characterized in that, In the process of cutting the groove using a full-cutting process, the bottom wall is cut, and after cutting, a first step surface and a second step surface for accommodating solder are formed on the first side wall and the second side wall, respectively.

7. The semiconductor chip packaging method according to claim 5, characterized in that, In the process of removing epoxy resin residue using laser cutting, the laser cutting width w and laser cutting depth h are set; the formula for calculating the laser cutting width w is: Among them, the The width of the cutter in the full-cutting process; The width between the first sidewall and the second sidewall.

8. The semiconductor chip packaging method according to claim 7, characterized in that, The tolerance range for laser cutting depth h is ±15 micrometers.

9. The semiconductor chip packaging method according to claim 1, characterized in that, The laser cutting includes ultraviolet laser cutting and green laser cutting.

10. A semiconductor chip, characterized in that, The device includes a lead frame and a wafer and pins disposed on the lead frame, wherein the wafer and pins are encapsulated on the lead frame with epoxy resin; and is packaged using a semiconductor chip packaging method as described in any one of claims 1-9.

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